diff --git a/pt2001/include/rusefi/pt2001_memory_map.h b/pt2001/include/rusefi/pt2001_memory_map.h
index effff3e..b29df8e 100644
--- a/pt2001/include/rusefi/pt2001_memory_map.h
+++ b/pt2001/include/rusefi/pt2001_memory_map.h
@@ -18,6 +18,8 @@ enum class MC33816Mem {
Thold_tot = PT2001_D1_Thold_tot,
Tboost_min = PT2001_D1_Tboost_min,
Tboost_max = PT2001_D1_Tboost_max,
+ Tboost_inj12 = PT2001_D1_Tboost_inj12,
+ Tboost_inj34 = PT2001_D1_Tboost_inj34,
// see dram2.def values, base 64 for channel 2
Vboost_high = PT2001_D2_Vboost_high,
Vboost_low = PT2001_D2_Vboost_low,
diff --git a/pt2001/project/rusefi/MicrocodeCh1/ch1.psc b/pt2001/project/rusefi/MicrocodeCh1/ch1.psc
index 4b087a9..5895fa7 100644
--- a/pt2001/project/rusefi/MicrocodeCh1/ch1.psc
+++ b/pt2001/project/rusefi/MicrocodeCh1/ch1.psc
@@ -9,6 +9,8 @@ init0: stgn gain12.6 sssc; * Set the gain of the opamp
ldjr1 eoinj0; * Load the eoinj line label Code RAM address into the register jr1
ldjr2 idle0; * Load the idle line label Code RAM address into the register jr2
cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase
+
+ * stoc on sssc;
* ### Idle phase- the uPC loops here until start signal is present ###
idle0: joslr inj1_start start1; * Perform an actuation on inj1 if start 1 (only) is active
@@ -42,7 +44,7 @@ boost0: load Iboost dac_sssc _ofs; * Load the boost phase curre
ldcd rst _ofs keep keep Tboost_max c2; * Start boost counter in case Iboost never reached
cwer boost0_err tc2 row5; * Jump to boost0_err in case boost phase takes too long
- stf low b0; * set flag0 low to force the DC-DC converter in idle mode
+ stf low b1; * set flag1 low to force the DC-DC converter in idle mode
stos off on on; * Turn VBAT off, BOOST on, LS on
wait row1245; * Wait for one of the previously defined conditions
@@ -51,17 +53,24 @@ boost0_mintime: wait row135; * Minimum time for boost pha
boost0_err: stos off off off; * Turn off all drivers
stf low b10; * Set ch1 error flag (OA_1) to signal MCU
- stf high b0; * set flag0 high to release the DC-DC converter idle mode
+ stf high b1; * set flag0 high to release the DC-DC converter idle mode
wait row1; * Wait for start signal to go low for the next injection attempt
* ### Peak phase continue on Vbat ###
-peak0: ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1
+peak0: store cnt2 Tboost_inj12 _ofs;
+ stos keep off keep;
+ ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1
load Ipeak dac_sssc _ofs; * Load the peak current threshold in the current DAC
cwer bypass0 tc1 row2; * Jump to bypass phase when tc1 reaches end of count
cwer peak_on0 tc2 row3; * Jump to peak_on when tc2 reaches end of count
cwer peak_off0 ocur row4; * Jump to peak_off when current is over threshold
- stf high b0; * set flag0 high to release the DC-DC converter idle mode
+ stf high b1; * set flag0 high to release the DC-DC converter idle mode
+ * we are not waiting until discharge to the current?
+ * discharge down to a known current
+ cwer peak_off0 _ocur row5; * Jump to peak_off when own-current is discharged
+ wait row125;
+
peak_on0: stos on off on; * Turn VBAT on, BOOST off, LS on
wait row124; * Wait for one of the previously defined conditions
@@ -91,7 +100,7 @@ hold_off0: ldcd rst _ofs keep keep Thold_off c2; * Load the length of the hol
* ### End of injection phase ###
eoinj0: stos off off off; * Turn VBAT off, BOOST off, LS off
- stf high b0; * set flag0 to high to release the DC-DC converter idle mode
+ stf high b1; * set flag1 to high to release the DC-DC converter idle mode
jmpf jr2; * Jump back to idle phase
* ### End of Channel 1 - uCore0 code ###
@@ -139,7 +148,7 @@ boost1: load Iboost dac_sssc _ofs; * Load the boost phase curre
ldcd rst _ofs keep keep Tboost_max c2; * Start boost counter in case Iboost never reached
cwer boost1_err tc2 row5; * Jump to boost1_err in case boost phase takes too long
- stf low b0; * set flag0 low to force the DC-DC converter in idle mode
+ stf low b1; * set flag0 low to force the DC-DC converter in idle mode
stos off on on; * Turn VBAT off, BOOST on, LS on
wait row1245; * Wait for one of the previously defined conditions
@@ -147,18 +156,23 @@ boost1: load Iboost dac_sssc _ofs; * Load the boost phase curre
boost1_mintime: wait row135; * Minimum time for boost phase has been reached, now wait for !start, overcurrent or timeout
boost1_err: stos off off off; * Turn off all drivers
- stf low b11; * Set ch1 error flag (OA_1) to signal MCU
- stf high b0; * set flag0 high to release the DC-DC converter idle mode
+ stf low b11; * Set ch1 error flag (OA_2) to signal MCU
+ stf high b1; * set flag0 high to release the DC-DC converter idle mode
wait row1; * Wait for start signal to go low for the next injection attempt
-
* ### Peak phase continue on Vbat ###
-peak1: ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1
+peak1: store cnt2 Tboost_inj34 _ofs;
+ stos keep off keep;
+ ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1
load Ipeak dac_sssc _ofs; * Load the peak current threshold in the current DAC
cwer bypass1 tc1 row2; * Jump to bypass phase when tc1 reaches end of count
cwer peak_on1 tc2 row3; * Jump to peak_on when tc2 reaches end of count
cwer peak_off1 ocur row4; * Jump to peak_off when current is over threshold
- stf high b0; * set flag0 high to release the DC-DC converter idle mode
+ stf high b1; * set flag0 high to release the DC-DC converter idle mode
+
+ * discharge down to a known current
+ cwer peak_off1 _ocur row5; * Jump to peak_off when own-current is discharged
+ wait row125;
peak_on1: stos on off on; * Turn VBAT on, BOOST off, LS on
wait row124; * Wait for one of the previously defined conditions
@@ -189,7 +203,7 @@ hold_off1: ldcd rst _ofs keep keep Thold_off c2; * Load the length of the hol
* ### End of injection phase ###
eoinj1: stos off off off; * Turn VBAT off, BOOST off, LS off
- stf high b0; * set flag0 to high to release the DC-DC converter idle mode
+ stf high b1; * set flag0 to high to release the DC-DC converter idle mode
jmpf jr2; * Jump back to idle phase
* ### End of Channel 1 - uCore1 code ###
\ No newline at end of file
diff --git a/pt2001/project/rusefi/MicrocodeCh1/dram1.def b/pt2001/project/rusefi/MicrocodeCh1/dram1.def
index 3551dea..036ff38 100644
--- a/pt2001/project/rusefi/MicrocodeCh1/dram1.def
+++ b/pt2001/project/rusefi/MicrocodeCh1/dram1.def
@@ -8,3 +8,5 @@
#define Thold_tot 7;
#define Tboost_max 8;
#define Tboost_min 9;
+#define Tboost_inj12 32;
+#define Tboost_inj34 33;
diff --git a/pt2001/project/rusefi/MicrocodeCh2/ch2.psc b/pt2001/project/rusefi/MicrocodeCh2/ch2.psc
index 8236092..03a0738 100644
--- a/pt2001/project/rusefi/MicrocodeCh2/ch2.psc
+++ b/pt2001/project/rusefi/MicrocodeCh2/ch2.psc
@@ -6,27 +6,24 @@ init0: stgn gain5.8 ossc; * Set the gain of the op
load Isense4_low dac_ossc _ofs; * Load Isense4_high current threshold in DAC 4L
load Isense4_high dac4h4n _ofs; * Load Isense4_high current threshold in DAC 4H
stdm null; * Set the boost voltage DAC access mode
- cwer dcdc_idle _f0 row1; * Wait table entry for Vboost under Vboost_low threshold condition
+ cwer dcdc_idle _f1 row1; * Wait table entry for flag1 going low
cwer dcdc_on _vb row2; * Wait table entry for Vboost under Vboost_low threshold condition
cwer dcdc_off vb row3; * Wait table entry for Vboost over Vboost_high threshold condition
* ### Asynchronous phase ###
dcdc_on: load Vboost_high dac4h4n _ofs; * Load the upper Vboost threshold in vboost_dac register
- stf high b1;
stdcctl async; * Enable asynchronous mode
wait row13; * Wait for one of the previously defined conditions
* ### Synchronous phase ###
dcdc_off: load Vboost_low dac4h4n _ofs; * Load the upper Vboost threshold in vboost_dac register
- stf low b1;
stdcctl sync; * Enable synchronous mode
wait row12; * Wait for one of the previously defined conditions
* ### Idle phase ###
dcdc_idle: stdcctl sync; * Enable synchronous mode
- stf low b1;
- stf high b1;
- jocr dcdc_idle _f0; * jump to previous line while flag 0 is low
+ stos keep off keep;
+ jocr dcdc_idle _f1; * jump to previous line while flag 0 is low
jmpr dcdc_on; * force the DC-DC converter on when flag 0 goes high
* ### End of Channel 2 - uCore0 code ###
diff --git a/pt2001/project/rusefi/Registers/ch1_config_reg.bin b/pt2001/project/rusefi/Registers/ch1_config_reg.bin
index 621dffa..dd4b763 100644
--- a/pt2001/project/rusefi/Registers/ch1_config_reg.bin
+++ b/pt2001/project/rusefi/Registers/ch1_config_reg.bin
@@ -5,11 +5,11 @@
0000001100000011
0000000000000000
0000000000000000
-0000000001110010
-1001000111100111
-0101011011010110
+0000000001111010
+0100000110110100
+1001000000011000
0000000000000000
-0000000000111001
+0000000000111101
0000000000000000
0000000000000000
0000000000000000
diff --git a/pt2001/project/rusefi/Registers/ch2_config_reg.bin b/pt2001/project/rusefi/Registers/ch2_config_reg.bin
index e53a45e..3713fe7 100644
--- a/pt2001/project/rusefi/Registers/ch2_config_reg.bin
+++ b/pt2001/project/rusefi/Registers/ch2_config_reg.bin
@@ -5,11 +5,11 @@
0000110000000000
0000000000000000
0000000000000000
-0000000000101011
-0010000110001100
-1101110010110110
+0000000000101000
+0010111011111100
+0110110101111000
0000000000000000
-0000000000010100
+0000000000010001
0000000000000000
0000000000000000
0000000000000000
diff --git a/pt2001/project/rusefi/Registers/dram1.bin b/pt2001/project/rusefi/Registers/dram1.bin
index a24a2da..326bbfc 100644
--- a/pt2001/project/rusefi/Registers/dram1.bin
+++ b/pt2001/project/rusefi/Registers/dram1.bin
@@ -1,6 +1,6 @@
-0000000011000000
-0000000010010010
-0000000001001001
+0000000010001101
+0000000001101101
+0000000000111010
0000000000111100
0001000001101000
0000000000111100
diff --git a/pt2001/project/rusefi/Registers/main_config_reg.bin b/pt2001/project/rusefi/Registers/main_config_reg.bin
index 6ca460f..41c17a5 100644
--- a/pt2001/project/rusefi/Registers/main_config_reg.bin
+++ b/pt2001/project/rusefi/Registers/main_config_reg.bin
@@ -1,5 +1,5 @@
0000000000000011
-0001001111111110
+0001001111111100
0000000000000000
0001111000000000
0000000000000000
diff --git a/pt2001/project/rusefi/project.xml b/pt2001/project/rusefi/project.xml
index 562b9ee..76749a5 100644
--- a/pt2001/project/rusefi/project.xml
+++ b/pt2001/project/rusefi/project.xml
@@ -21,7 +21,6 @@
bin\ch2.hex
Registers\dram1.hex
Registers\dram2.hex
- labels.xml
Actuator\inj1.xml
Actuator\inj2.xml
Actuator\inj3.xml
diff --git a/pt2001/project/rusefi/sample_code/PT2001_LoadData.c b/pt2001/project/rusefi/sample_code/PT2001_LoadData.c
index a5834a5..ab3670f 100644
--- a/pt2001/project/rusefi/sample_code/PT2001_LoadData.c
+++ b/pt2001/project/rusefi/sample_code/PT2001_LoadData.c
@@ -1,7 +1,7 @@
/*******************************************************************************
* Example Code
*
-* Copyright(C) 2023 NXP Semiconductors
+* Copyright(C) 2025 NXP Semiconductors
* NXP Semiconductors Confidential and Proprietary
*
* Software that is described herein is for illustrative purposes only
@@ -48,36 +48,37 @@
#include "PT2001_LoadData.h"
// Data to be loaded into the Code RAM 1 memory space
-unsigned short const PT2001_code_RAM1[114] =
+unsigned short const PT2001_code_RAM1[122] =
{
- 0x7612, 0x6C57, 0x917F, 0xA514, 0x8DD6, 0xC288, 0x4F9B, 0x1EC9, 0x5C0D, 0xF99D,
+ 0x7612, 0x6C67, 0x917F, 0xA514, 0x8DD6, 0xC288, 0x4F9B, 0x1EC9, 0x5C0D, 0xF99D,
0x4129, 0x2EEE, 0x97B0, 0x3534, 0x93BA, 0x5D25, 0xEE21, 0x2AAD, 0xE457, 0x2DB8,
- 0xBED3, 0xBEB9, 0x2F08, 0xDA3C, 0x0499, 0x8DDE, 0xB519, 0x8E21, 0xAE4D, 0xF3E1,
- 0x6E41, 0x9F0E, 0x2476, 0xBA8B, 0x4422, 0x0133, 0x6DAC, 0xA368, 0xE91F, 0x5E97,
- 0x7820, 0x4662, 0xFEE0, 0x6F02, 0x8A92, 0x9A83, 0xE194, 0x6FD0, 0x1895, 0x80AB,
- 0x4F93, 0xE1DA, 0x51BF, 0x70D8, 0xF25E, 0x7021, 0x2270, 0xF748, 0x51C5, 0xA4F1,
- 0x329C, 0x5ADC, 0xD84C, 0xF054, 0x6E39, 0x2389, 0xCD76, 0x52F5, 0xF072, 0x8D02,
- 0x4045, 0xDFEA, 0x1D65, 0xAD07, 0x33F3, 0x6650, 0x8854, 0x210D, 0x3A3C, 0xD20B,
- 0x25B3, 0x8090, 0x27DE, 0xDF3E, 0xE928, 0x7D95, 0x83CC, 0xA366, 0x7879, 0x8A2C,
- 0xE2E2, 0x1E41, 0x6530, 0x24F8, 0xB726, 0xF030, 0xCEA7, 0xF3FF, 0x4080, 0xF1DD,
- 0xB433, 0xBFCB, 0x95C2, 0xDEDE, 0x2E14, 0xF672, 0x0567, 0x102E, 0xE0BC, 0xBD5F,
- 0x21BF, 0x4D2B, 0x2ABD, 0x01B5
+ 0xBED3, 0xBEB8, 0x2F08, 0xDA3C, 0x0499, 0x8DDE, 0xB519, 0x8E20, 0xAE4D, 0x2E64,
+ 0xDBC7, 0x1D6A, 0x6315, 0xA415, 0xBA73, 0xF9AB, 0x6C56, 0x1A14, 0xE85A, 0x5FF6,
+ 0x3DAE, 0x0274, 0x0E54, 0x6F0C, 0xAA10, 0x2C14, 0xF516, 0x9E78, 0x8E6C, 0x360F,
+ 0xAAF8, 0x753D, 0xA317, 0x71B9, 0xF300, 0x1497, 0x2F8B, 0xF777, 0xE42C, 0x00F4,
+ 0x1B15, 0x6760, 0x5095, 0x6D56, 0x47B8, 0xA3D2, 0xEB76, 0xD610, 0xE6D4, 0x8D36,
+ 0x4041, 0xD7CB, 0xE618, 0xFF52, 0x4CFB, 0x2A72, 0x0C62, 0x3092, 0x5ED5, 0x2AB1,
+ 0x40E0, 0x7EA4, 0x276A, 0xDF8F, 0xE8C3, 0x7D81, 0xE79D, 0x164F, 0x9EE8, 0x798C,
+ 0xA799, 0x1EF5, 0x0152, 0x9031, 0x1105, 0x0EC7, 0x375E, 0xB78B, 0xBDEA, 0x002C,
+ 0xB55C, 0xDAC7, 0x6743, 0x3AE8, 0xDFB2, 0x4009, 0x0554, 0xE1C7, 0x85F3, 0xD90E,
+ 0x967A, 0xA91E, 0xDAEC, 0xFEE6, 0xCF46, 0x2C9A, 0x9695, 0xD631, 0x6520, 0x2DC3,
+ 0x53BE, 0xF116
};
// Data to be loaded into the Code RAM 2 memory space
-unsigned short const PT2001_code_RAM2[43] =
+unsigned short const PT2001_code_RAM2[40] =
{
- 0x761B, 0x6F45, 0x838D, 0x80B4, 0x53F2, 0x0EBC, 0x8F2D, 0xA78E, 0xE8AB, 0xE3DB,
- 0xF477, 0x800F, 0x2336, 0x2F77, 0x267B, 0xBC19, 0x007E, 0x4E55, 0x28AA, 0x52E4,
- 0x40CF, 0x0AFD, 0x8B32, 0xFF03, 0x3D8E, 0x802E, 0x1340, 0x95D0, 0x1E86, 0x6591,
- 0xDBEB, 0x786D, 0xB2DF, 0xF4BF, 0xBEB2, 0xF1F4, 0x9E53, 0xE743, 0xE842, 0x3DD7,
- 0x3DA2, 0x4663, 0x03AF
+ 0x761B, 0x6F45, 0x838D, 0x80B4, 0x57F3, 0x0EBC, 0x8D2D, 0xA78E, 0xE919, 0xE39D,
+ 0x4090, 0x34AF, 0x22D4, 0x2F77, 0x273C, 0x8965, 0x1B88, 0x4F99, 0xA82F, 0xEDA4,
+ 0x65D6, 0x865B, 0x22F7, 0x7D94, 0x1E8D, 0x3C41, 0x4787, 0x8EB9, 0xAE4F, 0xF3ED,
+ 0x6949, 0x830E, 0x2676, 0xB481, 0x44BA, 0x005E, 0x0EE0, 0xE62C, 0xE91D, 0x523D
+
};
// Data to be loaded into the Data RAM memory space
unsigned short const PT2001_data_RAM[128] =
{
- 0x00C0, 0x0092, 0x0049, 0x003C, 0x1068, 0x003C, 0x0168, 0xEA60, 0x0960, 0x0258,
+ 0x008D, 0x006D, 0x003A, 0x003C, 0x1068, 0x003C, 0x0168, 0xEA60, 0x0960, 0x0258,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
@@ -95,7 +96,7 @@ unsigned short const PT2001_data_RAM[128] =
// Data to be loaded into the Main register memory space
unsigned short const PT2001_main_config[29] =
{
- 0x0003, 0x13FE, 0x0000, 0x1E00, 0x0000, 0x0000, 0x0001, 0x0000, 0x001F, 0x0000,
+ 0x0003, 0x13FC, 0x0000, 0x1E00, 0x0000, 0x0000, 0x0001, 0x0000, 0x001F, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
};
@@ -103,8 +104,8 @@ unsigned short const PT2001_main_config[29] =
// Data to be loaded into the CH1 register memory space
unsigned short const PT2001_ch1_config[19] =
{
- 0x0008, 0x0000, 0x0000, 0x0000, 0x0303, 0x0000, 0x0000, 0x0072, 0x91E7, 0x56D6,
- 0x0000, 0x0039, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
+ 0x0008, 0x0000, 0x0000, 0x0000, 0x0303, 0x0000, 0x0000, 0x007A, 0x41B4, 0x9018,
+ 0x0000, 0x003D, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
};
// Data to be loaded into the CH2 register memory space
diff --git a/pt2001/project/rusefi/sample_code/PT2001_LoadData.h b/pt2001/project/rusefi/sample_code/PT2001_LoadData.h
index 3f37fc6..d5480b8 100644
--- a/pt2001/project/rusefi/sample_code/PT2001_LoadData.h
+++ b/pt2001/project/rusefi/sample_code/PT2001_LoadData.h
@@ -1,7 +1,7 @@
/*******************************************************************************
* Example Code
*
-* Copyright(C) 2023 NXP Semiconductors
+* Copyright(C) 2025 NXP Semiconductors
* NXP Semiconductors Confidential and Proprietary
*
* Software that is described herein is for illustrative purposes only
@@ -48,8 +48,8 @@
#ifndef PT2001_DATA_H_
#define PT2001_DATA_H_
-extern unsigned short const PT2001_code_RAM1[114]; // CODE RAM CH 1
-extern unsigned short const PT2001_code_RAM2[43]; // CODE RAM CH 2
+extern unsigned short const PT2001_code_RAM1[122]; // CODE RAM CH 1
+extern unsigned short const PT2001_code_RAM2[40]; // CODE RAM CH 2
extern unsigned short const PT2001_data_RAM[128]; // DATA RAM
extern unsigned short const PT2001_main_config[29]; // main configurations
extern unsigned short const PT2001_ch1_config[19]; // CH 1 configurations
diff --git a/pt2001/project/rusefi/sample_code/PT2001_dram.h b/pt2001/project/rusefi/sample_code/PT2001_dram.h
index b37733d..547beb0 100644
--- a/pt2001/project/rusefi/sample_code/PT2001_dram.h
+++ b/pt2001/project/rusefi/sample_code/PT2001_dram.h
@@ -1,7 +1,7 @@
/*******************************************************************************
* Example Code
*
-* Copyright(C) 2023 NXP Semiconductors
+* Copyright(C) 2025 NXP Semiconductors
* NXP Semiconductors Confidential and Proprietary
*
* Software that is described herein is for illustrative purposes only
@@ -58,6 +58,8 @@
#define PT2001_D1_Thold_tot 0x07
#define PT2001_D1_Tboost_max 0x08
#define PT2001_D1_Tboost_min 0x09
+#define PT2001_D1_Tboost_inj12 0x20
+#define PT2001_D1_Tboost_inj34 0x21
// DRAM 2 Parameter Addresses
#define PT2001_D2_Vboost_high 0x40