mirror of https://github.com/rusefi/openblt.git
Refs #400, #431. Added timeout functionality to break out of loops when waiting for hardware acknowledgements.
git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@482 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
parent
eab505d95c
commit
32d3ef07df
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@ -37,6 +37,8 @@
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/****************************************************************************************
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/****************************************************************************************
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* Macro definitions
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* Macro definitions
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****************************************************************************************/
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****************************************************************************************/
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/** \brief Timeout for transmitting a CAN message in milliseconds. */
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#define CAN_MSG_TX_TIMEOUT_MS (50u)
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/** \brief Transmit buffer 1 idle bit. */
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/** \brief Transmit buffer 1 idle bit. */
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#define CAN_TBS1 (0x00000004)
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#define CAN_TBS1 (0x00000004)
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/** \brief Transmit buffer 1 complete bit. */
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/** \brief Transmit buffer 1 complete bit. */
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@ -214,6 +216,8 @@ void CanInit(void)
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****************************************************************************************/
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****************************************************************************************/
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void CanTransmitPacket(blt_int8u *data, blt_int8u len)
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void CanTransmitPacket(blt_int8u *data, blt_int8u len)
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{
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{
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blt_int32u timeout;
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/* check that transmit buffer 1 is ready to accept a new message */
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/* check that transmit buffer 1 is ready to accept a new message */
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ASSERT_RT((CAN1SR & CAN_TBS1) != 0);
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ASSERT_RT((CAN1SR & CAN_TBS1) != 0);
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/* write dlc and configure message as a standard message with 11-bit identifier */
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/* write dlc and configure message as a standard message with 11-bit identifier */
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@ -234,11 +238,20 @@ void CanTransmitPacket(blt_int8u *data, blt_int8u len)
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CAN1TDB1 = (data[7] << 24) + (data[6] << 16) + (data[5] << 8) + data[4];
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CAN1TDB1 = (data[7] << 24) + (data[6] << 16) + (data[5] << 8) + data[4];
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/* write transmission request for transmit buffer 1 */
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/* write transmission request for transmit buffer 1 */
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CAN1CMR = CAN_TR | CAN_STB1;
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CAN1CMR = CAN_TR | CAN_STB1;
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/* set timeout time to wait for transmission completion */
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timeout = TimerGet() + CAN_MSG_TX_TIMEOUT_MS;
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/* wait for transmit completion */
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/* wait for transmit completion */
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while ((CAN1SR & CAN_TCS1) == 0)
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while ((CAN1SR & CAN_TCS1) == 0)
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{
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{
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/* keep the watchdog happy */
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/* keep the watchdog happy */
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CopService();
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CopService();
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/* break loop upon timeout. this would indicate a hardware failure or no other
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* nodes connected to the bus.
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*/
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if (TimerGet() > timeout)
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{
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break;
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}
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}
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}
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} /*** end of CanTransmitPacket ***/
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} /*** end of CanTransmitPacket ***/
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@ -41,7 +41,8 @@
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* reception of the first packet byte.
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* reception of the first packet byte.
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*/
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*/
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#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
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#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
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/** \brief Timeout for transmitting a byte in milliseconds. */
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#define UART_BYTE_TX_TIMEOUT_MS (10u)
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/** \brief Divisor latch access bit. */
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/** \brief Divisor latch access bit. */
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#define UART_DLAB (0x80)
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#define UART_DLAB (0x80)
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@ -261,6 +262,9 @@ static blt_bool UartReceiveByte(blt_int8u *data)
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****************************************************************************************/
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****************************************************************************************/
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static blt_bool UartTransmitByte(blt_int8u data)
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static blt_bool UartTransmitByte(blt_int8u data)
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{
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{
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blt_int32u timeout;
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blt_bool result = BLT_TRUE;
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/* check if tx holding register can accept new data */
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/* check if tx holding register can accept new data */
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if ((U0LSR & UART_THRE) == 0)
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if ((U0LSR & UART_THRE) == 0)
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{
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{
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@ -269,14 +273,22 @@ static blt_bool UartTransmitByte(blt_int8u data)
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}
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}
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/* write byte to transmit holding register */
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/* write byte to transmit holding register */
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U0THR = data;
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U0THR = data;
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/* set timeout time to wait for transmit completion. */
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timeout = TimerGet() + UART_BYTE_TX_TIMEOUT_MS;
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/* wait for tx holding register to be empty */
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/* wait for tx holding register to be empty */
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while ((U0LSR & UART_THRE) == 0)
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while ((U0LSR & UART_THRE) == 0)
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{
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{
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/* keep the watchdog happy */
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/* keep the watchdog happy */
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CopService();
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CopService();
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/* break loop upon timeout. this would indicate a hardware failure. */
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if (TimerGet() > timeout)
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{
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result = BLT_FALSE;
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break;
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}
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}
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}
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/* byte transmitted */
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/* give the result back to the caller */
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return BLT_TRUE;
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return result;
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} /*** end of UartTransmitByte ***/
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} /*** end of UartTransmitByte ***/
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#endif /* BOOT_COM_UART_ENABLE > 0 */
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#endif /* BOOT_COM_UART_ENABLE > 0 */
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@ -35,6 +35,13 @@
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#if (BOOT_COM_CAN_ENABLE > 0)
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#if (BOOT_COM_CAN_ENABLE > 0)
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/****************************************************************************************
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* Macro definitions
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****************************************************************************************/
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/** \brief Timeout for transmitting a CAN message in milliseconds. */
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#define CAN_MSG_TX_TIMEOUT_MS (50u)
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/****************************************************************************************
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/****************************************************************************************
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* Type definitions
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* Type definitions
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****************************************************************************************/
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****************************************************************************************/
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@ -186,8 +193,9 @@ void CanInit(void)
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void CanTransmitPacket(blt_int8u *data, blt_int8u len)
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void CanTransmitPacket(blt_int8u *data, blt_int8u len)
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{
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{
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CanTxMsg txMsg;
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CanTxMsg txMsg;
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uint8_t byteIdx;
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blt_int8u byteIdx;
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uint8_t txMailbox;
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blt_int8u txMailbox;
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blt_int32u timeout;
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/* prepare message */
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/* prepare message */
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if ((BOOT_COM_CAN_TX_MSG_ID & 0x80000000) == 0)
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if ((BOOT_COM_CAN_TX_MSG_ID & 0x80000000) == 0)
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@ -210,11 +218,20 @@ void CanTransmitPacket(blt_int8u *data, blt_int8u len)
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txMsg.Data[byteIdx] = data[byteIdx];
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txMsg.Data[byteIdx] = data[byteIdx];
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}
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}
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txMailbox = CAN_Transmit(CAN, &txMsg);
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txMailbox = CAN_Transmit(CAN, &txMsg);
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/* set timeout time to wait for transmission completion */
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timeout = TimerGet() + CAN_MSG_TX_TIMEOUT_MS;
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/* wait for transmit completion */
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/* wait for transmit completion */
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while (CAN_TransmitStatus(CAN, txMailbox) == CAN_TxStatus_Pending)
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while (CAN_TransmitStatus(CAN, txMailbox) == CAN_TxStatus_Pending)
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{
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{
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/* keep the watchdog happy */
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/* keep the watchdog happy */
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CopService();
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CopService();
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/* break loop upon timeout. this would indicate a hardware failure or no other
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* nodes connected to the bus.
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*/
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if (TimerGet() > timeout)
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{
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break;
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}
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}
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}
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} /*** end of CanTransmitPacket ***/
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} /*** end of CanTransmitPacket ***/
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* reception of the first packet byte.
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* reception of the first packet byte.
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*/
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*/
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#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
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#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
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/** \brief Timeout for transmitting a byte in milliseconds. */
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#define UART_BYTE_TX_TIMEOUT_MS (10u)
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/* map the configured UART channel index to the STM32's USART peripheral */
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/* map the configured UART channel index to the STM32's USART peripheral */
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#if (BOOT_COM_UART_CHANNEL_INDEX == 0)
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#if (BOOT_COM_UART_CHANNEL_INDEX == 0)
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/** \brief Set UART base address to USART1. */
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/** \brief Set UART base address to USART1. */
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****************************************************************************************/
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****************************************************************************************/
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static blt_bool UartTransmitByte(blt_int8u data)
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static blt_bool UartTransmitByte(blt_int8u data)
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{
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{
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blt_int32u timeout;
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blt_bool result = BLT_TRUE;
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/* check if tx holding register can accept new data */
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/* check if tx holding register can accept new data */
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if (USART_GetFlagStatus(USART_CHANNEL, USART_FLAG_TXE) == RESET)
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if (USART_GetFlagStatus(USART_CHANNEL, USART_FLAG_TXE) == RESET)
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{
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{
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}
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}
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/* write byte to transmit holding register */
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/* write byte to transmit holding register */
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USART_SendData(USART_CHANNEL, data);
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USART_SendData(USART_CHANNEL, data);
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/* set timeout time to wait for transmit completion. */
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timeout = TimerGet() + UART_BYTE_TX_TIMEOUT_MS;
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/* wait for tx holding register to be empty */
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/* wait for tx holding register to be empty */
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while (USART_GetFlagStatus(USART_CHANNEL, USART_FLAG_TXE) == RESET)
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while (USART_GetFlagStatus(USART_CHANNEL, USART_FLAG_TXE) == RESET)
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{
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{
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;
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/* keep the watchdog happy */
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CopService();
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/* break loop upon timeout. this would indicate a hardware failure. */
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if (TimerGet() > timeout)
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{
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result = BLT_FALSE;
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break;
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}
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}
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}
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/* byte transmitted */
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/* give the result back to the caller */
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return BLT_TRUE;
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return result;
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} /*** end of UartTransmitByte ***/
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} /*** end of UartTransmitByte ***/
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#endif /* BOOT_COM_UART_ENABLE > 0 */
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#endif /* BOOT_COM_UART_ENABLE > 0 */
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/****************************************************************************************
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/****************************************************************************************
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* Macro definitions
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* Macro definitions
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****************************************************************************************/
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****************************************************************************************/
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/** \brief Timeout for transmitting a CAN message in milliseconds. */
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#define CAN_MSG_TX_TIMEOUT_MS (50u)
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/** \brief Macro for accessing the CAN channel handle in the format that is expected
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/** \brief Macro for accessing the CAN channel handle in the format that is expected
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* by the XMClib CAN driver.
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* by the XMClib CAN driver.
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*/
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*/
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@ -108,11 +111,15 @@ void CanInit(void)
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while (canModuleFreqHz < 12000000)
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while (canModuleFreqHz < 12000000)
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{
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{
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canModuleFreqHz *= 2;
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canModuleFreqHz *= 2;
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/* keep the watchdog happy */
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CopService();
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}
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}
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/* decrease if too high */
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/* decrease if too high */
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while (canModuleFreqHz > 120000000)
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while (canModuleFreqHz > 120000000)
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{
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{
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canModuleFreqHz /= 2;
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canModuleFreqHz /= 2;
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/* keep the watchdog happy */
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CopService();
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}
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}
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/* configure CAN module*/
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/* configure CAN module*/
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void CanTransmitPacket(blt_int8u *data, blt_int8u len)
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void CanTransmitPacket(blt_int8u *data, blt_int8u len)
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{
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{
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blt_int8u byteIdx;
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blt_int8u byteIdx;
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blt_int32u timeout;
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/* copy message data */
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/* copy message data */
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transmitMsgObj.can_data_length = len;
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transmitMsgObj.can_data_length = len;
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XMC_CAN_MO_ResetStatus(&transmitMsgObj, XMC_CAN_MO_RESET_STATUS_TX_PENDING);
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XMC_CAN_MO_ResetStatus(&transmitMsgObj, XMC_CAN_MO_RESET_STATUS_TX_PENDING);
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/* submit message for transmission */
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/* submit message for transmission */
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XMC_CAN_MO_Transmit(&transmitMsgObj);
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XMC_CAN_MO_Transmit(&transmitMsgObj);
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/* set timeout time to wait for transmission completion */
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timeout = TimerGet() + CAN_MSG_TX_TIMEOUT_MS;
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/* wait for transmit completion */
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/* wait for transmit completion */
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while ((XMC_CAN_MO_GetStatus(&transmitMsgObj) & XMC_CAN_MO_STATUS_TX_PENDING) != 0)
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while ((XMC_CAN_MO_GetStatus(&transmitMsgObj) & XMC_CAN_MO_STATUS_TX_PENDING) != 0)
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{
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{
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/* keep the watchdog happy */
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/* keep the watchdog happy */
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CopService();
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CopService();
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/* break loop upon timeout. this would indicate a hardware failure or no other
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* nodes connected to the bus.
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*/
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if (TimerGet() > timeout)
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{
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break;
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}
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}
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}
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} /*** end of CanTransmitPacket ***/
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} /*** end of CanTransmitPacket ***/
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@ -42,6 +42,9 @@
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*/
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*/
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#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
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#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
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/** \brief Timeout for transmitting a byte in milliseconds. */
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#define UART_BYTE_TX_TIMEOUT_MS (10u)
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/** \brief Macro for accessing the UART channel handle in the format that is expected
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/** \brief Macro for accessing the UART channel handle in the format that is expected
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* by the XMClib UART driver.
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* by the XMClib UART driver.
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*/
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*/
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@ -230,6 +233,9 @@ static blt_bool UartReceiveByte(blt_int8u *data)
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****************************************************************************************/
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****************************************************************************************/
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static blt_bool UartTransmitByte(blt_int8u data)
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static blt_bool UartTransmitByte(blt_int8u data)
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{
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{
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blt_int32u timeout;
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blt_bool result = BLT_TRUE;
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/* check if tx fifo can accept new data */
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/* check if tx fifo can accept new data */
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if (XMC_USIC_CH_TXFIFO_IsFull(UART_CHANNEL) != 0)
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if (XMC_USIC_CH_TXFIFO_IsFull(UART_CHANNEL) != 0)
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{
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{
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@ -238,15 +244,24 @@ static blt_bool UartTransmitByte(blt_int8u data)
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}
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}
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/* submit data for transmission */
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/* submit data for transmission */
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XMC_UART_CH_Transmit(UART_CHANNEL, data);
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XMC_UART_CH_Transmit(UART_CHANNEL, data);
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/* set timeout time to wait for transmit completion. */
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timeout = TimerGet() + UART_BYTE_TX_TIMEOUT_MS;
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/* wait for transmission to be done */
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/* wait for transmission to be done */
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while( (XMC_USIC_CH_TXFIFO_GetEvent(UART_CHANNEL) & XMC_USIC_CH_TXFIFO_EVENT_STANDARD) == 0)
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while( (XMC_USIC_CH_TXFIFO_GetEvent(UART_CHANNEL) & XMC_USIC_CH_TXFIFO_EVENT_STANDARD) == 0)
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{
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{
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;
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/* keep the watchdog happy */
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CopService();
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/* break loop upon timeout. this would indicate a hardware failure. */
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if (TimerGet() > timeout)
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{
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result = BLT_FALSE;
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break;
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}
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}
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}
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/* reset event */
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/* reset event */
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XMC_USIC_CH_TXFIFO_ClearEvent(UART_CHANNEL, XMC_USIC_CH_TXFIFO_EVENT_STANDARD);
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XMC_USIC_CH_TXFIFO_ClearEvent(UART_CHANNEL, XMC_USIC_CH_TXFIFO_EVENT_STANDARD);
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/* byte transmitted */
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/* give the result back to the caller */
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return BLT_TRUE;
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return result;
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} /*** end of UartTransmitByte ***/
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} /*** end of UartTransmitByte ***/
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#endif /* BOOT_COM_UART_ENABLE > 0 */
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#endif /* BOOT_COM_UART_ENABLE > 0 */
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@ -44,6 +44,8 @@
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* reception of the first packet byte.
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* reception of the first packet byte.
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*/
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*/
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#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
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#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
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/** \brief Timeout for transmitting a byte in milliseconds. */
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#define UART_BYTE_TX_TIMEOUT_MS (10u)
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/****************************************************************************************
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/****************************************************************************************
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@ -223,6 +225,9 @@ static blt_bool UartReceiveByte(blt_int8u *data)
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****************************************************************************************/
|
****************************************************************************************/
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static blt_bool UartTransmitByte(blt_int8u data)
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static blt_bool UartTransmitByte(blt_int8u data)
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{
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{
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blt_int32u timeout;
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blt_bool result = BLT_TRUE;
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/* check if tx holding register can accept new data */
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/* check if tx holding register can accept new data */
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if ((LEUART1->STATUS & LEUART_STATUS_TXBL) == 0)
|
if ((LEUART1->STATUS & LEUART_STATUS_TXBL) == 0)
|
||||||
{
|
{
|
||||||
|
@ -236,9 +241,15 @@ static blt_bool UartTransmitByte(blt_int8u data)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
result = BLT_FALSE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* byte transmitted */
|
/* give the result back to the caller */
|
||||||
return BLT_TRUE;
|
return result;
|
||||||
} /*** end of UartTransmitByte ***/
|
} /*** end of UartTransmitByte ***/
|
||||||
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
|
@ -43,6 +43,8 @@
|
||||||
/****************************************************************************************
|
/****************************************************************************************
|
||||||
* Macro definitions
|
* Macro definitions
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
|
/** \brief Timeout for transmitting a CAN message in milliseconds. */
|
||||||
|
#define CAN_MSG_TX_TIMEOUT_MS (50u)
|
||||||
/** \brief Index of the used reception message object. */
|
/** \brief Index of the used reception message object. */
|
||||||
#define CAN_RX_MSGOBJECT_IDX (0)
|
#define CAN_RX_MSGOBJECT_IDX (0)
|
||||||
/** \brief Index of the used transmission message object. */
|
/** \brief Index of the used transmission message object. */
|
||||||
|
@ -167,6 +169,7 @@ void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||||
{
|
{
|
||||||
blt_int32u status;
|
blt_int32u status;
|
||||||
tCANMsgObject msgObject;
|
tCANMsgObject msgObject;
|
||||||
|
blt_int32u timeout;
|
||||||
|
|
||||||
/* get bitmask of message objects that are busy transmitting messages */
|
/* get bitmask of message objects that are busy transmitting messages */
|
||||||
status = CANStatusGet(CAN0_BASE, CAN_STS_TXREQUEST);
|
status = CANStatusGet(CAN0_BASE, CAN_STS_TXREQUEST);
|
||||||
|
@ -184,12 +187,21 @@ void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||||
msgObject.ulMsgLen = len;
|
msgObject.ulMsgLen = len;
|
||||||
msgObject.pucMsgData = data;
|
msgObject.pucMsgData = data;
|
||||||
CANMessageSet(CAN0_BASE, CAN_TX_MSGOBJECT_IDX+1, &msgObject, MSG_OBJ_TYPE_TX);
|
CANMessageSet(CAN0_BASE, CAN_TX_MSGOBJECT_IDX+1, &msgObject, MSG_OBJ_TYPE_TX);
|
||||||
|
/* set timeout time to wait for transmission completion */
|
||||||
|
timeout = TimerGet() + CAN_MSG_TX_TIMEOUT_MS;
|
||||||
/* now wait for the transmission to complete */
|
/* now wait for the transmission to complete */
|
||||||
do
|
do
|
||||||
{
|
{
|
||||||
status = CANStatusGet(CAN0_BASE, CAN_STS_TXREQUEST);
|
status = CANStatusGet(CAN0_BASE, CAN_STS_TXREQUEST);
|
||||||
/* service the watchdog */
|
/* service the watchdog */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure or no other
|
||||||
|
* nodes connected to the bus.
|
||||||
|
*/
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
while ((status & canBitNum2Mask[CAN_TX_MSGOBJECT_IDX]) != 0);
|
while ((status & canBitNum2Mask[CAN_TX_MSGOBJECT_IDX]) != 0);
|
||||||
} /*** end of CanTransmitPacket ***/
|
} /*** end of CanTransmitPacket ***/
|
||||||
|
|
|
@ -46,6 +46,8 @@
|
||||||
* reception of the first packet byte.
|
* reception of the first packet byte.
|
||||||
*/
|
*/
|
||||||
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
||||||
|
/** \brief Timeout for transmitting a byte in milliseconds. */
|
||||||
|
#define UART_BYTE_TX_TIMEOUT_MS (10u)
|
||||||
|
|
||||||
|
|
||||||
/****************************************************************************************
|
/****************************************************************************************
|
||||||
|
@ -209,20 +211,31 @@ static blt_bool UartReceiveByte(blt_int8u *data)
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
static blt_bool UartTransmitByte(blt_int8u data)
|
static blt_bool UartTransmitByte(blt_int8u data)
|
||||||
{
|
{
|
||||||
|
blt_int32u timeout;
|
||||||
|
blt_bool result = BLT_TRUE;
|
||||||
|
|
||||||
/* write byte to transmit holding register */
|
/* write byte to transmit holding register */
|
||||||
if (UARTCharPutNonBlocking(UART0_BASE, data) == false)
|
if (UARTCharPutNonBlocking(UART0_BASE, data) == false)
|
||||||
{
|
{
|
||||||
/* tx holding register can accept new data */
|
/* tx holding register can accept new data */
|
||||||
return BLT_FALSE;
|
return BLT_FALSE;
|
||||||
}
|
}
|
||||||
|
/* set timeout time to wait for transmit completion. */
|
||||||
|
timeout = TimerGet() + UART_BYTE_TX_TIMEOUT_MS;
|
||||||
/* wait for tx holding register to be empty */
|
/* wait for tx holding register to be empty */
|
||||||
while (UARTSpaceAvail(UART0_BASE) == false)
|
while (UARTSpaceAvail(UART0_BASE) == false)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
result = BLT_FALSE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* byte transmitted */
|
/* give the result back to the caller */
|
||||||
return BLT_TRUE;
|
return result;
|
||||||
} /*** end of UartTransmitByte ***/
|
} /*** end of UartTransmitByte ***/
|
||||||
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
|
@ -34,6 +34,16 @@
|
||||||
|
|
||||||
|
|
||||||
#if (BOOT_COM_CAN_ENABLE > 0)
|
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||||
|
/****************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
****************************************************************************************/
|
||||||
|
/** \brief Timeout for entering/leaving CAN initialization mode in milliseconds. */
|
||||||
|
#define CAN_INIT_TIMEOUT_MS (250u)
|
||||||
|
|
||||||
|
/** \brief Timeout for transmitting a CAN message in milliseconds. */
|
||||||
|
#define CAN_MSG_TX_TIMEOUT_MS (50u)
|
||||||
|
|
||||||
|
|
||||||
/****************************************************************************************
|
/****************************************************************************************
|
||||||
* Type definitions
|
* Type definitions
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
|
@ -218,6 +228,7 @@ void CanInit(void)
|
||||||
blt_int16u prescaler;
|
blt_int16u prescaler;
|
||||||
blt_int8u tseg1, tseg2;
|
blt_int8u tseg1, tseg2;
|
||||||
blt_bool result;
|
blt_bool result;
|
||||||
|
blt_int32u timeout;
|
||||||
|
|
||||||
/* the current implementation supports CAN1. throw an assertion error in case a
|
/* the current implementation supports CAN1. throw an assertion error in case a
|
||||||
* different CAN channel is configured.
|
* different CAN channel is configured.
|
||||||
|
@ -230,21 +241,35 @@ void CanInit(void)
|
||||||
CANx->IER = (blt_int32u)0;
|
CANx->IER = (blt_int32u)0;
|
||||||
/* set request to reset the can controller */
|
/* set request to reset the can controller */
|
||||||
CANx->MCR |= CAN_BIT_RESET ;
|
CANx->MCR |= CAN_BIT_RESET ;
|
||||||
|
/* set timeout time to wait for can controller reset */
|
||||||
|
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
|
||||||
/* wait for acknowledge that the can controller was reset */
|
/* wait for acknowledge that the can controller was reset */
|
||||||
while ((CANx->MCR & CAN_BIT_RESET) != 0)
|
while ((CANx->MCR & CAN_BIT_RESET) != 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* exit from sleep mode, which is the default mode after reset */
|
/* exit from sleep mode, which is the default mode after reset */
|
||||||
CANx->MCR &= ~CAN_BIT_SLEEP;
|
CANx->MCR &= ~CAN_BIT_SLEEP;
|
||||||
/* set request to enter initialisation mode */
|
/* set request to enter initialisation mode */
|
||||||
CANx->MCR |= CAN_BIT_INRQ ;
|
CANx->MCR |= CAN_BIT_INRQ ;
|
||||||
|
/* set timeout time to wait for entering initialization mode */
|
||||||
|
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
|
||||||
/* wait for acknowledge that initialization mode was entered */
|
/* wait for acknowledge that initialization mode was entered */
|
||||||
while ((CANx->MSR & CAN_BIT_INAK) == 0)
|
while ((CANx->MSR & CAN_BIT_INAK) == 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* configure the bittming */
|
/* configure the bittming */
|
||||||
CANx->BTR = (blt_int32u)((blt_int32u)(tseg1 - 1) << 16) | \
|
CANx->BTR = (blt_int32u)((blt_int32u)(tseg1 - 1) << 16) | \
|
||||||
|
@ -252,11 +277,18 @@ void CanInit(void)
|
||||||
(blt_int32u)(prescaler - 1);
|
(blt_int32u)(prescaler - 1);
|
||||||
/* set request to leave initialisation mode */
|
/* set request to leave initialisation mode */
|
||||||
CANx->MCR &= ~CAN_BIT_INRQ;
|
CANx->MCR &= ~CAN_BIT_INRQ;
|
||||||
|
/* set timeout time to wait for exiting initialization mode */
|
||||||
|
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
|
||||||
/* wait for acknowledge that initialization mode was exited */
|
/* wait for acknowledge that initialization mode was exited */
|
||||||
while ((CANx->MSR & CAN_BIT_INAK) != 0)
|
while ((CANx->MSR & CAN_BIT_INAK) != 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* enter initialisation mode for the acceptance filter */
|
/* enter initialisation mode for the acceptance filter */
|
||||||
CANx->FMR |= CAN_BIT_FINIT;
|
CANx->FMR |= CAN_BIT_FINIT;
|
||||||
|
@ -288,6 +320,7 @@ void CanInit(void)
|
||||||
void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||||
{
|
{
|
||||||
blt_int32u txMsgId = BOOT_COM_CAN_TX_MSG_ID;
|
blt_int32u txMsgId = BOOT_COM_CAN_TX_MSG_ID;
|
||||||
|
blt_int32u timeout;
|
||||||
|
|
||||||
/* make sure that transmit mailbox 0 is available */
|
/* make sure that transmit mailbox 0 is available */
|
||||||
ASSERT_RT((CANx->TSR&CAN_BIT_TME0) == CAN_BIT_TME0);
|
ASSERT_RT((CANx->TSR&CAN_BIT_TME0) == CAN_BIT_TME0);
|
||||||
|
@ -322,11 +355,20 @@ void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||||
((blt_int32u)data[4]));
|
((blt_int32u)data[4]));
|
||||||
/* request the start of message transmission */
|
/* request the start of message transmission */
|
||||||
CANx->sTxMailBox[0].TIR |= CAN_BIT_TXRQ;
|
CANx->sTxMailBox[0].TIR |= CAN_BIT_TXRQ;
|
||||||
|
/* set timeout time to wait for transmission completion */
|
||||||
|
timeout = TimerGet() + CAN_MSG_TX_TIMEOUT_MS;
|
||||||
/* wait for transmit completion */
|
/* wait for transmit completion */
|
||||||
while ((CANx->TSR&CAN_BIT_TME0) == 0)
|
while ((CANx->TSR&CAN_BIT_TME0) == 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure or no other
|
||||||
|
* nodes connected to the bus.
|
||||||
|
*/
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
} /*** end of CanTransmitPacket ***/
|
} /*** end of CanTransmitPacket ***/
|
||||||
|
|
||||||
|
|
|
@ -66,6 +66,17 @@
|
||||||
#define BOOT_FLASH_VECTOR_TABLE_CS_OFFSET (0x150)
|
#define BOOT_FLASH_VECTOR_TABLE_CS_OFFSET (0x150)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/** \brief Maximum time for a sector erase operation as specified by the STM32F1 data-
|
||||||
|
* sheet with an added margin of at least 20%.
|
||||||
|
*/
|
||||||
|
#define FLASH_ERASE_TIME_MAX_MS (100)
|
||||||
|
|
||||||
|
/** \brief Maximum time for a page program operation as specified by the STM32F1 data-
|
||||||
|
* sheet with an added margin of at least 20%.
|
||||||
|
*/
|
||||||
|
#define FLASH_PROGRAM_TIME_MAX_MS (5)
|
||||||
|
|
||||||
|
|
||||||
#define FLASH_KEY1 ((blt_int32u)0x45670123)
|
#define FLASH_KEY1 ((blt_int32u)0x45670123)
|
||||||
#define FLASH_KEY2 ((blt_int32u)0xCDEF89AB)
|
#define FLASH_KEY2 ((blt_int32u)0xCDEF89AB)
|
||||||
#define FLASH_LOCK_BIT ((blt_int32u)0x00000080)
|
#define FLASH_LOCK_BIT ((blt_int32u)0x00000080)
|
||||||
|
@ -669,6 +680,7 @@ static blt_bool FlashWriteBlock(tFlashBlockInfo *block)
|
||||||
blt_addr prog_addr;
|
blt_addr prog_addr;
|
||||||
blt_int32u prog_data;
|
blt_int32u prog_data;
|
||||||
blt_int32u word_cnt;
|
blt_int32u word_cnt;
|
||||||
|
blt_int32u timeout;
|
||||||
|
|
||||||
/* check that address is actually within flash */
|
/* check that address is actually within flash */
|
||||||
sector_num = FlashGetSector(block->base_addr);
|
sector_num = FlashGetSector(block->base_addr);
|
||||||
|
@ -712,19 +724,35 @@ static blt_bool FlashWriteBlock(tFlashBlockInfo *block)
|
||||||
prog_data = *(volatile blt_int32u *)(&block->data[word_cnt * sizeof(blt_int32u)]);
|
prog_data = *(volatile blt_int32u *)(&block->data[word_cnt * sizeof(blt_int32u)]);
|
||||||
/* program the first half word */
|
/* program the first half word */
|
||||||
*(volatile blt_int16u *)prog_addr = (blt_int16u)prog_data;
|
*(volatile blt_int16u *)prog_addr = (blt_int16u)prog_data;
|
||||||
|
/* set the timeout time for the program operation */
|
||||||
|
timeout = TimerGet() + FLASH_PROGRAM_TIME_MAX_MS;
|
||||||
/* wait for the program operation to complete */
|
/* wait for the program operation to complete */
|
||||||
while ((FLASH->SR & FLASH_BSY_BIT) == FLASH_BSY_BIT)
|
while ((FLASH->SR & FLASH_BSY_BIT) == FLASH_BSY_BIT)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* check for timeout */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
result = BLT_FALSE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* program the second half word */
|
/* program the second half word */
|
||||||
*(volatile blt_int16u *)(prog_addr+2) = (blt_int16u)(prog_data >> 16);
|
*(volatile blt_int16u *)(prog_addr+2) = (blt_int16u)(prog_data >> 16);
|
||||||
|
/* set the timeout time for the program operation */
|
||||||
|
timeout = TimerGet() + FLASH_PROGRAM_TIME_MAX_MS;
|
||||||
/* wait for the program operation to complete */
|
/* wait for the program operation to complete */
|
||||||
while ((FLASH->SR & FLASH_BSY_BIT) == FLASH_BSY_BIT)
|
while ((FLASH->SR & FLASH_BSY_BIT) == FLASH_BSY_BIT)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* check for timeout */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
result = BLT_FALSE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* verify that the written data is actually there */
|
/* verify that the written data is actually there */
|
||||||
if (*(volatile blt_int32u *)prog_addr != prog_data)
|
if (*(volatile blt_int32u *)prog_addr != prog_data)
|
||||||
|
@ -737,7 +765,7 @@ static blt_bool FlashWriteBlock(tFlashBlockInfo *block)
|
||||||
FLASH->CR &= ~FLASH_PG_BIT;
|
FLASH->CR &= ~FLASH_PG_BIT;
|
||||||
/* lock the flash array */
|
/* lock the flash array */
|
||||||
FlashLock();
|
FlashLock();
|
||||||
/* still here so all is okay */
|
/* give the result back to the caller */
|
||||||
return result;
|
return result;
|
||||||
} /*** end of FlashWriteBlock ***/
|
} /*** end of FlashWriteBlock ***/
|
||||||
|
|
||||||
|
@ -755,6 +783,8 @@ static blt_bool FlashEraseSectors(blt_int8u first_sector, blt_int8u last_sector)
|
||||||
blt_int16u block_cnt;
|
blt_int16u block_cnt;
|
||||||
blt_addr start_addr;
|
blt_addr start_addr;
|
||||||
blt_addr end_addr;
|
blt_addr end_addr;
|
||||||
|
blt_int32u timeout;
|
||||||
|
blt_bool result = BLT_TRUE;
|
||||||
|
|
||||||
/* validate the sector numbers */
|
/* validate the sector numbers */
|
||||||
if (first_sector > last_sector)
|
if (first_sector > last_sector)
|
||||||
|
@ -791,19 +821,27 @@ static blt_bool FlashEraseSectors(blt_int8u first_sector, blt_int8u last_sector)
|
||||||
FLASH->AR = start_addr + (block_cnt * FLASH_ERASE_BLOCK_SIZE);
|
FLASH->AR = start_addr + (block_cnt * FLASH_ERASE_BLOCK_SIZE);
|
||||||
/* start the block erase operation */
|
/* start the block erase operation */
|
||||||
FLASH->CR |= FLASH_STRT_BIT;
|
FLASH->CR |= FLASH_STRT_BIT;
|
||||||
|
/* set the timeout time for the erase operation */
|
||||||
|
timeout = TimerGet() + FLASH_ERASE_TIME_MAX_MS;
|
||||||
/* wait for the erase operation to complete */
|
/* wait for the erase operation to complete */
|
||||||
while ((FLASH->SR & FLASH_BSY_BIT) == FLASH_BSY_BIT)
|
while ((FLASH->SR & FLASH_BSY_BIT) == FLASH_BSY_BIT)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* check for timeout */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
result = BLT_FALSE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
/* reset the page erase bit because we're all done erasing */
|
/* reset the page erase bit because we're all done erasing */
|
||||||
FLASH->CR &= ~FLASH_PER_BIT;
|
FLASH->CR &= ~FLASH_PER_BIT;
|
||||||
/* lock the flash array */
|
/* lock the flash array */
|
||||||
FlashLock();
|
FlashLock();
|
||||||
/* still here so all went okay */
|
/* give the result back to the caller */
|
||||||
return BLT_TRUE;
|
return result;
|
||||||
} /*** end of FlashEraseSectors ***/
|
} /*** end of FlashEraseSectors ***/
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -63,6 +63,8 @@ typedef struct
|
||||||
* reception of the first packet byte.
|
* reception of the first packet byte.
|
||||||
*/
|
*/
|
||||||
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
||||||
|
/** \brief Timeout for transmitting a byte in milliseconds. */
|
||||||
|
#define UART_BYTE_TX_TIMEOUT_MS (10u)
|
||||||
/** \brief USART enable bit. */
|
/** \brief USART enable bit. */
|
||||||
#define UART_BIT_UE ((blt_int16u)0x2000)
|
#define UART_BIT_UE ((blt_int16u)0x2000)
|
||||||
/** \brief Transmitter enable bit. */
|
/** \brief Transmitter enable bit. */
|
||||||
|
@ -255,6 +257,9 @@ static blt_bool UartReceiveByte(blt_int8u *data)
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
static blt_bool UartTransmitByte(blt_int8u data)
|
static blt_bool UartTransmitByte(blt_int8u data)
|
||||||
{
|
{
|
||||||
|
blt_int32u timeout;
|
||||||
|
blt_bool result = BLT_TRUE;
|
||||||
|
|
||||||
/* check if tx holding register can accept new data */
|
/* check if tx holding register can accept new data */
|
||||||
if ((UARTx->SR & UART_BIT_TXE) == 0)
|
if ((UARTx->SR & UART_BIT_TXE) == 0)
|
||||||
{
|
{
|
||||||
|
@ -263,14 +268,22 @@ static blt_bool UartTransmitByte(blt_int8u data)
|
||||||
}
|
}
|
||||||
/* write byte to transmit holding register */
|
/* write byte to transmit holding register */
|
||||||
UARTx->DR = data;
|
UARTx->DR = data;
|
||||||
|
/* set timeout time to wait for transmit completion. */
|
||||||
|
timeout = TimerGet() + UART_BYTE_TX_TIMEOUT_MS;
|
||||||
/* wait for tx holding register to be empty */
|
/* wait for tx holding register to be empty */
|
||||||
while ((UARTx->SR & UART_BIT_TXE) == 0)
|
while ((UARTx->SR & UART_BIT_TXE) == 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
result = BLT_FALSE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* byte transmitted */
|
/* give the result back to the caller */
|
||||||
return BLT_TRUE;
|
return result;
|
||||||
} /*** end of UartTransmitByte ***/
|
} /*** end of UartTransmitByte ***/
|
||||||
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
|
@ -34,6 +34,16 @@
|
||||||
|
|
||||||
|
|
||||||
#if (BOOT_COM_CAN_ENABLE > 0)
|
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||||
|
/****************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
****************************************************************************************/
|
||||||
|
/** \brief Timeout for entering/leaving CAN initialization mode in milliseconds. */
|
||||||
|
#define CAN_INIT_TIMEOUT_MS (250u)
|
||||||
|
|
||||||
|
/** \brief Timeout for transmitting a CAN message in milliseconds. */
|
||||||
|
#define CAN_MSG_TX_TIMEOUT_MS (50u)
|
||||||
|
|
||||||
|
|
||||||
/****************************************************************************************
|
/****************************************************************************************
|
||||||
* Type definitions
|
* Type definitions
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
|
@ -227,6 +237,7 @@ void CanInit(void)
|
||||||
blt_int16u prescaler=0;
|
blt_int16u prescaler=0;
|
||||||
blt_int8u tseg1=0, tseg2=0;
|
blt_int8u tseg1=0, tseg2=0;
|
||||||
blt_bool result;
|
blt_bool result;
|
||||||
|
blt_int32u timeout;
|
||||||
|
|
||||||
/* the current implementation supports CAN1 and 2. throw an assertion error in case a
|
/* the current implementation supports CAN1 and 2. throw an assertion error in case a
|
||||||
* different CAN channel is configured.
|
* different CAN channel is configured.
|
||||||
|
@ -240,21 +251,35 @@ void CanInit(void)
|
||||||
CANx->IER = (blt_int32u)0;
|
CANx->IER = (blt_int32u)0;
|
||||||
/* set request to reset the can controller */
|
/* set request to reset the can controller */
|
||||||
CANx->MCR |= CAN_BIT_RESET ;
|
CANx->MCR |= CAN_BIT_RESET ;
|
||||||
|
/* set timeout time to wait for can controller reset */
|
||||||
|
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
|
||||||
/* wait for acknowledge that the can controller was reset */
|
/* wait for acknowledge that the can controller was reset */
|
||||||
while ((CANx->MCR & CAN_BIT_RESET) != 0)
|
while ((CANx->MCR & CAN_BIT_RESET) != 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* exit from sleep mode, which is the default mode after reset */
|
/* exit from sleep mode, which is the default mode after reset */
|
||||||
CANx->MCR &= ~CAN_BIT_SLEEP;
|
CANx->MCR &= ~CAN_BIT_SLEEP;
|
||||||
/* set request to enter initialisation mode */
|
/* set request to enter initialisation mode */
|
||||||
CANx->MCR |= CAN_BIT_INRQ ;
|
CANx->MCR |= CAN_BIT_INRQ ;
|
||||||
|
/* set timeout time to wait for entering initialization mode */
|
||||||
|
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
|
||||||
/* wait for acknowledge that initialization mode was entered */
|
/* wait for acknowledge that initialization mode was entered */
|
||||||
while ((CANx->MSR & CAN_BIT_INAK) == 0)
|
while ((CANx->MSR & CAN_BIT_INAK) == 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* configure the bittming */
|
/* configure the bittming */
|
||||||
CANx->BTR = (blt_int32u)((blt_int32u)(tseg1 - 1) << 16) | \
|
CANx->BTR = (blt_int32u)((blt_int32u)(tseg1 - 1) << 16) | \
|
||||||
|
@ -262,11 +287,18 @@ void CanInit(void)
|
||||||
(blt_int32u)(prescaler - 1);
|
(blt_int32u)(prescaler - 1);
|
||||||
/* set request to leave initialisation mode */
|
/* set request to leave initialisation mode */
|
||||||
CANx->MCR &= ~CAN_BIT_INRQ;
|
CANx->MCR &= ~CAN_BIT_INRQ;
|
||||||
|
/* set timeout time to wait for exiting initialization mode */
|
||||||
|
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
|
||||||
/* wait for acknowledge that initialization mode was exited */
|
/* wait for acknowledge that initialization mode was exited */
|
||||||
while ((CANx->MSR & CAN_BIT_INAK) != 0)
|
while ((CANx->MSR & CAN_BIT_INAK) != 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#if (BOOT_COM_CAN_CHANNEL_INDEX == 0)
|
#if (BOOT_COM_CAN_CHANNEL_INDEX == 0)
|
||||||
|
@ -319,6 +351,7 @@ void CanInit(void)
|
||||||
void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||||
{
|
{
|
||||||
blt_int32u txMsgId = BOOT_COM_CAN_TX_MSG_ID;
|
blt_int32u txMsgId = BOOT_COM_CAN_TX_MSG_ID;
|
||||||
|
blt_int32u timeout;
|
||||||
|
|
||||||
/* make sure that transmit mailbox 0 is available */
|
/* make sure that transmit mailbox 0 is available */
|
||||||
ASSERT_RT((CANx->TSR&CAN_BIT_TME0) == CAN_BIT_TME0);
|
ASSERT_RT((CANx->TSR&CAN_BIT_TME0) == CAN_BIT_TME0);
|
||||||
|
@ -353,11 +386,20 @@ void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||||
((blt_int32u)data[4]));
|
((blt_int32u)data[4]));
|
||||||
/* request the start of message transmission */
|
/* request the start of message transmission */
|
||||||
CANx->sTxMailBox[0].TIR |= CAN_BIT_TXRQ;
|
CANx->sTxMailBox[0].TIR |= CAN_BIT_TXRQ;
|
||||||
|
/* set timeout time to wait for transmission completion */
|
||||||
|
timeout = TimerGet() + CAN_MSG_TX_TIMEOUT_MS;
|
||||||
/* wait for transmit completion */
|
/* wait for transmit completion */
|
||||||
while ((CANx->TSR&CAN_BIT_TME0) == 0)
|
while ((CANx->TSR&CAN_BIT_TME0) == 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure or no other
|
||||||
|
* nodes connected to the bus.
|
||||||
|
*/
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
} /*** end of CanTransmitPacket ***/
|
} /*** end of CanTransmitPacket ***/
|
||||||
|
|
||||||
|
|
|
@ -41,6 +41,8 @@
|
||||||
* reception of the first packet byte.
|
* reception of the first packet byte.
|
||||||
*/
|
*/
|
||||||
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
||||||
|
/** \brief Timeout for transmitting a byte in milliseconds. */
|
||||||
|
#define UART_BYTE_TX_TIMEOUT_MS (10u)
|
||||||
/* map the configured UART channel index to the STM32's USART peripheral */
|
/* map the configured UART channel index to the STM32's USART peripheral */
|
||||||
#if (BOOT_COM_UART_CHANNEL_INDEX == 0)
|
#if (BOOT_COM_UART_CHANNEL_INDEX == 0)
|
||||||
/** \brief Set UART base address to USART1. */
|
/** \brief Set UART base address to USART1. */
|
||||||
|
@ -231,6 +233,9 @@ static blt_bool UartReceiveByte(blt_int8u *data)
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
static blt_bool UartTransmitByte(blt_int8u data)
|
static blt_bool UartTransmitByte(blt_int8u data)
|
||||||
{
|
{
|
||||||
|
blt_int32u timeout;
|
||||||
|
blt_bool result = BLT_TRUE;
|
||||||
|
|
||||||
/* check if tx holding register can accept new data */
|
/* check if tx holding register can accept new data */
|
||||||
if (USART_GetFlagStatus(USART_CHANNEL, USART_FLAG_TXE) == RESET)
|
if (USART_GetFlagStatus(USART_CHANNEL, USART_FLAG_TXE) == RESET)
|
||||||
{
|
{
|
||||||
|
@ -239,13 +244,22 @@ static blt_bool UartTransmitByte(blt_int8u data)
|
||||||
}
|
}
|
||||||
/* write byte to transmit holding register */
|
/* write byte to transmit holding register */
|
||||||
USART_SendData(USART_CHANNEL, data);
|
USART_SendData(USART_CHANNEL, data);
|
||||||
|
/* set timeout time to wait for transmit completion. */
|
||||||
|
timeout = TimerGet() + UART_BYTE_TX_TIMEOUT_MS;
|
||||||
/* wait for tx holding register to be empty */
|
/* wait for tx holding register to be empty */
|
||||||
while (USART_GetFlagStatus(USART_CHANNEL, USART_FLAG_TXE) == RESET)
|
while (USART_GetFlagStatus(USART_CHANNEL, USART_FLAG_TXE) == RESET)
|
||||||
{
|
{
|
||||||
;
|
/* keep the watchdog happy */
|
||||||
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
result = BLT_FALSE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* byte transmitted */
|
/* give the result back to the caller */
|
||||||
return BLT_TRUE;
|
return result;
|
||||||
} /*** end of UartTransmitByte ***/
|
} /*** end of UartTransmitByte ***/
|
||||||
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
|
@ -42,8 +42,8 @@
|
||||||
* reception of the first packet byte.
|
* reception of the first packet byte.
|
||||||
*/
|
*/
|
||||||
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
||||||
/** \brief Timeout for transmitting a byte. */
|
/** \brief Timeout for transmitting a byte in milliseconds. */
|
||||||
#define UART_TX_TIMEOUT_MS (5u)
|
#define UART_BYTE_TX_TIMEOUT_MS (10u)
|
||||||
/* map the configured UART channel index to the STM32's USART peripheral */
|
/* map the configured UART channel index to the STM32's USART peripheral */
|
||||||
#if (BOOT_COM_UART_CHANNEL_INDEX == 0)
|
#if (BOOT_COM_UART_CHANNEL_INDEX == 0)
|
||||||
/** \brief Set UART base address to USART1. */
|
/** \brief Set UART base address to USART1. */
|
||||||
|
@ -220,19 +220,20 @@ static blt_bool UartReceiveByte(blt_int8u *data)
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
static void UartTransmitByte(blt_int8u data)
|
static void UartTransmitByte(blt_int8u data)
|
||||||
{
|
{
|
||||||
blt_int32u txTimeoutTime;
|
blt_int32u timeout;
|
||||||
|
|
||||||
/* Determine timeout time for the transmit operation. */
|
|
||||||
txTimeoutTime = TimerGet() + UART_TX_TIMEOUT_MS;
|
|
||||||
/* write byte to transmit holding register */
|
/* write byte to transmit holding register */
|
||||||
LL_USART_TransmitData8(USART_CHANNEL, data);
|
LL_USART_TransmitData8(USART_CHANNEL, data);
|
||||||
|
/* set timeout time to wait for transmit completion. */
|
||||||
|
timeout = TimerGet() + UART_BYTE_TX_TIMEOUT_MS;
|
||||||
/* wait for tx holding register to be empty */
|
/* wait for tx holding register to be empty */
|
||||||
while (LL_USART_IsActiveFlag_TXE(USART_CHANNEL) == 0)
|
while (LL_USART_IsActiveFlag_TXE(USART_CHANNEL) == 0)
|
||||||
{
|
{
|
||||||
/* Check if a timeout occurred to prevent lockup. */
|
/* keep the watchdog happy */
|
||||||
if (TimerGet() > txTimeoutTime)
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
{
|
{
|
||||||
/* Cannot transmit so stop waiting for its completion. */
|
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -34,6 +34,16 @@
|
||||||
|
|
||||||
|
|
||||||
#if (BOOT_COM_CAN_ENABLE > 0)
|
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||||
|
/****************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
****************************************************************************************/
|
||||||
|
/** \brief Timeout for entering/leaving CAN initialization mode in milliseconds. */
|
||||||
|
#define CAN_INIT_TIMEOUT_MS (250u)
|
||||||
|
|
||||||
|
/** \brief Timeout for transmitting a CAN message in milliseconds. */
|
||||||
|
#define CAN_MSG_TX_TIMEOUT_MS (50u)
|
||||||
|
|
||||||
|
|
||||||
/****************************************************************************************
|
/****************************************************************************************
|
||||||
* Type definitions
|
* Type definitions
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
|
@ -227,6 +237,7 @@ void CanInit(void)
|
||||||
blt_int16u prescaler;
|
blt_int16u prescaler;
|
||||||
blt_int8u tseg1, tseg2;
|
blt_int8u tseg1, tseg2;
|
||||||
blt_bool result;
|
blt_bool result;
|
||||||
|
blt_int32u timeout;
|
||||||
|
|
||||||
/* the current implementation supports CAN1 and 2. throw an assertion error in case a
|
/* the current implementation supports CAN1 and 2. throw an assertion error in case a
|
||||||
* different CAN channel is configured.
|
* different CAN channel is configured.
|
||||||
|
@ -240,21 +251,35 @@ void CanInit(void)
|
||||||
CANx->IER = (blt_int32u)0;
|
CANx->IER = (blt_int32u)0;
|
||||||
/* set request to reset the can controller */
|
/* set request to reset the can controller */
|
||||||
CANx->MCR |= CAN_BIT_RESET ;
|
CANx->MCR |= CAN_BIT_RESET ;
|
||||||
|
/* set timeout time to wait for can controller reset */
|
||||||
|
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
|
||||||
/* wait for acknowledge that the can controller was reset */
|
/* wait for acknowledge that the can controller was reset */
|
||||||
while ((CANx->MCR & CAN_BIT_RESET) != 0)
|
while ((CANx->MCR & CAN_BIT_RESET) != 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* exit from sleep mode, which is the default mode after reset */
|
/* exit from sleep mode, which is the default mode after reset */
|
||||||
CANx->MCR &= ~CAN_BIT_SLEEP;
|
CANx->MCR &= ~CAN_BIT_SLEEP;
|
||||||
/* set request to enter initialisation mode */
|
/* set request to enter initialisation mode */
|
||||||
CANx->MCR |= CAN_BIT_INRQ ;
|
CANx->MCR |= CAN_BIT_INRQ ;
|
||||||
|
/* set timeout time to wait for entering initialization mode */
|
||||||
|
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
|
||||||
/* wait for acknowledge that initialization mode was entered */
|
/* wait for acknowledge that initialization mode was entered */
|
||||||
while ((CANx->MSR & CAN_BIT_INAK) == 0)
|
while ((CANx->MSR & CAN_BIT_INAK) == 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* configure the bittming */
|
/* configure the bittming */
|
||||||
CANx->BTR = (blt_int32u)((blt_int32u)(tseg1 - 1) << 16) | \
|
CANx->BTR = (blt_int32u)((blt_int32u)(tseg1 - 1) << 16) | \
|
||||||
|
@ -262,11 +287,18 @@ void CanInit(void)
|
||||||
(blt_int32u)(prescaler - 1);
|
(blt_int32u)(prescaler - 1);
|
||||||
/* set request to leave initialisation mode */
|
/* set request to leave initialisation mode */
|
||||||
CANx->MCR &= ~CAN_BIT_INRQ;
|
CANx->MCR &= ~CAN_BIT_INRQ;
|
||||||
|
/* set timeout time to wait for exiting initialization mode */
|
||||||
|
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
|
||||||
/* wait for acknowledge that initialization mode was exited */
|
/* wait for acknowledge that initialization mode was exited */
|
||||||
while ((CANx->MSR & CAN_BIT_INAK) != 0)
|
while ((CANx->MSR & CAN_BIT_INAK) != 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#if (BOOT_COM_CAN_CHANNEL_INDEX == 0)
|
#if (BOOT_COM_CAN_CHANNEL_INDEX == 0)
|
||||||
|
@ -319,6 +351,7 @@ void CanInit(void)
|
||||||
void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||||
{
|
{
|
||||||
blt_int32u txMsgId = BOOT_COM_CAN_TX_MSG_ID;
|
blt_int32u txMsgId = BOOT_COM_CAN_TX_MSG_ID;
|
||||||
|
blt_int32u timeout;
|
||||||
|
|
||||||
/* make sure that transmit mailbox 0 is available */
|
/* make sure that transmit mailbox 0 is available */
|
||||||
ASSERT_RT((CANx->TSR&CAN_BIT_TME0) == CAN_BIT_TME0);
|
ASSERT_RT((CANx->TSR&CAN_BIT_TME0) == CAN_BIT_TME0);
|
||||||
|
@ -353,11 +386,20 @@ void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||||
((blt_int32u)data[4]));
|
((blt_int32u)data[4]));
|
||||||
/* request the start of message transmission */
|
/* request the start of message transmission */
|
||||||
CANx->sTxMailBox[0].TIR |= CAN_BIT_TXRQ;
|
CANx->sTxMailBox[0].TIR |= CAN_BIT_TXRQ;
|
||||||
|
/* set timeout time to wait for transmission completion */
|
||||||
|
timeout = TimerGet() + CAN_MSG_TX_TIMEOUT_MS;
|
||||||
/* wait for transmit completion */
|
/* wait for transmit completion */
|
||||||
while ((CANx->TSR&CAN_BIT_TME0) == 0)
|
while ((CANx->TSR&CAN_BIT_TME0) == 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure or no other
|
||||||
|
* nodes connected to the bus.
|
||||||
|
*/
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
} /*** end of CanTransmitPacket ***/
|
} /*** end of CanTransmitPacket ***/
|
||||||
|
|
||||||
|
|
|
@ -42,6 +42,9 @@
|
||||||
* reception of the first packet byte.
|
* reception of the first packet byte.
|
||||||
*/
|
*/
|
||||||
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
||||||
|
/** \brief Timeout for transmitting a byte in milliseconds. */
|
||||||
|
#define UART_BYTE_TX_TIMEOUT_MS (10u)
|
||||||
|
|
||||||
/* map the configured UART channel index to the STM32's USART peripheral */
|
/* map the configured UART channel index to the STM32's USART peripheral */
|
||||||
#if (BOOT_COM_UART_CHANNEL_INDEX == 0)
|
#if (BOOT_COM_UART_CHANNEL_INDEX == 0)
|
||||||
/** \brief Set UART base address to USART1. */
|
/** \brief Set UART base address to USART1. */
|
||||||
|
@ -232,6 +235,9 @@ static blt_bool UartReceiveByte(blt_int8u *data)
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
static blt_bool UartTransmitByte(blt_int8u data)
|
static blt_bool UartTransmitByte(blt_int8u data)
|
||||||
{
|
{
|
||||||
|
blt_int32u timeout;
|
||||||
|
blt_bool result = BLT_TRUE;
|
||||||
|
|
||||||
/* check if tx holding register can accept new data */
|
/* check if tx holding register can accept new data */
|
||||||
if (USART_GetFlagStatus(USART_CHANNEL, USART_FLAG_TXE) == RESET)
|
if (USART_GetFlagStatus(USART_CHANNEL, USART_FLAG_TXE) == RESET)
|
||||||
{
|
{
|
||||||
|
@ -240,13 +246,22 @@ static blt_bool UartTransmitByte(blt_int8u data)
|
||||||
}
|
}
|
||||||
/* write byte to transmit holding register */
|
/* write byte to transmit holding register */
|
||||||
USART_SendData(USART_CHANNEL, data);
|
USART_SendData(USART_CHANNEL, data);
|
||||||
|
/* set timeout time to wait for transmit completion. */
|
||||||
|
timeout = TimerGet() + UART_BYTE_TX_TIMEOUT_MS;
|
||||||
/* wait for tx holding register to be empty */
|
/* wait for tx holding register to be empty */
|
||||||
while (USART_GetFlagStatus(USART_CHANNEL, USART_FLAG_TXE) == RESET)
|
while (USART_GetFlagStatus(USART_CHANNEL, USART_FLAG_TXE) == RESET)
|
||||||
{
|
{
|
||||||
;
|
/* keep the watchdog happy */
|
||||||
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
result = BLT_FALSE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* byte transmitted */
|
/* give the result back to the caller */
|
||||||
return BLT_TRUE;
|
return result;
|
||||||
} /*** end of UartTransmitByte ***/
|
} /*** end of UartTransmitByte ***/
|
||||||
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
|
@ -229,7 +229,7 @@ void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||||
blt_int32u txMsgId = BOOT_COM_CAN_TX_MSG_ID;
|
blt_int32u txMsgId = BOOT_COM_CAN_TX_MSG_ID;
|
||||||
CAN_TxHeaderTypeDef txMsgHeader;
|
CAN_TxHeaderTypeDef txMsgHeader;
|
||||||
blt_int32u txMsgMailbox;
|
blt_int32u txMsgMailbox;
|
||||||
blt_int32u txMsgTimeout;
|
blt_int32u timeout;
|
||||||
HAL_StatusTypeDef txStatus;
|
HAL_StatusTypeDef txStatus;
|
||||||
|
|
||||||
/* configure the message that should be transmitted. */
|
/* configure the message that should be transmitted. */
|
||||||
|
@ -256,18 +256,17 @@ void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||||
if (txStatus == HAL_OK)
|
if (txStatus == HAL_OK)
|
||||||
{
|
{
|
||||||
/* determine timeout time for the transmit completion. */
|
/* determine timeout time for the transmit completion. */
|
||||||
txMsgTimeout = TimerGet() + CAN_MSG_TX_TIMEOUT_MS;
|
timeout = TimerGet() + CAN_MSG_TX_TIMEOUT_MS;
|
||||||
/* poll for completion of the transmit operation. */
|
/* poll for completion of the transmit operation. */
|
||||||
while (HAL_CAN_IsTxMessagePending(&canHandle, txMsgMailbox) != 0)
|
while (HAL_CAN_IsTxMessagePending(&canHandle, txMsgMailbox) != 0)
|
||||||
{
|
{
|
||||||
/* service the watchdog. */
|
/* service the watchdog. */
|
||||||
CopService();
|
CopService();
|
||||||
/* did a timeout occur? */
|
/* break loop upon timeout. this would indicate a hardware failure or no other
|
||||||
if (TimerGet() > txMsgTimeout)
|
* nodes connected to the bus.
|
||||||
|
*/
|
||||||
|
if (TimerGet() > timeout)
|
||||||
{
|
{
|
||||||
/* stop waiting. no need for further action. if the response cannot be
|
|
||||||
* transmitted, then the receiving node will detect a timeout.
|
|
||||||
*/
|
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -42,8 +42,8 @@
|
||||||
* reception of the first packet byte.
|
* reception of the first packet byte.
|
||||||
*/
|
*/
|
||||||
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
||||||
/** \brief Timeout for transmitting a byte. */
|
/** \brief Timeout for transmitting a byte in milliseconds. */
|
||||||
#define UART_TX_TIMEOUT_MS (5u)
|
#define UART_BYTE_TX_TIMEOUT_MS (10u)
|
||||||
/* map the configured UART channel index to the STM32's USART peripheral */
|
/* map the configured UART channel index to the STM32's USART peripheral */
|
||||||
#if (BOOT_COM_UART_CHANNEL_INDEX == 0)
|
#if (BOOT_COM_UART_CHANNEL_INDEX == 0)
|
||||||
/** \brief Set UART base address to USART1. */
|
/** \brief Set UART base address to USART1. */
|
||||||
|
@ -228,19 +228,20 @@ static blt_bool UartReceiveByte(blt_int8u *data)
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
static void UartTransmitByte(blt_int8u data)
|
static void UartTransmitByte(blt_int8u data)
|
||||||
{
|
{
|
||||||
blt_int32u txTimeoutTime;
|
blt_int32u timeout;
|
||||||
|
|
||||||
/* Determine timeout time for the transmit operation. */
|
|
||||||
txTimeoutTime = TimerGet() + UART_TX_TIMEOUT_MS;
|
|
||||||
/* write byte to transmit holding register */
|
/* write byte to transmit holding register */
|
||||||
LL_USART_TransmitData8(USART_CHANNEL, data);
|
LL_USART_TransmitData8(USART_CHANNEL, data);
|
||||||
|
/* set timeout time to wait for transmit completion. */
|
||||||
|
timeout = TimerGet() + UART_BYTE_TX_TIMEOUT_MS;
|
||||||
/* wait for tx holding register to be empty */
|
/* wait for tx holding register to be empty */
|
||||||
while (LL_USART_IsActiveFlag_TXE(USART_CHANNEL) == 0)
|
while (LL_USART_IsActiveFlag_TXE(USART_CHANNEL) == 0)
|
||||||
{
|
{
|
||||||
/* Check if a timeout occurred to prevent lockup. */
|
/* keep the watchdog happy */
|
||||||
if (TimerGet() > txTimeoutTime)
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
{
|
{
|
||||||
/* Cannot transmit so stop waiting for its completion. */
|
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -48,6 +48,8 @@
|
||||||
* reception of the first packet byte.
|
* reception of the first packet byte.
|
||||||
*/
|
*/
|
||||||
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
||||||
|
/** \brief Timeout for transmitting a byte in milliseconds. */
|
||||||
|
#define UART_BYTE_TX_TIMEOUT_MS (10u)
|
||||||
|
|
||||||
|
|
||||||
/****************************************************************************************
|
/****************************************************************************************
|
||||||
|
@ -211,20 +213,31 @@ static blt_bool UartReceiveByte(blt_int8u *data)
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
static blt_bool UartTransmitByte(blt_int8u data)
|
static blt_bool UartTransmitByte(blt_int8u data)
|
||||||
{
|
{
|
||||||
|
blt_int32u timeout;
|
||||||
|
blt_bool result = BLT_TRUE;
|
||||||
|
|
||||||
/* write byte to transmit holding register */
|
/* write byte to transmit holding register */
|
||||||
if (UARTCharPutNonBlocking(UART0_BASE, data) == false)
|
if (UARTCharPutNonBlocking(UART0_BASE, data) == false)
|
||||||
{
|
{
|
||||||
/* tx holding register can accept new data */
|
/* tx holding register can accept new data */
|
||||||
return BLT_FALSE;
|
return BLT_FALSE;
|
||||||
}
|
}
|
||||||
|
/* set timeout time to wait for transmit completion. */
|
||||||
|
timeout = TimerGet() + UART_BYTE_TX_TIMEOUT_MS;
|
||||||
/* wait for tx holding register to be empty */
|
/* wait for tx holding register to be empty */
|
||||||
while (UARTSpaceAvail(UART0_BASE) == false)
|
while (UARTSpaceAvail(UART0_BASE) == false)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
result = BLT_FALSE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* byte transmitted */
|
/* give the result back to the caller */
|
||||||
return BLT_TRUE;
|
return result;
|
||||||
} /*** end of UartTransmitByte ***/
|
} /*** end of UartTransmitByte ***/
|
||||||
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
|
@ -39,6 +39,9 @@
|
||||||
/****************************************************************************************
|
/****************************************************************************************
|
||||||
* Macro definitions
|
* Macro definitions
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
|
/** \brief Timeout for transmitting a CAN message in milliseconds. */
|
||||||
|
#define CAN_MSG_TX_TIMEOUT_MS (50u)
|
||||||
|
|
||||||
/** \brief Macro for accessing the CAN channel handle in the format that is expected
|
/** \brief Macro for accessing the CAN channel handle in the format that is expected
|
||||||
* by the XMClib CAN driver.
|
* by the XMClib CAN driver.
|
||||||
*/
|
*/
|
||||||
|
@ -112,11 +115,15 @@ void CanInit(void)
|
||||||
while (canModuleFreqHz < 12000000)
|
while (canModuleFreqHz < 12000000)
|
||||||
{
|
{
|
||||||
canModuleFreqHz *= 2;
|
canModuleFreqHz *= 2;
|
||||||
|
/* keep the watchdog happy */
|
||||||
|
CopService();
|
||||||
}
|
}
|
||||||
/* decrease if too high */
|
/* decrease if too high */
|
||||||
while (canModuleFreqHz > 120000000)
|
while (canModuleFreqHz > 120000000)
|
||||||
{
|
{
|
||||||
canModuleFreqHz /= 2;
|
canModuleFreqHz /= 2;
|
||||||
|
/* keep the watchdog happy */
|
||||||
|
CopService();
|
||||||
}
|
}
|
||||||
|
|
||||||
/* configure CAN module*/
|
/* configure CAN module*/
|
||||||
|
@ -220,6 +227,7 @@ void CanInit(void)
|
||||||
void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||||
{
|
{
|
||||||
blt_int8u byteIdx;
|
blt_int8u byteIdx;
|
||||||
|
blt_int32u timeout;
|
||||||
|
|
||||||
/* copy message data */
|
/* copy message data */
|
||||||
transmitMsgObj.can_data_length = len;
|
transmitMsgObj.can_data_length = len;
|
||||||
|
@ -233,11 +241,20 @@ void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||||
XMC_CAN_MO_ResetStatus(&transmitMsgObj, XMC_CAN_MO_RESET_STATUS_TX_PENDING);
|
XMC_CAN_MO_ResetStatus(&transmitMsgObj, XMC_CAN_MO_RESET_STATUS_TX_PENDING);
|
||||||
/* submit message for transmission */
|
/* submit message for transmission */
|
||||||
XMC_CAN_MO_Transmit(&transmitMsgObj);
|
XMC_CAN_MO_Transmit(&transmitMsgObj);
|
||||||
|
/* set timeout time to wait for transmission completion */
|
||||||
|
timeout = TimerGet() + CAN_MSG_TX_TIMEOUT_MS;
|
||||||
/* wait for transmit completion */
|
/* wait for transmit completion */
|
||||||
while ((XMC_CAN_MO_GetStatus(&transmitMsgObj) & XMC_CAN_MO_STATUS_TX_PENDING) != 0)
|
while ((XMC_CAN_MO_GetStatus(&transmitMsgObj) & XMC_CAN_MO_STATUS_TX_PENDING) != 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure or no other
|
||||||
|
* nodes connected to the bus.
|
||||||
|
*/
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
} /*** end of CanTransmitPacket ***/
|
} /*** end of CanTransmitPacket ***/
|
||||||
|
|
||||||
|
|
|
@ -42,6 +42,9 @@
|
||||||
*/
|
*/
|
||||||
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
||||||
|
|
||||||
|
/** \brief Timeout for transmitting a byte in milliseconds. */
|
||||||
|
#define UART_BYTE_TX_TIMEOUT_MS (10u)
|
||||||
|
|
||||||
/** \brief Macro for accessing the UART channel handle in the format that is expected
|
/** \brief Macro for accessing the UART channel handle in the format that is expected
|
||||||
* by the XMClib UART driver.
|
* by the XMClib UART driver.
|
||||||
*/
|
*/
|
||||||
|
@ -232,6 +235,9 @@ static blt_bool UartReceiveByte(blt_int8u *data)
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
static blt_bool UartTransmitByte(blt_int8u data)
|
static blt_bool UartTransmitByte(blt_int8u data)
|
||||||
{
|
{
|
||||||
|
blt_int32u timeout;
|
||||||
|
blt_bool result = BLT_TRUE;
|
||||||
|
|
||||||
/* check if tx fifo can accept new data */
|
/* check if tx fifo can accept new data */
|
||||||
if (XMC_USIC_CH_TXFIFO_IsFull(UART_CHANNEL) != 0)
|
if (XMC_USIC_CH_TXFIFO_IsFull(UART_CHANNEL) != 0)
|
||||||
{
|
{
|
||||||
|
@ -240,15 +246,24 @@ static blt_bool UartTransmitByte(blt_int8u data)
|
||||||
}
|
}
|
||||||
/* submit data for transmission */
|
/* submit data for transmission */
|
||||||
XMC_UART_CH_Transmit(UART_CHANNEL, data);
|
XMC_UART_CH_Transmit(UART_CHANNEL, data);
|
||||||
|
/* set timeout time to wait for transmit completion. */
|
||||||
|
timeout = TimerGet() + UART_BYTE_TX_TIMEOUT_MS;
|
||||||
/* wait for transmission to be done */
|
/* wait for transmission to be done */
|
||||||
while( (XMC_USIC_CH_TXFIFO_GetEvent(UART_CHANNEL) & XMC_USIC_CH_TXFIFO_EVENT_STANDARD) == 0)
|
while( (XMC_USIC_CH_TXFIFO_GetEvent(UART_CHANNEL) & XMC_USIC_CH_TXFIFO_EVENT_STANDARD) == 0)
|
||||||
{
|
{
|
||||||
;
|
/* keep the watchdog happy */
|
||||||
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
result = BLT_FALSE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* reset event */
|
/* reset event */
|
||||||
XMC_USIC_CH_TXFIFO_ClearEvent(UART_CHANNEL, XMC_USIC_CH_TXFIFO_EVENT_STANDARD);
|
XMC_USIC_CH_TXFIFO_ClearEvent(UART_CHANNEL, XMC_USIC_CH_TXFIFO_EVENT_STANDARD);
|
||||||
/* byte transmitted */
|
/* give the result back to the caller */
|
||||||
return BLT_TRUE;
|
return result;
|
||||||
} /*** end of UartTransmitByte ***/
|
} /*** end of UartTransmitByte ***/
|
||||||
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
|
@ -107,6 +107,11 @@ typedef struct
|
||||||
/****************************************************************************************
|
/****************************************************************************************
|
||||||
* Macro definitions
|
* Macro definitions
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
|
/** \brief Timeout for entering/leaving CAN initialization mode in milliseconds. */
|
||||||
|
#define CAN_INIT_TIMEOUT_MS (250u)
|
||||||
|
/** \brief Timeout for transmitting a CAN message in milliseconds. */
|
||||||
|
#define CAN_MSG_TX_TIMEOUT_MS (50u)
|
||||||
|
|
||||||
#if (BOOT_COM_CAN_CHANNEL_INDEX == 0)
|
#if (BOOT_COM_CAN_CHANNEL_INDEX == 0)
|
||||||
/** \brief Set CAN base address to CAN0. */
|
/** \brief Set CAN base address to CAN0. */
|
||||||
#define CAN_REGS_BASE_ADDRESS (0x0140)
|
#define CAN_REGS_BASE_ADDRESS (0x0140)
|
||||||
|
@ -217,6 +222,7 @@ void CanInit(void)
|
||||||
blt_bool result;
|
blt_bool result;
|
||||||
blt_int32u accept_code;
|
blt_int32u accept_code;
|
||||||
blt_int32u accept_mask;
|
blt_int32u accept_mask;
|
||||||
|
blt_int32u timeout;
|
||||||
|
|
||||||
/* the current implementation supports CAN0..4. throw an assertion error in case a
|
/* the current implementation supports CAN0..4. throw an assertion error in case a
|
||||||
* different CAN channel is configured.
|
* different CAN channel is configured.
|
||||||
|
@ -225,10 +231,18 @@ void CanInit(void)
|
||||||
|
|
||||||
/* enter initialization mode. note that this automatically disables CAN interrupts */
|
/* enter initialization mode. note that this automatically disables CAN interrupts */
|
||||||
CAN->cctl0 = INITRQ_BIT;
|
CAN->cctl0 = INITRQ_BIT;
|
||||||
|
/* set timeout time for entering init mode */
|
||||||
|
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
|
||||||
/* wait for initialization mode entry handshake from the hardware */
|
/* wait for initialization mode entry handshake from the hardware */
|
||||||
while ((CAN->cctl1 & INITAK_BIT) == 0)
|
while ((CAN->cctl1 & INITAK_BIT) == 0)
|
||||||
{
|
{
|
||||||
;
|
/* keep the watchdog happy */
|
||||||
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* enable the CAN controller, disable wake up and listen modes and set the
|
/* enable the CAN controller, disable wake up and listen modes and set the
|
||||||
|
@ -278,10 +292,18 @@ void CanInit(void)
|
||||||
|
|
||||||
/* leave initialization mode and synchronize to the CAN bus */
|
/* leave initialization mode and synchronize to the CAN bus */
|
||||||
CAN->cctl0 &= ~INITRQ_BIT;
|
CAN->cctl0 &= ~INITRQ_BIT;
|
||||||
|
/* set timeout time for leaving init mode */
|
||||||
|
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
|
||||||
/* wait for CAN bus synchronization handshake from the hardware */
|
/* wait for CAN bus synchronization handshake from the hardware */
|
||||||
while ((CAN->cctl1 & INITAK_BIT) != 0)
|
while ((CAN->cctl1 & INITAK_BIT) != 0)
|
||||||
{
|
{
|
||||||
;
|
/* keep the watchdog happy */
|
||||||
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* bring transmit buffer 0 in the foreground as this is the only one used by this
|
/* bring transmit buffer 0 in the foreground as this is the only one used by this
|
||||||
|
@ -302,6 +324,7 @@ void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||||
{
|
{
|
||||||
blt_int8u byte_idx;
|
blt_int8u byte_idx;
|
||||||
blt_int32u txMsgId;
|
blt_int32u txMsgId;
|
||||||
|
blt_int32u timeout;
|
||||||
|
|
||||||
/* double check that the transmit slot is really available */
|
/* double check that the transmit slot is really available */
|
||||||
ASSERT_RT((CAN->ctflg & TXE0_BIT) != 0);
|
ASSERT_RT((CAN->ctflg & TXE0_BIT) != 0);
|
||||||
|
@ -342,11 +365,21 @@ void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||||
*/
|
*/
|
||||||
CAN->ctflg = TXE0_BIT;
|
CAN->ctflg = TXE0_BIT;
|
||||||
|
|
||||||
|
/* set timeout time to wait for transmission completion */
|
||||||
|
timeout = TimerGet() + CAN_MSG_TX_TIMEOUT_MS;
|
||||||
|
|
||||||
/* wait for transmit completion */
|
/* wait for transmit completion */
|
||||||
while ((CAN->ctflg & TXE0_BIT) == 0)
|
while ((CAN->ctflg & TXE0_BIT) == 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure or no other
|
||||||
|
* nodes connected to the bus.
|
||||||
|
*/
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
} /*** end of CanTransmitPacket ***/
|
} /*** end of CanTransmitPacket ***/
|
||||||
|
|
||||||
|
|
|
@ -57,6 +57,9 @@ typedef volatile struct
|
||||||
* reception of the first packet byte.
|
* reception of the first packet byte.
|
||||||
*/
|
*/
|
||||||
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
||||||
|
/** \brief Timeout for transmitting a byte in milliseconds. */
|
||||||
|
#define UART_BYTE_TX_TIMEOUT_MS (10u)
|
||||||
|
|
||||||
#if (BOOT_COM_UART_CHANNEL_INDEX == 0)
|
#if (BOOT_COM_UART_CHANNEL_INDEX == 0)
|
||||||
/** \brief Set UART base address to SCI0. */
|
/** \brief Set UART base address to SCI0. */
|
||||||
#define UART_REGS_BASE_ADDRESS (0x00c8)
|
#define UART_REGS_BASE_ADDRESS (0x00c8)
|
||||||
|
@ -250,6 +253,9 @@ static blt_bool UartReceiveByte(blt_int8u *data)
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
static blt_bool UartTransmitByte(blt_int8u data)
|
static blt_bool UartTransmitByte(blt_int8u data)
|
||||||
{
|
{
|
||||||
|
blt_int32u timeout;
|
||||||
|
blt_bool result = BLT_TRUE;
|
||||||
|
|
||||||
/* check if tx holding register can accept new data */
|
/* check if tx holding register can accept new data */
|
||||||
if ((UART->scisr1 & TDRE_BIT) == 0)
|
if ((UART->scisr1 & TDRE_BIT) == 0)
|
||||||
{
|
{
|
||||||
|
@ -258,14 +264,22 @@ static blt_bool UartTransmitByte(blt_int8u data)
|
||||||
}
|
}
|
||||||
/* write byte to transmit holding register */
|
/* write byte to transmit holding register */
|
||||||
UART->scidrl = data;
|
UART->scidrl = data;
|
||||||
|
/* set timeout time to wait for transmit completion. */
|
||||||
|
timeout = TimerGet() + UART_BYTE_TX_TIMEOUT_MS;
|
||||||
/* wait for tx holding register to be empty */
|
/* wait for tx holding register to be empty */
|
||||||
while ((UART->scisr1 & TDRE_BIT) == 0)
|
while ((UART->scisr1 & TDRE_BIT) == 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
result = BLT_FALSE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* byte transmitted */
|
/* give the result back to the caller */
|
||||||
return BLT_TRUE;
|
return result;
|
||||||
} /*** end of UartTransmitByte ***/
|
} /*** end of UartTransmitByte ***/
|
||||||
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
|
@ -33,6 +33,12 @@
|
||||||
#include <machine/intrinsics.h>
|
#include <machine/intrinsics.h>
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
****************************************************************************************/
|
||||||
|
#define CPU_INIT_MODE_TIMEOUT_MS (250u)
|
||||||
|
|
||||||
|
|
||||||
/****************************************************************************************
|
/****************************************************************************************
|
||||||
* Local function prototypes
|
* Local function prototypes
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
|
@ -73,13 +79,22 @@ void CpuIrqEnable(void)
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
void CpuEnterInitMode(void)
|
void CpuEnterInitMode(void)
|
||||||
{
|
{
|
||||||
|
blt_int32u timeout;
|
||||||
|
|
||||||
/* request clearing of the EndInit bit */
|
/* request clearing of the EndInit bit */
|
||||||
CpuWriteWDTCON0(WDT_CON0.reg & ~0x00000001);
|
CpuWriteWDTCON0(WDT_CON0.reg & ~0x00000001);
|
||||||
|
/* set timeout to wait for hardware handshake */
|
||||||
|
timeout = TimerGet() + CPU_INIT_MODE_TIMEOUT_MS;
|
||||||
/* wait for hardware handshake */
|
/* wait for hardware handshake */
|
||||||
while (WDT_CON0.bits.ENDINIT != 0)
|
while (WDT_CON0.bits.ENDINIT != 0)
|
||||||
{
|
{
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop if timeout occurred */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
} /*** end of CpuEnterInitMode ***/
|
} /*** end of CpuEnterInitMode ***/
|
||||||
|
|
||||||
|
|
|
@ -103,6 +103,16 @@
|
||||||
#define FLASH_CS_RANGE_TOTAL_WORDS ((FLASH_WRITE_BLOCK_SIZE/4u) - \
|
#define FLASH_CS_RANGE_TOTAL_WORDS ((FLASH_WRITE_BLOCK_SIZE/4u) - \
|
||||||
(FLASH_CS_RANGE_START_OFFSET/4u))
|
(FLASH_CS_RANGE_START_OFFSET/4u))
|
||||||
|
|
||||||
|
/** \brief Maximum time for a sector erase operation as specified by the Tricore data-
|
||||||
|
* sheet with an added margin of at least 20%.
|
||||||
|
*/
|
||||||
|
#define FLASH_ERASE_TIME_MAX_MS (5100)
|
||||||
|
|
||||||
|
/** \brief Maximum time for a page program operation as specified by the Tricore data-
|
||||||
|
* sheet with an added margin of at least 20%.
|
||||||
|
*/
|
||||||
|
#define FLASH_PROGRAM_TIME_MAX_MS (40)
|
||||||
|
|
||||||
|
|
||||||
/****************************************************************************************
|
/****************************************************************************************
|
||||||
* Plausibility checks
|
* Plausibility checks
|
||||||
|
@ -818,6 +828,7 @@ static blt_bool FlashTricoreProgramPage(blt_addr start_addr, blt_int8u *data)
|
||||||
blt_int8u *readPtr;
|
blt_int8u *readPtr;
|
||||||
blt_int32u idx;
|
blt_int32u idx;
|
||||||
FLASHn_FSR_t *pflashFSR;
|
FLASHn_FSR_t *pflashFSR;
|
||||||
|
blt_int32u timeout;
|
||||||
|
|
||||||
/* check address alignment to a page in PFLASH */
|
/* check address alignment to a page in PFLASH */
|
||||||
if ((start_addr % FLASH_WRITE_BLOCK_SIZE) != 0)
|
if ((start_addr % FLASH_WRITE_BLOCK_SIZE) != 0)
|
||||||
|
@ -834,6 +845,8 @@ static blt_bool FlashTricoreProgramPage(blt_addr start_addr, blt_int8u *data)
|
||||||
FLASH_WRITE_TO_U32_PTR_BY_ADDR(baseAddr + 0x5554u, 0x00000050u);
|
FLASH_WRITE_TO_U32_PTR_BY_ADDR(baseAddr + 0x5554u, 0x00000050u);
|
||||||
/* perform DSYNC */
|
/* perform DSYNC */
|
||||||
CpuSetDSYNC();
|
CpuSetDSYNC();
|
||||||
|
/* set timeout time for hardware handshake */
|
||||||
|
timeout = TimerGet() + FLASH_PROGRAM_TIME_MAX_MS;
|
||||||
/* wait until FSR.xFPAGE = '1' */
|
/* wait until FSR.xFPAGE = '1' */
|
||||||
while (pflashFSR->bits.PFPAGE != 1)
|
while (pflashFSR->bits.PFPAGE != 1)
|
||||||
{
|
{
|
||||||
|
@ -849,6 +862,11 @@ static blt_bool FlashTricoreProgramPage(blt_addr start_addr, blt_int8u *data)
|
||||||
}
|
}
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* fail in case of timeout */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
return BLT_FALSE;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* load FLASH_WRITE_BLOCK_SIZE bytes of program data into the assembly buffer */
|
/* load FLASH_WRITE_BLOCK_SIZE bytes of program data into the assembly buffer */
|
||||||
dataPtr = (blt_int32u *)data;
|
dataPtr = (blt_int32u *)data;
|
||||||
|
@ -868,6 +886,8 @@ static blt_bool FlashTricoreProgramPage(blt_addr start_addr, blt_int8u *data)
|
||||||
FLASH_WRITE_TO_U32_PTR_BY_ADDR(start_addr, 0x000000AAu);
|
FLASH_WRITE_TO_U32_PTR_BY_ADDR(start_addr, 0x000000AAu);
|
||||||
/* perform DSYNC */
|
/* perform DSYNC */
|
||||||
CpuSetDSYNC();
|
CpuSetDSYNC();
|
||||||
|
/* set timeout time for hardware handshake */
|
||||||
|
timeout = TimerGet() + FLASH_PROGRAM_TIME_MAX_MS;
|
||||||
/* wait until FSR.PROG = '1' */
|
/* wait until FSR.PROG = '1' */
|
||||||
while (pflashFSR->bits.PROG != 1)
|
while (pflashFSR->bits.PROG != 1)
|
||||||
{
|
{
|
||||||
|
@ -883,7 +903,14 @@ static blt_bool FlashTricoreProgramPage(blt_addr start_addr, blt_int8u *data)
|
||||||
}
|
}
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* fail in case of timeout */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
return BLT_FALSE;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
/* set timeout time for hardware handshake */
|
||||||
|
timeout = TimerGet() + FLASH_PROGRAM_TIME_MAX_MS;
|
||||||
/* wait until FSR.xBUSY = '0' */
|
/* wait until FSR.xBUSY = '0' */
|
||||||
while (pflashFSR->bits.PBUSY == 1)
|
while (pflashFSR->bits.PBUSY == 1)
|
||||||
{
|
{
|
||||||
|
@ -896,6 +923,11 @@ static blt_bool FlashTricoreProgramPage(blt_addr start_addr, blt_int8u *data)
|
||||||
}
|
}
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* fail in case of timeout */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
return BLT_FALSE;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* check FSR.VER flag */
|
/* check FSR.VER flag */
|
||||||
if (pflashFSR->bits.VER != 0)
|
if (pflashFSR->bits.VER != 0)
|
||||||
|
@ -948,6 +980,7 @@ static blt_bool FlashTricoreEraseSector(blt_addr start_addr)
|
||||||
blt_int8u sectorNum;
|
blt_int8u sectorNum;
|
||||||
blt_int32u *readPtr;
|
blt_int32u *readPtr;
|
||||||
blt_int32u idx;
|
blt_int32u idx;
|
||||||
|
blt_int32u timeout;
|
||||||
|
|
||||||
/* determine base address of the PFLASH module */
|
/* determine base address of the PFLASH module */
|
||||||
baseAddr = FLASH_GET_PFLASH_BASE(start_addr);
|
baseAddr = FLASH_GET_PFLASH_BASE(start_addr);
|
||||||
|
@ -964,6 +997,8 @@ static blt_bool FlashTricoreEraseSector(blt_addr start_addr)
|
||||||
FLASH_WRITE_TO_U32_PTR_BY_ADDR(start_addr, 0x00000030u);
|
FLASH_WRITE_TO_U32_PTR_BY_ADDR(start_addr, 0x00000030u);
|
||||||
/* perform DSYNC */
|
/* perform DSYNC */
|
||||||
CpuSetDSYNC();
|
CpuSetDSYNC();
|
||||||
|
/* set timeout time for hardware handshake */
|
||||||
|
timeout = TimerGet() + FLASH_ERASE_TIME_MAX_MS;
|
||||||
/* wait until FSR.ERASE = '1' */
|
/* wait until FSR.ERASE = '1' */
|
||||||
while (pflashFSR->bits.ERASE != 1)
|
while (pflashFSR->bits.ERASE != 1)
|
||||||
{
|
{
|
||||||
|
@ -979,7 +1014,14 @@ static blt_bool FlashTricoreEraseSector(blt_addr start_addr)
|
||||||
}
|
}
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* fail in case of timeout */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
return BLT_FALSE;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
/* set timeout time for hardware handshake */
|
||||||
|
timeout = TimerGet() + FLASH_ERASE_TIME_MAX_MS;
|
||||||
/* wait until FSR.xBUSY = '0' */
|
/* wait until FSR.xBUSY = '0' */
|
||||||
while (pflashFSR->bits.PBUSY == 1)
|
while (pflashFSR->bits.PBUSY == 1)
|
||||||
{
|
{
|
||||||
|
@ -992,6 +1034,11 @@ static blt_bool FlashTricoreEraseSector(blt_addr start_addr)
|
||||||
}
|
}
|
||||||
/* keep the watchdog happy */
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* fail in case of timeout */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
return BLT_FALSE;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* check FSR.VER flag */
|
/* check FSR.VER flag */
|
||||||
if (pflashFSR->bits.VER != 0)
|
if (pflashFSR->bits.VER != 0)
|
||||||
|
|
|
@ -66,6 +66,8 @@ typedef struct
|
||||||
* reception of the first packet byte.
|
* reception of the first packet byte.
|
||||||
*/
|
*/
|
||||||
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
||||||
|
/** \brief Timeout for transmitting a byte in milliseconds. */
|
||||||
|
#define UART_BYTE_TX_TIMEOUT_MS (10u)
|
||||||
|
|
||||||
|
|
||||||
/****************************************************************************************
|
/****************************************************************************************
|
||||||
|
@ -264,17 +266,29 @@ static blt_bool UartReceiveByte(blt_int8u *data)
|
||||||
****************************************************************************************/
|
****************************************************************************************/
|
||||||
static blt_bool UartTransmitByte(blt_int8u data)
|
static blt_bool UartTransmitByte(blt_int8u data)
|
||||||
{
|
{
|
||||||
|
blt_int32u timeout;
|
||||||
|
blt_bool result = BLT_TRUE;
|
||||||
|
|
||||||
/* reset transmit buffer interrupt request */
|
/* reset transmit buffer interrupt request */
|
||||||
UARTx->TBSRC.bits.CLRR = 1;
|
UARTx->TBSRC.bits.CLRR = 1;
|
||||||
/* write byte to transmit buffer register */
|
/* write byte to transmit buffer register */
|
||||||
UARTx->TBUF.reg = data;
|
UARTx->TBUF.reg = data;
|
||||||
|
/* set timeout time to wait for transmit completion. */
|
||||||
|
timeout = TimerGet() + UART_BYTE_TX_TIMEOUT_MS;
|
||||||
/* wait for transmit buffer register to be empty */
|
/* wait for transmit buffer register to be empty */
|
||||||
while (UARTx->TBSRC.bits.SRR == 0)
|
while (UARTx->TBSRC.bits.SRR == 0)
|
||||||
{
|
{
|
||||||
|
/* keep the watchdog happy */
|
||||||
CopService();
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
result = BLT_FALSE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/* byte transmitted */
|
/* give the result back to the caller */
|
||||||
return BLT_TRUE;
|
return result;
|
||||||
} /*** end of UartTransmitByte ***/
|
} /*** end of UartTransmitByte ***/
|
||||||
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue