diff --git a/Target/Demo/ARMCM33_STM32L5_Nucleo_L552ZE_CubeIDE/Boot/Core/Src/stm32l5xx_hal_msp.c b/Target/Demo/ARMCM33_STM32L5_Nucleo_L552ZE_CubeIDE/Boot/Core/Src/stm32l5xx_hal_msp.c
index 4242e981..7196b584 100644
--- a/Target/Demo/ARMCM33_STM32L5_Nucleo_L552ZE_CubeIDE/Boot/Core/Src/stm32l5xx_hal_msp.c
+++ b/Target/Demo/ARMCM33_STM32L5_Nucleo_L552ZE_CubeIDE/Boot/Core/Src/stm32l5xx_hal_msp.c
@@ -232,10 +232,10 @@ void HAL_MspDeInit(void)
   LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPUART1);
 
   /* GPIO ports clock disable. */
-  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOG);
-  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC);
-  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
-  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+  LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOG);
+  LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOC);
+  LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+  LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
 
   /* SYSCFG and PWR clock disable. */
   LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_PWR);