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+S10F1DF8000000000000000000000000DB +S1131E04044A137880210B43137013785BB2002BBC +S10B1E14FBDA704700000240F4 +S903053DBA diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/S32K118_25_flash.ld b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/S32K118_25_flash.ld new file mode 100644 index 00000000..c6fb889c --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/S32K118_25_flash.ld @@ -0,0 +1,278 @@ +/* +** ################################################################### +** Processor: S32K118 with 25 KB SRAM +** Compiler: GNU C Compiler +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2018 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) +/* +To use "new" operator with EWL in C++ project the following symbol shall be defined +*/ +/*EXTERN(_ZN10__cxxabiv119__terminate_handlerE)*/ + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x00000200; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x00000200; + +/* If symbol __flash_vector_table__=1 is defined at link time + * the interrupt vector will not be copied to RAM. + * Warning: Using the interrupt vector from Flash will not allow + * INT_SYS_InstallHandler because the section is Read Only. + */ +M_VECTOR_RAM_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : 0x00C0; + +/* Specify the memory areas */ +MEMORY +{ + /* Flash */ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x000000C0 + m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 + m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x00001BF0 + + /* SRAM_L */ + + /* SRAM_U */ + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x000030C0 + m_data_2 (RW) : ORIGIN = 0x200030C0, LENGTH = 0x00002740 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + __VECTOR_TABLE = .; + __interrupts_start__ = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + __interrupts_end__ = .; + . = ALIGN(4); + } > m_interrupts + + .flash_config : + { + . = ALIGN(4); + KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_flash_config + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* Define a global symbol at end of code. */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization. */ + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __RAM_START = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start. */ + *(.m_interrupts_ram) /* This is a user defined section. */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end. */ + } > m_data + + __VECTOR_RAM = DEFINED(__flash_vector_table__) ? ORIGIN(m_interrupts) : __VECTOR_RAM__ ; + __RAM_VECTOR_TABLE_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : (__interrupts_ram_end__ - __interrupts_ram_start__) ; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* Create a global symbol at data start. */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* Define a global symbol at data end. */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + __CODE_ROM = __DATA_END; /* Symbol is used by code initialization. */ + .code : AT(__CODE_ROM) + { + . = ALIGN(4); + __CODE_RAM = .; + __code_start__ = .; /* Create a global symbol at code start. */ + __code_ram_start__ = .; + *(.code_ram) /* Custom section for storing code in RAM */ + . = ALIGN(4); + __code_end__ = .; /* Define a global symbol at code end. */ + __code_ram_end__ = .; + } > m_data + + __CODE_END = __CODE_ROM + (__code_end__ - __code_start__); + __CUSTOM_ROM = __CODE_END; + + /* Custom Section Block that can be used to place data at absolute address. */ + /* Use __attribute__((section (".customSection"))) to place data here. */ + .customSectionBlock ORIGIN(m_data_2) : AT(__CUSTOM_ROM) + { + __customSection_start__ = .; + KEEP(*(.customSection)) /* Keep section even if not referenced. */ + __customSection_end__ = .; + } > m_data_2 + __CUSTOM_END = __CUSTOM_ROM + (__customSection_end__ - __customSection_start__); + + /* Uninitialized data section. */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section. */ + . = ALIGN(4); + __BSS_START = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __BSS_END = .; + } > m_data_2 + + .heap : + { + . = ALIGN(8); + __end__ = .; + __heap_start__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + PROVIDE(__end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; + __heap_end__ = .; + } > m_data_2 + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + __RAM_END = __StackTop; + + .stack __StackLimit : + { + . = ALIGN(8); + __stack_start__ = .; + . += STACK_SIZE; + __stack_end__ = .; + } > m_data_2 + + /* Labels required by EWL */ + __START_BSS = __BSS_START; + __END_BSS = __BSS_END; + __SP_INIT = __StackTop; + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap") +} + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/blt_conf.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/blt_conf.h new file mode 100644 index 00000000..b8eb972f --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/blt_conf.h @@ -0,0 +1,176 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/blt_conf.h +* \brief Bootloader configuration header file. +* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef BLT_CONF_H +#define BLT_CONF_H + +/**************************************************************************************** +* C P U D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* To properly initialize the baudrate clocks of the communication interface, typically + * the speed of the crystal oscillator and/or the speed at which the system runs is + * needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and + * BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is + * not dependent on the targets architecture, the byte ordering needs to be known. + * Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects + * little endian mode. + * + * Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be + * called the moment the user program is about to be started. This could be used to + * de-initialize application specific parts, for example to stop blinking an LED, etc. + */ +/** \brief Frequency of the external crystal oscillator. */ +#define BOOT_CPU_XTAL_SPEED_KHZ (40000) +/** \brief Desired system speed. */ +#define BOOT_CPU_SYSTEM_SPEED_KHZ (48000) +/** \brief Motorola or Intel style byte ordering. */ +#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0) +/** \brief Enable/disable hook function call right before user program start. */ +#define BOOT_CPU_USER_PROGRAM_START_HOOK (1) + + +/**************************************************************************************** +* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N +****************************************************************************************/ +/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE + * configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed + * in bits/second. The maximum amount of data bytes in a message for data transmission + * and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA, + * respectively. It is common for a microcontroller to have more than 1 UART interface + * on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface. + * + */ +/** \brief Enable/disable UART transport layer. */ +#define BOOT_COM_RS232_ENABLE (1) +/** \brief Configure the desired communication speed. */ +#define BOOT_COM_RS232_BAUDRATE (57600) +/** \brief Configure number of bytes in the target->host data packet. */ +#define BOOT_COM_RS232_TX_MAX_DATA (64) +/** \brief Configure number of bytes in the host->target data packet. */ +#define BOOT_COM_RS232_RX_MAX_DATA (64) +/** \brief Select the desired UART peripheral as a zero based index. */ +#define BOOT_COM_RS232_CHANNEL_INDEX (0) + +/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE + * configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed + * in bits/second. Two CAN messages are reserved for communication with the host. The + * message identifier for sending data from the target to the host is configured with + * BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with + * BOOT_COM_CAN_RXMSG_ID. Note that an extended 29-bit CAN identifier is configured by + * OR-ing with mask 0x80000000. The maximum amount of data bytes in a message for data + * transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and + * BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more + * than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the + * CAN controller channel. + * + */ +/** \brief Enable/disable CAN transport layer. */ +#define BOOT_COM_CAN_ENABLE (1) +/** \brief Configure the desired CAN baudrate. */ +#define BOOT_COM_CAN_BAUDRATE (500000) +/** \brief Configure CAN message ID target->host. */ +#define BOOT_COM_CAN_TX_MSG_ID (0x7E1 /*| 0x80000000*/) +/** \brief Configure number of bytes in the target->host CAN message. */ +#define BOOT_COM_CAN_TX_MAX_DATA (8) +/** \brief Configure CAN message ID host->target. */ +#define BOOT_COM_CAN_RX_MSG_ID (0x667 /*| 0x80000000*/) +/** \brief Configure number of bytes in the host->target CAN message. */ +#define BOOT_COM_CAN_RX_MAX_DATA (8) +/** \brief Select the desired CAN peripheral as a zero based index. */ +#define BOOT_COM_CAN_CHANNEL_INDEX (0) + + +/**************************************************************************************** +* B A C K D O O R E N T R Y C O N F I G U R A T I O N +****************************************************************************************/ +/* It is possible to implement an application specific method to force the bootloader to + * stay active after a reset. Such a backdoor entry into the bootloader is desired in + * situations where the user program does not run properly and therefore cannot + * reactivate the bootloader. By enabling these hook functions, the application can + * implement the backdoor, which overrides the default backdoor entry that is programmed + * into the bootloader. When desired for security purposes, these hook functions can + * also be implemented in a way that disables the backdoor entry altogether. + */ +/** \brief Enable/disable the backdoor override hook functions. */ +#define BOOT_BACKDOOR_HOOKS_ENABLE (0) + + +/**************************************************************************************** +* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* The NVM driver typically supports erase and program operations of the internal memory + * present on the microcontroller. Through these hook functions the NVM driver can be + * extended to support additional memory types such as external flash memory and serial + * eeproms. The size of the internal memory in kilobytes is specified with configurable + * BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can + * be overridden with a application specific method by enabling configuration switch + * BOOT_NVM_CHECKSUM_HOOKS_ENABLE. + */ +/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */ +#define BOOT_NVM_HOOKS_ENABLE (0) +/** \brief Configure the size of the default memory device (typically flash EEPROM). */ +#define BOOT_NVM_SIZE_KB (256) +/** \brief Enable/disable hooks functions to override the user program checksum handling. */ +#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0) + + +/**************************************************************************************** +* W A T C H D O G D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* The COP driver cannot be configured internally in the bootloader, because its use + * and configuration is application specific. The bootloader does need to service the + * watchdog in case it is used. When the application requires the use of a watchdog, + * set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through + * hook functions. + */ +/** \brief Enable/disable the hook functions for controlling the watchdog. */ +#define BOOT_COP_HOOKS_ENABLE (1) + + +/**************************************************************************************** +* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N +****************************************************************************************/ +/* A security mechanism can be enabled in the bootloader's XCP module by setting configu- + * rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming + * operations can be performed, access to this resource need to be unlocked. + * In the Microboot settings on tab "XCP Protection" you need to specify a DLL that + * implements the unlocking algorithm. The demo programs are configured for the (simple) + * algorithm in "libseednkey.dll". The source code for this DLL is available so it can be + * customized to your needs. + * During the unlock sequence, Microboot requests a seed from the bootloader, which is in + * the format of a byte array. Using this seed the unlock algorithm in the DLL computes + * a key, which is also a byte array, and sends this back to the bootloader. The + * bootloader then verifies this key to determine if programming and erase operations are + * permitted. + * After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook() + * are called by the bootloader to obtain the seed and to verify the key, respectively. + */ +#define BOOT_XCP_SEED_KEY_ENABLE (0) + + +#endif /* BLT_CONF_H */ +/*********************************** end of blt_conf.h *********************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/boot.dox b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/boot.dox new file mode 100644 index 00000000..94742d6d --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/boot.dox @@ -0,0 +1,7 @@ +/** +\defgroup Boot_ARMCM0_S32K14_S32K118EVB_GCC Bootloader +\brief Bootloader. +\ingroup ARMCM0_S32K14_S32K118EVB_GCC +*/ + + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/hooks.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/hooks.c new file mode 100644 index 00000000..3bd5251b --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/hooks.c @@ -0,0 +1,307 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/hooks.c +* \brief Bootloader callback source file. +* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "led.h" /* LED driver header */ +#include "device_registers.h" /* device registers */ + + +/**************************************************************************************** +* B A C K D O O R E N T R Y H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Initializes the backdoor entry option. +** \return none. +** +****************************************************************************************/ +void BackDoorInitHook(void) +{ +} /*** end of BackDoorInitHook ***/ + + +/************************************************************************************//** +** \brief Checks if a backdoor entry is requested. +** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool BackDoorEntryHook(void) +{ + /* default implementation always activates the bootloader after a reset */ + return BLT_TRUE; +} /*** end of BackDoorEntryHook ***/ +#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* C P U D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0) +/************************************************************************************//** +** \brief Callback that gets called when the bootloader is about to exit and +** hand over control to the user program. This is the last moment that +** some final checking can be performed and if necessary prevent the +** bootloader from activiting the user program. +** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep +** keep the bootloader active. +** +****************************************************************************************/ +blt_bool CpuUserProgramStartHook(void) +{ + /* additional and optional backdoor entry through the pushbutton (SW2) on the board. to + * force the bootloader to stay active after reset, keep it pressed during reset. + */ + if ((PTD->PDIR & GPIO_PDIR_PDI(1 << 3U)) != 0U) + { + /* pushbutton pressed, so do not start the user program and keep the + * bootloader active instead. + */ + return BLT_FALSE; + } + + /* clean up the LED driver */ + LedBlinkExit(); + + /* okay to start the user program */ + return BLT_TRUE; +} /*** end of CpuUserProgramStartHook ***/ +#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */ + + +/**************************************************************************************** +* W A T C H D O G D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_COP_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Callback that gets called at the end of the internal COP driver +** initialization routine. It can be used to configure and enable the +** watchdog. +** \return none. +** +****************************************************************************************/ +void CopInitHook(void) +{ + /* this function is called upon initialization. might as well use it to initialize + * the LED driver. It is kind of a visual watchdog anyways. + */ + LedBlinkInit(100); +} /*** end of CopInitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the end of the internal COP driver +** service routine. This gets called upon initialization and during +** potential long lasting loops and routine. It can be used to service +** the watchdog to prevent a watchdog reset. +** \return none. +** +****************************************************************************************/ +void CopServiceHook(void) +{ + /* run the LED blink task. this is a better place to do it than in the main() program + * loop. certain operations such as flash erase can take a long time, which would cause + * a blink interval to be skipped. this function is also called during such operations, + * so no blink intervals will be skipped when calling the LED blink task here. + */ + LedBlinkTask(); +} /*** end of CopServiceHook ***/ +#endif /* BOOT_COP_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_NVM_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Callback that gets called at the start of the internal NVM driver +** initialization routine. +** \return none. +** +****************************************************************************************/ +void NvmInitHook(void) +{ +} /*** end of NvmInitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of a firmware update to reinitialize +** the NVM driver. +** \return none. +** +****************************************************************************************/ +void NvmReinitHook(void) +{ +} /*** end of NvmReinitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of the NVM driver write +** routine. It allows additional memory to be operated on. If the address +** is not within the range of the additional memory, then +** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't +** been written yet. +** \param addr Start address. +** \param len Length in bytes. +** \param data Pointer to the data buffer. +** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is +** not within the supported memory range, or BLT_NVM_ERROR is the write +** operation failed. +** +****************************************************************************************/ +blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data) +{ + return BLT_NVM_NOT_IN_RANGE; +} /*** end of NvmWriteHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of the NVM driver erase +** routine. It allows additional memory to be operated on. If the address +** is not within the range of the additional memory, then +** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory +** hasn't been erased yet. +** \param addr Start address. +** \param len Length in bytes. +** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is +** not within the supported memory range, or BLT_NVM_ERROR is the erase +** operation failed. +** +****************************************************************************************/ +blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len) +{ + return BLT_NVM_NOT_IN_RANGE; +} /*** end of NvmEraseHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the end of the NVM programming session. +** \return BLT_TRUE is successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmDoneHook(void) +{ + return BLT_TRUE; +} /*** end of NvmDoneHook ***/ +#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */ + + +#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Verifies the checksum, which indicates that a valid user program is +** present and can be started. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmVerifyChecksumHook(void) +{ + return BLT_TRUE; +} /*** end of NvmVerifyChecksum ***/ + + +/************************************************************************************//** +** \brief Writes a checksum of the user program to non-volatile memory. This is +** performed once the entire user program has been programmed. Through +** the checksum, the bootloader can check if a valid user programming is +** present and can be started. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmWriteChecksumHook(void) +{ + return BLT_TRUE; +} +#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_XCP_SEED_KEY_ENABLE > 0) +/************************************************************************************//** +** \brief Provides a seed to the XCP master that will be used for the key +** generation when the master attempts to unlock the specified resource. +** Called by the GET_SEED command. +** \param resource Resource that the seed if requested for (XCP_RES_XXX). +** \param seed Pointer to byte buffer wher the seed will be stored. +** \return Length of the seed in bytes. +** +****************************************************************************************/ +blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed) +{ + /* request seed for unlocking ProGraMming resource */ + if ((resource & XCP_RES_PGM) != 0) + { + seed[0] = 0x55; + } + + /* return seed length */ + return 1; +} /*** end of XcpGetSeedHook ***/ + + +/************************************************************************************//** +** \brief Called by the UNLOCK command and checks if the key to unlock the +** specified resource was correct. If so, then the resource protection +** will be removed. +** \param resource resource to unlock (XCP_RES_XXX). +** \param key pointer to the byte buffer holding the key. +** \param len length of the key in bytes. +** \return 1 if the key was correct, 0 otherwise. +** +****************************************************************************************/ +blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len) +{ + /* suppress compiler warning for unused parameter */ + len = len; + + /* the example key algorithm in "libseednkey.dll" works as follows: + * - PGM will be unlocked if key = seed - 1 + */ + + /* check key for unlocking ProGraMming resource */ + if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1))) + { + /* correct key received for unlocking PGM resource */ + return 1; + } + + /* still here so key incorrect */ + return 0; +} /*** end of XcpVerifyKeyHook ***/ +#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */ + + +/*********************************** end of hooks.c ************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/led.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/led.c new file mode 100644 index 00000000..c4fb84ef --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/led.c @@ -0,0 +1,108 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/led.c +* \brief LED driver source file. +* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "led.h" /* module header */ +#include "device_registers.h" /* device registers */ + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Holds the desired LED blink interval time. */ +static blt_int16u ledBlinkIntervalMs; + + +/************************************************************************************//** +** \brief Initializes the LED blink driver. +** \param interval_ms Specifies the desired LED blink interval time in milliseconds. +** \return none. +** +****************************************************************************************/ +void LedBlinkInit(blt_int16u interval_ms) +{ + /* LED GPIO pin configuration. PE8 = GPIO, MUX = ALT1. */ + PORTE->PCR[8] = PORT_PCR_MUX(1); + /* Configure Port E pin 8 GPIO as digital output. */ + PTE->PDDR |= GPIO_PDDR_PDD(1 << 8U); + /* Turn the LED off on Port E pin 8. */ + PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U); + /* store the interval time between LED toggles */ + ledBlinkIntervalMs = interval_ms; +} /*** end of LedBlinkInit ***/ + + +/************************************************************************************//** +** \brief Task function for blinking the LED as a fixed timer interval. +** \return none. +** +****************************************************************************************/ +void LedBlinkTask(void) +{ + static blt_bool ledOn = BLT_FALSE; + static blt_int32u nextBlinkEvent = 0; + + /* check for blink event */ + if (TimerGet() >= nextBlinkEvent) + { + /* toggle the LED state */ + if (ledOn == BLT_FALSE) + { + ledOn = BLT_TRUE; + /* Turn the LED on. */ + PTE->PSOR |= GPIO_PSOR_PTSO(1 << 8U); + } + else + { + ledOn = BLT_FALSE; + /* Turn the LED off. */ + PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U); + } + /* schedule the next blink event */ + nextBlinkEvent = TimerGet() + ledBlinkIntervalMs; + } +} /*** end of LedBlinkTask ***/ + + +/************************************************************************************//** +** \brief Cleans up the LED blink driver. This is intended to be used upon program +** exit. +** \return none. +** +****************************************************************************************/ +void LedBlinkExit(void) +{ + /* Turn the LED off. */ + PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U); +} /*** end of LedBlinkExit ***/ + + +/*********************************** end of led.c **************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/led.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/led.h new file mode 100644 index 00000000..1dcb725e --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/led.h @@ -0,0 +1,40 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/led.h +* \brief LED driver header file. +* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef LED_H +#define LED_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void LedBlinkInit(blt_int16u interval_ms); +void LedBlinkTask(void); +void LedBlinkExit(void); + + +#endif /* LED_H */ +/*********************************** end of led.h **************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/S32K118.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/S32K118.h new file mode 100644 index 00000000..d1f10a17 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/S32K118.h @@ -0,0 +1,10438 @@ +/* +** ################################################################### +** Processor: S32K118 +** Reference manual: S32K1XXRM Rev. 9, 09/2018 +** Version: rev. 1.3, 2019-02-19 +** Build: b190219 +** +** Abstract: +** Peripheral Access Layer for S32K118 +** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2017-12-14) - Mihai Volmer +** Initial version based on S32K1XXRM Rev. 6, 12/2017. +** - rev. 1.1 (2018-02-08) - Mihai Volmer +** Renamed the NVIC register array IP to IPR to reflect the register access difference from Cortex-M4 NVIC registers +** Fixed CSE_PRAM base address +** - rev. 1.2 (2018-07-19) - Dan Nastasa +** Updated the header based on S32K1XXRM Rev. 8, 06/2018. +** Added MTB_DWT peripheral to the header file +** - rev. 1.3 (2019-02-19) - Ionut Pavel +** Updated the header based on S32K1XXRM Rev. 9, 09/2018. +** Removed LMEM_LMDR2 register from the header file. +** Modified LMEM_LMPECR register to Read-Only. +** +** ################################################################### +*/ + +/*! + * @file S32K118.h + * @version 1.3 + * @date 2019-02-19 + * @brief Peripheral Access Layer for S32K118 + * + * This file contains register definitions and macros for easy access to their + * bit fields. + * + * This file assumes LITTLE endian system. + */ + +/** +* @page misra_violations MISRA-C:2012 violations +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced +* The SoC header defines typedef for all modules. +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced +* The SoC header defines macros for all modules and registers. +* +* @section [global] +* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro +* These are generated macros used for accessing the bit-fields from registers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.1, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.2, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.4, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.5, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler +* This type qualifier is needed to ensure correct I/O access and addressing. +*/ + +/* ---------------------------------------------------------------------------- + -- MCU activation + ---------------------------------------------------------------------------- */ + +/* Prevention from multiple including the same memory map */ +#if !defined(S32K118_H_) /* Check if memory map has not been already included */ +#define S32K118_H_ +#define MCU_S32K118 + +/* Check if another memory map has not been also included */ +#if (defined(MCU_ACTIVE)) + #error S32K118 memory map: There is already included another memory map. Only one memory map can be included. +#endif /* (defined(MCU_ACTIVE)) */ +#define MCU_ACTIVE + +#include + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0003u + +/* ---------------------------------------------------------------------------- + -- Generic macros + ---------------------------------------------------------------------------- */ + +/* IO definitions (access restrictions to peripheral registers) */ +/** +* IO Type Qualifiers are used +* \li to specify the access to peripheral variables. +* \li for automatic generation of peripheral register debug information. +*/ +#ifndef __IO +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ +#endif + + +/** +* @brief 32 bits memory read macro. +*/ +#if !defined(REG_READ32) + #define REG_READ32(address) (*(volatile uint32_t*)(address)) +#endif + +/** +* @brief 32 bits memory write macro. +*/ +#if !defined(REG_WRITE32) + #define REG_WRITE32(address, value) ((*(volatile uint32_t*)(address))= (uint32_t)(value)) +#endif + +/** +* @brief 32 bits bits setting macro. +*/ +#if !defined(REG_BIT_SET32) + #define REG_BIT_SET32(address, mask) ((*(volatile uint32_t*)(address))|= (uint32_t)(mask)) +#endif + +/** +* @brief 32 bits bits clearing macro. +*/ +#if !defined(REG_BIT_CLEAR32) + #define REG_BIT_CLEAR32(address, mask) ((*(volatile uint32_t*)(address))&= ((uint32_t)~((uint32_t)(mask)))) +#endif + +/** +* @brief 32 bit clear bits and set with new value +* @note It is user's responsability to make sure that value has only "mask" bits set - (value&~mask)==0 +*/ +#if !defined(REG_RMW32) + #define REG_RMW32(address, mask, value) (REG_WRITE32((address), ((REG_READ32(address)& ((uint32_t)~((uint32_t)(mask))))| ((uint32_t)(value))))) +#endif + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers for S32K118 + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers_S32K118 Interrupt vector numbers for S32K118 + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 48u /**< Number of interrupts in the Vector table */ + +/** + * @brief Defines the Interrupt Numbers definitions + * + * This enumeration is used to configure the interrupts. + * + * Implements : IRQn_Type_Class + */ +typedef enum +{ + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_IRQn = 0u, /**< DMA channel 0 transfer complete */ + DMA1_IRQn = 1u, /**< DMA channel 1 transfer complete */ + DMA2_IRQn = 2u, /**< DMA channel 2 transfer complete */ + DMA3_IRQn = 3u, /**< DMA channel 3 transfer complete */ + DMA_Error_IRQn = 4u, /**< DMA error interrupt channels 0-3 */ + ERM_fault_IRQn = 5u, /**< ERM single and double bit error correction */ + RTC_IRQn = 6u, /**< RTC alarm interrupt */ + RTC_Seconds_IRQn = 7u, /**< RTC seconds interrupt */ + LPTMR0_IRQn = 8u, /**< LPTIMER interrupt request */ + PORT_IRQn = 9u, /**< Port A, B, C, D and E pin detect interrupt */ + CAN0_ORed_Err_Wakeup_IRQn = 10u, /**< OR’ed [Bus Off OR Bus Off Done OR Transmit Warning OR Receive Warning], Interrupt indicating that errors were detected on the CAN bus, Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode */ + CAN0_ORed_0_31_MB_IRQn = 11u, /**< OR'ed Message buffer (0-15, 16-31) */ + FTM0_Ch0_7_IRQn = 12u, /**< FTM0 Channel 0 to 7 interrupt */ + FTM0_Fault_IRQn = 13u, /**< FTM0 Fault interrupt */ + FTM0_Ovf_Reload_IRQn = 14u, /**< FTM0 Counter overflow and Reload interrupt */ + FTM1_Ch0_7_IRQn = 15u, /**< FTM1 Channel 0 to 7 interrupt */ + FTM1_Fault_IRQn = 16u, /**< FTM1 Fault interrupt */ + FTM1_Ovf_Reload_IRQn = 17u, /**< FTM1 Counter overflow and Reload interrupt */ + FTFC_IRQn = 18u, /**< FTFC Command complete, Read collision and Double bit fault detect */ + PDB0_IRQn = 19u, /**< PDB0 interrupt */ + LPIT0_IRQn = 20u, /**< LPIT interrupt */ + SCG_CMU_LVD_LVWSCG_IRQn = 21u, /**< PMC Low voltage detect interrupt, SCG bus interrupt request and CMU loss of range interrupt */ + WDOG_IRQn = 22u, /**< WDOG interrupt request out before wdg reset out */ + RCM_IRQn = 23u, /**< RCM Asynchronous Interrupt */ + LPI2C0_Master_Slave_IRQn = 24u, /**< LPI2C0 Master Interrupt and Slave Interrupt */ + FLEXIO_IRQn = 25u, /**< FlexIO Interrupt */ + LPSPI0_IRQn = 26u, /**< LPSPI0 Interrupt */ + LPSPI1_IRQn = 27u, /**< LPSPI1 Interrupt */ + ADC0_IRQn = 28u, /**< ADC0 interrupt request. */ + CMP0_IRQn = 29u, /**< CMP0 interrupt request */ + LPUART1_RxTx_IRQn = 30u, /**< LPUART1 Transmit / Receive Interrupt */ + LPUART0_RxTx_IRQn = 31u /**< LPUART0 Transmit / Receive Interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers_S32K118 */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer for S32K118 + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer_S32K118 Device Peripheral Access Layer for S32K118 + * @{ + */ + +/* @brief This module covers memory mapped registers available on SoC */ + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + + +/** ADC - Size of Registers Arrays */ +#define ADC_SC1_COUNT 16u +#define ADC_R_COUNT 16u +#define ADC_CV_COUNT 2u + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[ADC_SC1_COUNT]; /**< ADC Status and Control Register 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ + __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x44 */ + __I uint32_t R[ADC_R_COUNT]; /**< ADC Data Result Registers, array offset: 0x48, array step: 0x4 */ + __IO uint32_t CV[ADC_CV_COUNT]; /**< Compare Value Registers, array offset: 0x88, array step: 0x4 */ + __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x90 */ + __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x94 */ + __IO uint32_t BASE_OFS; /**< BASE Offset Register, offset: 0x98 */ + __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x9C */ + __IO uint32_t USR_OFS; /**< USER Offset Correction Register, offset: 0xA0 */ + __IO uint32_t XOFS; /**< ADC X Offset Correction Register, offset: 0xA4 */ + __IO uint32_t YOFS; /**< ADC Y Offset Correction Register, offset: 0xA8 */ + __IO uint32_t G; /**< ADC Gain Register, offset: 0xAC */ + __IO uint32_t UG; /**< ADC User Gain Register, offset: 0xB0 */ + __IO uint32_t CLPS; /**< ADC General Calibration Value Register S, offset: 0xB4 */ + __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register 3, offset: 0xB8 */ + __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register 2, offset: 0xBC */ + __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register 1, offset: 0xC0 */ + __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register 0, offset: 0xC4 */ + __IO uint32_t CLPX; /**< ADC Plus-Side General Calibration Value Register X, offset: 0xC8 */ + __IO uint32_t CLP9; /**< ADC Plus-Side General Calibration Value Register 9, offset: 0xCC */ + __IO uint32_t CLPS_OFS; /**< ADC General Calibration Offset Value Register S, offset: 0xD0 */ + __IO uint32_t CLP3_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 3, offset: 0xD4 */ + __IO uint32_t CLP2_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 2, offset: 0xD8 */ + __IO uint32_t CLP1_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 1, offset: 0xDC */ + __IO uint32_t CLP0_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 0, offset: 0xE0 */ + __IO uint32_t CLPX_OFS; /**< ADC Plus-Side General Calibration Offset Value Register X, offset: 0xE4 */ + __IO uint32_t CLP9_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 9, offset: 0xE8 */ +} ADC_Type, *ADC_MemMapPtr; + + /** Number of instances of the ADC module. */ +#define ADC_INSTANCE_COUNT (1u) + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x4003B000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0 } + /** Number of interrupt vector arrays for the ADC module. */ +#define ADC_IRQS_ARR_COUNT (1u) + /** Number of interrupt channels for the ADC module. */ +#define ADC_IRQS_CH_COUNT (1u) +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* SC1 Bit Fields */ +#define ADC_SC1_ADCH_MASK 0x1Fu +#define ADC_SC1_ADCH_SHIFT 0u +#define ADC_SC1_ADCH_WIDTH 5u +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<VTOR} + +/* FTM module features */ + +/* @brief Number of PWM channels */ +#define FEATURE_FTM_CHANNEL_COUNT (8U) +/* @brief Number of fault channels */ +#define FTM_FEATURE_FAULT_CHANNELS (4U) +/* @brief Width of control channel */ +#define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH (8U) +/* @brief Output channel offset */ +#define FTM_FEATURE_OUTPUT_CHANNEL_OFFSET (16U) +/* @brief Max counter value */ +#define FTM_FEATURE_CNT_MAX_VALUE_U32 (0x0000FFFFU) +/* @brief Input capture for single shot */ +#define FTM_FEATURE_INPUT_CAPTURE_SINGLE_SHOT (2U) +/* @brief Dithering has supported on the generated PWM signals */ +#define FEATURE_FTM_HAS_SUPPORTED_DITHERING (1U) +/* @brief Number of interrupt vector for channels of the FTM module. */ +#define FEATURE_FTM_HAS_NUM_IRQS_CHANS (1U) + +/* LPIT module features */ + +/*! @brief Number of interrupt vector for channels of the LPIT module. */ +#define FEATURE_LPIT_HAS_NUM_IRQS_CHANS (1U) +/*! @brief Clock names for LPIT. */ +#define LPIT_CLOCK_NAMES {LPIT0_CLK} + +/* LPI2C module features */ + +/* @brief DMA instance used for LPI2C module */ +#define LPI2C_DMA_INSTANCE 0U + +/* @brief EDMA requests for LPI2C module. */ +#define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}} +/* @brief PCC clocks for LPI2C module. */ +#define LPI2C_PCC_CLOCKS {LPI2C0_CLK} + +/* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */ +#define LPI2C_HAS_FAST_PLUS_MODE (0U) +#define LPI2C_HAS_HIGH_SPEED_MODE (0U) +#define LPI2C_HAS_ULTRA_FAST_MODE (0U) + +/* LPI2C module features */ + +/* @brief DMA instance used for LPI2C module */ +#define LPI2C_DMA_INSTANCE 0U + +/* @brief EDMA requests for LPI2C module. */ +#define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}} +/* @brief PCC clocks for LPI2C module. */ +#define LPI2C_PCC_CLOCKS {LPI2C0_CLK} + +/* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */ +#define LPI2C_HAS_FAST_PLUS_MODE (0U) +#define LPI2C_HAS_HIGH_SPEED_MODE (0U) +#define LPI2C_HAS_ULTRA_FAST_MODE (0U) + +/* MSCM module features */ + +/* @brief Has interrupt router control registers (IRSPRCn). */ +#define FEATURE_MSCM_HAS_INTERRUPT_ROUTER (0) +/* @brief Has directed CPU interrupt routerregisters (IRCPxxx). */ +#define FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER (0) + +/* CSEc module features */ + +/*! @brief CSE_PRAM offset of the page length parameter used by the following +commands: CMD_ENC_ECB, CMD_ENC_CBC, CMD_DEC_ECB, CMD_DEC_CBC, CMD_MP_COMPRESS */ +#define FEATURE_CSEC_PAGE_LENGTH_OFFSET (0xEU) +/*! @brief CSE_PRAM offset of the message length parameter used by the following +commands: CMD_GENERATE_MAC, CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_MESSAGE_LENGTH_OFFSET (0xCU) +/*! @brief CSE_PRAM offset of the MAC length parameter used by the following +commands: CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_MAC_LENGTH_OFFSET (0x8U) +/*! @brief CSE_PRAM offset of the boot size parameter used by the following +commands: CMD_BOOT_DEFINE */ +#define FEATURE_CSEC_BOOT_SIZE_OFFSET (0x1CU) +/*! @brief CSE_PRAM offset of the boot flavor parameter used by the following +commands: CMD_BOOT_DEFINE */ +#define FEATURE_CSEC_BOOT_FLAVOR_OFFSET (0x1BU) +/*! @brief CSE_PRAM offset of the Flash start address parameter used by the +following commands: CMD_GENERATE_MAC, CMD_VERIFY_MAC (pointer method) */ +#define FEATURE_CSEC_FLASH_START_ADDRESS_OFFSET (0x10U) +/*! @brief CSE_PRAM offset of the verification status parameter used by the +following commands: CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_VERIFICATION_STATUS_OFFSET (0x14U) +/*! @brief CSE_PRAM offset of the error bits field contained by all commands */ +#define FEATURE_CSEC_ERROR_BITS_OFFSET (0x4U) +/*! @brief CSE_PRAM offset of the SREG parameter used by the following commands: +CMD_GET_ID */ +#define FEATURE_CSEC_SREG_OFFSET (0x2FU) + +/*! @brief CSE_PRAM offset of page 0 */ +#define FEATURE_CSEC_PAGE_0_OFFSET (0x0U) +/*! @brief CSE_PRAM offset of page 1 */ +#define FEATURE_CSEC_PAGE_1_OFFSET (0x10U) +/*! @brief CSE_PRAM offset of page 2 */ +#define FEATURE_CSEC_PAGE_2_OFFSET (0x20U) +/*! @brief CSE_PRAM offset of page 3 */ +#define FEATURE_CSEC_PAGE_3_OFFSET (0x30U) +/*! @brief CSE_PRAM offset of page 4 */ +#define FEATURE_CSEC_PAGE_4_OFFSET (0x40U) +/*! @brief CSE_PRAM offset of page 5 */ +#define FEATURE_CSEC_PAGE_5_OFFSET (0x50U) +/*! @brief CSE_PRAM offset of page 6 */ +#define FEATURE_CSEC_PAGE_6_OFFSET (0x60U) +/*! @brief CSE_PRAM offset of page 7 */ +#define FEATURE_CSEC_PAGE_7_OFFSET (0x70U) + +/* CRC module features */ + +/* @brief CRC module use for S32K. */ +#define FEATURE_CRC_DRIVER_SOFT_POLYNOMIAL +/* @brief Default CRC bit width */ +#define FEATURE_CRC_DEFAULT_WIDTH CRC_BITS_16 +/* @brief Default CRC read transpose */ +#define FEATURE_CRC_DEFAULT_READ_TRANSPOSE CRC_TRANSPOSE_NONE +/* @brief Default CRC write transpose */ +#define FEATURE_CRC_DEFAULT_WRITE_TRANSPOSE CRC_TRANSPOSE_NONE +/* @brief Default polynomial 0x1021U */ +#define FEATURE_CRC_DEFAULT_POLYNOMIAL (0x1021U) +/* @brief Default seed value is 0xFFFFU */ +#define FEATURE_CRC_DEFAULT_SEED (0xFFFFU) + +/* PORT module features */ +/*! @brief PORT Used for setting Pins */ +#define FEATURE_PINS_DRIVER_USING_PORT (1) +/* @brief Has control lock (register bit PCR[LK]). */ +#define FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FEATURE_PINS_HAS_OPEN_DRAIN (0) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FEATURE_PORT_HAS_DIGITAL_FILTER (1) +/* @brief Has trigger output to trigger other peripherals (register bit field PCR[IRQC] values). */ +#define FEATURE_PORT_HAS_TRIGGER_OUT (0) +/* @brief Has setting flag only (register bit field PCR[IRQC] values). */ +#define FEATURE_PORT_HAS_FLAG_SET_ONLY (0) +/* @brief Has over-current feature (register bit field PCR[OCIE] values). */ +#define FEATURE_PINS_HAS_OVER_CURRENT (0) +/* @brief Has pull resistor selection available. */ +#define FEATURE_PINS_HAS_PULL_SELECTION (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FEATURE_PINS_HAS_SLEW_RATE (0) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength (register bit PCR[DSE]). */ +#define FEATURE_PINS_HAS_DRIVE_STRENGTH (1) +/* @brief Has drive strength control bits*/ +#define FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL (0) +/* @brief Has port input disable control bits*/ +#define FEATURE_PORT_HAS_INPUT_DISABLE (0) +/* @brief SIM_CHIPCTL_ADC_INTERLEAVE_EN bit is not available */ +#define FEATURE_PINS_HAS_ADC_INTERLEAVE_EN (0) + +/* MPU module features */ + +/* @brief Specifies hardware revision level. */ +#define FEATURE_MPU_HARDWARE_REVISION_LEVEL (1U) +/* @brief Has process identifier support. */ +#define FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1U) +/* @brief Specifies total number of bus masters. */ +#define FEATURE_MPU_MASTER_COUNT (3U) +/* @brief Specifies maximum number of masters which have separated +privilege rights for user and supervisor mode accesses (e.g. master0~3 in S32K1xx). +*/ +#define FEATURE_MPU_MAX_LOW_MASTER_NUMBER (3U) +/* @brief Specifies maximum number of masters which have only +read and write permissions (e.g. master4~7 in S32K1xx). +*/ +#define FEATURE_MPU_MAX_HIGH_MASTER_NUMBER (7U) + +/* @brief Specifies number of set access control right bits for + masters which have separated privilege rights for user and + supervisor mode accesses (e.g. master0~3 in S32K1xx). +*/ +#define FEATURE_MPU_LOW_MASTER_CONTROL_WIDTH (6U) +/* @brief Specifies number of set access control right bits for + masters which have only read and write permissions(e.g. master4~7 in S32K1xx). +*/ +#define FEATURE_MPU_HIGH_MASTER_CONTROL_WIDTH (2U) + +/* @brief The MPU Logical Bus Master Number for core bus master. */ +#define FEATURE_MPU_MASTER_CORE (0U) +/* @brief The MPU Logical Bus Master Number for Debugger master. */ +#define FEATURE_MPU_MASTER_DEBUGGER (1U) +/* @brief The MPU Logical Bus Master Number for DMA master. */ +#define FEATURE_MPU_MASTER_DMA (2U) +/* @brief Specifies master number. */ +#define FEATURE_MPU_MASTER \ +{ \ + FEATURE_MPU_MASTER_CORE, /*!< CORE */ \ + FEATURE_MPU_MASTER_DEBUGGER, /*!< DEBUGGER */ \ + FEATURE_MPU_MASTER_DMA, /*!< DMA */ \ +} + +/* @brief Specifies total number of slave ports. */ +#define FEATURE_MPU_SLAVE_COUNT (2U) +/* @brief The MPU Slave Port Assignment for Flash Controller and boot ROM. */ +#define FEATURE_MPU_SLAVE_FLASH_BOOTROM (0U) +/* @brief The MPU Slave Port Assignment for SRAM, MTB, DWT and MCM. */ +#define FEATURE_MPU_SLAVE_SRAM_MTB_DWT_MCM (1U) +/* @brief The MPU Slave Port mask. */ +#define FEATURE_MPU_SLAVE_MASK (0xC0000000U) +#define FEATURE_MPU_SLAVE_SHIFT (30u) +#define FEATURE_MPU_SLAVE_WIDTH (2u) +#define FEATURE_MPU_SLAVE(x) (((uint32_t)(((uint32_t)(x))<> (uint32_t)FEATURE_DMA_CH_WIDTH) +/* @brief DMA virtual channel to channel */ +#define FEATURE_DMA_VCH_TO_CH(x) ((x) & ((uint32_t)FEATURE_DMA_CHANNELS - 1U)) +/* @brief DMA supports the following particular channel priorities: */ +#define FEATURE_DMA_4_CH_PRIORITIES +/* @brief DMA supports bus bandwidth control. */ +#define FEATURE_DMA_ENGINE_STALL + +/* DMAMUX module features */ + +/* @brief DMAMUX peripheral is available in silicon. */ +#define FEATURE_DMAMUX_AVAILABLE +/* @brief Number of DMA channels. */ +#define FEATURE_DMAMUX_CHANNELS (4U) +/* @brief Has the periodic trigger capability */ +#define FEATURE_DMAMUX_HAS_TRIG (1) +/* @brief Conversion from request source to the actual DMAMUX channel */ +#define FEATURE_DMAMUX_REQ_SRC_TO_CH(x) (x) +/* @brief Mapping between request source and DMAMUX instance */ +#define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x) (0U) +/* @brief Conversion from eDMA channel index to DMAMUX channel. */ +#define FEATURE_DMAMUX_DMA_CH_TO_CH(x) (x) +/* @brief Conversion from DMAMUX channel DMAMUX register index. */ +#define FEATURE_DMAMUX_CHN_REG_INDEX(x) (x) +/* @brief Clock names for DMAMUX. */ +#define FEATURE_DMAMUX_CLOCK_NAMES {DMAMUX0_CLK} + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum { + EDMA_REQ_DISABLED = 0U, + EDMA_REQ_LPUART0_RX = 2U, + EDMA_REQ_LPUART0_TX = 3U, + EDMA_REQ_LPUART1_RX = 4U, + EDMA_REQ_LPUART1_TX = 5U, + EDMA_REQ_FLEXIO_SHIFTER0 = 10U, + EDMA_REQ_FLEXIO_SHIFTER1 = 11U, + EDMA_REQ_FLEXIO_SHIFTER2 = 12U, + EDMA_REQ_FLEXIO_SHIFTER3 = 13U, + EDMA_REQ_LPSPI0_RX = 14U, + EDMA_REQ_LPSPI0_TX = 15U, + EDMA_REQ_LPSPI1_RX = 16U, + EDMA_REQ_LPSPI1_TX = 17U, + EDMA_REQ_FTM1_CHANNEL_0 = 20U, + EDMA_REQ_FTM1_CHANNEL_1 = 21U, + EDMA_REQ_FTM1_CHANNEL_2 = 22U, + EDMA_REQ_FTM1_CHANNEL_3 = 23U, + EDMA_REQ_FTM1_CHANNEL_4 = 24U, + EDMA_REQ_FTM1_CHANNEL_5 = 25U, + EDMA_REQ_FTM1_CHANNEL_6 = 26U, + EDMA_REQ_FTM1_CHANNEL_7 = 27U, + EDMA_REQ_FTM0_OR_CH0_CH7 = 36U, + EDMA_REQ_ADC0 = 42U, + EDMA_REQ_LPI2C0_RX = 44U, + EDMA_REQ_LPI2C0_TX = 45U, + EDMA_REQ_PDB0 = 46U, + EDMA_REQ_CMP0 = 48U, + EDMA_REQ_PORTA = 49U, + EDMA_REQ_PORTB = 50U, + EDMA_REQ_PORTC = 51U, + EDMA_REQ_PORTD = 52U, + EDMA_REQ_PORTE = 53U, + EDMA_REQ_FLEXCAN0 = 54U, + EDMA_REQ_LPTMR0 = 59U, + EDMA_REQ_DMAMUX_ALWAYS_ENABLED0 = 62U, + EDMA_REQ_DMAMUX_ALWAYS_ENABLED1 = 63U +} dma_request_source_t; + + +/* TRGMUX module features */ +/*! + * @brief Enumeration for trigger source module of TRGMUX + * + * Describes all possible inputs (trigger sources) of the TRGMUX IP + * This enumeration depends on the supported instances in device + */ +enum trgmux_trigger_source_e +{ + TRGMUX_TRIG_SOURCE_DISABLED = 0U, + TRGMUX_TRIG_SOURCE_VDD = 1U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN0 = 2U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN1 = 3U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN2 = 4U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN3 = 5U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN4 = 6U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN5 = 7U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN6 = 8U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN7 = 9U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN8 = 10U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN9 = 11U, + TRGMUX_TRIG_SOURCE_CMP0_OUT = 14U, + TRGMUX_TRIG_SOURCE_LPIT_CH0 = 17U, + TRGMUX_TRIG_SOURCE_LPIT_CH1 = 18U, + TRGMUX_TRIG_SOURCE_LPIT_CH2 = 19U, + TRGMUX_TRIG_SOURCE_LPIT_CH3 = 20U, + TRGMUX_TRIG_SOURCE_LPTMR0 = 21U, + TRGMUX_TRIG_SOURCE_FTM0_INIT_TRIG = 22U, + TRGMUX_TRIG_SOURCE_FTM0_EXT_TRIG = 23U, + TRGMUX_TRIG_SOURCE_FTM1_INIT_TRIG = 24U, + TRGMUX_TRIG_SOURCE_FTM1_EXT_TRIG = 25U, + TRGMUX_TRIG_SOURCE_ADC0_SC1A_COCO = 30U, + TRGMUX_TRIG_SOURCE_ADC0_SC1B_COCO = 31U, + TRGMUX_TRIG_SOURCE_PDB0_CH0_TRIG = 34U, + TRGMUX_TRIG_SOURCE_PDB0_PULSE_OUT = 36U, + TRGMUX_TRIG_SOURCE_RTC_ALARM = 43U, + TRGMUX_TRIG_SOURCE_RTC_SECOND = 44U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG0 = 45U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG1 = 46U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG2 = 47U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG3 = 48U, + TRGMUX_TRIG_SOURCE_LPUART0_RX_DATA = 49U, + TRGMUX_TRIG_SOURCE_LPUART0_TX_DATA = 50U, + TRGMUX_TRIG_SOURCE_LPUART0_RX_IDLE = 51U, + TRGMUX_TRIG_SOURCE_LPUART1_RX_DATA = 52U, + TRGMUX_TRIG_SOURCE_LPUART1_TX_DATA = 53U, + TRGMUX_TRIG_SOURCE_LPUART1_RX_IDLE = 54U, + TRGMUX_TRIG_SOURCE_LPI2C0_MASTER_TRIG = 55U, + TRGMUX_TRIG_SOURCE_LPI2C0_SLAVE_TRIG = 56U, + TRGMUX_TRIG_SOURCE_LPSPI0_FRAME = 59U, + TRGMUX_TRIG_SOURCE_LPSPI0_RX_DATA = 60U, + TRGMUX_TRIG_SOURCE_LPSPI1_FRAME = 61U, + TRGMUX_TRIG_SOURCE_LPSPI1_RX_DATA = 62U, + TRGMUX_TRIG_SOURCE_SIM_SW_TRIG = 63U, +}; + +/*! + * @brief Enumeration for target module of TRGMUX + * + * Describes all possible outputs (target modules) of the TRGMUX IP + * This enumeration depends on the supported instances in device + */ +enum trgmux_target_module_e +{ + TRGMUX_TARGET_MODULE_DMA_CH0 = 0U, + TRGMUX_TARGET_MODULE_DMA_CH1 = 1U, + TRGMUX_TARGET_MODULE_DMA_CH2 = 2U, + TRGMUX_TARGET_MODULE_DMA_CH3 = 3U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT0 = 4U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT1 = 5U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT2 = 6U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT3 = 7U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT4 = 8U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT5 = 9U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA0 = 12U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA1 = 13U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA2 = 14U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA3 = 15U, + TRGMUX_TARGET_MODULE_CMP0_SAMPLE = 28U, + TRGMUX_TARGET_MODULE_FTM0_HWTRIG0 = 40U, + TRGMUX_TARGET_MODULE_FTM0_FAULT0 = 41U, + TRGMUX_TARGET_MODULE_FTM0_FAULT1 = 42U, + TRGMUX_TARGET_MODULE_FTM0_FAULT2 = 43U, + TRGMUX_TARGET_MODULE_FTM1_HWTRIG0 = 44U, + TRGMUX_TARGET_MODULE_FTM1_FAULT0 = 45U, + TRGMUX_TARGET_MODULE_FTM1_FAULT1 = 46U, + TRGMUX_TARGET_MODULE_FTM1_FAULT2 = 47U, + TRGMUX_TARGET_MODULE_PDB0_TRG_IN = 56U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM0 = 68U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM1 = 69U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM2 = 70U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM3 = 71U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH0 = 72U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH1 = 73U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH2 = 74U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH3 = 75U, + TRGMUX_TARGET_MODULE_LPUART0_TRG = 76U, + TRGMUX_TARGET_MODULE_LPUART1_TRG = 80U, + TRGMUX_TARGET_MODULE_LPI2C0_TRG = 84U, + TRGMUX_TARGET_MODULE_LPSPI0_TRG = 92U, + TRGMUX_TARGET_MODULE_LPSPI1_TRG = 96U, + TRGMUX_TARGET_MODULE_LPTMR0_ALT0 = 100U, +}; + +/* @brief Constant array storing the value of all TRGMUX output(target module) identifiers */ +#define FEATURE_TRGMUX_TARGET_MODULE \ +{ \ + TRGMUX_TARGET_MODULE_DMA_CH0, \ + TRGMUX_TARGET_MODULE_DMA_CH1, \ + TRGMUX_TARGET_MODULE_DMA_CH2, \ + TRGMUX_TARGET_MODULE_DMA_CH3, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT0, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT1, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT2, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT3, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT4, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT5, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA0, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA1, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA2, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA3, \ + TRGMUX_TARGET_MODULE_CMP0_SAMPLE, \ + TRGMUX_TARGET_MODULE_FTM0_HWTRIG0, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT0, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT1, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT2, \ + TRGMUX_TARGET_MODULE_FTM1_HWTRIG0, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT0, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT1, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT2, \ + TRGMUX_TARGET_MODULE_PDB0_TRG_IN, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM0, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM1, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM2, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM3, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH0, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH1, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH2, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH3, \ + TRGMUX_TARGET_MODULE_LPUART0_TRG, \ + TRGMUX_TARGET_MODULE_LPUART1_TRG, \ + TRGMUX_TARGET_MODULE_LPI2C0_TRG, \ + TRGMUX_TARGET_MODULE_LPSPI0_TRG, \ + TRGMUX_TARGET_MODULE_LPSPI1_TRG, \ + TRGMUX_TARGET_MODULE_LPTMR0_ALT0 \ +} + + +/* LPSPI module features */ +/* @brief Initial value for state structure */ +#define FEATURE_LPSPI_STATE_STRUCTURES_NULL {NULL, NULL} +/* @brief Clock indexes for LPSPI clock */ +#define FEATURE_LPSPI_CLOCKS_NAMES {LPSPI0_CLK, LPSPI1_CLK}; + +/* FlexIO module features */ + +/* @brief Define the maximum number of shifters for any FlexIO instance. */ +#define FEATURE_FLEXIO_MAX_SHIFTER_COUNT (4U) +/* @brief Define DMA request names for Flexio. */ +#define FEATURE_FLEXIO_DMA_REQ_0 EDMA_REQ_FLEXIO_SHIFTER0 +#define FEATURE_FLEXIO_DMA_REQ_1 EDMA_REQ_FLEXIO_SHIFTER1 +#define FEATURE_FLEXIO_DMA_REQ_2 EDMA_REQ_FLEXIO_SHIFTER2 +#define FEATURE_FLEXIO_DMA_REQ_3 EDMA_REQ_FLEXIO_SHIFTER3 + +/* LPUART module features */ + +/* @brief Has extended data register ED. */ +#define FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FEATURE_LPUART_FIFO_SIZE (4U) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits. */ +#define FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Flag clearance mask for STAT register. */ +#define FEATURE_LPUART_STAT_REG_FLAGS_MASK (0xC01FC000U) +/* @brief Flag clearance mask for FIFO register. */ +#define FEATURE_LPUART_FIFO_REG_FLAGS_MASK (0x00030000U) +/* @brief Reset mask for FIFO register. */ +#define FEATURE_LPUART_FIFO_RESET_MASK (0x0003C000U) +/* @brief Default oversampling ratio. */ +#define FEATURE_LPUART_DEFAULT_OSR (0x0FUL) +/* @brief Default baud rate modulo divisor. */ +#define FEATURE_LPUART_DEFAULT_SBR (0x04UL) +/* @brief Clock names for LPUART. */ +#define LPUART_CLOCK_NAMES {LPUART0_CLK, LPUART1_CLK} + +/* ADC module features */ + +/*! @brief ADC feature flag for extended number of SC1 and R registers, + * generically named 'alias registers' */ +#define FEATURE_ADC_HAS_EXTRA_NUM_REGS (0) + +#define NUMBER_OF_ALT_CLOCKS ADC_CLK_ALT_1 +/*! @brief ADC feature flag for defining number of external ADC channels. + * If each ADC instance has different number of external channels, then + * this define is set with the maximum value. */ +#define FEATURE_ADC_MAX_NUM_EXT_CHANS (16) +#define FEATURE_ADC_HAS_CHANNEL_2 (1) +#define FEATURE_ADC_HAS_CHANNEL_8 (1) +#define ADC_CLOCKS {ADC0_CLK} +/*! @brief ADC number of control channels */ +#if FEATURE_ADC_HAS_EXTRA_NUM_REGS +#define ADC_CTRL_CHANS_COUNT ADC_aSC1_COUNT +#else +#define ADC_CTRL_CHANS_COUNT ADC_SC1_COUNT +#endif /* FEATURE_ADC_HAS_EXTRA_NUM_REGS */ + +/*! @brief ADC default Sample Time from RM */ +#define ADC_DEFAULT_SAMPLE_TIME (0x0CU) +/*! @brief ADC default User Gain from RM */ +#define ADC_DEFAULT_USER_GAIN (0x04U) +/* @brief Max of adc clock frequency */ +#define ADC_CLOCK_FREQ_MAX_RUNTIME (50000000u) +/* @brief Min of adc clock frequency */ +#define ADC_CLOCK_FREQ_MIN_RUNTIME (2000000u) + +/* CAN module features */ + +/* @brief Frames available in Rx FIFO flag shift */ +#define FEATURE_CAN_RXFIFO_FRAME_AVAILABLE (5U) +/* @brief Rx FIFO warning flag shift */ +#define FEATURE_CAN_RXFIFO_WARNING (6U) +/* @brief Rx FIFO overflow flag shift */ +#define FEATURE_CAN_RXFIFO_OVERFLOW (7U) +/* @brief Has Flexible Data Rate for CAN0 */ +#define FEATURE_CAN0_HAS_FD (1) +/* @brief Maximum number of Message Buffers supported for payload size 8 for CAN0 */ +#define FEATURE_CAN0_MAX_MB_NUM (32U) +/* @brief Has PE clock source select (bit field CAN_CTRL1[CLKSRC]). */ +#define FEATURE_CAN_HAS_PE_CLKSRC_SELECT (1) +/* @brief Has DMA enable (bit field MCR[DMA]). */ +#define FEATURE_CAN_HAS_DMA_ENABLE (1) +/* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */ +#define FEATURE_CAN_MAX_MB_NUM (32U) +/* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */ +#define FEATURE_CAN_MAX_MB_NUM_ARRAY { FEATURE_CAN0_MAX_MB_NUM } +/* @brief Has Pretending Networking mode */ +#define FEATURE_CAN_HAS_PRETENDED_NETWORKING (1) +/* @brief Has Stuff Bit Count Enable Bit */ +#define FEATURE_CAN_HAS_STFCNTEN_ENABLE (0) +/* @brief Has ISO CAN FD Enable Bit */ +#define FEATURE_CAN_HAS_ISOCANFDEN_ENABLE (1) +/* @brief Has Message Buffer Data Size Region 1 */ +#define FEATURE_CAN_HAS_MBDSR1 (0) +/* @brief Has Message Buffer Data Size Region 2 */ +#define FEATURE_CAN_HAS_MBDSR2 (0) +/* @brief DMA hardware requests for all FlexCAN instances */ +#define FEATURE_CAN_EDMA_REQUESTS { EDMA_REQ_FLEXCAN0 } + +/* @brief Maximum number of Message Buffers IRQs */ +#define FEATURE_CAN_MB_IRQS_MAX_COUNT (2U) +/* @brief Message Buffers IRQs */ +#define FEATURE_CAN_MB_IRQS { CAN_ORed_0_15_MB_IRQS, \ + CAN_ORed_16_31_MB_IRQS } +/* @brief Has Wake Up Irq channels (CAN_Wake_Up_IRQS_CH_COUNT > 0u) */ +#define FEATURE_CAN_HAS_WAKE_UP_IRQ (1) +/* @brief Has Self Wake Up mode */ +#define FEATURE_CAN_HAS_SELF_WAKE_UP (0) +/* @brief Has Flexible Data Rate */ +#define FEATURE_CAN_HAS_FD (1) +/* @brief Clock name for the PE oscillator clock source */ +#define FEATURE_CAN_PE_OSC_CLK_NAME SOSC_CLK +/* @bried FlexCAN has Detection And Correction of Memory Errors */ +#define FEATURE_CAN_HAS_MEM_ERR_DET (0) + +/* LPTMR module features */ + +/* @brief LPTMR pulse counter input options */ +#define FEATURE_LPTMR_HAS_INPUT_ALT1_SELECTION (1U) + +/* OSIF module features */ + +#define FEATURE_OSIF_USE_SYSTICK (1) +#define FEATURE_OSIF_USE_PIT (0) +#define FEATURE_OSIF_FREERTOS_ISR_CONTEXT_METHOD (1) /* Cortex M device */ + +/* PDB module features */ + +/* @brief PDB has back-to-back at instance level */ +#define FEATURE_PDB_HAS_INSTANCE_BACKTOBACK (0) + +#endif /* S32K118_FEATURES_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/devassert.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/devassert.h new file mode 100644 index 00000000..243c8d45 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/devassert.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DEVASSERT_H +#define DEVASSERT_H + +#include + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced. + * The macro is defined to be used by drivers to validate input parameters and can be disabled. + * + * @section [global] + * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro defined. + * The macros are used to validate input parameters to driver functions. + * + */ + +/** +\page Error_detection_and_reporting Error detection and reporting + +S32 SDK drivers can use a mechanism to validate data coming from upper software layers (application code) by performing +a number of checks on input parameters' range or other invariants that can be statically checked (not dependent on +runtime conditions). A failed validation is indicative of a software bug in application code, therefore it is important +to use this mechanism during development. + +The validation is performed by using DEV_ASSERT macro. +A default implementation of this macro is provided in this file. However, application developers can provide their own +implementation in a custom file. This requires defining the CUSTOM_DEVASSERT symbol with the specific file name in the +project configuration (for example: -DCUSTOM_DEVASSERT="custom_devassert.h") + +The default implementation accommodates two behaviors, based on DEV_ERROR_DETECT symbol: + - When DEV_ERROR_DETECT symbol is defined in the project configuration (for example: -DDEV_ERROR_DETECT), the validation + performed by the DEV_ASSERT macro is enabled, and a failed validation triggers a software breakpoint and further execution is + prevented (application spins in an infinite loop) + This configuration is recommended for development environments, as it prevents further execution and allows investigating + potential problems from the point of error detection. + - When DEV_ERROR_DETECT symbol is not defined, the DEV_ASSERT macro is implemented as no-op, therefore disabling all validations. + This configuration can be used to eliminate the overhead of development-time checks. + +It is the application developer's responsibility to decide the error detection strategy for production code: one can opt to +disable development-time checking altogether (by not defining DEV_ERROR_DETECT symbol), or one can opt to keep the checks +in place and implement a recovery mechanism in case of a failed validation, by defining CUSTOM_DEVASSERT to point +to the file containing the custom implementation. +*/ + +#if defined (CUSTOM_DEVASSERT) + /* If the CUSTOM_DEVASSERT symbol is defined, then add the custom implementation */ + #include CUSTOM_DEVASSERT +#elif defined (DEV_ERROR_DETECT) + /* Implement default assert macro */ +static inline void DevAssert(volatile bool x) +{ + if(x) { } else { BKPT_ASM; for(;;) {} } +} + #define DEV_ASSERT(x) DevAssert(x) +#else + /* Assert macro does nothing */ + #define DEV_ASSERT(x) ((void)0) +#endif + +#endif /* DEVASSERT_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/device_registers.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/device_registers.h new file mode 100644 index 00000000..583a35d5 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/device_registers.h @@ -0,0 +1,67 @@ +/* +** ################################################################### +** Abstract: +** Common include file for CMSIS register access layer headers. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** ################################################################### +*/ + +#ifndef DEVICE_REGISTERS_H +#define DEVICE_REGISTERS_H + +/** +* @page misra_violations MISRA-C:2012 violations +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced. +* The macro defines the device currently in use and may be used by components for specific checks. +* +*/ + + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ + +#if defined(CPU_S32K118) + + #define S32K11x_SERIES + + /* Specific core definitions */ + #include "s32_core_cm0.h" + /* Register definitions */ + #include "S32K118.h" + /* CPU specific feature definitions */ + #include "S32K118_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#include "devassert.h" + +#endif /* DEVICE_REGISTERS_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/s32_core_cm0.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/s32_core_cm0.h new file mode 100644 index 00000000..2dcd6e17 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/s32_core_cm0.h @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/*! + * @file s32_core_cm0.h + * + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro + * Function-like macros are used instead of inline functions in order to ensure + * that the performance will not be decreased if the functions will not be + * inlined by the compiler. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. + * The macros defined are used only on some of the drivers, so this might be reported + * when the analysis is made only on one driver. + */ + +/* + * Tool Chains: + * GNUC flag is defined also by ARM compiler - it shows the current major version of the compatible GCC version + * __GNUC__ : GNU Compiler Collection + * __ghs__ : Green Hills ARM Compiler + * __ICCARM__ : IAR ARM Compiler + * __DCC__ : Wind River Diab Compiler + * __ARMCC_VERSION : ARM Compiler + */ + +#if !defined (CORE_CM0_H) +#define CORE_CM0_H + + +#ifdef __cplusplus +extern "C" { +#endif + +/** \brief BKPT_ASM + * + * Macro to be used to trigger an debug interrupt + */ +#if defined ( __DCC__ ) +#define BKPT_ASM __asm ("BKPT 0\n\t") +#else +#define BKPT_ASM __asm ("BKPT #0\n\t") +#endif + +/** \brief Enable interrupts + */ +#if defined (__GNUC__) +#define ENABLE_INTERRUPTS() __asm volatile ("cpsie i" : : : "memory"); +#elif defined ( __DCC__ ) +#define ENABLE_INTERRUPTS() __asm (".short 0xb662"); +#else +#define ENABLE_INTERRUPTS() __asm("cpsie i") +#endif + + +/** \brief Disable interrupts + */ +#if defined (__GNUC__) +#define DISABLE_INTERRUPTS() __asm volatile ("cpsid i" : : : "memory"); +#elif defined ( __DCC__ ) +#define DISABLE_INTERRUPTS() __asm (".short 0xb672"); +#else +#define DISABLE_INTERRUPTS() __asm("cpsid i") +#endif + + +/** \brief Enter low-power standby state + * WFI (Wait For Interrupt) makes the processor suspend execution (Clock is stopped) until an IRQ interrupts. + */ +#if defined (__GNUC__) +#define STANDBY() __asm volatile ("wfi") +#elif defined ( __DCC__ ) +#define STANDBY() __asm (".short 0xbf30"); +#else +#define STANDBY() __asm ("wfi") +#endif + +/** \brief No-op + */ +#define NOP() __asm volatile ("nop") + + +/** \brief Reverse byte order in a word. + * ARM Documentation Cortex-M0 Devices Generic User Guide + * Accordingly to 3.5.7. REV, REV16, and REVSH + * Restriction "This function requires low registers R0-R7 register" + */ +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ARMCC_VERSION) +#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=l" (b) : "l" (a)) +#elif defined (__ghs__) +#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=r" (b) : "r" (a)) +#else +#define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \ + | ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U)) +#endif + +/** \brief Reverse byte order in each halfword independently. + * ARM Documentation Cortex-M0 Devices Generic User Guide + * Accordingly to 3.5.7. REV, REV16, and REVSH + * Restriction "This function requires low registers R0-R7 register" + */ +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ARMCC_VERSION) +#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=l" (b) : "l" (a)) +#elif defined (__ghs__) +#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=r" (b) : "r" (a)) +#else +#define REV_BYTES_16(a, b) (b = ((a & 0xFF000000U) >> 8U) | ((a & 0xFF0000U) << 8U) \ + | ((a & 0xFF00U) >> 8U) | ((a & 0xFFU) << 8U)) +#endif + +/** \brief Places a function in RAM. + */ +#if defined ( __GNUC__ ) || defined (__ARMCC_VERSION) + #define START_FUNCTION_DECLARATION_RAMSECTION + #define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram"))); +#elif defined ( __ghs__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("ghs callmode=far") + #define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));\ + _Pragma("ghs callmode=default") +#elif defined ( __ICCARM__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION __ramfunc + #define END_FUNCTION_DECLARATION_RAMSECTION ; +#elif defined ( __DCC__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("section CODE \".code_ram\" \"\" far-absolute") \ + _Pragma("use_section CODE") + #define END_FUNCTION_DECLARATION_RAMSECTION ; \ + _Pragma("section CODE \".text\"") +#else + /* Keep compatibility with software analysis tools */ + #define START_FUNCTION_DECLARATION_RAMSECTION + #define END_FUNCTION_DECLARATION_RAMSECTION ; +#endif + + /* For GCC, IAR, GHS, Diab and ARMC there is no need to specify the section when + defining a function, it is enough to specify it at the declaration. This + also enables compatibility with software analysis tools. */ + #define START_FUNCTION_DEFINITION_RAMSECTION + #define END_FUNCTION_DEFINITION_RAMSECTION + +#if defined (__ICCARM__) + #define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_suppress=Ta022") + #define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_default=Ta022") +#else + #define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL + #define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL +#endif + +/** \brief Get Core ID + * + * GET_CORE_ID returns the processor identification number for cm0 + */ +#define GET_CORE_ID() 0U + +/** \brief Data alignment. + */ +#if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION) + #define ALIGNED(x) __attribute__((aligned(x))) +#elif defined ( __ICCARM__ ) + #define stringify(s) tostring(s) + #define tostring(s) #s + #define ALIGNED(x) _Pragma(stringify(data_alignment=x)) +#else + /* Keep compatibility with software analysis tools */ + #define ALIGNED(x) +#endif + +/** \brief Endianness. + */ +#define CORE_LITTLE_ENDIAN + +#ifdef __cplusplus +} +#endif + +#endif /* CORE_CM0_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/system_S32K118.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/system_S32K118.c new file mode 100644 index 00000000..868b365b --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/system_S32K118.c @@ -0,0 +1,176 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * An object with static storage duration declared at block scope cannot be + * accessed directly from outside the block. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed + * between a pointer to object and an integer type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed + * between pointer to void and an arithmetic type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. + * Function is defined for usage by application code. + * + */ + +#include "device_registers.h" +#include "system_S32K118.h" +#include "stdbool.h" + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/*FUNCTION********************************************************************** + * + * Function Name : SystemInit + * Description : This function disables the watchdog, enables FPU + * and the power mode protection if the corresponding feature macro + * is enabled. SystemInit is called from startup_device file. + * + * Implements : SystemInit_Activity + *END**************************************************************************/ +void SystemInit(void) +{ +/**************************************************************************/ +/* WDOG DISABLE*/ +/**************************************************************************/ + +#if (DISABLE_WDOG) + /* Write of the WDOG unlock key to CNT register, must be done in order to allow any modifications*/ + WDOG->CNT = (uint32_t ) FEATURE_WDOG_UNLOCK_VALUE; + /* The dummy read is used in order to make sure that the WDOG registers will be configured only + * after the write of the unlock value was completed. */ + (void)WDOG->CNT; + + /* Initial write of WDOG configuration register: + * enables support for 32-bit refresh/unlock command write words, + * clock select from LPO, update enable, watchdog disabled */ + WDOG->CS = (uint32_t ) ( (1UL << WDOG_CS_CMD32EN_SHIFT) | + (FEATURE_WDOG_CLK_FROM_LPO << WDOG_CS_CLK_SHIFT) | + (0U << WDOG_CS_EN_SHIFT) | + (1U << WDOG_CS_UPDATE_SHIFT) ); + + /* Configure timeout */ + WDOG->TOVAL = (uint32_t )0xFFFF; +#endif /* (DISABLE_WDOG) */ +} + +/*FUNCTION********************************************************************** + * + * Function Name : SystemCoreClockUpdate + * Description : This function must be called whenever the core clock is changed + * during program execution. It evaluates the clock register settings and calculates + * the current core clock. + * + * Implements : SystemCoreClockUpdate_Activity + *END**************************************************************************/ +void SystemCoreClockUpdate(void) +{ + uint32_t SCGOUTClock = 0U; /* Variable to store output clock frequency of the SCG module */ + uint32_t regValue; /* Temporary variable */ + uint32_t divider; + bool validSystemClockSource = true; + + divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U; + + switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) + { + case 0x1: + /* System OSC */ + SCGOUTClock = CPU_XTAL_CLK_HZ; + break; + case 0x2: + /* Slow IRC */ + regValue = (SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT; + if (regValue != 0UL) + { + SCGOUTClock = FEATURE_SCG_SIRC_HIGH_RANGE_FREQ; + } + else + { + validSystemClockSource = false; + } + break; + case 0x3: + /* Fast IRC */ + regValue = (SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT; + if (regValue == 0x0UL) + { + SCGOUTClock = FEATURE_SCG_FIRC_FREQ0; + } + else + { + validSystemClockSource = false; + } + break; + default: + validSystemClockSource = false; + break; + } + + if (validSystemClockSource == true) + { + SystemCoreClock = (SCGOUTClock / divider); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : SystemSoftwareReset + * Description : This function is used to initiate a system reset + * + * Implements : SystemSoftwareReset_Activity + *END**************************************************************************/ +void SystemSoftwareReset(void) +{ + uint32_t regValue; + + /* Read Application Interrupt and Reset Control Register */ + regValue = S32_SCB->AIRCR; + + /* Clear register key */ + regValue &= ~( S32_SCB_AIRCR_VECTKEY_MASK); + + /* Configure System reset request bit and Register Key */ + regValue |= S32_SCB_AIRCR_VECTKEY(FEATURE_SCB_VECTKEY); + regValue |= S32_SCB_AIRCR_SYSRESETREQ(0x1u); + + /* Write computed register value */ + S32_SCB->AIRCR = regValue; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/system_S32K118.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/system_S32K118.h new file mode 100644 index 00000000..6e98f97f --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/system_S32K118.h @@ -0,0 +1,105 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*! @addtogroup soc_support_S32K118*/ +/*! @{*/ + +/*! + * @file system_S32K118.h + * @brief Device specific configuration file for S32K118 + */ + +#ifndef SYSTEM_S32K118_H_ +#define SYSTEM_S32K118_H_ /**< Symbol preventing repeated inclusion */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** + * CPU Settings. + *****************************************************************************/ + +/* Watchdog disable */ +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +/* Value of the external crystal or oscillator clock frequency in Hz */ +#ifndef CPU_XTAL_CLK_HZ + #define CPU_XTAL_CLK_HZ 8000000u +#endif + +/* Value of the fast internal oscillator clock frequency in Hz */ +#ifndef CPU_INT_FAST_CLK_HZ + #define CPU_INT_FAST_CLK_HZ 48000000u +#endif + +/* Default System clock value */ +#ifndef DEFAULT_SYSTEM_CLOCK + #define DEFAULT_SYSTEM_CLOCK 48000000u +#endif + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the SoC. + * + * This function disables the watchdog. + * if the corresponding feature macro is enabled. + * SystemInit is called from startup_device file. + */ +void SystemInit(void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + * This function must be called when user does not want to use clock manager component. + * If clock manager is used, the CLOCK_SYS_GetFreq function must be used with CORE_CLOCK + * parameter. + * + */ +void SystemCoreClockUpdate(void); + +/** + * @brief Initiates a system reset. + * + * This function is used to initiate a system reset + */ +void SystemSoftwareReset(void); + +#ifdef __cplusplus +} +#endif + +/*! @}*/ +#endif /* #if !defined(SYSTEM_S32K118_H_) */ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/main.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/main.c new file mode 100644 index 00000000..58518ee6 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/main.c @@ -0,0 +1,189 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/main.c +* \brief Bootloader application source file. +* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "device_registers.h" /* device registers */ +#include "system_S32K118.h" /* device sconfiguration */ + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static void Init(void); +static void SystemClockConfig(void); + + +/************************************************************************************//** +** \brief This is the entry point for the bootloader application and is called +** by the reset interrupt vector after the C-startup routines executed. +** \return Program return code. +** +****************************************************************************************/ +int main(void) +{ + /* Initialize the microcontroller. */ + Init(); + /* Initialize the bootloader. */ + BootInit(); + + /* Start the infinite program loop. */ + while (1) + { + /* Run the bootloader task. */ + BootTask(); + } + + /* Program should never get here. */ + return 0; +} /*** end of main ***/ + + +/************************************************************************************//** +** \brief Initializes the microcontroller. +** \return none. +** +****************************************************************************************/ +static void Init(void) +{ + /* Configure the system clock. */ + SystemClockConfig(); + /* Enable the peripheral clock for the ports that are used. */ + PCC->PCCn[PCC_PORTB_INDEX] |= PCC_PCCn_CGC_MASK; + PCC->PCCn[PCC_PORTD_INDEX] |= PCC_PCCn_CGC_MASK; + PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK; + + /* Configure SW2 (PD3) GPIO pin for (optional) backdoor entry input. */ + /* Input GPIO pin configuration. PD3 = GPIO, MUX = ALT1. */ + PORTD->PCR[3] |= PORT_PCR_MUX(1); + /* Disable pull device, as SW2 already has a pull down resistor on the board. */ + PORTD->PCR[3] &= ~PORT_PCR_PE(1); + /* Configure and enable Port D pin 3 GPIO as digital input */ + PTD->PDDR &= ~GPIO_PDDR_PDD(1 << 3U); + PTD->PIDR &= ~GPIO_PIDR_PID(1 << 3U); +#if (BOOT_COM_RS232_ENABLE > 0) + /* UART RX GPIO pin configuration. PB0 = UART0 RX, MUX = ALT2. */ + PORTB->PCR[0] |= PORT_PCR_MUX(2); + /* UART TX GPIO pin configuration. PB1 = UART0 TX, MUX = ALT2. */ + PORTB->PCR[1] |= PORT_PCR_MUX(2); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) + /* CAN RX GPIO pin configuration. PE4 = CAN0 RX, MUX = ALT5. */ + PORTE->PCR[4] |= PORT_PCR_MUX(5); + /* CAN TX GPIO pin configuration. PE5 = CAN0 TX, MUX = ALT5. */ + PORTE->PCR[5] |= PORT_PCR_MUX(5); +#endif +} /*** end of Init ***/ + + +/************************************************************************************//** +** \brief System Clock Configuration. This code was derived from a S32 Design Studio +** example program. It enables the SOCS (40 MHz external crystal), FIRC (48 +** MHz internal) and SIRC (8 MHz internal). The FIRC is used as a source for +** the system clock and configures the normal RUN mode for the following clock +** settings: +** - CORE_CLK = 48 MHz +** - SYS_CLK = 48 MHz +** - BUS_CLK = 48 MHz +** - FLASH_CLK = 24 MHz +** - SOSCDIV1_CLK = 40 MHz +** - SOSCDIV2_CLK = 40 MHz +** - FIRCDIV1_CLK = 48 MHz +** - FIRCDIV2_CLK = 48 MHz +** - SIRCDIV1_CLK = 8 MHz +** - SIRCDIV2_CLK = 8 MHz +** \return none. +** +****************************************************************************************/ +static void SystemClockConfig(void) +{ + /* --------- SOSC Initialization (40 MHz) ------------------------------------------ */ + /* SOSCDIV1 & SOSCDIV2 =1: divide by 1. */ + SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1) | SCG_SOSCDIV_SOSCDIV2(1); + /* Range=3: High freq (SOSC betw 8MHz - 40MHz). + * HGO=0: Config xtal osc for low power. + * EREFS=1: Input is external XTAL. + */ + SCG->SOSCCFG = SCG_SOSCCFG_RANGE(3) | SCG_SOSCCFG_EREFS_MASK; + /* Ensure SOSCCSR unlocked. */ + while (SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK) + { + ; + } + + /* LK=0: SOSCCSR can be written. + * SOSCCMRE=0: OSC CLK monitor IRQ if enabled. + * SOSCCM=0: OSC CLK monitor disabled. + * SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled. + * SOSCLPEN=0: Sys OSC disabled in VLP modes. + * SOSCSTEN=0: Sys OSC disabled in Stop modes. + * SOSCEN=1: Enable oscillator. + */ + SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK; + /* Wait for system OSC clock to become valid. */ + while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK)) + { + ; + } + + /* --------- FIRC Initialization --------------------------------------------------- */ + /* Fast IRC is enabled and trimmed to 48 MHz in reset (default). Enable FIRCDIV2_CLK + * and FIRCDIV1_CLK, divide by 1 = 48 MHz. + */ + SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV1(1) | SCG_FIRCDIV_FIRCDIV2(1); + + /* --------- SIRC Initialization --------------------------------------------------- */ + /* Slow IRC is enabled with high range (8 MHz) in reset. Enable SIRCDIV2_CLK and + * SIRCDIV1_CLK, divide by 1 = 8MHz asynchronous clock source. + */ + SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1) | SCG_SIRCDIV_SIRCDIV2(1); + + /* --------- Change to normal RUN mode with 48MHz FIRC ----------------------------- */ + /* Select FIRC as clock source. + * DIVCORE=0, div. by 1: Core clock = 48 MHz. + * DIVBUS=0, div. by 1: bus clock = 48 MHz. + * DIVSLOW=1, div. by 2: SCG slow, flash clock= 24 MHz + */ + SCG->RCCR = SCG_RCCR_SCS(3) | SCG_RCCR_DIVCORE(0) | SCG_RCCR_DIVBUS(0) | + SCG_RCCR_DIVSLOW(1); + + /* Wait until system clock source is FIRC. */ + while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 3U) + { + ; + } + /* Evaluate the clock register settings and calculates the current core clock. This + * function must be called when the clock manager component is not used. + */ + SystemCoreClockUpdate(); +} /*** end of SystemClockConfig ***/ + + +/*********************************** end of main.c *************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/startup/startup.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/startup/startup.c new file mode 100644 index 00000000..2d0efc61 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/startup/startup.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * All variables with this problem are defined in the linker files. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.11, When an array with external linkage + * is declared, its size should be explicitly specified. + * The size of the arrays can not be explicitly determined. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed + * between a pointer to object and an integer type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed + * between pointer to void and an arithmetic type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 2.1, A project shall not contain unreachable + * code. + * The condition compares two address defined in linker files that can be different. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. + * Function is defined for usage by application code. + * + * @section [global] + * Violates MISRA 2012 Mandatory Rule 17.3, Symbol 'MFSPR' undeclared, assumed + * to return int. + * This is an e200 Power Architecture Assembly instruction used to retrieve + * the core number. + * + */ + +#include "startup.h" +#include + + +/******************************************************************************* + * Static Variables + ******************************************************************************/ +static volatile uint32_t * const s_vectors[NUMBER_OF_CORES] = FEATURE_INTERRUPT_INT_VECTORS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : init_data_bss + * Description : Make necessary initializations for RAM. + * - Copy the vector table from ROM to RAM. + * - Copy initialized data from ROM to RAM. + * - Copy code that should reside in RAM from ROM + * - Clear the zero-initialized data section. + * + * Tool Chains: + * __GNUC__ : GNU Compiler Collection + * __ghs__ : Green Hills ARM Compiler + * __ICCARM__ : IAR ARM Compiler + * __DCC__ : Wind River Diab Compiler + * __ARMCC_VERSION : ARMC Compiler + * + * Implements : init_data_bss_Activity + *END**************************************************************************/ +void init_data_bss(void) +{ + uint32_t n; + uint8_t coreId; +/* For ARMC we are using the library method of initializing DATA, Custom Section and + * Code RAM sections so the below variables are not needed */ +#if !defined(__ARMCC_VERSION) + /* Declare pointers for various data sections. These pointers + * are initialized using values pulled in from the linker file */ + uint8_t * data_ram; + uint8_t * code_ram; + uint8_t * bss_start; + uint8_t * custom_ram; + const uint8_t * data_rom, * data_rom_end; + const uint8_t * code_rom, * code_rom_end; + const uint8_t * bss_end; + const uint8_t * custom_rom, * custom_rom_end; +#endif + /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ + +#if defined(__ARMCC_VERSION) + extern uint32_t __RAM_VECTOR_TABLE_SIZE; + extern uint32_t __VECTOR_ROM; + extern uint32_t __VECTOR_RAM; +#else + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#endif + /* Get section information from linker files */ +#if defined(__ICCARM__) + /* Data */ + data_ram = __section_begin(".data"); + data_rom = __section_begin(".data_init"); + data_rom_end = __section_end(".data_init"); + + /* CODE RAM */ + #pragma section = "__CODE_ROM" + #pragma section = "__CODE_RAM" + code_ram = __section_begin("__CODE_RAM"); + code_rom = __section_begin("__CODE_ROM"); + code_rom_end = __section_end("__CODE_ROM"); + + /* BSS */ + bss_start = __section_begin(".bss"); + bss_end = __section_end(".bss"); + + custom_ram = __section_begin(".customSection"); + custom_rom = __section_begin(".customSection_init"); + custom_rom_end = __section_end(".customSection_init"); + +#elif defined (__ARMCC_VERSION) + /* VECTOR TABLE*/ + uint8_t * vector_table_size = (uint8_t *)__RAM_VECTOR_TABLE_SIZE; + uint32_t * vector_rom = (uint32_t *)__VECTOR_ROM; + uint32_t * vector_ram = (uint32_t *)__VECTOR_RAM; +#else + extern uint32_t __DATA_ROM[]; + extern uint32_t __DATA_RAM[]; + extern uint32_t __DATA_END[]; + + extern uint32_t __CODE_RAM[]; + extern uint32_t __CODE_ROM[]; + extern uint32_t __CODE_END[]; + + extern uint32_t __BSS_START[]; + extern uint32_t __BSS_END[]; + + extern uint32_t __CUSTOM_ROM[]; + extern uint32_t __CUSTOM_END[]; + + /* Data */ + data_ram = (uint8_t *)__DATA_RAM; + data_rom = (uint8_t *)__DATA_ROM; + data_rom_end = (uint8_t *)__DATA_END; + /* CODE RAM */ + code_ram = (uint8_t *)__CODE_RAM; + code_rom = (uint8_t *)__CODE_ROM; + code_rom_end = (uint8_t *)__CODE_END; + /* BSS */ + bss_start = (uint8_t *)__BSS_START; + bss_end = (uint8_t *)__BSS_END; + + /* Custom section */ + custom_ram = CUSTOMSECTION_SECTION_START; + custom_rom = (uint8_t *)__CUSTOM_ROM; + custom_rom_end = (uint8_t *)__CUSTOM_END; + +#endif + +#if !defined(__ARMCC_VERSION) + /* Copy initialized data from ROM to RAM */ + while (data_rom_end != data_rom) + { + *data_ram = *data_rom; + data_ram++; + data_rom++; + } + + /* Copy functions from ROM to RAM */ + while (code_rom_end != code_rom) + { + *code_ram = *code_rom; + code_ram++; + code_rom++; + } + + /* Clear the zero-initialized data section */ + while(bss_end != bss_start) + { + *bss_start = 0; + bss_start++; + } + + /* Copy customsection rom to ram */ + while(custom_rom_end != custom_rom) + { + *custom_ram = *custom_rom; + custom_rom++; + custom_ram++; + } +#endif + coreId = (uint8_t)GET_CORE_ID(); +#if defined (__ARMCC_VERSION) + /* Copy the vector table from ROM to RAM */ + /* Workaround */ + for (n = 0; n < (((uint32_t)(vector_table_size))/sizeof(uint32_t)); n++) + { + vector_ram[n] = vector_rom[n]; + } + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t) __VECTOR_RAM; +#else + /* Check if VECTOR_TABLE copy is needed */ + if (__VECTOR_RAM != __VECTOR_TABLE) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < (((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t)); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t)__VECTOR_RAM; + } + else + { + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t)__VECTOR_TABLE; + } +#endif + +} + +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/startup/startup.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/startup/startup.h new file mode 100644 index 00000000..8384b7db --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/startup/startup.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef STARTUP_H +#define STARTUP_H + +#include +#include "device_registers.h" +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, Local macro not referenced. + * The defined macro is used as include guard. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * All variables with this problem are defined in the linker files. + * + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief define symbols that specific start and end addres of some basic sections. + */ +#if (defined(S32K14x_SERIES) || defined(S32K11x_SERIES) || defined(S32V234_SERIES) || defined(MPC574x_SERIES) || defined(S32R_SERIES) || defined(S32MTV_SERIES) || defined(SJA1110_SERIES)) || defined (S32K144W_M4_SERIES) + #if (defined(__ICCARM__)) + #define INTERRUPTS_SECTION_START __section_begin(".intvec") + #define INTERRUPTS_SECTION_END __section_end(".intvec") + #define BSS_SECTION_START __section_begin(".bss") + #define BSS_SECTION_END __section_end(".bss") + #define DATA_SECTION_START __section_begin(".data") + #define DATA_SECTION_END __section_end(".data") + #define CUSTOMSECTION_SECTION_START __section_begin(".customSection") + #define CUSTOMSECTION_SECTION_END __section_end(".customSection") + #define CODE_RAM_SECTION_START __section_begin("__CODE_RAM") + #define CODE_RAM_SECTION_END __section_end("__CODE_RAM") + #define DATA_INIT_SECTION_START __section_begin(".data_init") + #define DATA_INIT_SECTION_END __section_end(".data_init") + #define CODE_ROM_SECTION_START __section_begin("__CODE_ROM") + #define CODE_ROM_SECTION_END __section_end("__CODE_ROM") + + #elif (defined(__ARMCC_VERSION)) + #define INTERRUPTS_SECTION_START (uint8_t *)__VECTOR_ROM_START + #define INTERRUPTS_SECTION_END (uint8_t *)__VECTOR_ROM_END + #define BSS_SECTION_START (uint8_t *)__BSS_START + #define BSS_SECTION_END (uint8_t *)__BSS_END + #define DATA_SECTION_START (uint8_t *)__DATA_RAM_START + #define DATA_SECTION_END (uint8_t *)__DATA_RAM_END + #define CUSTOMSECTION_SECTION_START (uint8_t *)__CUSTOM_SECTION_START + #define CUSTOMSECTION_SECTION_END (uint8_t *)__CUSTOM_SECTION_END + #define CODE_RAM_SECTION_START (uint8_t *)__CODE_RAM_START + #define CODE_RAM_SECTION_END (uint8_t *)__CODE_RAM_END + + extern uint32_t __VECTOR_ROM_START; + extern uint32_t __VECTOR_ROM_END; + extern uint32_t __BSS_START; + extern uint32_t __BSS_END; + extern uint32_t __DATA_RAM_START; + extern uint32_t __DATA_RAM_END; + extern uint32_t __CUSTOM_SECTION_START; + extern uint32_t __CUSTOM_SECTION_END; + extern uint32_t __CODE_RAM_START; + extern uint32_t __CODE_RAM_END; + #else + #define INTERRUPTS_SECTION_START (uint8_t *)&__interrupts_start__ + #define INTERRUPTS_SECTION_END (uint8_t *)&__interrupts_end__ + #define BSS_SECTION_START (uint8_t *)&__bss_start__ + #define BSS_SECTION_END (uint8_t *)&__bss_end__ + #define DATA_SECTION_START (uint8_t *)&__data_start__ + #define DATA_SECTION_END (uint8_t *)&__data_end__ + #define CUSTOMSECTION_SECTION_START (uint8_t *)&__customSection_start__ + #define CUSTOMSECTION_SECTION_END (uint8_t *)&__customSection_end__ + #define CODE_RAM_SECTION_START (uint8_t *)&__code_ram_start__ + #define CODE_RAM_SECTION_END (uint8_t *)&__code_ram_end__ + + extern uint32_t __interrupts_start__; + extern uint32_t __interrupts_end__; + extern uint32_t __bss_start__; + extern uint32_t __bss_end__; + extern uint32_t __data_start__; + extern uint32_t __data_end__; + extern uint32_t __customSection_start__; + extern uint32_t __customSection_end__; + extern uint32_t __code_ram_start__; + extern uint32_t __code_ram_end__; + #endif +#endif + +#if (defined(__ICCARM__)) + #pragma section = ".data" + #pragma section = ".data_init" + #pragma section = ".bss" + #pragma section = ".intvec" + #pragma section = ".customSection" + #pragma section = ".customSection_init" + #pragma section = "__CODE_RAM" + #pragma section = "__CODE_ROM" +#endif + +/*! + * @brief Make necessary initializations for RAM. + * + * - Copy initialized data from ROM to RAM. + * - Clear the zero-initialized data section. + * - Copy the vector table from ROM to RAM. This could be an option. + */ +void init_data_bss(void); + +#endif /* STARTUP_H*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/startup/startup_S32K118.S b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/startup/startup_S32K118.S new file mode 100644 index 00000000..4f53518d --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/startup/startup_S32K118.S @@ -0,0 +1,227 @@ +/* ---------------------------------------------------------------------------------------*/ +/* @file: startup_S32K118.s */ +/* @purpose: GNU Compiler Collection Startup File */ +/* S32K118 */ +/* @version: 1.0 */ +/* @date: 2018-1-22 */ +/* @build: b170107 */ +/* ---------------------------------------------------------------------------------------*/ +/* */ +/* Copyright 2018 NXP */ +/* All rights reserved. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES */ +/* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. */ +/* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, */ +/* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ +/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR */ +/* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) */ +/* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, */ +/* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING */ +/* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF */ +/* THE POSSIBILITY OF SUCH DAMAGE. */ +/*****************************************************************************/ +/* Version: GNU Compiler Collection */ +/*****************************************************************************/ + .syntax unified + .arch armv6-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* Non Maskable Interrupt */ + .long HardFault_Handler /* Cortex-M0 SV Hard Fault Interrupt */ + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler /* Cortex-M0 SV Call Interrupt */ + .long 0 + .long 0 + .long PendSV_Handler /* Cortex-M0 Pend SV Interrupt */ + .long SysTick_Handler /* Cortex-M0 System Tick Interrupt */ + + + .long DMA0_IRQHandler /* DMA channel 0 transfer complete */ + .long DMA1_IRQHandler /* DMA channel 1 transfer complete */ + .long DMA2_IRQHandler /* DMA channel 2 transfer complete */ + .long DMA3_IRQHandler /* DMA channel 3 transfer complete */ + .long DMA_Error_IRQHandler /* DMA error interrupt channels 0-3 */ + .long ERM_fault_IRQHandler /* ERM single and double bit error correction */ + .long RTC_IRQHandler /* RTC alarm interrupt */ + .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */ + .long LPTMR0_IRQHandler /* LPTIMER interrupt request */ + .long PORT_IRQHandler /* Port A, B, C, D and E pin detect interrupt */ + .long CAN0_ORed_Err_Wakeup_IRQHandler /* OR’ed [Bus Off OR Bus Off Done OR Transmit Warning OR Receive Warning], Interrupt indicating that errors were detected on the CAN bus, Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode */ + .long CAN0_ORed_0_31_MB_IRQHandler /* OR’ed Message buffer (0-15, 16-31) */ + .long FTM0_Ch0_7_IRQHandler /* FTM0 Channel 0 to 7 interrupt */ + .long FTM0_Fault_IRQHandler /* FTM0 Fault interrupt */ + .long FTM0_Ovf_Reload_IRQHandler /* FTM0 Counter overflow and Reload interrupt */ + .long FTM1_Ch0_7_IRQHandler /* FTM1 Channel 0 to 7 interrupt */ + .long FTM1_Fault_IRQHandler /* FTM1 Fault interrupt */ + .long FTM1_Ovf_Reload_IRQHandler /* FTM1 Counter overflow and Reload interrupt */ + .long FTFC_IRQHandler /* FTFC Command complete, Read collision and Double bit fault detect */ + .long PDB0_IRQHandler /* PDB0 interrupt */ + .long LPIT0_IRQHandler /* LPIT interrupt */ + .long SCG_CMU_LVD_LVWSCG_IRQHandler /* PMC Low voltage detect interrupt, SCG bus interrupt request and CMU loss of range interrupt */ + .long WDOG_IRQHandler /* WDOG interrupt request out before wdg reset out */ + .long RCM_IRQHandler /* RCM Asynchronous Interrupt */ + .long LPI2C0_Master_Slave_IRQHandler /* LPI2C0 Master Interrupt and Slave Interrupt */ + .long FLEXIO_IRQHandler /* FlexIO Interrupt */ + .long LPSPI0_IRQHandler /* LPSPI0 Interrupt */ + .long LPSPI1_IRQHandler /* LPSPI1 Interrupt */ + .long ADC0_IRQHandler /* ADC0 interrupt request. */ + .long CMP0_IRQHandler /* CMP0 interrupt request */ + .long LPUART1_RxTx_IRQHandler /* LPUART1 Transmit / Receive Interrupt */ + .long LPUART0_RxTx_IRQHandler /* LPUART0 Transmit / Receive Interrupt */ + + .size __isr_vector, . - __isr_vector + +/* Flash Configuration */ + .section .FlashConfig, "a" + .long 0xFFFFFFFF /* 8 bytes backdoor comparison key */ + .long 0xFFFFFFFF /* */ + .long 0xFFFFFFFF /* 4 bytes program flash protection bytes */ + .long 0xFFFF7FFE /* FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured) */ + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + + /* Init the rest of the registers */ + ldr r1,=0 + ldr r2,=0 + ldr r3,=0 + ldr r4,=0 + ldr r5,=0 + ldr r6,=0 + ldr r7,=0 + mov r8,r7 + mov r9,r7 + mov r10,r7 + mov r11,r7 + mov r12,r7 + +#ifdef START_FROM_FLASH + + /* Init ECC RAM */ + + ldr r1, =__RAM_START + ldr r2, =__RAM_END + + subs r2, r1 + subs r2, #1 + ble .LC5 + + movs r0, 0 + movs r3, #4 +.LC4: + str r0, [r1] + add r1, r1, r3 + subs r2, 4 + bge .LC4 +.LC5: +#endif + + /* Initialize the stack pointer */ + ldr r0,=__StackTop + mov r13,r0 + +#ifndef __NO_SYSTEM_INIT + /* Call the system init routine */ + ldr r0,=SystemInit + blx r0 +#endif + + /* Init .data and .bss sections */ + ldr r0,=init_data_bss + blx r0 + cpsie i /* Unmask interrupts */ + +#ifndef __START +#ifdef __EWL__ +#define __START __thumb_startup +#else +#define __START _start +#endif +#endif + bl __START + +JumpToSelf: + b JumpToSelf + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler DMA0_IRQHandler + def_irq_handler DMA1_IRQHandler + def_irq_handler DMA2_IRQHandler + def_irq_handler DMA3_IRQHandler + def_irq_handler DMA_Error_IRQHandler + def_irq_handler ERM_fault_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler RTC_Seconds_IRQHandler + def_irq_handler LPTMR0_IRQHandler + def_irq_handler PORT_IRQHandler + def_irq_handler CAN0_ORed_Err_Wakeup_IRQHandler + def_irq_handler CAN0_ORed_0_31_MB_IRQHandler + def_irq_handler FTM0_Ch0_7_IRQHandler + def_irq_handler FTM0_Fault_IRQHandler + def_irq_handler FTM0_Ovf_Reload_IRQHandler + def_irq_handler FTM1_Ch0_7_IRQHandler + def_irq_handler FTM1_Fault_IRQHandler + def_irq_handler FTM1_Ovf_Reload_IRQHandler + def_irq_handler FTFC_IRQHandler + def_irq_handler PDB0_IRQHandler + def_irq_handler LPIT0_IRQHandler + def_irq_handler SCG_CMU_LVD_LVWSCG_IRQHandler + def_irq_handler WDOG_IRQHandler + def_irq_handler RCM_IRQHandler + def_irq_handler LPI2C0_Master_Slave_IRQHandler + def_irq_handler FLEXIO_IRQHandler + def_irq_handler LPSPI0_IRQHandler + def_irq_handler LPSPI1_IRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler CMP0_IRQHandler + def_irq_handler LPUART1_RxTx_IRQHandler + def_irq_handler LPUART0_RxTx_IRQHandler + + .end diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.cproject b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.cproject new file mode 100644 index 00000000..934ca17c --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.cproject @@ -0,0 +1,151 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.project b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.project new file mode 100644 index 00000000..aa7f79b4 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.project @@ -0,0 +1,26 @@ + + + Prog + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/com.nxp.s32ds.cle.runtime.component.prefs b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/com.nxp.s32ds.cle.runtime.component.prefs new file mode 100644 index 00000000..637f1f53 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/com.nxp.s32ds.cle.runtime.component.prefs @@ -0,0 +1,8 @@ +com.nxp.s32ds.cle.runtime.component.registry.archetype.id=application +com.nxp.s32ds.cle.runtime.component.registry.archetype.platform.id= +com.nxp.s32ds.cle.runtime.hardware.registry.core.id=CortexM0P +com.nxp.s32ds.cle.runtime.hardware.registry.device.id=S32K118 +com.nxp.s32ds.cle.runtime.hardware.registry.deviceCore.id=S32K118_M0P +com.nxp.s32ds.cle.runtime.hardware.registry.family.id=S32K1 +com.nxp.s32ds.cle.runtime.lang.registry.lang.id=c +eclipse.preferences.version=1 diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/com.processorexpert.core.ide.newprojectwizard.prefs b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/com.processorexpert.core.ide.newprojectwizard.prefs new file mode 100644 index 00000000..87ca305f --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/com.processorexpert.core.ide.newprojectwizard.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +versionGenerated/versionGenerated=1.8.4.RT7_b1743-0713 diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/language.settings.xml b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/language.settings.xml new file mode 100644 index 00000000..79b318f7 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/language.settings.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/org.eclipse.cdt.codan.core.prefs b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 00000000..98b63502 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/org.eclipse.cdt.core.prefs b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 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+S10B2FC0000000000000000005 +S903253D9A diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/Prog_Debug.launch b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/Prog_Debug.launch new file mode 100644 index 00000000..be1e9f3f --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/Prog_Debug.launch @@ -0,0 +1,221 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/S32K118_25_flash.ld b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/S32K118_25_flash.ld new file mode 100644 index 00000000..cf44acda --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/S32K118_25_flash.ld @@ -0,0 +1,278 @@ +/* +** ################################################################### +** Processor: S32K118 with 25 KB SRAM +** Compiler: GNU C Compiler +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2018 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) +/* +To use "new" operator with EWL in C++ project the following symbol shall be defined +*/ +/*EXTERN(_ZN10__cxxabiv119__terminate_handlerE)*/ + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x00000200; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x00000200; + +/* If symbol __flash_vector_table__=1 is defined at link time + * the interrupt vector will not be copied to RAM. + * Warning: Using the interrupt vector from Flash will not allow + * INT_SYS_InstallHandler because the section is Read Only. + */ +M_VECTOR_RAM_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : 0x00C0; + +/* Specify the memory areas */ +MEMORY +{ + /* Flash */ + m_interrupts (RX) : ORIGIN = 0x00002000, LENGTH = 0x000000C4 + m_flash_config (RX) : ORIGIN = 0x00002400, LENGTH = 0x00000010 + m_text (RX) : ORIGIN = 0x00002410, LENGTH = 0x0003FBF0 - 0x2000 + + /* SRAM_L */ + + /* SRAM_U */ + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x000030C0 + m_data_2 (RW) : ORIGIN = 0x200030C0, LENGTH = 0x00002740 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + __VECTOR_TABLE = .; + __interrupts_start__ = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + __interrupts_end__ = .; + . = ALIGN(4); + } > m_interrupts + + .flash_config : + { + . = ALIGN(4); + KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_flash_config + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* Define a global symbol at end of code. */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization. */ + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __RAM_START = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start. */ + *(.m_interrupts_ram) /* This is a user defined section. */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end. */ + } > m_data + + __VECTOR_RAM = DEFINED(__flash_vector_table__) ? ORIGIN(m_interrupts) : __VECTOR_RAM__ ; + __RAM_VECTOR_TABLE_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : (__interrupts_ram_end__ - __interrupts_ram_start__) ; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* Create a global symbol at data start. */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* Define a global symbol at data end. */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + __CODE_ROM = __DATA_END; /* Symbol is used by code initialization. */ + .code : AT(__CODE_ROM) + { + . = ALIGN(4); + __CODE_RAM = .; + __code_start__ = .; /* Create a global symbol at code start. */ + __code_ram_start__ = .; + *(.code_ram) /* Custom section for storing code in RAM */ + . = ALIGN(4); + __code_end__ = .; /* Define a global symbol at code end. */ + __code_ram_end__ = .; + } > m_data + + __CODE_END = __CODE_ROM + (__code_end__ - __code_start__); + __CUSTOM_ROM = __CODE_END; + + /* Custom Section Block that can be used to place data at absolute address. */ + /* Use __attribute__((section (".customSection"))) to place data here. */ + .customSectionBlock ORIGIN(m_data_2) : AT(__CUSTOM_ROM) + { + __customSection_start__ = .; + KEEP(*(.customSection)) /* Keep section even if not referenced. */ + __customSection_end__ = .; + } > m_data_2 + __CUSTOM_END = __CUSTOM_ROM + (__customSection_end__ - __customSection_start__); + + /* Uninitialized data section. */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section. */ + . = ALIGN(4); + __BSS_START = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __BSS_END = .; + } > m_data_2 + + .heap : + { + . = ALIGN(8); + __end__ = .; + __heap_start__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + PROVIDE(__end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; + __heap_end__ = .; + } > m_data_2 + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + __RAM_END = __StackTop; + + .stack __StackLimit : + { + . = ALIGN(8); + __stack_start__ = .; + . += STACK_SIZE; + __stack_end__ = .; + } > m_data_2 + + /* Labels required by EWL */ + __START_BSS = __BSS_START; + __END_BSS = __BSS_END; + __SP_INIT = __StackTop; + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap") +} + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/boot.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/boot.c new file mode 100644 index 00000000..dabb48bf --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/boot.c @@ -0,0 +1,772 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/boot.c +* \brief Demo program bootloader interface source file. +* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +#if (BOOT_COM_RS232_ENABLE > 0) +static void BootComRs232Init(void); +static void BootComRs232CheckActivationRequest(void); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) +static void BootComCanInit(void); +static void BootComCanCheckActivationRequest(void); +#endif + + +/************************************************************************************//** +** \brief Initializes the communication interface. +** \return none. +** +****************************************************************************************/ +void BootComInit(void) +{ +#if (BOOT_COM_RS232_ENABLE > 0) + BootComRs232Init(); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) + BootComCanInit(); +#endif +} /*** end of BootComInit ***/ + + +/************************************************************************************//** +** \brief Receives the CONNECT request from the host, which indicates that the +** bootloader should be activated and, if so, activates it. +** \return none. +** +****************************************************************************************/ +void BootComCheckActivationRequest(void) +{ +#if (BOOT_COM_RS232_ENABLE > 0) + BootComRs232CheckActivationRequest(); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) + BootComCanCheckActivationRequest(); +#endif +} /*** end of BootComCheckActivationRequest ***/ + + +/************************************************************************************//** +** \brief Bootloader activation function. +** \return none. +** +****************************************************************************************/ +void BootActivate(void) +{ + /* Activate the bootloader by performing a software reset. */ + SystemSoftwareReset(); +} /*** end of BootActivate ***/ + + +#if (BOOT_COM_RS232_ENABLE > 0) +/**************************************************************************************** +* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E +****************************************************************************************/ + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Timeout time for the reception of a CTO packet. The timer is started upon + * reception of the first packet byte. + */ +#define RS232_CTO_RX_PACKET_TIMEOUT_MS (100u) +/** \brief Set the peripheral LPUART base pointer. */ +#define LPUARTx (LPUART0) +/** \brief Set the PCC index offset for LPUART. */ +#define PCC_LPUARTx_INDEX (PCC_LPUART0_INDEX) + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static unsigned char Rs232ReceiveByte(unsigned char *data); + + +/************************************************************************************//** +** \brief Initializes the UART communication interface. +** \return none. +** +****************************************************************************************/ +static void BootComRs232Init(void) +{ + unsigned long sourceClockFreqHz; + unsigned long div2RegValue; + unsigned short baudrateSbr0_12; + unsigned char const div2DividerLookup[] = + { + 0U, /* 0b000. Output disabled. */ + 1U, /* 0b001. Divide by 1. */ + 2U, /* 0b010. Divide by 2. */ + 4U, /* 0b011. Divide by 4. */ + 8U, /* 0b100. Divide by 8. */ + 16U, /* 0b101. Divide by 16. */ + 32U, /* 0b110. Divide by 32. */ + 64U, /* 0b111. Divide by 64. */ + }; + + /* Make sure the UART peripheral clock is disabled before configuring its source + * clock. + */ + PCC->PCCn[PCC_LPUARTx_INDEX] &= ~PCC_PCCn_CGC_MASK; + /* Select option 2 as the UART peripheral source clock and enable the clock. Option 2 + * is the SIRCDIV2_CLK, which is available on all peripherals and configurations. + */ + PCC->PCCn[PCC_LPUARTx_INDEX] |= PCC_PCCn_PCS(2) | PCC_PCCn_CGC_MASK; + /* Obtain the DIV2 divider value of the SIRC_CLK. */ + div2RegValue = (SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT; + /* Check if the DIV2 register value for SIRC is 0. In this case SIRCDIV2_CLK is + * currently disabled. + */ + if (div2RegValue == 0U) + { + /* Configure the DIV2 for a default divide by 1 to make sure the SIRCDIV2_CLK is + * actually enabled. + */ + div2RegValue = 1U; + SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV2(div2RegValue); + } + /* Determine the SIRC clock frequency. If SIRC high range is enabled, it is 8 MHz. If + * SIRC low range is enabled, it is 2 MHz. + */ + sourceClockFreqHz = 8000000U; + if ((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) == SCG_SIRCCFG_RANGE(0)) + { + sourceClockFreqHz = 2000000U; + } + /* Now process the configured DIV2 divider factor to get the actual frequency of the + * UART peripheral source clock. + */ + sourceClockFreqHz /= div2DividerLookup[div2RegValue]; + /* Configure the baudrate from BOOT_COM_RS232_BAUDRATE, taking into account that an + * oversampling of 8 will be configured. Default 8,n,1 format is used. Integer + * rounding is used to get the best value for baudrateSbr0_12. Actual baudrate equals + * sourceClockFreqHz / 8 / baudrateSbr0_12. + */ + baudrateSbr0_12 = (((sourceClockFreqHz / BOOT_COM_RS232_BAUDRATE) + (8U - 1U)) / 8U) & + LPUART_BAUD_SBR_MASK; + /* OSR=7: Over sampling ratio = 7+1=8. + * SBNS=0: One stop bit. + * BOTHEDGE=0: receiver samples only on rising edge. + * M10=0: Rx and Tx use 7 to 9 bit data characters. + * RESYNCDIS=0: Resync during rec'd data word supported. + * LBKDIE, RXEDGIE=0: interrupts disable. + * TDMAE, RDMAE, TDMAE=0: DMA requests disabled. + * MAEN1, MAEN2, MATCFG=0: Match disabled. + */ + LPUARTx->BAUD = LPUART_BAUD_SBR(baudrateSbr0_12) | LPUART_BAUD_OSR(7); + /* Clear the error/interrupt flags */ + LPUARTx->STAT = FEATURE_LPUART_STAT_REG_FLAGS_MASK; + /* Reset all features/interrupts by default */ + LPUARTx->CTRL = 0x00000000; + /* Reset match addresses */ + LPUARTx->MATCH = 0x00000000; +#if FEATURE_LPUART_HAS_MODEM_SUPPORT + /* Reset IrDA modem features */ + LPUARTx->MODIR = 0x00000000; +#endif +#if FEATURE_LPUART_FIFO_SIZE > 0U + /* Reset FIFO feature */ + LPUARTx->FIFO = FEATURE_LPUART_FIFO_RESET_MASK; + /* Enable the transmit and receive FIFOs. */ + LPUARTx->FIFO |= LPUART_FIFO_TXFE(1) | LPUART_FIFO_RXFE(1); + /* Set the reception water mark to 0 and the transmitter water mark to 1. */ + LPUARTx->WATER = LPUART_WATER_TXWATER(1) | LPUART_WATER_RXWATER(0); +#endif + /* Enable transmitter and receiver, no parity, 8 bit char: + * RE=1: Receiver enabled. + * TE=1: Transmitter enabled. + * PE,PT=0: No hw parity generation or checking. + * M7,M,R8T9,R9T8=0: 8-bit data characters. + * DOZEEN=0: LPUART enabled in Doze mode. + * ORIE,NEIE,FEIE,PEIE,TIE,TCIE,RIE,ILIE,MA1IE,MA2IE=0: no IRQ. + * TxDIR=0: TxD pin is input if in single-wire mode. + * TXINV=0: Transmit data not inverted. + * RWU,WAKE=0: normal operation; rcvr not in standby. + * IDLCFG=0: one idle character. + * ILT=0: Idle char bit count starts after start bit. + * SBK=0: Normal transmitter operation - no break char. + * LOOPS,RSRC=0: no loop back. + */ + LPUARTx->CTRL = LPUART_CTRL_RE_MASK | LPUART_CTRL_TE_MASK; +} /*** end of BootComRs232Init ***/ + + +/************************************************************************************//** +** \brief Receives the CONNECT request from the host, which indicates that the +** bootloader should be activated and, if so, activates it. +** \return none. +** +****************************************************************************************/ +static void BootComRs232CheckActivationRequest(void) +{ + static unsigned char xcpCtoReqPacket[BOOT_COM_RS232_RX_MAX_DATA+1]; + static unsigned char xcpCtoRxLength; + static unsigned char xcpCtoRxInProgress = 0; + static unsigned long xcpCtoRxStartTime = 0; + + /* start of cto packet received? */ + if (xcpCtoRxInProgress == 0) + { + /* store the message length when received */ + if (Rs232ReceiveByte(&xcpCtoReqPacket[0]) == 1) + { + /* check that the length has a valid value. it should not be 0 */ + if ( (xcpCtoReqPacket[0] > 0) && + (xcpCtoReqPacket[0] <= BOOT_COM_RS232_RX_MAX_DATA) ) + { + /* store the start time */ + xcpCtoRxStartTime = TimerGet(); + /* indicate that a cto packet is being received */ + xcpCtoRxInProgress = 1; + /* reset packet data count */ + xcpCtoRxLength = 0; + } + } + } + else + { + /* store the next packet byte */ + if (Rs232ReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1) + { + /* increment the packet data count */ + xcpCtoRxLength++; + + /* check to see if the entire packet was received */ + if (xcpCtoRxLength == xcpCtoReqPacket[0]) + { + /* done with cto packet reception */ + xcpCtoRxInProgress = 0; + + /* check if this was an XCP CONNECT command */ + if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00)) + { + /* connection request received so start the bootloader */ + BootActivate(); + } + } + } + else + { + /* check packet reception timeout */ + if (TimerGet() > (xcpCtoRxStartTime + RS232_CTO_RX_PACKET_TIMEOUT_MS)) + { + /* cancel cto packet reception due to timeout. note that this automatically + * discards the already received packet bytes, allowing the host to retry. + */ + xcpCtoRxInProgress = 0; + } + } + } +} /*** end of BootComRs232CheckActivationRequest ***/ + + +/************************************************************************************//** +** \brief Receives a communication interface byte if one is present. +** \param data Pointer to byte where the data is to be stored. +** \return 1 if a byte was received, 0 otherwise. +** +****************************************************************************************/ +static unsigned char Rs232ReceiveByte(unsigned char *data) +{ + unsigned char result = 0; + + /* Check if a new byte was received by means of the RDRF-bit. */ + if (((LPUARTx->STAT & LPUART_STAT_RDRF_MASK) >> LPUART_STAT_RDRF_SHIFT) != 0U) + { + /* Retrieve and store the newly received byte. */ + *data = LPUARTx->DATA; + /* Update the result. */ + result = 1; + } + + /* Give the result back to the caller. */ + return result; +} /*** end of Rs232ReceiveByte ***/ +#endif /* BOOT_COM_RS232_ENABLE > 0 */ + + +#if (BOOT_COM_CAN_ENABLE > 0) +/**************************************************************************************** +* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E +****************************************************************************************/ + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Timeout for entering/leaving CAN initialization mode in milliseconds. */ +#define CAN_INIT_TIMEOUT_MS (250U) + +/** \brief Set the peripheral CAN0 base pointer. */ +#define CANx (CAN0) +/** \brief Set the PCC index offset for CAN0. */ +#define PCC_FlexCANx_INDEX (PCC_FlexCAN0_INDEX) +/** \brief Set the number of message boxes supported by CAN0. */ +#define CANx_MAX_MB_NUM (FEATURE_CAN0_MAX_MB_NUM) + +/** \brief The mailbox used for receiving the XCP command message. */ +#define CAN_RX_MSGBOX_NUM (9U) + + +/**************************************************************************************** +* Type definitions +****************************************************************************************/ +/** \brief Structure type for grouping CAN bus timing related information. */ +typedef struct t_can_bus_timing +{ + unsigned char timeQuanta; /**< Total number of time quanta */ + unsigned char propSeg; /**< CAN propagation segment */ + unsigned char phaseSeg1; /**< CAN phase segment 1 */ + unsigned char phaseSeg2; /**< CAN phase segment 2 */ +} tCanBusTiming; + + +/**************************************************************************************** +* Local constant declarations +****************************************************************************************/ +/** \brief CAN bit timing table for dynamically calculating the bittiming settings. + * \details According to the CAN protocol 1 bit-time can be made up of between 8..25 + * time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC + * always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + TSEG2) + * * 100%. This array contains possible and valid time quanta configurations + * with a sample point between 68..78%. A visual representation of the TQ in + * a bit is: + * | SYNCSEG | TIME1SEG | TIME2SEG | + * Or with an alternative representation: + * | SYNCSEG | PROPSEG | PHASE1SEG | PHASE2SEG | + * With the alternative representation TIME1SEG = PROPSEG + PHASE1SEG. + * + */ +static const tCanBusTiming canTiming[] = +{ + /* Time-Quanta | PROPSEG | PSEG1 | PSEG2 | Sample-Point */ + /* ---------------------------------------------------- */ + { 8U, 3U, 2U, 2U }, /*1+3+2+1=8 | 3 | 2 | 2 | 75% */ + { 9U, 3U, 3U, 2U }, /* 9 | 3 | 3 | 2 | 78% */ + { 10U, 3U, 3U, 3U }, /* 10 | 3 | 3 | 3 | 70% */ + { 11U, 4U, 3U, 3U }, /* 11 | 4 | 3 | 3 | 73% */ + { 12U, 4U, 4U, 3U }, /* 12 | 4 | 4 | 3 | 75% */ + { 13U, 5U, 4U, 3U }, /* 13 | 5 | 4 | 3 | 77% */ + { 14U, 5U, 4U, 4U }, /* 14 | 5 | 4 | 4 | 71% */ + { 15U, 6U, 4U, 4U }, /* 15 | 6 | 4 | 4 | 73% */ + { 16U, 6U, 5U, 4U }, /* 16 | 6 | 5 | 4 | 75% */ + { 17U, 7U, 5U, 4U }, /* 17 | 7 | 5 | 4 | 76% */ + { 18U, 7U, 5U, 5U }, /* 18 | 7 | 5 | 5 | 72% */ + { 19U, 8U, 5U, 5U }, /* 19 | 8 | 5 | 5 | 74% */ + { 20U, 8U, 6U, 5U }, /* 20 | 8 | 6 | 5 | 75% */ + { 21U, 8U, 7U, 5U }, /* 21 | 8 | 7 | 5 | 76% */ + { 22U, 8U, 7U, 6U }, /* 22 | 8 | 7 | 6 | 73% */ + { 23U, 8U, 8U, 6U }, /* 23 | 8 | 8 | 6 | 74% */ + { 24U, 8U, 8U, 7U }, /* 24 | 8 | 8 | 7 | 71% */ + { 25U, 8U, 8U, 8U } /* 25 | 8 | 8 | 8 | 68% */ +}; + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Dummy variable to store the CAN controller's free running timer value in. + * This is needed at the end of a CAN message reception to unlock the mailbox + * again. If this variable is declared locally within the function, it generates + * an unwanted compiler warning about assigning a value and not using it. + * For this reason this dummy variabled is declare here as a module global. + */ +static volatile unsigned long dummyTimerVal; + + +/************************************************************************************//** +** \brief Search algorithm to match the desired baudrate to a possible bus +** timing configuration. +** \param baud The desired baudrate in kbps. Valid values are 10..1000. +** \param prescaler Pointer to where the value for the prescaler will be stored. +** \param busTimingCfg Pointer to where the bus timing values will be stored. +** \return 1 if the CAN bustiming register values were found, 0 otherwise. +** +****************************************************************************************/ +static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned short * prescaler, + tCanBusTiming * busTimingCfg) +{ + unsigned char cnt; + unsigned long canClockFreqkHz; + unsigned long div2RegValue; + unsigned char const div2DividerLookup[] = + { + 0U, /* 0b000. Output disabled. */ + 1U, /* 0b001. Divide by 1. */ + 2U, /* 0b010. Divide by 2. */ + 4U, /* 0b011. Divide by 4. */ + 8U, /* 0b100. Divide by 8. */ + 16U, /* 0b101. Divide by 16. */ + 32U, /* 0b110. Divide by 32. */ + 64U, /* 0b111. Divide by 64. */ + }; + + /* Obtain the DIV2 divider value of the SOSC_CLK. */ + div2RegValue = (SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV2_MASK) >> SCG_SOSCDIV_SOSCDIV2_SHIFT; + /* Check if the DIV2 register value for SOSC is 0. In this case SOSCDIV2_CLK is + * currently disabled. + */ + if (div2RegValue == 0U) + { + /* Configure the DIV2 for a default divide by 1 to make sure the SOSCDIV2_CLK is + * actually enabled. + */ + div2RegValue = 1U; + SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(div2RegValue); + } + /* Determine the SOSC clock frequency. */ + canClockFreqkHz = BOOT_CPU_XTAL_SPEED_KHZ; + /* Now process the configured DIV2 divider factor to get the actual frequency of the + * CAN peripheral source clock. + */ + canClockFreqkHz /= div2DividerLookup[div2RegValue]; + + /* Loop through all possible time quanta configurations to find a match. */ + for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++) + { + if ((canClockFreqkHz % (baud * canTiming[cnt].timeQuanta)) == 0U) + { + /* Compute the prescaler that goes with this TQ configuration. */ + *prescaler = canClockFreqkHz/(baud * canTiming[cnt].timeQuanta); + + /* Make sure the prescaler is valid. */ + if ((*prescaler > 0U) && (*prescaler <= 256U)) + { + /* Store the bustiming configuration. */ + *busTimingCfg = canTiming[cnt]; + /* Found a good bus timing configuration. */ + return 1U; + } + } + } + /* Could not find a good bus timing configuration. */ + return 0U; +} /*** end of CanGetSpeedConfig ***/ + + +/************************************************************************************//** +** \brief Places the CAN controller in freeze mode. Note that the CAN controller +** can only be placed in freeze mode, if it is actually enabled. +** \return none. +** +****************************************************************************************/ +static void CanFreezeModeEnter(void) +{ + unsigned long timeout; + + /* Request to enter freeze mode. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(1U); + CANx->MCR = (CANx->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(1U); + /* Set timeout time for entering freeze mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for freeze mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_FRZACK_MASK)) == 0U) + { + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } +} /*** end of CanFreezeModeEnter ***/ + + +/************************************************************************************//** +** \brief Leaves the CAN controller's freeze mode. Note that this operation can +** only be done, if it is actually enabled. +** \return none. +** +****************************************************************************************/ +static void CanFreezeModeExit(void) +{ + unsigned long timeout; + + /* Request to leave freeze mode. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(0U); + CANx->MCR = (CANx->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(0U); + /* Set timeout time for leaving freeze mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for non freeze mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_FRZACK_MASK)) != 0U) + { + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } +} /*** end of CanFreezeModeExit ***/ + + +/************************************************************************************//** +** \brief Places the CAN controller in disabled mode. +** \return none. +** +****************************************************************************************/ +static void CanDisabledModeEnter(void) +{ + unsigned long timeout; + + /* Only continue if the CAN controller is currently enabled. */ + if ((CANx->MCR & CAN_MCR_MDIS_MASK) == 0U) + { + /* Request disabled mode. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(1U); + /* Set timeout time for entering disabled mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for disabled mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_LPMACK_MASK)) == 0U) + { + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } + } +} /*** end of CanDisabledModeEnter ***/ + +/************************************************************************************//** +** \brief Places the CAN controller in enabled mode. +** \return none. +** +****************************************************************************************/ +static void CanDisabledModeExit(void) +{ + unsigned long timeout; + + /* Only continue if the CAN controller is currently disabled. */ + if ((CANx->MCR & CAN_MCR_MDIS_MASK) != 0U) + { + /* Request enabled mode. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(0U); + /* Set timeout time for leaving disabled mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for disabled mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_LPMACK_MASK)) != 0U) + { + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } + } +} /*** end of CanDisabledModeExit ***/ + + +/************************************************************************************//** +** \brief Initializes the CAN communication interface. +** \return none. +** +****************************************************************************************/ +static void BootComCanInit(void) +{ + unsigned short prescaler = 0; + tCanBusTiming timingCfg = { 0 }; + unsigned char rjw; + unsigned short idx; + unsigned long timeout; + unsigned long rxMsgId = BOOT_COM_CAN_RX_MSG_ID; + + /* Enable the CAN peripheral clock. */ + PCC->PCCn[PCC_FlexCANx_INDEX] |= PCC_PCCn_CGC_MASK; + + /* The source clock needs to be configured first. For this the CAN controller must be + * in disabled mode, but that can only be entered after first entering freeze mode, + * which in turn can only be in enabled mode. So first enable the module, then goto + * freeze mode and finally enter disabled mode. + */ + CanDisabledModeExit(); + CanFreezeModeEnter(); + CanDisabledModeEnter(); + /* Configure SOSCDIV2 as the source clock. This assumes that an external oscillator + * is available, which is typically the case to meet the clock tolerance requirements + * of the CAN 2.0B secification. + */ + CANx->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK; + /* Leave disabled mode. */ + CanDisabledModeExit(); + /* Make sure freeze mode is active to be able to initialize the CAN controller. */ + CanFreezeModeEnter(); + + /* Obtain bittiming configuration information. */ + (void)CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &timingCfg); + + /* Reset the current bittiming configuration. */ + CANx->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_PROPSEG_MASK | + CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | CAN_CTRL1_RJW_MASK | + CAN_CTRL1_SMP_MASK); + /* Configure the baudrate prescaler. */ + CANx->CTRL1 |= CAN_CTRL1_PRESDIV(prescaler - 1U); + /* Configure the propagation segment. */ + CANx->CTRL1 |= CAN_CTRL1_PROPSEG(timingCfg.propSeg - 1U); + /* Configure the phase segments. */ + CANx->CTRL1 |= CAN_CTRL1_PSEG1(timingCfg.phaseSeg1 - 1U); + CANx->CTRL1 |= CAN_CTRL1_PSEG2(timingCfg.phaseSeg2 - 1U); + /* The resynchronization jump width (RJW) can be 1 - 4 TQ, yet should never be larger + * than pseg1. Configure the longest possible value for RJW. + */ + rjw = (timingCfg.phaseSeg1 < 4) ? timingCfg.phaseSeg1 : 4; + CANx->CTRL1 |= CAN_CTRL1_RJW(rjw - 1U); + /* All the entries in canTiming[] have a PSEG1 >= 2, so three samples can be used to + * determine the value of the received bit, instead of the default one. + */ + CANx->CTRL1 |= CAN_CTRL1_SMP(1U); + + /* Clear the message box RAM. Each message box covers 4 words (1 word = 32-bits. */ + for (idx = 0; idx < (CANx_MAX_MB_NUM * 4U); idx++) + { + CANx->RAMn[idx] = 0U; + } + /* Clear the reception mask register for each message box. */ + for (idx = 0; idx < CANx_MAX_MB_NUM; idx++) + { + CANx->RXIMR[idx] = 0U; + } + /* Configure the maximum number of message boxes. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB(CANx_MAX_MB_NUM - 1U); + /* Disable the self reception feature. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_SRXDIS_MASK) | CAN_MCR_SRXDIS(1U); + + /* Enable individual reception masking. This disables the legacy support for the + * global reception mask and the mailbox 14/15 individual reception mask. + */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_IRMQ_MASK) | CAN_MCR_IRMQ(1U); + /* Disable the reception FIFO. This driver only needs to receive one CAN message + * identifier. It is sufficient to use just one dedicated mailbox for this. + */ + CANx->MCR &= ~CAN_MCR_RFEN_MASK; + /* Configure the mask of the invididual message reception mailbox to check all ID bits + * and also the IDE bit. + */ + CANx->RXIMR[CAN_RX_MSGBOX_NUM] = 0x40000000U | 0x1FFFFFFFU; + /* Configure the reception mailbox to receive just the CAN message configured with + * BOOT_COM_CAN_RX_MSG_ID. + * EDL, BRS, ESI=0: CANFD not used. + * CODE=0b0100: mailbox set to active and empty. + * IDE=0: 11-bit CAN identifier. + * SRR, RTR, TIME STAMP=0: not applicable. + */ + CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] = 0x04000000; + /* Store the message identifier to receive in the mailbox RAM. */ + if ((rxMsgId & 0x80000000U) != 0U) + { + /* It is a 29-bit extended CAN identifier. */ + rxMsgId &= ~0x80000000U; + /* Set the IDE bit to configure the message for a 29-bit identifier. */ + CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] |= CAN_WMBn_CS_IDE_MASK; + /* Store the 29-bit CAN identifier. */ + CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(rxMsgId); + } + else + { + /* Store the 11-bit CAN identifier. */ + CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(rxMsgId << 18U); + } + + /* Disable all message box interrupts. */ + CANx->IMASK1 = 0U; + /* Clear all mesasge box interrupt flags. */ + CANx->IFLAG1 = CAN_IMASK1_BUF31TO0M_MASK; + /* Clear all error interrupt flags */ + CANx->ESR1 = CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK | + CAN_ESR1_TWRNINT_MASK | CAN_ESR1_BOFFDONEINT_MASK | + CAN_ESR1_ERRINT_FAST_MASK | CAN_ESR1_ERROVR_MASK; + + /* Switch to normal user mode. */ + CANx->MCR &= ~CAN_MCR_SUPV_MASK; + CANx->CTRL1 &= ~(CAN_CTRL1_LOM_MASK | CAN_CTRL1_LPB_MASK); + /* Exit freeze mode. */ + CanFreezeModeExit(); + /* Set timeout time for entering normal user mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for normal user mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_NOTRDY_MASK)) != 0U) + { + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } +} /*** end of BootComCanInit ***/ + + +/************************************************************************************//** +** \brief Receives the CONNECT request from the host, which indicates that the +** bootloader should be activated and, if so, activates it. +** \return none. +** +****************************************************************************************/ +static void BootComCanCheckActivationRequest(void) +{ + unsigned char * pMsgBoxData; + unsigned char byteIdx; + unsigned char rxMsgData[8]; + unsigned char rxMsgLen; + + /* Check if a message was received in the individual mailbox configured to receive + * the BOOT_COM_CAN_RX_MSG_ID message. + */ + if ((CANx->IFLAG1 & (1U << CAN_RX_MSGBOX_NUM)) != 0U) + { + /* Note that there is no need to verify the identifier of the CAN message because the + * mailbox is configured to only receive the BOOT_COM_CAN_TX_MSG_ID message. Start + * by reading out the DLC of the newly received CAN message. + */ + rxMsgLen = (CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] & CAN_WMBn_CS_DLC_MASK) >> CAN_WMBn_CS_DLC_SHIFT; + /* Read the data bytes of the CAN message from the mailbox RAM. */ + pMsgBoxData = (unsigned char *)(&CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 2U]); + for (byteIdx = 0; byteIdx < rxMsgLen; byteIdx++) + { + rxMsgData[byteIdx] = pMsgBoxData[((byteIdx) & ~3U) + (3U - ((byteIdx) & 3U))]; + } + /* Clear the mailbox interrupt flag by writing a 1 to the corresponding box. */ + CANx->IFLAG1 = (1U << CAN_RX_MSGBOX_NUM); + /* Read the free running timer to unlock the mailbox. */ + dummyTimerVal = CANx->TIMER; + + /* check if this was an XCP CONNECT command */ + if ((rxMsgData[0] == 0xff) && (rxMsgLen == 2)) + { + /* connection request received so start the bootloader */ + BootActivate(); + } + } +} /*** end of BootComCanCheckActivationRequest ***/ +#endif /* BOOT_COM_CAN_ENABLE > 0 */ + + +/*********************************** end of boot.c *************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/boot.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/boot.h new file mode 100644 index 00000000..9d2c34c3 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/boot.h @@ -0,0 +1,40 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/boot.h +* \brief Demo program bootloader interface header file. +* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef BOOT_H +#define BOOT_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void BootComInit(void); +void BootComCheckActivationRequest(void); +void BootActivate(void); + + +#endif /* BOOT_H */ +/*********************************** end of boot.h *************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/header.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/header.h new file mode 100644 index 00000000..857057fa --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/header.h @@ -0,0 +1,42 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/header.h +* \brief Generic header file. +* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef HEADER_H +#define HEADER_H + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "../Boot/blt_conf.h" /* bootloader configuration */ +#include "boot.h" /* bootloader interface driver */ +#include "led.h" /* LED driver */ +#include "timer.h" /* Timer driver */ +#include "device_registers.h" /* Device registers */ +#include "system_S32K118.h" /* Device sconfiguration */ + +#endif /* HEADER_H */ +/*********************************** end of header.h ***********************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/led.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/led.c new file mode 100644 index 00000000..97e67db4 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/led.c @@ -0,0 +1,96 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/led.c +* \brief LED driver source file. +* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Toggle interval time in milliseconds. */ +#define LED_TOGGLE_MS (500U) + + +/************************************************************************************//** +** \brief Initializes the LED. +** \return none. +** +****************************************************************************************/ +void LedInit(void) +{ + /* LED GPIO pin configuration. PE8 = GPIO, MUX = ALT1. */ + PORTE->PCR[8] = PORT_PCR_MUX(1); + /* Configure Port E pin 8 GPIO as digital output. */ + PTE->PDDR |= GPIO_PDDR_PDD(1 << 8U); + /* Turn the LED off on Port E pin 8. */ + PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U); +} /*** end of LedInit ***/ + + +/************************************************************************************//** +** \brief Toggles the LED at a fixed time interval. +** \return none. +** +****************************************************************************************/ +void LedToggle(void) +{ + static unsigned char led_toggle_state = 0; + static unsigned long timer_counter_last = 0; + unsigned long timer_counter_now; + + /* Check if toggle interval time passed. */ + timer_counter_now = TimerGet(); + if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS) + { + /* Not yet time to toggle. */ + return; + } + + /* Determine toggle action. */ + if (led_toggle_state == 0) + { + led_toggle_state = 1; + /* Turn the LED on. */ + PTE->PSOR |= GPIO_PSOR_PTSO(1 << 8U); + } + else + { + led_toggle_state = 0; + /* Turn the LED off. */ + PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U); + } + + /* Store toggle time to determine next toggle interval. */ + timer_counter_last = timer_counter_now; +} /*** end of LedToggle ***/ + + +/*********************************** end of led.c **************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/led.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/led.h new file mode 100644 index 00000000..28d28c0c --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/led.h @@ -0,0 +1,39 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/led.h +* \brief LED driver header file. +* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef LED_H +#define LED_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void LedInit(void); +void LedToggle(void); + + +#endif /* LED_H */ +/*********************************** end of led.h **************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/S32K118.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/S32K118.h new file mode 100644 index 00000000..d1f10a17 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/S32K118.h @@ -0,0 +1,10438 @@ +/* +** ################################################################### +** Processor: S32K118 +** Reference manual: S32K1XXRM Rev. 9, 09/2018 +** Version: rev. 1.3, 2019-02-19 +** Build: b190219 +** +** Abstract: +** Peripheral Access Layer for S32K118 +** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2017-12-14) - Mihai Volmer +** Initial version based on S32K1XXRM Rev. 6, 12/2017. +** - rev. 1.1 (2018-02-08) - Mihai Volmer +** Renamed the NVIC register array IP to IPR to reflect the register access difference from Cortex-M4 NVIC registers +** Fixed CSE_PRAM base address +** - rev. 1.2 (2018-07-19) - Dan Nastasa +** Updated the header based on S32K1XXRM Rev. 8, 06/2018. +** Added MTB_DWT peripheral to the header file +** - rev. 1.3 (2019-02-19) - Ionut Pavel +** Updated the header based on S32K1XXRM Rev. 9, 09/2018. +** Removed LMEM_LMDR2 register from the header file. +** Modified LMEM_LMPECR register to Read-Only. +** +** ################################################################### +*/ + +/*! + * @file S32K118.h + * @version 1.3 + * @date 2019-02-19 + * @brief Peripheral Access Layer for S32K118 + * + * This file contains register definitions and macros for easy access to their + * bit fields. + * + * This file assumes LITTLE endian system. + */ + +/** +* @page misra_violations MISRA-C:2012 violations +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced +* The SoC header defines typedef for all modules. +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced +* The SoC header defines macros for all modules and registers. +* +* @section [global] +* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro +* These are generated macros used for accessing the bit-fields from registers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.1, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.2, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.4, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.5, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler +* This type qualifier is needed to ensure correct I/O access and addressing. +*/ + +/* ---------------------------------------------------------------------------- + -- MCU activation + ---------------------------------------------------------------------------- */ + +/* Prevention from multiple including the same memory map */ +#if !defined(S32K118_H_) /* Check if memory map has not been already included */ +#define S32K118_H_ +#define MCU_S32K118 + +/* Check if another memory map has not been also included */ +#if (defined(MCU_ACTIVE)) + #error S32K118 memory map: There is already included another memory map. Only one memory map can be included. +#endif /* (defined(MCU_ACTIVE)) */ +#define MCU_ACTIVE + +#include + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0003u + +/* ---------------------------------------------------------------------------- + -- Generic macros + ---------------------------------------------------------------------------- */ + +/* IO definitions (access restrictions to peripheral registers) */ +/** +* IO Type Qualifiers are used +* \li to specify the access to peripheral variables. +* \li for automatic generation of peripheral register debug information. +*/ +#ifndef __IO +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ +#endif + + +/** +* @brief 32 bits memory read macro. +*/ +#if !defined(REG_READ32) + #define REG_READ32(address) (*(volatile uint32_t*)(address)) +#endif + +/** +* @brief 32 bits memory write macro. +*/ +#if !defined(REG_WRITE32) + #define REG_WRITE32(address, value) ((*(volatile uint32_t*)(address))= (uint32_t)(value)) +#endif + +/** +* @brief 32 bits bits setting macro. +*/ +#if !defined(REG_BIT_SET32) + #define REG_BIT_SET32(address, mask) ((*(volatile uint32_t*)(address))|= (uint32_t)(mask)) +#endif + +/** +* @brief 32 bits bits clearing macro. +*/ +#if !defined(REG_BIT_CLEAR32) + #define REG_BIT_CLEAR32(address, mask) ((*(volatile uint32_t*)(address))&= ((uint32_t)~((uint32_t)(mask)))) +#endif + +/** +* @brief 32 bit clear bits and set with new value +* @note It is user's responsability to make sure that value has only "mask" bits set - (value&~mask)==0 +*/ +#if !defined(REG_RMW32) + #define REG_RMW32(address, mask, value) (REG_WRITE32((address), ((REG_READ32(address)& ((uint32_t)~((uint32_t)(mask))))| ((uint32_t)(value))))) +#endif + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers for S32K118 + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers_S32K118 Interrupt vector numbers for S32K118 + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 48u /**< Number of interrupts in the Vector table */ + +/** + * @brief Defines the Interrupt Numbers definitions + * + * This enumeration is used to configure the interrupts. + * + * Implements : IRQn_Type_Class + */ +typedef enum +{ + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_IRQn = 0u, /**< DMA channel 0 transfer complete */ + DMA1_IRQn = 1u, /**< DMA channel 1 transfer complete */ + DMA2_IRQn = 2u, /**< DMA channel 2 transfer complete */ + DMA3_IRQn = 3u, /**< DMA channel 3 transfer complete */ + DMA_Error_IRQn = 4u, /**< DMA error interrupt channels 0-3 */ + ERM_fault_IRQn = 5u, /**< ERM single and double bit error correction */ + RTC_IRQn = 6u, /**< RTC alarm interrupt */ + RTC_Seconds_IRQn = 7u, /**< RTC seconds interrupt */ + LPTMR0_IRQn = 8u, /**< LPTIMER interrupt request */ + PORT_IRQn = 9u, /**< Port A, B, C, D and E pin detect interrupt */ + CAN0_ORed_Err_Wakeup_IRQn = 10u, /**< OR’ed [Bus Off OR Bus Off Done OR Transmit Warning OR Receive Warning], Interrupt indicating that errors were detected on the CAN bus, Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode */ + CAN0_ORed_0_31_MB_IRQn = 11u, /**< OR'ed Message buffer (0-15, 16-31) */ + FTM0_Ch0_7_IRQn = 12u, /**< FTM0 Channel 0 to 7 interrupt */ + FTM0_Fault_IRQn = 13u, /**< FTM0 Fault interrupt */ + FTM0_Ovf_Reload_IRQn = 14u, /**< FTM0 Counter overflow and Reload interrupt */ + FTM1_Ch0_7_IRQn = 15u, /**< FTM1 Channel 0 to 7 interrupt */ + FTM1_Fault_IRQn = 16u, /**< FTM1 Fault interrupt */ + FTM1_Ovf_Reload_IRQn = 17u, /**< FTM1 Counter overflow and Reload interrupt */ + FTFC_IRQn = 18u, /**< FTFC Command complete, Read collision and Double bit fault detect */ + PDB0_IRQn = 19u, /**< PDB0 interrupt */ + LPIT0_IRQn = 20u, /**< LPIT interrupt */ + SCG_CMU_LVD_LVWSCG_IRQn = 21u, /**< PMC Low voltage detect interrupt, SCG bus interrupt request and CMU loss of range interrupt */ + WDOG_IRQn = 22u, /**< WDOG interrupt request out before wdg reset out */ + RCM_IRQn = 23u, /**< RCM Asynchronous Interrupt */ + LPI2C0_Master_Slave_IRQn = 24u, /**< LPI2C0 Master Interrupt and Slave Interrupt */ + FLEXIO_IRQn = 25u, /**< FlexIO Interrupt */ + LPSPI0_IRQn = 26u, /**< LPSPI0 Interrupt */ + LPSPI1_IRQn = 27u, /**< LPSPI1 Interrupt */ + ADC0_IRQn = 28u, /**< ADC0 interrupt request. */ + CMP0_IRQn = 29u, /**< CMP0 interrupt request */ + LPUART1_RxTx_IRQn = 30u, /**< LPUART1 Transmit / Receive Interrupt */ + LPUART0_RxTx_IRQn = 31u /**< LPUART0 Transmit / Receive Interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers_S32K118 */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer for S32K118 + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer_S32K118 Device Peripheral Access Layer for S32K118 + * @{ + */ + +/* @brief This module covers memory mapped registers available on SoC */ + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + + +/** ADC - Size of Registers Arrays */ +#define ADC_SC1_COUNT 16u +#define ADC_R_COUNT 16u +#define ADC_CV_COUNT 2u + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[ADC_SC1_COUNT]; /**< ADC Status and Control Register 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ + __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x44 */ + __I uint32_t R[ADC_R_COUNT]; /**< ADC Data Result Registers, array offset: 0x48, array step: 0x4 */ + __IO uint32_t CV[ADC_CV_COUNT]; /**< Compare Value Registers, array offset: 0x88, array step: 0x4 */ + __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x90 */ + __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x94 */ + __IO uint32_t BASE_OFS; /**< BASE Offset Register, offset: 0x98 */ + __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x9C */ + __IO uint32_t USR_OFS; /**< USER Offset Correction Register, offset: 0xA0 */ + __IO uint32_t XOFS; /**< ADC X Offset Correction Register, offset: 0xA4 */ + __IO uint32_t YOFS; /**< ADC Y Offset Correction Register, offset: 0xA8 */ + __IO uint32_t G; /**< ADC Gain Register, offset: 0xAC */ + __IO uint32_t UG; /**< ADC User Gain Register, offset: 0xB0 */ + __IO uint32_t CLPS; /**< ADC General Calibration Value Register S, offset: 0xB4 */ + __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register 3, offset: 0xB8 */ + __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register 2, offset: 0xBC */ + __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register 1, offset: 0xC0 */ + __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register 0, offset: 0xC4 */ + __IO uint32_t CLPX; /**< ADC Plus-Side General Calibration Value Register X, offset: 0xC8 */ + __IO uint32_t CLP9; /**< ADC Plus-Side General Calibration Value Register 9, offset: 0xCC */ + __IO uint32_t CLPS_OFS; /**< ADC General Calibration Offset Value Register S, offset: 0xD0 */ + __IO uint32_t CLP3_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 3, offset: 0xD4 */ + __IO uint32_t CLP2_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 2, offset: 0xD8 */ + __IO uint32_t CLP1_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 1, offset: 0xDC */ + __IO uint32_t CLP0_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 0, offset: 0xE0 */ + __IO uint32_t CLPX_OFS; /**< ADC Plus-Side General Calibration Offset Value Register X, offset: 0xE4 */ + __IO uint32_t CLP9_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 9, offset: 0xE8 */ +} ADC_Type, *ADC_MemMapPtr; + + /** Number of instances of the ADC module. */ +#define ADC_INSTANCE_COUNT (1u) + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x4003B000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0 } + /** Number of interrupt vector arrays for the ADC module. */ +#define ADC_IRQS_ARR_COUNT (1u) + /** Number of interrupt channels for the ADC module. */ +#define ADC_IRQS_CH_COUNT (1u) +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* SC1 Bit Fields */ +#define ADC_SC1_ADCH_MASK 0x1Fu +#define ADC_SC1_ADCH_SHIFT 0u +#define ADC_SC1_ADCH_WIDTH 5u +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<VTOR} + +/* FTM module features */ + +/* @brief Number of PWM channels */ +#define FEATURE_FTM_CHANNEL_COUNT (8U) +/* @brief Number of fault channels */ +#define FTM_FEATURE_FAULT_CHANNELS (4U) +/* @brief Width of control channel */ +#define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH (8U) +/* @brief Output channel offset */ +#define FTM_FEATURE_OUTPUT_CHANNEL_OFFSET (16U) +/* @brief Max counter value */ +#define FTM_FEATURE_CNT_MAX_VALUE_U32 (0x0000FFFFU) +/* @brief Input capture for single shot */ +#define FTM_FEATURE_INPUT_CAPTURE_SINGLE_SHOT (2U) +/* @brief Dithering has supported on the generated PWM signals */ +#define FEATURE_FTM_HAS_SUPPORTED_DITHERING (1U) +/* @brief Number of interrupt vector for channels of the FTM module. */ +#define FEATURE_FTM_HAS_NUM_IRQS_CHANS (1U) + +/* LPIT module features */ + +/*! @brief Number of interrupt vector for channels of the LPIT module. */ +#define FEATURE_LPIT_HAS_NUM_IRQS_CHANS (1U) +/*! @brief Clock names for LPIT. */ +#define LPIT_CLOCK_NAMES {LPIT0_CLK} + +/* LPI2C module features */ + +/* @brief DMA instance used for LPI2C module */ +#define LPI2C_DMA_INSTANCE 0U + +/* @brief EDMA requests for LPI2C module. */ +#define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}} +/* @brief PCC clocks for LPI2C module. */ +#define LPI2C_PCC_CLOCKS {LPI2C0_CLK} + +/* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */ +#define LPI2C_HAS_FAST_PLUS_MODE (0U) +#define LPI2C_HAS_HIGH_SPEED_MODE (0U) +#define LPI2C_HAS_ULTRA_FAST_MODE (0U) + +/* LPI2C module features */ + +/* @brief DMA instance used for LPI2C module */ +#define LPI2C_DMA_INSTANCE 0U + +/* @brief EDMA requests for LPI2C module. */ +#define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}} +/* @brief PCC clocks for LPI2C module. */ +#define LPI2C_PCC_CLOCKS {LPI2C0_CLK} + +/* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */ +#define LPI2C_HAS_FAST_PLUS_MODE (0U) +#define LPI2C_HAS_HIGH_SPEED_MODE (0U) +#define LPI2C_HAS_ULTRA_FAST_MODE (0U) + +/* MSCM module features */ + +/* @brief Has interrupt router control registers (IRSPRCn). */ +#define FEATURE_MSCM_HAS_INTERRUPT_ROUTER (0) +/* @brief Has directed CPU interrupt routerregisters (IRCPxxx). */ +#define FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER (0) + +/* CSEc module features */ + +/*! @brief CSE_PRAM offset of the page length parameter used by the following +commands: CMD_ENC_ECB, CMD_ENC_CBC, CMD_DEC_ECB, CMD_DEC_CBC, CMD_MP_COMPRESS */ +#define FEATURE_CSEC_PAGE_LENGTH_OFFSET (0xEU) +/*! @brief CSE_PRAM offset of the message length parameter used by the following +commands: CMD_GENERATE_MAC, CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_MESSAGE_LENGTH_OFFSET (0xCU) +/*! @brief CSE_PRAM offset of the MAC length parameter used by the following +commands: CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_MAC_LENGTH_OFFSET (0x8U) +/*! @brief CSE_PRAM offset of the boot size parameter used by the following +commands: CMD_BOOT_DEFINE */ +#define FEATURE_CSEC_BOOT_SIZE_OFFSET (0x1CU) +/*! @brief CSE_PRAM offset of the boot flavor parameter used by the following +commands: CMD_BOOT_DEFINE */ +#define FEATURE_CSEC_BOOT_FLAVOR_OFFSET (0x1BU) +/*! @brief CSE_PRAM offset of the Flash start address parameter used by the +following commands: CMD_GENERATE_MAC, CMD_VERIFY_MAC (pointer method) */ +#define FEATURE_CSEC_FLASH_START_ADDRESS_OFFSET (0x10U) +/*! @brief CSE_PRAM offset of the verification status parameter used by the +following commands: CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_VERIFICATION_STATUS_OFFSET (0x14U) +/*! @brief CSE_PRAM offset of the error bits field contained by all commands */ +#define FEATURE_CSEC_ERROR_BITS_OFFSET (0x4U) +/*! @brief CSE_PRAM offset of the SREG parameter used by the following commands: +CMD_GET_ID */ +#define FEATURE_CSEC_SREG_OFFSET (0x2FU) + +/*! @brief CSE_PRAM offset of page 0 */ +#define FEATURE_CSEC_PAGE_0_OFFSET (0x0U) +/*! @brief CSE_PRAM offset of page 1 */ +#define FEATURE_CSEC_PAGE_1_OFFSET (0x10U) +/*! @brief CSE_PRAM offset of page 2 */ +#define FEATURE_CSEC_PAGE_2_OFFSET (0x20U) +/*! @brief CSE_PRAM offset of page 3 */ +#define FEATURE_CSEC_PAGE_3_OFFSET (0x30U) +/*! @brief CSE_PRAM offset of page 4 */ +#define FEATURE_CSEC_PAGE_4_OFFSET (0x40U) +/*! @brief CSE_PRAM offset of page 5 */ +#define FEATURE_CSEC_PAGE_5_OFFSET (0x50U) +/*! @brief CSE_PRAM offset of page 6 */ +#define FEATURE_CSEC_PAGE_6_OFFSET (0x60U) +/*! @brief CSE_PRAM offset of page 7 */ +#define FEATURE_CSEC_PAGE_7_OFFSET (0x70U) + +/* CRC module features */ + +/* @brief CRC module use for S32K. */ +#define FEATURE_CRC_DRIVER_SOFT_POLYNOMIAL +/* @brief Default CRC bit width */ +#define FEATURE_CRC_DEFAULT_WIDTH CRC_BITS_16 +/* @brief Default CRC read transpose */ +#define FEATURE_CRC_DEFAULT_READ_TRANSPOSE CRC_TRANSPOSE_NONE +/* @brief Default CRC write transpose */ +#define FEATURE_CRC_DEFAULT_WRITE_TRANSPOSE CRC_TRANSPOSE_NONE +/* @brief Default polynomial 0x1021U */ +#define FEATURE_CRC_DEFAULT_POLYNOMIAL (0x1021U) +/* @brief Default seed value is 0xFFFFU */ +#define FEATURE_CRC_DEFAULT_SEED (0xFFFFU) + +/* PORT module features */ +/*! @brief PORT Used for setting Pins */ +#define FEATURE_PINS_DRIVER_USING_PORT (1) +/* @brief Has control lock (register bit PCR[LK]). */ +#define FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FEATURE_PINS_HAS_OPEN_DRAIN (0) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FEATURE_PORT_HAS_DIGITAL_FILTER (1) +/* @brief Has trigger output to trigger other peripherals (register bit field PCR[IRQC] values). */ +#define FEATURE_PORT_HAS_TRIGGER_OUT (0) +/* @brief Has setting flag only (register bit field PCR[IRQC] values). */ +#define FEATURE_PORT_HAS_FLAG_SET_ONLY (0) +/* @brief Has over-current feature (register bit field PCR[OCIE] values). */ +#define FEATURE_PINS_HAS_OVER_CURRENT (0) +/* @brief Has pull resistor selection available. */ +#define FEATURE_PINS_HAS_PULL_SELECTION (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FEATURE_PINS_HAS_SLEW_RATE (0) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength (register bit PCR[DSE]). */ +#define FEATURE_PINS_HAS_DRIVE_STRENGTH (1) +/* @brief Has drive strength control bits*/ +#define FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL (0) +/* @brief Has port input disable control bits*/ +#define FEATURE_PORT_HAS_INPUT_DISABLE (0) +/* @brief SIM_CHIPCTL_ADC_INTERLEAVE_EN bit is not available */ +#define FEATURE_PINS_HAS_ADC_INTERLEAVE_EN (0) + +/* MPU module features */ + +/* @brief Specifies hardware revision level. */ +#define FEATURE_MPU_HARDWARE_REVISION_LEVEL (1U) +/* @brief Has process identifier support. */ +#define FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1U) +/* @brief Specifies total number of bus masters. */ +#define FEATURE_MPU_MASTER_COUNT (3U) +/* @brief Specifies maximum number of masters which have separated +privilege rights for user and supervisor mode accesses (e.g. master0~3 in S32K1xx). +*/ +#define FEATURE_MPU_MAX_LOW_MASTER_NUMBER (3U) +/* @brief Specifies maximum number of masters which have only +read and write permissions (e.g. master4~7 in S32K1xx). +*/ +#define FEATURE_MPU_MAX_HIGH_MASTER_NUMBER (7U) + +/* @brief Specifies number of set access control right bits for + masters which have separated privilege rights for user and + supervisor mode accesses (e.g. master0~3 in S32K1xx). +*/ +#define FEATURE_MPU_LOW_MASTER_CONTROL_WIDTH (6U) +/* @brief Specifies number of set access control right bits for + masters which have only read and write permissions(e.g. master4~7 in S32K1xx). +*/ +#define FEATURE_MPU_HIGH_MASTER_CONTROL_WIDTH (2U) + +/* @brief The MPU Logical Bus Master Number for core bus master. */ +#define FEATURE_MPU_MASTER_CORE (0U) +/* @brief The MPU Logical Bus Master Number for Debugger master. */ +#define FEATURE_MPU_MASTER_DEBUGGER (1U) +/* @brief The MPU Logical Bus Master Number for DMA master. */ +#define FEATURE_MPU_MASTER_DMA (2U) +/* @brief Specifies master number. */ +#define FEATURE_MPU_MASTER \ +{ \ + FEATURE_MPU_MASTER_CORE, /*!< CORE */ \ + FEATURE_MPU_MASTER_DEBUGGER, /*!< DEBUGGER */ \ + FEATURE_MPU_MASTER_DMA, /*!< DMA */ \ +} + +/* @brief Specifies total number of slave ports. */ +#define FEATURE_MPU_SLAVE_COUNT (2U) +/* @brief The MPU Slave Port Assignment for Flash Controller and boot ROM. */ +#define FEATURE_MPU_SLAVE_FLASH_BOOTROM (0U) +/* @brief The MPU Slave Port Assignment for SRAM, MTB, DWT and MCM. */ +#define FEATURE_MPU_SLAVE_SRAM_MTB_DWT_MCM (1U) +/* @brief The MPU Slave Port mask. */ +#define FEATURE_MPU_SLAVE_MASK (0xC0000000U) +#define FEATURE_MPU_SLAVE_SHIFT (30u) +#define FEATURE_MPU_SLAVE_WIDTH (2u) +#define FEATURE_MPU_SLAVE(x) (((uint32_t)(((uint32_t)(x))<> (uint32_t)FEATURE_DMA_CH_WIDTH) +/* @brief DMA virtual channel to channel */ +#define FEATURE_DMA_VCH_TO_CH(x) ((x) & ((uint32_t)FEATURE_DMA_CHANNELS - 1U)) +/* @brief DMA supports the following particular channel priorities: */ +#define FEATURE_DMA_4_CH_PRIORITIES +/* @brief DMA supports bus bandwidth control. */ +#define FEATURE_DMA_ENGINE_STALL + +/* DMAMUX module features */ + +/* @brief DMAMUX peripheral is available in silicon. */ +#define FEATURE_DMAMUX_AVAILABLE +/* @brief Number of DMA channels. */ +#define FEATURE_DMAMUX_CHANNELS (4U) +/* @brief Has the periodic trigger capability */ +#define FEATURE_DMAMUX_HAS_TRIG (1) +/* @brief Conversion from request source to the actual DMAMUX channel */ +#define FEATURE_DMAMUX_REQ_SRC_TO_CH(x) (x) +/* @brief Mapping between request source and DMAMUX instance */ +#define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x) (0U) +/* @brief Conversion from eDMA channel index to DMAMUX channel. */ +#define FEATURE_DMAMUX_DMA_CH_TO_CH(x) (x) +/* @brief Conversion from DMAMUX channel DMAMUX register index. */ +#define FEATURE_DMAMUX_CHN_REG_INDEX(x) (x) +/* @brief Clock names for DMAMUX. */ +#define FEATURE_DMAMUX_CLOCK_NAMES {DMAMUX0_CLK} + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum { + EDMA_REQ_DISABLED = 0U, + EDMA_REQ_LPUART0_RX = 2U, + EDMA_REQ_LPUART0_TX = 3U, + EDMA_REQ_LPUART1_RX = 4U, + EDMA_REQ_LPUART1_TX = 5U, + EDMA_REQ_FLEXIO_SHIFTER0 = 10U, + EDMA_REQ_FLEXIO_SHIFTER1 = 11U, + EDMA_REQ_FLEXIO_SHIFTER2 = 12U, + EDMA_REQ_FLEXIO_SHIFTER3 = 13U, + EDMA_REQ_LPSPI0_RX = 14U, + EDMA_REQ_LPSPI0_TX = 15U, + EDMA_REQ_LPSPI1_RX = 16U, + EDMA_REQ_LPSPI1_TX = 17U, + EDMA_REQ_FTM1_CHANNEL_0 = 20U, + EDMA_REQ_FTM1_CHANNEL_1 = 21U, + EDMA_REQ_FTM1_CHANNEL_2 = 22U, + EDMA_REQ_FTM1_CHANNEL_3 = 23U, + EDMA_REQ_FTM1_CHANNEL_4 = 24U, + EDMA_REQ_FTM1_CHANNEL_5 = 25U, + EDMA_REQ_FTM1_CHANNEL_6 = 26U, + EDMA_REQ_FTM1_CHANNEL_7 = 27U, + EDMA_REQ_FTM0_OR_CH0_CH7 = 36U, + EDMA_REQ_ADC0 = 42U, + EDMA_REQ_LPI2C0_RX = 44U, + EDMA_REQ_LPI2C0_TX = 45U, + EDMA_REQ_PDB0 = 46U, + EDMA_REQ_CMP0 = 48U, + EDMA_REQ_PORTA = 49U, + EDMA_REQ_PORTB = 50U, + EDMA_REQ_PORTC = 51U, + EDMA_REQ_PORTD = 52U, + EDMA_REQ_PORTE = 53U, + EDMA_REQ_FLEXCAN0 = 54U, + EDMA_REQ_LPTMR0 = 59U, + EDMA_REQ_DMAMUX_ALWAYS_ENABLED0 = 62U, + EDMA_REQ_DMAMUX_ALWAYS_ENABLED1 = 63U +} dma_request_source_t; + + +/* TRGMUX module features */ +/*! + * @brief Enumeration for trigger source module of TRGMUX + * + * Describes all possible inputs (trigger sources) of the TRGMUX IP + * This enumeration depends on the supported instances in device + */ +enum trgmux_trigger_source_e +{ + TRGMUX_TRIG_SOURCE_DISABLED = 0U, + TRGMUX_TRIG_SOURCE_VDD = 1U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN0 = 2U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN1 = 3U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN2 = 4U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN3 = 5U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN4 = 6U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN5 = 7U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN6 = 8U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN7 = 9U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN8 = 10U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN9 = 11U, + TRGMUX_TRIG_SOURCE_CMP0_OUT = 14U, + TRGMUX_TRIG_SOURCE_LPIT_CH0 = 17U, + TRGMUX_TRIG_SOURCE_LPIT_CH1 = 18U, + TRGMUX_TRIG_SOURCE_LPIT_CH2 = 19U, + TRGMUX_TRIG_SOURCE_LPIT_CH3 = 20U, + TRGMUX_TRIG_SOURCE_LPTMR0 = 21U, + TRGMUX_TRIG_SOURCE_FTM0_INIT_TRIG = 22U, + TRGMUX_TRIG_SOURCE_FTM0_EXT_TRIG = 23U, + TRGMUX_TRIG_SOURCE_FTM1_INIT_TRIG = 24U, + TRGMUX_TRIG_SOURCE_FTM1_EXT_TRIG = 25U, + TRGMUX_TRIG_SOURCE_ADC0_SC1A_COCO = 30U, + TRGMUX_TRIG_SOURCE_ADC0_SC1B_COCO = 31U, + TRGMUX_TRIG_SOURCE_PDB0_CH0_TRIG = 34U, + TRGMUX_TRIG_SOURCE_PDB0_PULSE_OUT = 36U, + TRGMUX_TRIG_SOURCE_RTC_ALARM = 43U, + TRGMUX_TRIG_SOURCE_RTC_SECOND = 44U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG0 = 45U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG1 = 46U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG2 = 47U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG3 = 48U, + TRGMUX_TRIG_SOURCE_LPUART0_RX_DATA = 49U, + TRGMUX_TRIG_SOURCE_LPUART0_TX_DATA = 50U, + TRGMUX_TRIG_SOURCE_LPUART0_RX_IDLE = 51U, + TRGMUX_TRIG_SOURCE_LPUART1_RX_DATA = 52U, + TRGMUX_TRIG_SOURCE_LPUART1_TX_DATA = 53U, + TRGMUX_TRIG_SOURCE_LPUART1_RX_IDLE = 54U, + TRGMUX_TRIG_SOURCE_LPI2C0_MASTER_TRIG = 55U, + TRGMUX_TRIG_SOURCE_LPI2C0_SLAVE_TRIG = 56U, + TRGMUX_TRIG_SOURCE_LPSPI0_FRAME = 59U, + TRGMUX_TRIG_SOURCE_LPSPI0_RX_DATA = 60U, + TRGMUX_TRIG_SOURCE_LPSPI1_FRAME = 61U, + TRGMUX_TRIG_SOURCE_LPSPI1_RX_DATA = 62U, + TRGMUX_TRIG_SOURCE_SIM_SW_TRIG = 63U, +}; + +/*! + * @brief Enumeration for target module of TRGMUX + * + * Describes all possible outputs (target modules) of the TRGMUX IP + * This enumeration depends on the supported instances in device + */ +enum trgmux_target_module_e +{ + TRGMUX_TARGET_MODULE_DMA_CH0 = 0U, + TRGMUX_TARGET_MODULE_DMA_CH1 = 1U, + TRGMUX_TARGET_MODULE_DMA_CH2 = 2U, + TRGMUX_TARGET_MODULE_DMA_CH3 = 3U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT0 = 4U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT1 = 5U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT2 = 6U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT3 = 7U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT4 = 8U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT5 = 9U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA0 = 12U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA1 = 13U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA2 = 14U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA3 = 15U, + TRGMUX_TARGET_MODULE_CMP0_SAMPLE = 28U, + TRGMUX_TARGET_MODULE_FTM0_HWTRIG0 = 40U, + TRGMUX_TARGET_MODULE_FTM0_FAULT0 = 41U, + TRGMUX_TARGET_MODULE_FTM0_FAULT1 = 42U, + TRGMUX_TARGET_MODULE_FTM0_FAULT2 = 43U, + TRGMUX_TARGET_MODULE_FTM1_HWTRIG0 = 44U, + TRGMUX_TARGET_MODULE_FTM1_FAULT0 = 45U, + TRGMUX_TARGET_MODULE_FTM1_FAULT1 = 46U, + TRGMUX_TARGET_MODULE_FTM1_FAULT2 = 47U, + TRGMUX_TARGET_MODULE_PDB0_TRG_IN = 56U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM0 = 68U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM1 = 69U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM2 = 70U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM3 = 71U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH0 = 72U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH1 = 73U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH2 = 74U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH3 = 75U, + TRGMUX_TARGET_MODULE_LPUART0_TRG = 76U, + TRGMUX_TARGET_MODULE_LPUART1_TRG = 80U, + TRGMUX_TARGET_MODULE_LPI2C0_TRG = 84U, + TRGMUX_TARGET_MODULE_LPSPI0_TRG = 92U, + TRGMUX_TARGET_MODULE_LPSPI1_TRG = 96U, + TRGMUX_TARGET_MODULE_LPTMR0_ALT0 = 100U, +}; + +/* @brief Constant array storing the value of all TRGMUX output(target module) identifiers */ +#define FEATURE_TRGMUX_TARGET_MODULE \ +{ \ + TRGMUX_TARGET_MODULE_DMA_CH0, \ + TRGMUX_TARGET_MODULE_DMA_CH1, \ + TRGMUX_TARGET_MODULE_DMA_CH2, \ + TRGMUX_TARGET_MODULE_DMA_CH3, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT0, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT1, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT2, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT3, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT4, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT5, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA0, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA1, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA2, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA3, \ + TRGMUX_TARGET_MODULE_CMP0_SAMPLE, \ + TRGMUX_TARGET_MODULE_FTM0_HWTRIG0, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT0, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT1, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT2, \ + TRGMUX_TARGET_MODULE_FTM1_HWTRIG0, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT0, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT1, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT2, \ + TRGMUX_TARGET_MODULE_PDB0_TRG_IN, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM0, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM1, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM2, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM3, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH0, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH1, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH2, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH3, \ + TRGMUX_TARGET_MODULE_LPUART0_TRG, \ + TRGMUX_TARGET_MODULE_LPUART1_TRG, \ + TRGMUX_TARGET_MODULE_LPI2C0_TRG, \ + TRGMUX_TARGET_MODULE_LPSPI0_TRG, \ + TRGMUX_TARGET_MODULE_LPSPI1_TRG, \ + TRGMUX_TARGET_MODULE_LPTMR0_ALT0 \ +} + + +/* LPSPI module features */ +/* @brief Initial value for state structure */ +#define FEATURE_LPSPI_STATE_STRUCTURES_NULL {NULL, NULL} +/* @brief Clock indexes for LPSPI clock */ +#define FEATURE_LPSPI_CLOCKS_NAMES {LPSPI0_CLK, LPSPI1_CLK}; + +/* FlexIO module features */ + +/* @brief Define the maximum number of shifters for any FlexIO instance. */ +#define FEATURE_FLEXIO_MAX_SHIFTER_COUNT (4U) +/* @brief Define DMA request names for Flexio. */ +#define FEATURE_FLEXIO_DMA_REQ_0 EDMA_REQ_FLEXIO_SHIFTER0 +#define FEATURE_FLEXIO_DMA_REQ_1 EDMA_REQ_FLEXIO_SHIFTER1 +#define FEATURE_FLEXIO_DMA_REQ_2 EDMA_REQ_FLEXIO_SHIFTER2 +#define FEATURE_FLEXIO_DMA_REQ_3 EDMA_REQ_FLEXIO_SHIFTER3 + +/* LPUART module features */ + +/* @brief Has extended data register ED. */ +#define FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FEATURE_LPUART_FIFO_SIZE (4U) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits. */ +#define FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Flag clearance mask for STAT register. */ +#define FEATURE_LPUART_STAT_REG_FLAGS_MASK (0xC01FC000U) +/* @brief Flag clearance mask for FIFO register. */ +#define FEATURE_LPUART_FIFO_REG_FLAGS_MASK (0x00030000U) +/* @brief Reset mask for FIFO register. */ +#define FEATURE_LPUART_FIFO_RESET_MASK (0x0003C000U) +/* @brief Default oversampling ratio. */ +#define FEATURE_LPUART_DEFAULT_OSR (0x0FUL) +/* @brief Default baud rate modulo divisor. */ +#define FEATURE_LPUART_DEFAULT_SBR (0x04UL) +/* @brief Clock names for LPUART. */ +#define LPUART_CLOCK_NAMES {LPUART0_CLK, LPUART1_CLK} + +/* ADC module features */ + +/*! @brief ADC feature flag for extended number of SC1 and R registers, + * generically named 'alias registers' */ +#define FEATURE_ADC_HAS_EXTRA_NUM_REGS (0) + +#define NUMBER_OF_ALT_CLOCKS ADC_CLK_ALT_1 +/*! @brief ADC feature flag for defining number of external ADC channels. + * If each ADC instance has different number of external channels, then + * this define is set with the maximum value. */ +#define FEATURE_ADC_MAX_NUM_EXT_CHANS (16) +#define FEATURE_ADC_HAS_CHANNEL_2 (1) +#define FEATURE_ADC_HAS_CHANNEL_8 (1) +#define ADC_CLOCKS {ADC0_CLK} +/*! @brief ADC number of control channels */ +#if FEATURE_ADC_HAS_EXTRA_NUM_REGS +#define ADC_CTRL_CHANS_COUNT ADC_aSC1_COUNT +#else +#define ADC_CTRL_CHANS_COUNT ADC_SC1_COUNT +#endif /* FEATURE_ADC_HAS_EXTRA_NUM_REGS */ + +/*! @brief ADC default Sample Time from RM */ +#define ADC_DEFAULT_SAMPLE_TIME (0x0CU) +/*! @brief ADC default User Gain from RM */ +#define ADC_DEFAULT_USER_GAIN (0x04U) +/* @brief Max of adc clock frequency */ +#define ADC_CLOCK_FREQ_MAX_RUNTIME (50000000u) +/* @brief Min of adc clock frequency */ +#define ADC_CLOCK_FREQ_MIN_RUNTIME (2000000u) + +/* CAN module features */ + +/* @brief Frames available in Rx FIFO flag shift */ +#define FEATURE_CAN_RXFIFO_FRAME_AVAILABLE (5U) +/* @brief Rx FIFO warning flag shift */ +#define FEATURE_CAN_RXFIFO_WARNING (6U) +/* @brief Rx FIFO overflow flag shift */ +#define FEATURE_CAN_RXFIFO_OVERFLOW (7U) +/* @brief Has Flexible Data Rate for CAN0 */ +#define FEATURE_CAN0_HAS_FD (1) +/* @brief Maximum number of Message Buffers supported for payload size 8 for CAN0 */ +#define FEATURE_CAN0_MAX_MB_NUM (32U) +/* @brief Has PE clock source select (bit field CAN_CTRL1[CLKSRC]). */ +#define FEATURE_CAN_HAS_PE_CLKSRC_SELECT (1) +/* @brief Has DMA enable (bit field MCR[DMA]). */ +#define FEATURE_CAN_HAS_DMA_ENABLE (1) +/* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */ +#define FEATURE_CAN_MAX_MB_NUM (32U) +/* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */ +#define FEATURE_CAN_MAX_MB_NUM_ARRAY { FEATURE_CAN0_MAX_MB_NUM } +/* @brief Has Pretending Networking mode */ +#define FEATURE_CAN_HAS_PRETENDED_NETWORKING (1) +/* @brief Has Stuff Bit Count Enable Bit */ +#define FEATURE_CAN_HAS_STFCNTEN_ENABLE (0) +/* @brief Has ISO CAN FD Enable Bit */ +#define FEATURE_CAN_HAS_ISOCANFDEN_ENABLE (1) +/* @brief Has Message Buffer Data Size Region 1 */ +#define FEATURE_CAN_HAS_MBDSR1 (0) +/* @brief Has Message Buffer Data Size Region 2 */ +#define FEATURE_CAN_HAS_MBDSR2 (0) +/* @brief DMA hardware requests for all FlexCAN instances */ +#define FEATURE_CAN_EDMA_REQUESTS { EDMA_REQ_FLEXCAN0 } + +/* @brief Maximum number of Message Buffers IRQs */ +#define FEATURE_CAN_MB_IRQS_MAX_COUNT (2U) +/* @brief Message Buffers IRQs */ +#define FEATURE_CAN_MB_IRQS { CAN_ORed_0_15_MB_IRQS, \ + CAN_ORed_16_31_MB_IRQS } +/* @brief Has Wake Up Irq channels (CAN_Wake_Up_IRQS_CH_COUNT > 0u) */ +#define FEATURE_CAN_HAS_WAKE_UP_IRQ (1) +/* @brief Has Self Wake Up mode */ +#define FEATURE_CAN_HAS_SELF_WAKE_UP (0) +/* @brief Has Flexible Data Rate */ +#define FEATURE_CAN_HAS_FD (1) +/* @brief Clock name for the PE oscillator clock source */ +#define FEATURE_CAN_PE_OSC_CLK_NAME SOSC_CLK +/* @bried FlexCAN has Detection And Correction of Memory Errors */ +#define FEATURE_CAN_HAS_MEM_ERR_DET (0) + +/* LPTMR module features */ + +/* @brief LPTMR pulse counter input options */ +#define FEATURE_LPTMR_HAS_INPUT_ALT1_SELECTION (1U) + +/* OSIF module features */ + +#define FEATURE_OSIF_USE_SYSTICK (1) +#define FEATURE_OSIF_USE_PIT (0) +#define FEATURE_OSIF_FREERTOS_ISR_CONTEXT_METHOD (1) /* Cortex M device */ + +/* PDB module features */ + +/* @brief PDB has back-to-back at instance level */ +#define FEATURE_PDB_HAS_INSTANCE_BACKTOBACK (0) + +#endif /* S32K118_FEATURES_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/devassert.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/devassert.h new file mode 100644 index 00000000..243c8d45 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/devassert.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DEVASSERT_H +#define DEVASSERT_H + +#include + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced. + * The macro is defined to be used by drivers to validate input parameters and can be disabled. + * + * @section [global] + * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro defined. + * The macros are used to validate input parameters to driver functions. + * + */ + +/** +\page Error_detection_and_reporting Error detection and reporting + +S32 SDK drivers can use a mechanism to validate data coming from upper software layers (application code) by performing +a number of checks on input parameters' range or other invariants that can be statically checked (not dependent on +runtime conditions). A failed validation is indicative of a software bug in application code, therefore it is important +to use this mechanism during development. + +The validation is performed by using DEV_ASSERT macro. +A default implementation of this macro is provided in this file. However, application developers can provide their own +implementation in a custom file. This requires defining the CUSTOM_DEVASSERT symbol with the specific file name in the +project configuration (for example: -DCUSTOM_DEVASSERT="custom_devassert.h") + +The default implementation accommodates two behaviors, based on DEV_ERROR_DETECT symbol: + - When DEV_ERROR_DETECT symbol is defined in the project configuration (for example: -DDEV_ERROR_DETECT), the validation + performed by the DEV_ASSERT macro is enabled, and a failed validation triggers a software breakpoint and further execution is + prevented (application spins in an infinite loop) + This configuration is recommended for development environments, as it prevents further execution and allows investigating + potential problems from the point of error detection. + - When DEV_ERROR_DETECT symbol is not defined, the DEV_ASSERT macro is implemented as no-op, therefore disabling all validations. + This configuration can be used to eliminate the overhead of development-time checks. + +It is the application developer's responsibility to decide the error detection strategy for production code: one can opt to +disable development-time checking altogether (by not defining DEV_ERROR_DETECT symbol), or one can opt to keep the checks +in place and implement a recovery mechanism in case of a failed validation, by defining CUSTOM_DEVASSERT to point +to the file containing the custom implementation. +*/ + +#if defined (CUSTOM_DEVASSERT) + /* If the CUSTOM_DEVASSERT symbol is defined, then add the custom implementation */ + #include CUSTOM_DEVASSERT +#elif defined (DEV_ERROR_DETECT) + /* Implement default assert macro */ +static inline void DevAssert(volatile bool x) +{ + if(x) { } else { BKPT_ASM; for(;;) {} } +} + #define DEV_ASSERT(x) DevAssert(x) +#else + /* Assert macro does nothing */ + #define DEV_ASSERT(x) ((void)0) +#endif + +#endif /* DEVASSERT_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/device_registers.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/device_registers.h new file mode 100644 index 00000000..583a35d5 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/device_registers.h @@ -0,0 +1,67 @@ +/* +** ################################################################### +** Abstract: +** Common include file for CMSIS register access layer headers. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** ################################################################### +*/ + +#ifndef DEVICE_REGISTERS_H +#define DEVICE_REGISTERS_H + +/** +* @page misra_violations MISRA-C:2012 violations +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced. +* The macro defines the device currently in use and may be used by components for specific checks. +* +*/ + + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ + +#if defined(CPU_S32K118) + + #define S32K11x_SERIES + + /* Specific core definitions */ + #include "s32_core_cm0.h" + /* Register definitions */ + #include "S32K118.h" + /* CPU specific feature definitions */ + #include "S32K118_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#include "devassert.h" + +#endif /* DEVICE_REGISTERS_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/s32_core_cm0.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/s32_core_cm0.h new file mode 100644 index 00000000..2dcd6e17 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/s32_core_cm0.h @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/*! + * @file s32_core_cm0.h + * + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro + * Function-like macros are used instead of inline functions in order to ensure + * that the performance will not be decreased if the functions will not be + * inlined by the compiler. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. + * The macros defined are used only on some of the drivers, so this might be reported + * when the analysis is made only on one driver. + */ + +/* + * Tool Chains: + * GNUC flag is defined also by ARM compiler - it shows the current major version of the compatible GCC version + * __GNUC__ : GNU Compiler Collection + * __ghs__ : Green Hills ARM Compiler + * __ICCARM__ : IAR ARM Compiler + * __DCC__ : Wind River Diab Compiler + * __ARMCC_VERSION : ARM Compiler + */ + +#if !defined (CORE_CM0_H) +#define CORE_CM0_H + + +#ifdef __cplusplus +extern "C" { +#endif + +/** \brief BKPT_ASM + * + * Macro to be used to trigger an debug interrupt + */ +#if defined ( __DCC__ ) +#define BKPT_ASM __asm ("BKPT 0\n\t") +#else +#define BKPT_ASM __asm ("BKPT #0\n\t") +#endif + +/** \brief Enable interrupts + */ +#if defined (__GNUC__) +#define ENABLE_INTERRUPTS() __asm volatile ("cpsie i" : : : "memory"); +#elif defined ( __DCC__ ) +#define ENABLE_INTERRUPTS() __asm (".short 0xb662"); +#else +#define ENABLE_INTERRUPTS() __asm("cpsie i") +#endif + + +/** \brief Disable interrupts + */ +#if defined (__GNUC__) +#define DISABLE_INTERRUPTS() __asm volatile ("cpsid i" : : : "memory"); +#elif defined ( __DCC__ ) +#define DISABLE_INTERRUPTS() __asm (".short 0xb672"); +#else +#define DISABLE_INTERRUPTS() __asm("cpsid i") +#endif + + +/** \brief Enter low-power standby state + * WFI (Wait For Interrupt) makes the processor suspend execution (Clock is stopped) until an IRQ interrupts. + */ +#if defined (__GNUC__) +#define STANDBY() __asm volatile ("wfi") +#elif defined ( __DCC__ ) +#define STANDBY() __asm (".short 0xbf30"); +#else +#define STANDBY() __asm ("wfi") +#endif + +/** \brief No-op + */ +#define NOP() __asm volatile ("nop") + + +/** \brief Reverse byte order in a word. + * ARM Documentation Cortex-M0 Devices Generic User Guide + * Accordingly to 3.5.7. REV, REV16, and REVSH + * Restriction "This function requires low registers R0-R7 register" + */ +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ARMCC_VERSION) +#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=l" (b) : "l" (a)) +#elif defined (__ghs__) +#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=r" (b) : "r" (a)) +#else +#define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \ + | ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U)) +#endif + +/** \brief Reverse byte order in each halfword independently. + * ARM Documentation Cortex-M0 Devices Generic User Guide + * Accordingly to 3.5.7. REV, REV16, and REVSH + * Restriction "This function requires low registers R0-R7 register" + */ +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ARMCC_VERSION) +#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=l" (b) : "l" (a)) +#elif defined (__ghs__) +#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=r" (b) : "r" (a)) +#else +#define REV_BYTES_16(a, b) (b = ((a & 0xFF000000U) >> 8U) | ((a & 0xFF0000U) << 8U) \ + | ((a & 0xFF00U) >> 8U) | ((a & 0xFFU) << 8U)) +#endif + +/** \brief Places a function in RAM. + */ +#if defined ( __GNUC__ ) || defined (__ARMCC_VERSION) + #define START_FUNCTION_DECLARATION_RAMSECTION + #define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram"))); +#elif defined ( __ghs__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("ghs callmode=far") + #define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));\ + _Pragma("ghs callmode=default") +#elif defined ( __ICCARM__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION __ramfunc + #define END_FUNCTION_DECLARATION_RAMSECTION ; +#elif defined ( __DCC__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("section CODE \".code_ram\" \"\" far-absolute") \ + _Pragma("use_section CODE") + #define END_FUNCTION_DECLARATION_RAMSECTION ; \ + _Pragma("section CODE \".text\"") +#else + /* Keep compatibility with software analysis tools */ + #define START_FUNCTION_DECLARATION_RAMSECTION + #define END_FUNCTION_DECLARATION_RAMSECTION ; +#endif + + /* For GCC, IAR, GHS, Diab and ARMC there is no need to specify the section when + defining a function, it is enough to specify it at the declaration. This + also enables compatibility with software analysis tools. */ + #define START_FUNCTION_DEFINITION_RAMSECTION + #define END_FUNCTION_DEFINITION_RAMSECTION + +#if defined (__ICCARM__) + #define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_suppress=Ta022") + #define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_default=Ta022") +#else + #define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL + #define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL +#endif + +/** \brief Get Core ID + * + * GET_CORE_ID returns the processor identification number for cm0 + */ +#define GET_CORE_ID() 0U + +/** \brief Data alignment. + */ +#if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION) + #define ALIGNED(x) __attribute__((aligned(x))) +#elif defined ( __ICCARM__ ) + #define stringify(s) tostring(s) + #define tostring(s) #s + #define ALIGNED(x) _Pragma(stringify(data_alignment=x)) +#else + /* Keep compatibility with software analysis tools */ + #define ALIGNED(x) +#endif + +/** \brief Endianness. + */ +#define CORE_LITTLE_ENDIAN + +#ifdef __cplusplus +} +#endif + +#endif /* CORE_CM0_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/system_S32K118.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/system_S32K118.c new file mode 100644 index 00000000..868b365b --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/system_S32K118.c @@ -0,0 +1,176 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * An object with static storage duration declared at block scope cannot be + * accessed directly from outside the block. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed + * between a pointer to object and an integer type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed + * between pointer to void and an arithmetic type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. + * Function is defined for usage by application code. + * + */ + +#include "device_registers.h" +#include "system_S32K118.h" +#include "stdbool.h" + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/*FUNCTION********************************************************************** + * + * Function Name : SystemInit + * Description : This function disables the watchdog, enables FPU + * and the power mode protection if the corresponding feature macro + * is enabled. SystemInit is called from startup_device file. + * + * Implements : SystemInit_Activity + *END**************************************************************************/ +void SystemInit(void) +{ +/**************************************************************************/ +/* WDOG DISABLE*/ +/**************************************************************************/ + +#if (DISABLE_WDOG) + /* Write of the WDOG unlock key to CNT register, must be done in order to allow any modifications*/ + WDOG->CNT = (uint32_t ) FEATURE_WDOG_UNLOCK_VALUE; + /* The dummy read is used in order to make sure that the WDOG registers will be configured only + * after the write of the unlock value was completed. */ + (void)WDOG->CNT; + + /* Initial write of WDOG configuration register: + * enables support for 32-bit refresh/unlock command write words, + * clock select from LPO, update enable, watchdog disabled */ + WDOG->CS = (uint32_t ) ( (1UL << WDOG_CS_CMD32EN_SHIFT) | + (FEATURE_WDOG_CLK_FROM_LPO << WDOG_CS_CLK_SHIFT) | + (0U << WDOG_CS_EN_SHIFT) | + (1U << WDOG_CS_UPDATE_SHIFT) ); + + /* Configure timeout */ + WDOG->TOVAL = (uint32_t )0xFFFF; +#endif /* (DISABLE_WDOG) */ +} + +/*FUNCTION********************************************************************** + * + * Function Name : SystemCoreClockUpdate + * Description : This function must be called whenever the core clock is changed + * during program execution. It evaluates the clock register settings and calculates + * the current core clock. + * + * Implements : SystemCoreClockUpdate_Activity + *END**************************************************************************/ +void SystemCoreClockUpdate(void) +{ + uint32_t SCGOUTClock = 0U; /* Variable to store output clock frequency of the SCG module */ + uint32_t regValue; /* Temporary variable */ + uint32_t divider; + bool validSystemClockSource = true; + + divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U; + + switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) + { + case 0x1: + /* System OSC */ + SCGOUTClock = CPU_XTAL_CLK_HZ; + break; + case 0x2: + /* Slow IRC */ + regValue = (SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT; + if (regValue != 0UL) + { + SCGOUTClock = FEATURE_SCG_SIRC_HIGH_RANGE_FREQ; + } + else + { + validSystemClockSource = false; + } + break; + case 0x3: + /* Fast IRC */ + regValue = (SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT; + if (regValue == 0x0UL) + { + SCGOUTClock = FEATURE_SCG_FIRC_FREQ0; + } + else + { + validSystemClockSource = false; + } + break; + default: + validSystemClockSource = false; + break; + } + + if (validSystemClockSource == true) + { + SystemCoreClock = (SCGOUTClock / divider); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : SystemSoftwareReset + * Description : This function is used to initiate a system reset + * + * Implements : SystemSoftwareReset_Activity + *END**************************************************************************/ +void SystemSoftwareReset(void) +{ + uint32_t regValue; + + /* Read Application Interrupt and Reset Control Register */ + regValue = S32_SCB->AIRCR; + + /* Clear register key */ + regValue &= ~( S32_SCB_AIRCR_VECTKEY_MASK); + + /* Configure System reset request bit and Register Key */ + regValue |= S32_SCB_AIRCR_VECTKEY(FEATURE_SCB_VECTKEY); + regValue |= S32_SCB_AIRCR_SYSRESETREQ(0x1u); + + /* Write computed register value */ + S32_SCB->AIRCR = regValue; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/system_S32K118.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/system_S32K118.h new file mode 100644 index 00000000..6e98f97f --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/system_S32K118.h @@ -0,0 +1,105 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*! @addtogroup soc_support_S32K118*/ +/*! @{*/ + +/*! + * @file system_S32K118.h + * @brief Device specific configuration file for S32K118 + */ + +#ifndef SYSTEM_S32K118_H_ +#define SYSTEM_S32K118_H_ /**< Symbol preventing repeated inclusion */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** + * CPU Settings. + *****************************************************************************/ + +/* Watchdog disable */ +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +/* Value of the external crystal or oscillator clock frequency in Hz */ +#ifndef CPU_XTAL_CLK_HZ + #define CPU_XTAL_CLK_HZ 8000000u +#endif + +/* Value of the fast internal oscillator clock frequency in Hz */ +#ifndef CPU_INT_FAST_CLK_HZ + #define CPU_INT_FAST_CLK_HZ 48000000u +#endif + +/* Default System clock value */ +#ifndef DEFAULT_SYSTEM_CLOCK + #define DEFAULT_SYSTEM_CLOCK 48000000u +#endif + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the SoC. + * + * This function disables the watchdog. + * if the corresponding feature macro is enabled. + * SystemInit is called from startup_device file. + */ +void SystemInit(void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + * This function must be called when user does not want to use clock manager component. + * If clock manager is used, the CLOCK_SYS_GetFreq function must be used with CORE_CLOCK + * parameter. + * + */ +void SystemCoreClockUpdate(void); + +/** + * @brief Initiates a system reset. + * + * This function is used to initiate a system reset + */ +void SystemSoftwareReset(void); + +#ifdef __cplusplus +} +#endif + +/*! @}*/ +#endif /* #if !defined(SYSTEM_S32K118_H_) */ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/main.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/main.c new file mode 100644 index 00000000..556b5d8c --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/main.c @@ -0,0 +1,187 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/main.c +* \brief Demo program application source file. +* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static void Init(void); +static void SystemClockConfig(void); + + +/************************************************************************************//** +** \brief This is the entry point for the bootloader application and is called +** by the reset interrupt vector after the C-startup routines executed. +** \return Program return code. +** +****************************************************************************************/ +int main(void) +{ + /* Initialize the microcontroller. */ + Init(); + /* Initialize the bootloader interface */ + BootComInit(); + + /* Start the infinite program loop. */ + while (1) + { + /* Toggle LED with a fixed frequency. */ + LedToggle(); + /* Check for bootloader activation request */ + BootComCheckActivationRequest(); + } + + /* Program should never get here. */ + return 0; +} /*** end of main ***/ + + +/************************************************************************************//** +** \brief Initializes the microcontroller. +** \return none. +** +****************************************************************************************/ +static void Init(void) +{ + /* Configure the system clock. */ + SystemClockConfig(); + /* Enable the peripheral clock for the ports that are used. */ + PCC->PCCn[PCC_PORTB_INDEX] |= PCC_PCCn_CGC_MASK; + PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK; + +#if (BOOT_COM_RS232_ENABLE > 0) + /* UART RX GPIO pin configuration. PB0 = UART0 RX, MUX = ALT2. */ + PORTB->PCR[0] |= PORT_PCR_MUX(2); + /* UART TX GPIO pin configuration. PB1 = UART0 TX, MUX = ALT2. */ + PORTB->PCR[1] |= PORT_PCR_MUX(2); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) + /* CAN RX GPIO pin configuration. PE4 = CAN0 RX, MUX = ALT5. */ + PORTE->PCR[4] |= PORT_PCR_MUX(5); + /* CAN TX GPIO pin configuration. PE5 = CAN0 TX, MUX = ALT5. */ + PORTE->PCR[5] |= PORT_PCR_MUX(5); +#endif + + /* Initialize the timer driver. */ + TimerInit(); + /* Initialize the led driver. */ + LedInit(); + /* Enable the global interrupts. */ + ENABLE_INTERRUPTS(); +} /*** end of Init ***/ + + +/************************************************************************************//** +** \brief System Clock Configuration. This code was derived from a S32 Design Studio +** example program. It enables the SOCS (40 MHz external crystal), FIRC (48 +** MHz internal) and SIRC (8 MHz internal). The FIRC is used as a source for +** the system clock and configures the normal RUN mode for the following clock +** settings: +** - CORE_CLK = 48 MHz +** - SYS_CLK = 48 MHz +** - BUS_CLK = 48 MHz +** - FLASH_CLK = 24 MHz +** - SOSCDIV1_CLK = 40 MHz +** - SOSCDIV2_CLK = 40 MHz +** - FIRCDIV1_CLK = 48 MHz +** - FIRCDIV2_CLK = 48 MHz +** - SIRCDIV1_CLK = 8 MHz +** - SIRCDIV2_CLK = 8 MHz +** \return none. +** +****************************************************************************************/ +static void SystemClockConfig(void) +{ + /* --------- SOSC Initialization (40 MHz) ------------------------------------------ */ + /* SOSCDIV1 & SOSCDIV2 =1: divide by 1. */ + SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1) | SCG_SOSCDIV_SOSCDIV2(1); + /* Range=3: High freq (SOSC betw 8MHz - 40MHz). + * HGO=0: Config xtal osc for low power. + * EREFS=1: Input is external XTAL. + */ + SCG->SOSCCFG = SCG_SOSCCFG_RANGE(3) | SCG_SOSCCFG_EREFS_MASK; + /* Ensure SOSCCSR unlocked. */ + while (SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK) + { + ; + } + + /* LK=0: SOSCCSR can be written. + * SOSCCMRE=0: OSC CLK monitor IRQ if enabled. + * SOSCCM=0: OSC CLK monitor disabled. + * SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled. + * SOSCLPEN=0: Sys OSC disabled in VLP modes. + * SOSCSTEN=0: Sys OSC disabled in Stop modes. + * SOSCEN=1: Enable oscillator. + */ + SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK; + /* Wait for system OSC clock to become valid. */ + while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK)) + { + ; + } + + /* --------- FIRC Initialization --------------------------------------------------- */ + /* Fast IRC is enabled and trimmed to 48 MHz in reset (default). Enable FIRCDIV2_CLK + * and FIRCDIV1_CLK, divide by 1 = 48 MHz. + */ + SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV1(1) | SCG_FIRCDIV_FIRCDIV2(1); + + /* --------- SIRC Initialization --------------------------------------------------- */ + /* Slow IRC is enabled with high range (8 MHz) in reset. Enable SIRCDIV2_CLK and + * SIRCDIV1_CLK, divide by 1 = 8MHz asynchronous clock source. + */ + SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1) | SCG_SIRCDIV_SIRCDIV2(1); + + /* --------- Change to normal RUN mode with 48MHz FIRC ----------------------------- */ + /* Select FIRC as clock source. + * DIVCORE=0, div. by 1: Core clock = 48 MHz. + * DIVBUS=0, div. by 1: bus clock = 48 MHz. + * DIVSLOW=1, div. by 2: SCG slow, flash clock= 24 MHz + */ + SCG->RCCR = SCG_RCCR_SCS(3) | SCG_RCCR_DIVCORE(0) | SCG_RCCR_DIVBUS(0) | + SCG_RCCR_DIVSLOW(1); + + /* Wait until system clock source is FIRC. */ + while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 3U) + { + ; + } + /* Evaluate the clock register settings and calculates the current core clock. This + * function must be called when the clock manager component is not used. + */ + SystemCoreClockUpdate(); +} /*** end of SystemClockConfig ***/ + + +/*********************************** end of main.c *************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/prog.dox b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/prog.dox new file mode 100644 index 00000000..99399e11 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/prog.dox @@ -0,0 +1,13 @@ +/** +\defgroup Prog_ARMCM0_S32K14_S32K118EVB_GCC User Program +\ingroup ARMCM0_S32K14_S32K118EVB_GCC +\brief User Program. +\details The intention of the demo user program is two-fold. (1) To test the + bootloader, you need some sort of firmware to see if you can perform a + firmware update with the bootloader. This program can be used for this + purpose. (2) To make firmware programmable by the bootloader, a few + adjustments to the firmware are required. The demo user program serves as an + example for how these adjustments can be implemented. This demo user program + is a template that can be used as a starting point for creating your own + demo user program. +*/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/startup/startup.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/startup/startup.c new file mode 100644 index 00000000..2d0efc61 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/startup/startup.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * All variables with this problem are defined in the linker files. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.11, When an array with external linkage + * is declared, its size should be explicitly specified. + * The size of the arrays can not be explicitly determined. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed + * between a pointer to object and an integer type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed + * between pointer to void and an arithmetic type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 2.1, A project shall not contain unreachable + * code. + * The condition compares two address defined in linker files that can be different. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. + * Function is defined for usage by application code. + * + * @section [global] + * Violates MISRA 2012 Mandatory Rule 17.3, Symbol 'MFSPR' undeclared, assumed + * to return int. + * This is an e200 Power Architecture Assembly instruction used to retrieve + * the core number. + * + */ + +#include "startup.h" +#include + + +/******************************************************************************* + * Static Variables + ******************************************************************************/ +static volatile uint32_t * const s_vectors[NUMBER_OF_CORES] = FEATURE_INTERRUPT_INT_VECTORS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : init_data_bss + * Description : Make necessary initializations for RAM. + * - Copy the vector table from ROM to RAM. + * - Copy initialized data from ROM to RAM. + * - Copy code that should reside in RAM from ROM + * - Clear the zero-initialized data section. + * + * Tool Chains: + * __GNUC__ : GNU Compiler Collection + * __ghs__ : Green Hills ARM Compiler + * __ICCARM__ : IAR ARM Compiler + * __DCC__ : Wind River Diab Compiler + * __ARMCC_VERSION : ARMC Compiler + * + * Implements : init_data_bss_Activity + *END**************************************************************************/ +void init_data_bss(void) +{ + uint32_t n; + uint8_t coreId; +/* For ARMC we are using the library method of initializing DATA, Custom Section and + * Code RAM sections so the below variables are not needed */ +#if !defined(__ARMCC_VERSION) + /* Declare pointers for various data sections. These pointers + * are initialized using values pulled in from the linker file */ + uint8_t * data_ram; + uint8_t * code_ram; + uint8_t * bss_start; + uint8_t * custom_ram; + const uint8_t * data_rom, * data_rom_end; + const uint8_t * code_rom, * code_rom_end; + const uint8_t * bss_end; + const uint8_t * custom_rom, * custom_rom_end; +#endif + /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ + +#if defined(__ARMCC_VERSION) + extern uint32_t __RAM_VECTOR_TABLE_SIZE; + extern uint32_t __VECTOR_ROM; + extern uint32_t __VECTOR_RAM; +#else + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#endif + /* Get section information from linker files */ +#if defined(__ICCARM__) + /* Data */ + data_ram = __section_begin(".data"); + data_rom = __section_begin(".data_init"); + data_rom_end = __section_end(".data_init"); + + /* CODE RAM */ + #pragma section = "__CODE_ROM" + #pragma section = "__CODE_RAM" + code_ram = __section_begin("__CODE_RAM"); + code_rom = __section_begin("__CODE_ROM"); + code_rom_end = __section_end("__CODE_ROM"); + + /* BSS */ + bss_start = __section_begin(".bss"); + bss_end = __section_end(".bss"); + + custom_ram = __section_begin(".customSection"); + custom_rom = __section_begin(".customSection_init"); + custom_rom_end = __section_end(".customSection_init"); + +#elif defined (__ARMCC_VERSION) + /* VECTOR TABLE*/ + uint8_t * vector_table_size = (uint8_t *)__RAM_VECTOR_TABLE_SIZE; + uint32_t * vector_rom = (uint32_t *)__VECTOR_ROM; + uint32_t * vector_ram = (uint32_t *)__VECTOR_RAM; +#else + extern uint32_t __DATA_ROM[]; + extern uint32_t __DATA_RAM[]; + extern uint32_t __DATA_END[]; + + extern uint32_t __CODE_RAM[]; + extern uint32_t __CODE_ROM[]; + extern uint32_t __CODE_END[]; + + extern uint32_t __BSS_START[]; + extern uint32_t __BSS_END[]; + + extern uint32_t __CUSTOM_ROM[]; + extern uint32_t __CUSTOM_END[]; + + /* Data */ + data_ram = (uint8_t *)__DATA_RAM; + data_rom = (uint8_t *)__DATA_ROM; + data_rom_end = (uint8_t *)__DATA_END; + /* CODE RAM */ + code_ram = (uint8_t *)__CODE_RAM; + code_rom = (uint8_t *)__CODE_ROM; + code_rom_end = (uint8_t *)__CODE_END; + /* BSS */ + bss_start = (uint8_t *)__BSS_START; + bss_end = (uint8_t *)__BSS_END; + + /* Custom section */ + custom_ram = CUSTOMSECTION_SECTION_START; + custom_rom = (uint8_t *)__CUSTOM_ROM; + custom_rom_end = (uint8_t *)__CUSTOM_END; + +#endif + +#if !defined(__ARMCC_VERSION) + /* Copy initialized data from ROM to RAM */ + while (data_rom_end != data_rom) + { + *data_ram = *data_rom; + data_ram++; + data_rom++; + } + + /* Copy functions from ROM to RAM */ + while (code_rom_end != code_rom) + { + *code_ram = *code_rom; + code_ram++; + code_rom++; + } + + /* Clear the zero-initialized data section */ + while(bss_end != bss_start) + { + *bss_start = 0; + bss_start++; + } + + /* Copy customsection rom to ram */ + while(custom_rom_end != custom_rom) + { + *custom_ram = *custom_rom; + custom_rom++; + custom_ram++; + } +#endif + coreId = (uint8_t)GET_CORE_ID(); +#if defined (__ARMCC_VERSION) + /* Copy the vector table from ROM to RAM */ + /* Workaround */ + for (n = 0; n < (((uint32_t)(vector_table_size))/sizeof(uint32_t)); n++) + { + vector_ram[n] = vector_rom[n]; + } + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t) __VECTOR_RAM; +#else + /* Check if VECTOR_TABLE copy is needed */ + if (__VECTOR_RAM != __VECTOR_TABLE) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < (((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t)); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t)__VECTOR_RAM; + } + else + { + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t)__VECTOR_TABLE; + } +#endif + +} + +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/startup/startup.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/startup/startup.h new file mode 100644 index 00000000..8384b7db --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/startup/startup.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef STARTUP_H +#define STARTUP_H + +#include +#include "device_registers.h" +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, Local macro not referenced. + * The defined macro is used as include guard. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * All variables with this problem are defined in the linker files. + * + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief define symbols that specific start and end addres of some basic sections. + */ +#if (defined(S32K14x_SERIES) || defined(S32K11x_SERIES) || defined(S32V234_SERIES) || defined(MPC574x_SERIES) || defined(S32R_SERIES) || defined(S32MTV_SERIES) || defined(SJA1110_SERIES)) || defined (S32K144W_M4_SERIES) + #if (defined(__ICCARM__)) + #define INTERRUPTS_SECTION_START __section_begin(".intvec") + #define INTERRUPTS_SECTION_END __section_end(".intvec") + #define BSS_SECTION_START __section_begin(".bss") + #define BSS_SECTION_END __section_end(".bss") + #define DATA_SECTION_START __section_begin(".data") + #define DATA_SECTION_END __section_end(".data") + #define CUSTOMSECTION_SECTION_START __section_begin(".customSection") + #define CUSTOMSECTION_SECTION_END __section_end(".customSection") + #define CODE_RAM_SECTION_START __section_begin("__CODE_RAM") + #define CODE_RAM_SECTION_END __section_end("__CODE_RAM") + #define DATA_INIT_SECTION_START __section_begin(".data_init") + #define DATA_INIT_SECTION_END __section_end(".data_init") + #define CODE_ROM_SECTION_START __section_begin("__CODE_ROM") + #define CODE_ROM_SECTION_END __section_end("__CODE_ROM") + + #elif (defined(__ARMCC_VERSION)) + #define INTERRUPTS_SECTION_START (uint8_t *)__VECTOR_ROM_START + #define INTERRUPTS_SECTION_END (uint8_t *)__VECTOR_ROM_END + #define BSS_SECTION_START (uint8_t *)__BSS_START + #define BSS_SECTION_END (uint8_t *)__BSS_END + #define DATA_SECTION_START (uint8_t *)__DATA_RAM_START + #define DATA_SECTION_END (uint8_t *)__DATA_RAM_END + #define CUSTOMSECTION_SECTION_START (uint8_t *)__CUSTOM_SECTION_START + #define CUSTOMSECTION_SECTION_END (uint8_t *)__CUSTOM_SECTION_END + #define CODE_RAM_SECTION_START (uint8_t *)__CODE_RAM_START + #define CODE_RAM_SECTION_END (uint8_t *)__CODE_RAM_END + + extern uint32_t __VECTOR_ROM_START; + extern uint32_t __VECTOR_ROM_END; + extern uint32_t __BSS_START; + extern uint32_t __BSS_END; + extern uint32_t __DATA_RAM_START; + extern uint32_t __DATA_RAM_END; + extern uint32_t __CUSTOM_SECTION_START; + extern uint32_t __CUSTOM_SECTION_END; + extern uint32_t __CODE_RAM_START; + extern uint32_t __CODE_RAM_END; + #else + #define INTERRUPTS_SECTION_START (uint8_t *)&__interrupts_start__ + #define INTERRUPTS_SECTION_END (uint8_t *)&__interrupts_end__ + #define BSS_SECTION_START (uint8_t *)&__bss_start__ + #define BSS_SECTION_END (uint8_t *)&__bss_end__ + #define DATA_SECTION_START (uint8_t *)&__data_start__ + #define DATA_SECTION_END (uint8_t *)&__data_end__ + #define CUSTOMSECTION_SECTION_START (uint8_t *)&__customSection_start__ + #define CUSTOMSECTION_SECTION_END (uint8_t *)&__customSection_end__ + #define CODE_RAM_SECTION_START (uint8_t *)&__code_ram_start__ + #define CODE_RAM_SECTION_END (uint8_t *)&__code_ram_end__ + + extern uint32_t __interrupts_start__; + extern uint32_t __interrupts_end__; + extern uint32_t __bss_start__; + extern uint32_t __bss_end__; + extern uint32_t __data_start__; + extern uint32_t __data_end__; + extern uint32_t __customSection_start__; + extern uint32_t __customSection_end__; + extern uint32_t __code_ram_start__; + extern uint32_t __code_ram_end__; + #endif +#endif + +#if (defined(__ICCARM__)) + #pragma section = ".data" + #pragma section = ".data_init" + #pragma section = ".bss" + #pragma section = ".intvec" + #pragma section = ".customSection" + #pragma section = ".customSection_init" + #pragma section = "__CODE_RAM" + #pragma section = "__CODE_ROM" +#endif + +/*! + * @brief Make necessary initializations for RAM. + * + * - Copy initialized data from ROM to RAM. + * - Clear the zero-initialized data section. + * - Copy the vector table from ROM to RAM. This could be an option. + */ +void init_data_bss(void); + +#endif /* STARTUP_H*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/startup/startup_S32K118.S b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/startup/startup_S32K118.S new file mode 100644 index 00000000..d872acfa --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/startup/startup_S32K118.S @@ -0,0 +1,228 @@ +/* ---------------------------------------------------------------------------------------*/ +/* @file: startup_S32K118.s */ +/* @purpose: GNU Compiler Collection Startup File */ +/* S32K118 */ +/* @version: 1.0 */ +/* @date: 2018-1-22 */ +/* @build: b170107 */ +/* ---------------------------------------------------------------------------------------*/ +/* */ +/* Copyright 2018 NXP */ +/* All rights reserved. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES */ +/* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. */ +/* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, */ +/* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ +/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR */ +/* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) */ +/* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, */ +/* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING */ +/* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF */ +/* THE POSSIBILITY OF SUCH DAMAGE. */ +/*****************************************************************************/ +/* Version: GNU Compiler Collection */ +/*****************************************************************************/ + .syntax unified + .arch armv6-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* Non Maskable Interrupt */ + .long HardFault_Handler /* Cortex-M0 SV Hard Fault Interrupt */ + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler /* Cortex-M0 SV Call Interrupt */ + .long 0 + .long 0 + .long PendSV_Handler /* Cortex-M0 Pend SV Interrupt */ + .long SysTick_Handler /* Cortex-M0 System Tick Interrupt */ + + + .long DMA0_IRQHandler /* DMA channel 0 transfer complete */ + .long DMA1_IRQHandler /* DMA channel 1 transfer complete */ + .long DMA2_IRQHandler /* DMA channel 2 transfer complete */ + .long DMA3_IRQHandler /* DMA channel 3 transfer complete */ + .long DMA_Error_IRQHandler /* DMA error interrupt channels 0-3 */ + .long ERM_fault_IRQHandler /* ERM single and double bit error correction */ + .long RTC_IRQHandler /* RTC alarm interrupt */ + .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */ + .long LPTMR0_IRQHandler /* LPTIMER interrupt request */ + .long PORT_IRQHandler /* Port A, B, C, D and E pin detect interrupt */ + .long CAN0_ORed_Err_Wakeup_IRQHandler /* OR’ed [Bus Off OR Bus Off Done OR Transmit Warning OR Receive Warning], Interrupt indicating that errors were detected on the CAN bus, Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode */ + .long CAN0_ORed_0_31_MB_IRQHandler /* OR’ed Message buffer (0-15, 16-31) */ + .long FTM0_Ch0_7_IRQHandler /* FTM0 Channel 0 to 7 interrupt */ + .long FTM0_Fault_IRQHandler /* FTM0 Fault interrupt */ + .long FTM0_Ovf_Reload_IRQHandler /* FTM0 Counter overflow and Reload interrupt */ + .long FTM1_Ch0_7_IRQHandler /* FTM1 Channel 0 to 7 interrupt */ + .long FTM1_Fault_IRQHandler /* FTM1 Fault interrupt */ + .long FTM1_Ovf_Reload_IRQHandler /* FTM1 Counter overflow and Reload interrupt */ + .long FTFC_IRQHandler /* FTFC Command complete, Read collision and Double bit fault detect */ + .long PDB0_IRQHandler /* PDB0 interrupt */ + .long LPIT0_IRQHandler /* LPIT interrupt */ + .long SCG_CMU_LVD_LVWSCG_IRQHandler /* PMC Low voltage detect interrupt, SCG bus interrupt request and CMU loss of range interrupt */ + .long WDOG_IRQHandler /* WDOG interrupt request out before wdg reset out */ + .long RCM_IRQHandler /* RCM Asynchronous Interrupt */ + .long LPI2C0_Master_Slave_IRQHandler /* LPI2C0 Master Interrupt and Slave Interrupt */ + .long FLEXIO_IRQHandler /* FlexIO Interrupt */ + .long LPSPI0_IRQHandler /* LPSPI0 Interrupt */ + .long LPSPI1_IRQHandler /* LPSPI1 Interrupt */ + .long ADC0_IRQHandler /* ADC0 interrupt request. */ + .long CMP0_IRQHandler /* CMP0 interrupt request */ + .long LPUART1_RxTx_IRQHandler /* LPUART1 Transmit / Receive Interrupt */ + .long LPUART0_RxTx_IRQHandler /* LPUART0 Transmit / Receive Interrupt */ + .long 0x55AA11EE /* Reserved for OpenBLT checksum */ + + .size __isr_vector, . - __isr_vector + +/* Flash Configuration */ + .section .FlashConfig, "a" + .long 0xFFFFFFFF /* 8 bytes backdoor comparison key */ + .long 0xFFFFFFFF /* */ + .long 0xFFFFFFFF /* 4 bytes program flash protection bytes */ + .long 0xFFFF7FFE /* FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured) */ + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + + /* Init the rest of the registers */ + ldr r1,=0 + ldr r2,=0 + ldr r3,=0 + ldr r4,=0 + ldr r5,=0 + ldr r6,=0 + ldr r7,=0 + mov r8,r7 + mov r9,r7 + mov r10,r7 + mov r11,r7 + mov r12,r7 + +#ifdef START_FROM_FLASH + + /* Init ECC RAM */ + + ldr r1, =__RAM_START + ldr r2, =__RAM_END + + subs r2, r1 + subs r2, #1 + ble .LC5 + + movs r0, 0 + movs r3, #4 +.LC4: + str r0, [r1] + add r1, r1, r3 + subs r2, 4 + bge .LC4 +.LC5: +#endif + + /* Initialize the stack pointer */ + ldr r0,=__StackTop + mov r13,r0 + +#ifndef __NO_SYSTEM_INIT + /* Call the system init routine */ + ldr r0,=SystemInit + blx r0 +#endif + + /* Init .data and .bss sections */ + ldr r0,=init_data_bss + blx r0 + cpsie i /* Unmask interrupts */ + +#ifndef __START +#ifdef __EWL__ +#define __START __thumb_startup +#else +#define __START _start +#endif +#endif + bl __START + +JumpToSelf: + b JumpToSelf + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler DMA0_IRQHandler + def_irq_handler DMA1_IRQHandler + def_irq_handler DMA2_IRQHandler + def_irq_handler DMA3_IRQHandler + def_irq_handler DMA_Error_IRQHandler + def_irq_handler ERM_fault_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler RTC_Seconds_IRQHandler + def_irq_handler LPTMR0_IRQHandler + def_irq_handler PORT_IRQHandler + def_irq_handler CAN0_ORed_Err_Wakeup_IRQHandler + def_irq_handler CAN0_ORed_0_31_MB_IRQHandler + def_irq_handler FTM0_Ch0_7_IRQHandler + def_irq_handler FTM0_Fault_IRQHandler + def_irq_handler FTM0_Ovf_Reload_IRQHandler + def_irq_handler FTM1_Ch0_7_IRQHandler + def_irq_handler FTM1_Fault_IRQHandler + def_irq_handler FTM1_Ovf_Reload_IRQHandler + def_irq_handler FTFC_IRQHandler + def_irq_handler PDB0_IRQHandler + def_irq_handler LPIT0_IRQHandler + def_irq_handler SCG_CMU_LVD_LVWSCG_IRQHandler + def_irq_handler WDOG_IRQHandler + def_irq_handler RCM_IRQHandler + def_irq_handler LPI2C0_Master_Slave_IRQHandler + def_irq_handler FLEXIO_IRQHandler + def_irq_handler LPSPI0_IRQHandler + def_irq_handler LPSPI1_IRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler CMP0_IRQHandler + def_irq_handler LPUART1_RxTx_IRQHandler + def_irq_handler LPUART0_RxTx_IRQHandler + + .end diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/timer.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/timer.c new file mode 100644 index 00000000..3b764d8f --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/timer.c @@ -0,0 +1,88 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/timer.c +* \brief Timer driver source file. +* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Local variable for storing the number of milliseconds that have elapsed since + * startup. + */ +static unsigned long millisecond_counter; + + +/************************************************************************************//** +** \brief Initializes the timer. +** \return none. +** +****************************************************************************************/ +void TimerInit(void) +{ + /* Configure the systick frequency as a 1 ms event generator. */ + S32_SysTick->RVR = (SystemCoreClock / 1000U) - 1U; + /* Reset the current counter value. */ + S32_SysTick->CVR = 0U; + /* Select core clock as source and enable the timer. */ + S32_SysTick->CSR = S32_SysTick_CSR_ENABLE_MASK | + S32_SysTick_CSR_TICKINT_MASK | + S32_SysTick_CSR_CLKSOURCE_MASK; + /* Reset the millisecond counter value. */ + millisecond_counter = 0U; +} /*** end of TimerInit ***/ + + +/************************************************************************************//** +** \brief Obtains the counter value of the millisecond timer. +** \return Current value of the millisecond timer. +** +****************************************************************************************/ +unsigned long TimerGet(void) +{ + /* Read and return the tick counter value. */ + return millisecond_counter; +} /*** end of TimerGet ***/ + + +/************************************************************************************//** +** \brief Interrupt service routine of the timer. +** \return none. +** +****************************************************************************************/ +void SysTick_Handler(void) +{ + /* Increment the millisecond counter. */ + millisecond_counter++; +} /*** end of SysTick_Handler ***/ + + +/*********************************** end of timer.c ************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/timer.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/timer.h new file mode 100644 index 00000000..c9798948 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/timer.h @@ -0,0 +1,38 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/timer.h +* \brief Timer driver header file. +* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef TIMER_H +#define TIMER_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void TimerInit(void); +unsigned long TimerGet(void); + +#endif /* TIMER_H */ +/*********************************** end of timer.h ************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/demo.dox b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/demo.dox new file mode 100644 index 00000000..796e0c8a --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/demo.dox @@ -0,0 +1,8 @@ +/** +\defgroup ARMCM0_S32K14_S32K118EVB_GCC Demo for S32K118EVB/GCC +\ingroup Demos +\brief Preconfigured programs for the NXP S32K118EVB board and the S32 Design Studio + development environment, which is based on the ARM GCC toolchain. +*/ + + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/S32K118_25_flash.icf b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/S32K118_25_flash.icf new file mode 100644 index 00000000..384e4be7 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/S32K118_25_flash.icf @@ -0,0 +1,125 @@ +/* +** ################################################################### +** Processor: S32K118 with 25 KB SRAM +** Compiler: IAR ANSI C/C++ Compiler for ARM +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2018 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +/* If symbol __flash_vector_table__=1 is defined at link time + * the interrupt vector will not be copied to RAM. + * Warning: Using the interrupt vector from FLASH will not allow + * INT_SYS_InstallHandler because the section is Read Only. + */ +define symbol __ram_vector_table_size__ = isdefinedsymbol(__flash_vector_table__) ? 0 : 0x000000C0; +define symbol __ram_vector_table_offset__ = isdefinedsymbol(__flash_vector_table__) ? 0 : 0x000000BF; + +/* Flash */ +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000000BF; + +define symbol m_flash_config_start = 0x00000400; +define symbol m_flash_config_end = 0x0000040F; + +define symbol m_text_start = 0x00000410; +define symbol m_text_end = 0x00001FFF; + +/* SRAM_L */ +define symbol m_custom_start = 0x1FFFFC00; +define symbol m_custom_end = 0x1FFFFFFF; + +/* SRAM_U */ +define symbol m_interrupts_ram_start = 0x20000000; +define symbol m_interrupts_ram_end = 0x20000000 + __ram_vector_table_offset__; + +define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__; +define symbol m_data_end = 0x200030BF; + +define symbol m_data_2_start = 0x200030C0; +define symbol m_data_2_end = 0x200057FF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x00000200; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x00000200; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = isdefinedsymbol(__flash_vector_table__) ? m_interrupts_start : m_interrupts_ram_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__; + +define exported symbol __RAM_START = m_interrupts_ram_start; +define exported symbol __RAM_END = m_data_2_end; + +define memory mem with size = 4G; +define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end]; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA_region_2 = mem:[from m_data_2_start to m_data_2_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end]; +define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; +define region CUSTOM_region = mem:[from m_custom_start to m_custom_end]; + + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +/* Custom Section Block that can be used to place data at absolute address. */ +/* Use __attribute__((section (".customSection"))) to place data here. */ +/* Use this section only when MTB (Micro Trace Buffer) is not used, because MTB uses the same RAM area, as described in S32K Reference Manual. */ +define block customSectionBlock { section .customSection }; + +define block __CODE_ROM { section .textrw_init }; +define block __CODE_RAM { section .textrw }; + +initialize manually { section .textrw }; +initialize manually { section .bss }; +initialize manually { section .customSection }; +initialize manually { section .data }; +initialize manually { section __DLIB_PERTHREAD }; +do not initialize { section .noinit, section .bss, section .data, section __DLIB_PERTHREAD, section .customSection }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in m_flash_config_region { section FlashConfig }; +place in TEXT_region { readonly }; +place in TEXT_region { block __CODE_ROM }; +place in DATA_region { block RW }; +place in DATA_region { block __CODE_RAM }; +place in CUSTOM_region { first block customSectionBlock }; +place in DATA_region_2 { block ZI }; +place in DATA_region_2 { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in m_interrupts_ram_region { section m_interrupts_ram }; + + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/bin/openblt_s32k118.out b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/bin/openblt_s32k118.out new file mode 100644 index 00000000..4109b770 Binary files /dev/null and b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/bin/openblt_s32k118.out differ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/bin/openblt_s32k118.srec b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/bin/openblt_s32k118.srec new file mode 100644 index 00000000..6f76d0b5 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/bin/openblt_s32k118.srec @@ -0,0 +1,443 @@ +S01700006F70656E626C745F7333326B3131382E73726563DD +S113000000580020091D0000030B0000030B000032 +S113001000000000000000000000000000000000DC +S1130020000000000000000000000000030B0000BE +S11300300000000000000000030B0000030B0000A0 +S1130040030B0000030B0000030B0000030B000074 +S1130050030B0000030B0000030B0000030B000064 +S1130060030B0000030B0000030B0000030B000054 +S1130070030B0000030B0000030B0000030B000044 +S1130080030B0000030B0000030B0000030B000034 +S1130090030B0000030B0000030B0000030B000024 +S11300A0030B0000030B0000030B0000030B000014 +S11300B0030B0000030B0000030B0000030B000004 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+*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef BLT_CONF_H +#define BLT_CONF_H + +/**************************************************************************************** +* C P U D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* To properly initialize the baudrate clocks of the communication interface, typically + * the speed of the crystal oscillator and/or the speed at which the system runs is + * needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and + * BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is + * not dependent on the targets architecture, the byte ordering needs to be known. + * Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects + * little endian mode. + * + * Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be + * called the moment the user program is about to be started. This could be used to + * de-initialize application specific parts, for example to stop blinking an LED, etc. + */ +/** \brief Frequency of the external crystal oscillator. */ +#define BOOT_CPU_XTAL_SPEED_KHZ (40000) +/** \brief Desired system speed. */ +#define BOOT_CPU_SYSTEM_SPEED_KHZ (48000) +/** \brief Motorola or Intel style byte ordering. */ +#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0) +/** \brief Enable/disable hook function call right before user program start. */ +#define BOOT_CPU_USER_PROGRAM_START_HOOK (1) + + +/**************************************************************************************** +* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N +****************************************************************************************/ +/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE + * configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed + * in bits/second. The maximum amount of data bytes in a message for data transmission + * and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA, + * respectively. It is common for a microcontroller to have more than 1 UART interface + * on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface. + * + */ +/** \brief Enable/disable UART transport layer. */ +#define BOOT_COM_RS232_ENABLE (1) +/** \brief Configure the desired communication speed. */ +#define BOOT_COM_RS232_BAUDRATE (57600) +/** \brief Configure number of bytes in the target->host data packet. */ +#define BOOT_COM_RS232_TX_MAX_DATA (64) +/** \brief Configure number of bytes in the host->target data packet. */ +#define BOOT_COM_RS232_RX_MAX_DATA (64) +/** \brief Select the desired UART peripheral as a zero based index. */ +#define BOOT_COM_RS232_CHANNEL_INDEX (0) + +/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE + * configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed + * in bits/second. Two CAN messages are reserved for communication with the host. The + * message identifier for sending data from the target to the host is configured with + * BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with + * BOOT_COM_CAN_RXMSG_ID. Note that an extended 29-bit CAN identifier is configured by + * OR-ing with mask 0x80000000. The maximum amount of data bytes in a message for data + * transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and + * BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more + * than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the + * CAN controller channel. + * + */ +/** \brief Enable/disable CAN transport layer. */ +#define BOOT_COM_CAN_ENABLE (1) +/** \brief Configure the desired CAN baudrate. */ +#define BOOT_COM_CAN_BAUDRATE (500000) +/** \brief Configure CAN message ID target->host. */ +#define BOOT_COM_CAN_TX_MSG_ID (0x7E1 /*| 0x80000000*/) +/** \brief Configure number of bytes in the target->host CAN message. */ +#define BOOT_COM_CAN_TX_MAX_DATA (8) +/** \brief Configure CAN message ID host->target. */ +#define BOOT_COM_CAN_RX_MSG_ID (0x667 /*| 0x80000000*/) +/** \brief Configure number of bytes in the host->target CAN message. */ +#define BOOT_COM_CAN_RX_MAX_DATA (8) +/** \brief Select the desired CAN peripheral as a zero based index. */ +#define BOOT_COM_CAN_CHANNEL_INDEX (0) + + +/**************************************************************************************** +* B A C K D O O R E N T R Y C O N F I G U R A T I O N +****************************************************************************************/ +/* It is possible to implement an application specific method to force the bootloader to + * stay active after a reset. Such a backdoor entry into the bootloader is desired in + * situations where the user program does not run properly and therefore cannot + * reactivate the bootloader. By enabling these hook functions, the application can + * implement the backdoor, which overrides the default backdoor entry that is programmed + * into the bootloader. When desired for security purposes, these hook functions can + * also be implemented in a way that disables the backdoor entry altogether. + */ +/** \brief Enable/disable the backdoor override hook functions. */ +#define BOOT_BACKDOOR_HOOKS_ENABLE (0) + + +/**************************************************************************************** +* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* The NVM driver typically supports erase and program operations of the internal memory + * present on the microcontroller. Through these hook functions the NVM driver can be + * extended to support additional memory types such as external flash memory and serial + * eeproms. The size of the internal memory in kilobytes is specified with configurable + * BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can + * be overridden with a application specific method by enabling configuration switch + * BOOT_NVM_CHECKSUM_HOOKS_ENABLE. + */ +/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */ +#define BOOT_NVM_HOOKS_ENABLE (0) +/** \brief Configure the size of the default memory device (typically flash EEPROM). */ +#define BOOT_NVM_SIZE_KB (256) +/** \brief Enable/disable hooks functions to override the user program checksum handling. */ +#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0) + + +/**************************************************************************************** +* W A T C H D O G D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* The COP driver cannot be configured internally in the bootloader, because its use + * and configuration is application specific. The bootloader does need to service the + * watchdog in case it is used. When the application requires the use of a watchdog, + * set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through + * hook functions. + */ +/** \brief Enable/disable the hook functions for controlling the watchdog. */ +#define BOOT_COP_HOOKS_ENABLE (1) + + +/**************************************************************************************** +* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N +****************************************************************************************/ +/* A security mechanism can be enabled in the bootloader's XCP module by setting configu- + * rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming + * operations can be performed, access to this resource need to be unlocked. + * In the Microboot settings on tab "XCP Protection" you need to specify a DLL that + * implements the unlocking algorithm. The demo programs are configured for the (simple) + * algorithm in "libseednkey.dll". The source code for this DLL is available so it can be + * customized to your needs. + * During the unlock sequence, Microboot requests a seed from the bootloader, which is in + * the format of a byte array. Using this seed the unlock algorithm in the DLL computes + * a key, which is also a byte array, and sends this back to the bootloader. The + * bootloader then verifies this key to determine if programming and erase operations are + * permitted. + * After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook() + * are called by the bootloader to obtain the seed and to verify the key, respectively. + */ +#define BOOT_XCP_SEED_KEY_ENABLE (0) + + +#endif /* BLT_CONF_H */ +/*********************************** end of blt_conf.h *********************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/boot.dox b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/boot.dox new file mode 100644 index 00000000..b81a6301 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/boot.dox @@ -0,0 +1,7 @@ +/** +\defgroup Boot_ARMCM0_S32K14_S32K118EVB_IAR Bootloader +\brief Bootloader. +\ingroup ARMCM0_S32K14_S32K118EVB_IAR +*/ + + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/hooks.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/hooks.c new file mode 100644 index 00000000..3bd5251b --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/hooks.c @@ -0,0 +1,307 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/hooks.c +* \brief Bootloader callback source file. +* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "led.h" /* LED driver header */ +#include "device_registers.h" /* device registers */ + + +/**************************************************************************************** +* B A C K D O O R E N T R Y H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Initializes the backdoor entry option. +** \return none. +** +****************************************************************************************/ +void BackDoorInitHook(void) +{ +} /*** end of BackDoorInitHook ***/ + + +/************************************************************************************//** +** \brief Checks if a backdoor entry is requested. +** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool BackDoorEntryHook(void) +{ + /* default implementation always activates the bootloader after a reset */ + return BLT_TRUE; +} /*** end of BackDoorEntryHook ***/ +#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* C P U D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0) +/************************************************************************************//** +** \brief Callback that gets called when the bootloader is about to exit and +** hand over control to the user program. This is the last moment that +** some final checking can be performed and if necessary prevent the +** bootloader from activiting the user program. +** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep +** keep the bootloader active. +** +****************************************************************************************/ +blt_bool CpuUserProgramStartHook(void) +{ + /* additional and optional backdoor entry through the pushbutton (SW2) on the board. to + * force the bootloader to stay active after reset, keep it pressed during reset. + */ + if ((PTD->PDIR & GPIO_PDIR_PDI(1 << 3U)) != 0U) + { + /* pushbutton pressed, so do not start the user program and keep the + * bootloader active instead. + */ + return BLT_FALSE; + } + + /* clean up the LED driver */ + LedBlinkExit(); + + /* okay to start the user program */ + return BLT_TRUE; +} /*** end of CpuUserProgramStartHook ***/ +#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */ + + +/**************************************************************************************** +* W A T C H D O G D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_COP_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Callback that gets called at the end of the internal COP driver +** initialization routine. It can be used to configure and enable the +** watchdog. +** \return none. +** +****************************************************************************************/ +void CopInitHook(void) +{ + /* this function is called upon initialization. might as well use it to initialize + * the LED driver. It is kind of a visual watchdog anyways. + */ + LedBlinkInit(100); +} /*** end of CopInitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the end of the internal COP driver +** service routine. This gets called upon initialization and during +** potential long lasting loops and routine. It can be used to service +** the watchdog to prevent a watchdog reset. +** \return none. +** +****************************************************************************************/ +void CopServiceHook(void) +{ + /* run the LED blink task. this is a better place to do it than in the main() program + * loop. certain operations such as flash erase can take a long time, which would cause + * a blink interval to be skipped. this function is also called during such operations, + * so no blink intervals will be skipped when calling the LED blink task here. + */ + LedBlinkTask(); +} /*** end of CopServiceHook ***/ +#endif /* BOOT_COP_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_NVM_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Callback that gets called at the start of the internal NVM driver +** initialization routine. +** \return none. +** +****************************************************************************************/ +void NvmInitHook(void) +{ +} /*** end of NvmInitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of a firmware update to reinitialize +** the NVM driver. +** \return none. +** +****************************************************************************************/ +void NvmReinitHook(void) +{ +} /*** end of NvmReinitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of the NVM driver write +** routine. It allows additional memory to be operated on. If the address +** is not within the range of the additional memory, then +** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't +** been written yet. +** \param addr Start address. +** \param len Length in bytes. +** \param data Pointer to the data buffer. +** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is +** not within the supported memory range, or BLT_NVM_ERROR is the write +** operation failed. +** +****************************************************************************************/ +blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data) +{ + return BLT_NVM_NOT_IN_RANGE; +} /*** end of NvmWriteHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of the NVM driver erase +** routine. It allows additional memory to be operated on. If the address +** is not within the range of the additional memory, then +** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory +** hasn't been erased yet. +** \param addr Start address. +** \param len Length in bytes. +** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is +** not within the supported memory range, or BLT_NVM_ERROR is the erase +** operation failed. +** +****************************************************************************************/ +blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len) +{ + return BLT_NVM_NOT_IN_RANGE; +} /*** end of NvmEraseHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the end of the NVM programming session. +** \return BLT_TRUE is successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmDoneHook(void) +{ + return BLT_TRUE; +} /*** end of NvmDoneHook ***/ +#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */ + + +#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Verifies the checksum, which indicates that a valid user program is +** present and can be started. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmVerifyChecksumHook(void) +{ + return BLT_TRUE; +} /*** end of NvmVerifyChecksum ***/ + + +/************************************************************************************//** +** \brief Writes a checksum of the user program to non-volatile memory. This is +** performed once the entire user program has been programmed. Through +** the checksum, the bootloader can check if a valid user programming is +** present and can be started. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmWriteChecksumHook(void) +{ + return BLT_TRUE; +} +#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_XCP_SEED_KEY_ENABLE > 0) +/************************************************************************************//** +** \brief Provides a seed to the XCP master that will be used for the key +** generation when the master attempts to unlock the specified resource. +** Called by the GET_SEED command. +** \param resource Resource that the seed if requested for (XCP_RES_XXX). +** \param seed Pointer to byte buffer wher the seed will be stored. +** \return Length of the seed in bytes. +** +****************************************************************************************/ +blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed) +{ + /* request seed for unlocking ProGraMming resource */ + if ((resource & XCP_RES_PGM) != 0) + { + seed[0] = 0x55; + } + + /* return seed length */ + return 1; +} /*** end of XcpGetSeedHook ***/ + + +/************************************************************************************//** +** \brief Called by the UNLOCK command and checks if the key to unlock the +** specified resource was correct. If so, then the resource protection +** will be removed. +** \param resource resource to unlock (XCP_RES_XXX). +** \param key pointer to the byte buffer holding the key. +** \param len length of the key in bytes. +** \return 1 if the key was correct, 0 otherwise. +** +****************************************************************************************/ +blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len) +{ + /* suppress compiler warning for unused parameter */ + len = len; + + /* the example key algorithm in "libseednkey.dll" works as follows: + * - PGM will be unlocked if key = seed - 1 + */ + + /* check key for unlocking ProGraMming resource */ + if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1))) + { + /* correct key received for unlocking PGM resource */ + return 1; + } + + /* still here so key incorrect */ + return 0; +} /*** end of XcpVerifyKeyHook ***/ +#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */ + + +/*********************************** end of hooks.c ************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/ide/s32k118.dep b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/ide/s32k118.dep new file mode 100644 index 00000000..4098019d --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/ide/s32k118.dep @@ -0,0 +1,716 @@ + + + 4 + 688922450 + + Debug + + $PROJ_DIR$\..\lib\startup.c + $PROJ_DIR$\..\main.c + $PROJ_DIR$\..\timer.h + $PROJ_DIR$\..\obj\s32k118.pbd + $PROJ_DIR$\..\boot.c + $PROJ_DIR$\..\obj\timer.xcl + $PROJ_DIR$\..\lib\S32K118_features.h + $PROJ_DIR$\..\lib\startup.h + $PROJ_DIR$\..\startup_S32K118.s + $PROJ_DIR$\..\obj\system_S32K118.xcl + $PROJ_DIR$\..\bin\demoprog_s32k118.out + $PROJ_DIR$\..\led.h + $PROJ_DIR$\..\obj\system_S32K118.__cstat.et + $PROJ_DIR$\..\obj\boot.o + $PROJ_DIR$\..\obj\led.o + $PROJ_DIR$\..\timer.c + $PROJ_DIR$\..\obj\timer.o + $PROJ_DIR$\..\obj\timer.__cstat.et + $PROJ_DIR$\..\obj\led.xcl + $TOOLKIT_DIR$\inc\c\yvals.h + $PROJ_DIR$\..\obj\boot.xcl + $PROJ_DIR$\..\obj\main.o + $PROJ_DIR$\..\lib\system_S32K118.c + $PROJ_DIR$\..\lib\system_S32K118.h + $PROJ_DIR$\..\obj\main.xcl + $PROJ_DIR$\..\header.h + $PROJ_DIR$\..\led.c + $PROJ_DIR$\..\obj\startup.xcl + $PROJ_DIR$\..\obj\startup_S32K118.o + $PROJ_DIR$\..\obj\startup.__cstat.et + $PROJ_DIR$\..\boot.h + $PROJ_DIR$\..\obj\system_S32K118.o + $PROJ_DIR$\..\lib\devassert.h + $PROJ_DIR$\..\lib\device_registers.h + $PROJ_DIR$\..\lib\s32_core_cm0.h + $PROJ_DIR$\..\lib\S32K118.h + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + $PROJ_DIR$\..\obj\boot.__cstat.et + $TOOLKIT_DIR$\lib\m6M_tl.a + $TOOLKIT_DIR$\inc\c\stdint.h + $TOOLKIT_DIR$\lib\rt6M_tl.a + $PROJ_DIR$\..\S32K118_25_flash.icf + $PROJ_DIR$\..\obj\demoprog_s32k118.map + $TOOLKIT_DIR$\lib\shb_l.a + $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h + $TOOLKIT_DIR$\inc\c\ycheck.h + $PROJ_DIR$\..\obj\main.__cstat.et + $PROJ_DIR$\..\obj\led.__cstat.et + $PROJ_DIR$\..\bin\demoprog_s32k118.srec + $TOOLKIT_DIR$\inc\c\stdbool.h + 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$PROJ_DIR$\..\obj\cpu_comp.xcl + $PROJ_DIR$\..\..\..\..\Source\file.h + $PROJ_DIR$\..\..\..\..\Source\net.c + $PROJ_DIR$\..\..\..\..\Source\net.h + $PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\rs232.c + $PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\types.h + $PROJ_DIR$\..\obj\cpu_comp.o + $PROJ_DIR$\..\..\..\..\Source\can.h + $PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\timer.c + $PROJ_DIR$\..\..\..\..\Source\cop.h + $PROJ_DIR$\..\..\..\..\Source\nvm.h + $PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\cpu.c + $PROJ_DIR$\..\..\..\..\Source\assert.h + $PROJ_DIR$\..\..\..\..\Source\backdoor.c + $PROJ_DIR$\..\..\..\..\Source\backdoor.h + $PROJ_DIR$\..\..\..\..\Source\cpu.h + $PROJ_DIR$\..\..\..\..\Source\cop.c + $PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\can.c + $PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\flash.c + $PROJ_DIR$\..\..\..\..\Source\plausibility.h + $PROJ_DIR$\..\bin\openblt_s32k118.srec + $PROJ_DIR$\..\obj\flash.o + $PROJ_DIR$\..\obj\flash.xcl + $PROJ_DIR$\..\obj\nvm.xcl + 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Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/led.c +* \brief LED driver source file. +* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "led.h" /* module header */ +#include "device_registers.h" /* device registers */ + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Holds the desired LED blink interval time. */ +static blt_int16u ledBlinkIntervalMs; + + +/************************************************************************************//** +** \brief Initializes the LED blink driver. +** \param interval_ms Specifies the desired LED blink interval time in milliseconds. +** \return none. +** +****************************************************************************************/ +void LedBlinkInit(blt_int16u interval_ms) +{ + /* LED GPIO pin configuration. PE8 = GPIO, MUX = ALT1. */ + PORTE->PCR[8] = PORT_PCR_MUX(1); + /* Configure Port E pin 8 GPIO as digital output. */ + PTE->PDDR |= GPIO_PDDR_PDD(1 << 8U); + /* Turn the LED off on Port E pin 8. */ + PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U); + /* store the interval time between LED toggles */ + ledBlinkIntervalMs = interval_ms; +} /*** end of LedBlinkInit ***/ + + +/************************************************************************************//** +** \brief Task function for blinking the LED as a fixed timer interval. +** \return none. +** +****************************************************************************************/ +void LedBlinkTask(void) +{ + static blt_bool ledOn = BLT_FALSE; + static blt_int32u nextBlinkEvent = 0; + + /* check for blink event */ + if (TimerGet() >= nextBlinkEvent) + { + /* toggle the LED state */ + if (ledOn == BLT_FALSE) + { + ledOn = BLT_TRUE; + /* Turn the LED on. */ + PTE->PSOR |= GPIO_PSOR_PTSO(1 << 8U); + } + else + { + ledOn = BLT_FALSE; + /* Turn the LED off. */ + PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U); + } + /* schedule the next blink event */ + nextBlinkEvent = TimerGet() + ledBlinkIntervalMs; + } +} /*** end of LedBlinkTask ***/ + + +/************************************************************************************//** +** \brief Cleans up the LED blink driver. This is intended to be used upon program +** exit. +** \return none. +** +****************************************************************************************/ +void LedBlinkExit(void) +{ + /* Turn the LED off. */ + PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U); +} /*** end of LedBlinkExit ***/ + + +/*********************************** end of led.c **************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/led.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/led.h new file mode 100644 index 00000000..1dcb725e --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/led.h @@ -0,0 +1,40 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/led.h +* \brief LED driver header file. +* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef LED_H +#define LED_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void LedBlinkInit(blt_int16u interval_ms); +void LedBlinkTask(void); +void LedBlinkExit(void); + + +#endif /* LED_H */ +/*********************************** end of led.h **************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/S32K118.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/S32K118.h new file mode 100644 index 00000000..d1f10a17 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/S32K118.h @@ -0,0 +1,10438 @@ +/* +** ################################################################### +** Processor: S32K118 +** Reference manual: S32K1XXRM Rev. 9, 09/2018 +** Version: rev. 1.3, 2019-02-19 +** Build: b190219 +** +** Abstract: +** Peripheral Access Layer for S32K118 +** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2017-12-14) - Mihai Volmer +** Initial version based on S32K1XXRM Rev. 6, 12/2017. +** - rev. 1.1 (2018-02-08) - Mihai Volmer +** Renamed the NVIC register array IP to IPR to reflect the register access difference from Cortex-M4 NVIC registers +** Fixed CSE_PRAM base address +** - rev. 1.2 (2018-07-19) - Dan Nastasa +** Updated the header based on S32K1XXRM Rev. 8, 06/2018. +** Added MTB_DWT peripheral to the header file +** - rev. 1.3 (2019-02-19) - Ionut Pavel +** Updated the header based on S32K1XXRM Rev. 9, 09/2018. +** Removed LMEM_LMDR2 register from the header file. +** Modified LMEM_LMPECR register to Read-Only. +** +** ################################################################### +*/ + +/*! + * @file S32K118.h + * @version 1.3 + * @date 2019-02-19 + * @brief Peripheral Access Layer for S32K118 + * + * This file contains register definitions and macros for easy access to their + * bit fields. + * + * This file assumes LITTLE endian system. + */ + +/** +* @page misra_violations MISRA-C:2012 violations +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced +* The SoC header defines typedef for all modules. +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced +* The SoC header defines macros for all modules and registers. +* +* @section [global] +* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro +* These are generated macros used for accessing the bit-fields from registers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.1, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.2, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.4, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.5, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler +* This type qualifier is needed to ensure correct I/O access and addressing. +*/ + +/* ---------------------------------------------------------------------------- + -- MCU activation + ---------------------------------------------------------------------------- */ + +/* Prevention from multiple including the same memory map */ +#if !defined(S32K118_H_) /* Check if memory map has not been already included */ +#define S32K118_H_ +#define MCU_S32K118 + +/* Check if another memory map has not been also included */ +#if (defined(MCU_ACTIVE)) + #error S32K118 memory map: There is already included another memory map. Only one memory map can be included. +#endif /* (defined(MCU_ACTIVE)) */ +#define MCU_ACTIVE + +#include + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0003u + +/* ---------------------------------------------------------------------------- + -- Generic macros + ---------------------------------------------------------------------------- */ + +/* IO definitions (access restrictions to peripheral registers) */ +/** +* IO Type Qualifiers are used +* \li to specify the access to peripheral variables. +* \li for automatic generation of peripheral register debug information. +*/ +#ifndef __IO +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ +#endif + + +/** +* @brief 32 bits memory read macro. +*/ +#if !defined(REG_READ32) + #define REG_READ32(address) (*(volatile uint32_t*)(address)) +#endif + +/** +* @brief 32 bits memory write macro. +*/ +#if !defined(REG_WRITE32) + #define REG_WRITE32(address, value) ((*(volatile uint32_t*)(address))= (uint32_t)(value)) +#endif + +/** +* @brief 32 bits bits setting macro. +*/ +#if !defined(REG_BIT_SET32) + #define REG_BIT_SET32(address, mask) ((*(volatile uint32_t*)(address))|= (uint32_t)(mask)) +#endif + +/** +* @brief 32 bits bits clearing macro. +*/ +#if !defined(REG_BIT_CLEAR32) + #define REG_BIT_CLEAR32(address, mask) ((*(volatile uint32_t*)(address))&= ((uint32_t)~((uint32_t)(mask)))) +#endif + +/** +* @brief 32 bit clear bits and set with new value +* @note It is user's responsability to make sure that value has only "mask" bits set - (value&~mask)==0 +*/ +#if !defined(REG_RMW32) + #define REG_RMW32(address, mask, value) (REG_WRITE32((address), ((REG_READ32(address)& ((uint32_t)~((uint32_t)(mask))))| ((uint32_t)(value))))) +#endif + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers for S32K118 + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers_S32K118 Interrupt vector numbers for S32K118 + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 48u /**< Number of interrupts in the Vector table */ + +/** + * @brief Defines the Interrupt Numbers definitions + * + * This enumeration is used to configure the interrupts. + * + * Implements : IRQn_Type_Class + */ +typedef enum +{ + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_IRQn = 0u, /**< DMA channel 0 transfer complete */ + DMA1_IRQn = 1u, /**< DMA channel 1 transfer complete */ + DMA2_IRQn = 2u, /**< DMA channel 2 transfer complete */ + DMA3_IRQn = 3u, /**< DMA channel 3 transfer complete */ + DMA_Error_IRQn = 4u, /**< DMA error interrupt channels 0-3 */ + ERM_fault_IRQn = 5u, /**< ERM single and double bit error correction */ + RTC_IRQn = 6u, /**< RTC alarm interrupt */ + RTC_Seconds_IRQn = 7u, /**< RTC seconds interrupt */ + LPTMR0_IRQn = 8u, /**< LPTIMER interrupt request */ + PORT_IRQn = 9u, /**< Port A, B, C, D and E pin detect interrupt */ + CAN0_ORed_Err_Wakeup_IRQn = 10u, /**< OR’ed [Bus Off OR Bus Off Done OR Transmit Warning OR Receive Warning], Interrupt indicating that errors were detected on the CAN bus, Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode */ + CAN0_ORed_0_31_MB_IRQn = 11u, /**< OR'ed Message buffer (0-15, 16-31) */ + FTM0_Ch0_7_IRQn = 12u, /**< FTM0 Channel 0 to 7 interrupt */ + FTM0_Fault_IRQn = 13u, /**< FTM0 Fault interrupt */ + FTM0_Ovf_Reload_IRQn = 14u, /**< FTM0 Counter overflow and Reload interrupt */ + FTM1_Ch0_7_IRQn = 15u, /**< FTM1 Channel 0 to 7 interrupt */ + FTM1_Fault_IRQn = 16u, /**< FTM1 Fault interrupt */ + FTM1_Ovf_Reload_IRQn = 17u, /**< FTM1 Counter overflow and Reload interrupt */ + FTFC_IRQn = 18u, /**< FTFC Command complete, Read collision and Double bit fault detect */ + PDB0_IRQn = 19u, /**< PDB0 interrupt */ + LPIT0_IRQn = 20u, /**< LPIT interrupt */ + SCG_CMU_LVD_LVWSCG_IRQn = 21u, /**< PMC Low voltage detect interrupt, SCG bus interrupt request and CMU loss of range interrupt */ + WDOG_IRQn = 22u, /**< WDOG interrupt request out before wdg reset out */ + RCM_IRQn = 23u, /**< RCM Asynchronous Interrupt */ + LPI2C0_Master_Slave_IRQn = 24u, /**< LPI2C0 Master Interrupt and Slave Interrupt */ + FLEXIO_IRQn = 25u, /**< FlexIO Interrupt */ + LPSPI0_IRQn = 26u, /**< LPSPI0 Interrupt */ + LPSPI1_IRQn = 27u, /**< LPSPI1 Interrupt */ + ADC0_IRQn = 28u, /**< ADC0 interrupt request. */ + CMP0_IRQn = 29u, /**< CMP0 interrupt request */ + LPUART1_RxTx_IRQn = 30u, /**< LPUART1 Transmit / Receive Interrupt */ + LPUART0_RxTx_IRQn = 31u /**< LPUART0 Transmit / Receive Interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers_S32K118 */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer for S32K118 + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer_S32K118 Device Peripheral Access Layer for S32K118 + * @{ + */ + +/* @brief This module covers memory mapped registers available on SoC */ + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + + +/** ADC - Size of Registers Arrays */ +#define ADC_SC1_COUNT 16u +#define ADC_R_COUNT 16u +#define ADC_CV_COUNT 2u + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[ADC_SC1_COUNT]; /**< ADC Status and Control Register 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ + __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x44 */ + __I uint32_t R[ADC_R_COUNT]; /**< ADC Data Result Registers, array offset: 0x48, array step: 0x4 */ + __IO uint32_t CV[ADC_CV_COUNT]; /**< Compare Value Registers, array offset: 0x88, array step: 0x4 */ + __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x90 */ + __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x94 */ + __IO uint32_t BASE_OFS; /**< BASE Offset Register, offset: 0x98 */ + __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x9C */ + __IO uint32_t USR_OFS; /**< USER Offset Correction Register, offset: 0xA0 */ + __IO uint32_t XOFS; /**< ADC X Offset Correction Register, offset: 0xA4 */ + __IO uint32_t YOFS; /**< ADC Y Offset Correction Register, offset: 0xA8 */ + __IO uint32_t G; /**< ADC Gain Register, offset: 0xAC */ + __IO uint32_t UG; /**< ADC User Gain Register, offset: 0xB0 */ + __IO uint32_t CLPS; /**< ADC General Calibration Value Register S, offset: 0xB4 */ + __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register 3, offset: 0xB8 */ + __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register 2, offset: 0xBC */ + __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register 1, offset: 0xC0 */ + __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register 0, offset: 0xC4 */ + __IO uint32_t CLPX; /**< ADC Plus-Side General Calibration Value Register X, offset: 0xC8 */ + __IO uint32_t CLP9; /**< ADC Plus-Side General Calibration Value Register 9, offset: 0xCC */ + __IO uint32_t CLPS_OFS; /**< ADC General Calibration Offset Value Register S, offset: 0xD0 */ + __IO uint32_t CLP3_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 3, offset: 0xD4 */ + __IO uint32_t CLP2_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 2, offset: 0xD8 */ + __IO uint32_t CLP1_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 1, offset: 0xDC */ + __IO uint32_t CLP0_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 0, offset: 0xE0 */ + __IO uint32_t CLPX_OFS; /**< ADC Plus-Side General Calibration Offset Value Register X, offset: 0xE4 */ + __IO uint32_t CLP9_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 9, offset: 0xE8 */ +} ADC_Type, *ADC_MemMapPtr; + + /** Number of instances of the ADC module. */ +#define ADC_INSTANCE_COUNT (1u) + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x4003B000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0 } + /** Number of interrupt vector arrays for the ADC module. */ +#define ADC_IRQS_ARR_COUNT (1u) + /** Number of interrupt channels for the ADC module. */ +#define ADC_IRQS_CH_COUNT (1u) +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* SC1 Bit Fields */ +#define ADC_SC1_ADCH_MASK 0x1Fu +#define ADC_SC1_ADCH_SHIFT 0u +#define ADC_SC1_ADCH_WIDTH 5u +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<VTOR} + +/* FTM module features */ + +/* @brief Number of PWM channels */ +#define FEATURE_FTM_CHANNEL_COUNT (8U) +/* @brief Number of fault channels */ +#define FTM_FEATURE_FAULT_CHANNELS (4U) +/* @brief Width of control channel */ +#define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH (8U) +/* @brief Output channel offset */ +#define FTM_FEATURE_OUTPUT_CHANNEL_OFFSET (16U) +/* @brief Max counter value */ +#define FTM_FEATURE_CNT_MAX_VALUE_U32 (0x0000FFFFU) +/* @brief Input capture for single shot */ +#define FTM_FEATURE_INPUT_CAPTURE_SINGLE_SHOT (2U) +/* @brief Dithering has supported on the generated PWM signals */ +#define FEATURE_FTM_HAS_SUPPORTED_DITHERING (1U) +/* @brief Number of interrupt vector for channels of the FTM module. */ +#define FEATURE_FTM_HAS_NUM_IRQS_CHANS (1U) + +/* LPIT module features */ + +/*! @brief Number of interrupt vector for channels of the LPIT module. */ +#define FEATURE_LPIT_HAS_NUM_IRQS_CHANS (1U) +/*! @brief Clock names for LPIT. */ +#define LPIT_CLOCK_NAMES {LPIT0_CLK} + +/* LPI2C module features */ + +/* @brief DMA instance used for LPI2C module */ +#define LPI2C_DMA_INSTANCE 0U + +/* @brief EDMA requests for LPI2C module. */ +#define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}} +/* @brief PCC clocks for LPI2C module. */ +#define LPI2C_PCC_CLOCKS {LPI2C0_CLK} + +/* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */ +#define LPI2C_HAS_FAST_PLUS_MODE (0U) +#define LPI2C_HAS_HIGH_SPEED_MODE (0U) +#define LPI2C_HAS_ULTRA_FAST_MODE (0U) + +/* LPI2C module features */ + +/* @brief DMA instance used for LPI2C module */ +#define LPI2C_DMA_INSTANCE 0U + +/* @brief EDMA requests for LPI2C module. */ +#define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}} +/* @brief PCC clocks for LPI2C module. */ +#define LPI2C_PCC_CLOCKS {LPI2C0_CLK} + +/* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */ +#define LPI2C_HAS_FAST_PLUS_MODE (0U) +#define LPI2C_HAS_HIGH_SPEED_MODE (0U) +#define LPI2C_HAS_ULTRA_FAST_MODE (0U) + +/* MSCM module features */ + +/* @brief Has interrupt router control registers (IRSPRCn). */ +#define FEATURE_MSCM_HAS_INTERRUPT_ROUTER (0) +/* @brief Has directed CPU interrupt routerregisters (IRCPxxx). */ +#define FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER (0) + +/* CSEc module features */ + +/*! @brief CSE_PRAM offset of the page length parameter used by the following +commands: CMD_ENC_ECB, CMD_ENC_CBC, CMD_DEC_ECB, CMD_DEC_CBC, CMD_MP_COMPRESS */ +#define FEATURE_CSEC_PAGE_LENGTH_OFFSET (0xEU) +/*! @brief CSE_PRAM offset of the message length parameter used by the following +commands: CMD_GENERATE_MAC, CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_MESSAGE_LENGTH_OFFSET (0xCU) +/*! @brief CSE_PRAM offset of the MAC length parameter used by the following +commands: CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_MAC_LENGTH_OFFSET (0x8U) +/*! @brief CSE_PRAM offset of the boot size parameter used by the following +commands: CMD_BOOT_DEFINE */ +#define FEATURE_CSEC_BOOT_SIZE_OFFSET (0x1CU) +/*! @brief CSE_PRAM offset of the boot flavor parameter used by the following +commands: CMD_BOOT_DEFINE */ +#define FEATURE_CSEC_BOOT_FLAVOR_OFFSET (0x1BU) +/*! @brief CSE_PRAM offset of the Flash start address parameter used by the +following commands: CMD_GENERATE_MAC, CMD_VERIFY_MAC (pointer method) */ +#define FEATURE_CSEC_FLASH_START_ADDRESS_OFFSET (0x10U) +/*! @brief CSE_PRAM offset of the verification status parameter used by the +following commands: CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_VERIFICATION_STATUS_OFFSET (0x14U) +/*! @brief CSE_PRAM offset of the error bits field contained by all commands */ +#define FEATURE_CSEC_ERROR_BITS_OFFSET (0x4U) +/*! @brief CSE_PRAM offset of the SREG parameter used by the following commands: +CMD_GET_ID */ +#define FEATURE_CSEC_SREG_OFFSET (0x2FU) + +/*! @brief CSE_PRAM offset of page 0 */ +#define FEATURE_CSEC_PAGE_0_OFFSET (0x0U) +/*! @brief CSE_PRAM offset of page 1 */ +#define FEATURE_CSEC_PAGE_1_OFFSET (0x10U) +/*! @brief CSE_PRAM offset of page 2 */ +#define FEATURE_CSEC_PAGE_2_OFFSET (0x20U) +/*! @brief CSE_PRAM offset of page 3 */ +#define FEATURE_CSEC_PAGE_3_OFFSET (0x30U) +/*! @brief CSE_PRAM offset of page 4 */ +#define FEATURE_CSEC_PAGE_4_OFFSET (0x40U) +/*! @brief CSE_PRAM offset of page 5 */ +#define FEATURE_CSEC_PAGE_5_OFFSET (0x50U) +/*! @brief CSE_PRAM offset of page 6 */ +#define FEATURE_CSEC_PAGE_6_OFFSET (0x60U) +/*! @brief CSE_PRAM offset of page 7 */ +#define FEATURE_CSEC_PAGE_7_OFFSET (0x70U) + +/* CRC module features */ + +/* @brief CRC module use for S32K. */ +#define FEATURE_CRC_DRIVER_SOFT_POLYNOMIAL +/* @brief Default CRC bit width */ +#define FEATURE_CRC_DEFAULT_WIDTH CRC_BITS_16 +/* @brief Default CRC read transpose */ +#define FEATURE_CRC_DEFAULT_READ_TRANSPOSE CRC_TRANSPOSE_NONE +/* @brief Default CRC write transpose */ +#define FEATURE_CRC_DEFAULT_WRITE_TRANSPOSE CRC_TRANSPOSE_NONE +/* @brief Default polynomial 0x1021U */ +#define FEATURE_CRC_DEFAULT_POLYNOMIAL (0x1021U) +/* @brief Default seed value is 0xFFFFU */ +#define FEATURE_CRC_DEFAULT_SEED (0xFFFFU) + +/* PORT module features */ +/*! @brief PORT Used for setting Pins */ +#define FEATURE_PINS_DRIVER_USING_PORT (1) +/* @brief Has control lock (register bit PCR[LK]). */ +#define FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FEATURE_PINS_HAS_OPEN_DRAIN (0) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FEATURE_PORT_HAS_DIGITAL_FILTER (1) +/* @brief Has trigger output to trigger other peripherals (register bit field PCR[IRQC] values). */ +#define FEATURE_PORT_HAS_TRIGGER_OUT (0) +/* @brief Has setting flag only (register bit field PCR[IRQC] values). */ +#define FEATURE_PORT_HAS_FLAG_SET_ONLY (0) +/* @brief Has over-current feature (register bit field PCR[OCIE] values). */ +#define FEATURE_PINS_HAS_OVER_CURRENT (0) +/* @brief Has pull resistor selection available. */ +#define FEATURE_PINS_HAS_PULL_SELECTION (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FEATURE_PINS_HAS_SLEW_RATE (0) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength (register bit PCR[DSE]). */ +#define FEATURE_PINS_HAS_DRIVE_STRENGTH (1) +/* @brief Has drive strength control bits*/ +#define FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL (0) +/* @brief Has port input disable control bits*/ +#define FEATURE_PORT_HAS_INPUT_DISABLE (0) +/* @brief SIM_CHIPCTL_ADC_INTERLEAVE_EN bit is not available */ +#define FEATURE_PINS_HAS_ADC_INTERLEAVE_EN (0) + +/* MPU module features */ + +/* @brief Specifies hardware revision level. */ +#define FEATURE_MPU_HARDWARE_REVISION_LEVEL (1U) +/* @brief Has process identifier support. */ +#define FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1U) +/* @brief Specifies total number of bus masters. */ +#define FEATURE_MPU_MASTER_COUNT (3U) +/* @brief Specifies maximum number of masters which have separated +privilege rights for user and supervisor mode accesses (e.g. master0~3 in S32K1xx). +*/ +#define FEATURE_MPU_MAX_LOW_MASTER_NUMBER (3U) +/* @brief Specifies maximum number of masters which have only +read and write permissions (e.g. master4~7 in S32K1xx). +*/ +#define FEATURE_MPU_MAX_HIGH_MASTER_NUMBER (7U) + +/* @brief Specifies number of set access control right bits for + masters which have separated privilege rights for user and + supervisor mode accesses (e.g. master0~3 in S32K1xx). +*/ +#define FEATURE_MPU_LOW_MASTER_CONTROL_WIDTH (6U) +/* @brief Specifies number of set access control right bits for + masters which have only read and write permissions(e.g. master4~7 in S32K1xx). +*/ +#define FEATURE_MPU_HIGH_MASTER_CONTROL_WIDTH (2U) + +/* @brief The MPU Logical Bus Master Number for core bus master. */ +#define FEATURE_MPU_MASTER_CORE (0U) +/* @brief The MPU Logical Bus Master Number for Debugger master. */ +#define FEATURE_MPU_MASTER_DEBUGGER (1U) +/* @brief The MPU Logical Bus Master Number for DMA master. */ +#define FEATURE_MPU_MASTER_DMA (2U) +/* @brief Specifies master number. */ +#define FEATURE_MPU_MASTER \ +{ \ + FEATURE_MPU_MASTER_CORE, /*!< CORE */ \ + FEATURE_MPU_MASTER_DEBUGGER, /*!< DEBUGGER */ \ + FEATURE_MPU_MASTER_DMA, /*!< DMA */ \ +} + +/* @brief Specifies total number of slave ports. */ +#define FEATURE_MPU_SLAVE_COUNT (2U) +/* @brief The MPU Slave Port Assignment for Flash Controller and boot ROM. */ +#define FEATURE_MPU_SLAVE_FLASH_BOOTROM (0U) +/* @brief The MPU Slave Port Assignment for SRAM, MTB, DWT and MCM. */ +#define FEATURE_MPU_SLAVE_SRAM_MTB_DWT_MCM (1U) +/* @brief The MPU Slave Port mask. */ +#define FEATURE_MPU_SLAVE_MASK (0xC0000000U) +#define FEATURE_MPU_SLAVE_SHIFT (30u) +#define FEATURE_MPU_SLAVE_WIDTH (2u) +#define FEATURE_MPU_SLAVE(x) (((uint32_t)(((uint32_t)(x))<> (uint32_t)FEATURE_DMA_CH_WIDTH) +/* @brief DMA virtual channel to channel */ +#define FEATURE_DMA_VCH_TO_CH(x) ((x) & ((uint32_t)FEATURE_DMA_CHANNELS - 1U)) +/* @brief DMA supports the following particular channel priorities: */ +#define FEATURE_DMA_4_CH_PRIORITIES +/* @brief DMA supports bus bandwidth control. */ +#define FEATURE_DMA_ENGINE_STALL + +/* DMAMUX module features */ + +/* @brief DMAMUX peripheral is available in silicon. */ +#define FEATURE_DMAMUX_AVAILABLE +/* @brief Number of DMA channels. */ +#define FEATURE_DMAMUX_CHANNELS (4U) +/* @brief Has the periodic trigger capability */ +#define FEATURE_DMAMUX_HAS_TRIG (1) +/* @brief Conversion from request source to the actual DMAMUX channel */ +#define FEATURE_DMAMUX_REQ_SRC_TO_CH(x) (x) +/* @brief Mapping between request source and DMAMUX instance */ +#define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x) (0U) +/* @brief Conversion from eDMA channel index to DMAMUX channel. */ +#define FEATURE_DMAMUX_DMA_CH_TO_CH(x) (x) +/* @brief Conversion from DMAMUX channel DMAMUX register index. */ +#define FEATURE_DMAMUX_CHN_REG_INDEX(x) (x) +/* @brief Clock names for DMAMUX. */ +#define FEATURE_DMAMUX_CLOCK_NAMES {DMAMUX0_CLK} + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum { + EDMA_REQ_DISABLED = 0U, + EDMA_REQ_LPUART0_RX = 2U, + EDMA_REQ_LPUART0_TX = 3U, + EDMA_REQ_LPUART1_RX = 4U, + EDMA_REQ_LPUART1_TX = 5U, + EDMA_REQ_FLEXIO_SHIFTER0 = 10U, + EDMA_REQ_FLEXIO_SHIFTER1 = 11U, + EDMA_REQ_FLEXIO_SHIFTER2 = 12U, + EDMA_REQ_FLEXIO_SHIFTER3 = 13U, + EDMA_REQ_LPSPI0_RX = 14U, + EDMA_REQ_LPSPI0_TX = 15U, + EDMA_REQ_LPSPI1_RX = 16U, + EDMA_REQ_LPSPI1_TX = 17U, + EDMA_REQ_FTM1_CHANNEL_0 = 20U, + EDMA_REQ_FTM1_CHANNEL_1 = 21U, + EDMA_REQ_FTM1_CHANNEL_2 = 22U, + EDMA_REQ_FTM1_CHANNEL_3 = 23U, + EDMA_REQ_FTM1_CHANNEL_4 = 24U, + EDMA_REQ_FTM1_CHANNEL_5 = 25U, + EDMA_REQ_FTM1_CHANNEL_6 = 26U, + EDMA_REQ_FTM1_CHANNEL_7 = 27U, + EDMA_REQ_FTM0_OR_CH0_CH7 = 36U, + EDMA_REQ_ADC0 = 42U, + EDMA_REQ_LPI2C0_RX = 44U, + EDMA_REQ_LPI2C0_TX = 45U, + EDMA_REQ_PDB0 = 46U, + EDMA_REQ_CMP0 = 48U, + EDMA_REQ_PORTA = 49U, + EDMA_REQ_PORTB = 50U, + EDMA_REQ_PORTC = 51U, + EDMA_REQ_PORTD = 52U, + EDMA_REQ_PORTE = 53U, + EDMA_REQ_FLEXCAN0 = 54U, + EDMA_REQ_LPTMR0 = 59U, + EDMA_REQ_DMAMUX_ALWAYS_ENABLED0 = 62U, + EDMA_REQ_DMAMUX_ALWAYS_ENABLED1 = 63U +} dma_request_source_t; + + +/* TRGMUX module features */ +/*! + * @brief Enumeration for trigger source module of TRGMUX + * + * Describes all possible inputs (trigger sources) of the TRGMUX IP + * This enumeration depends on the supported instances in device + */ +enum trgmux_trigger_source_e +{ + TRGMUX_TRIG_SOURCE_DISABLED = 0U, + TRGMUX_TRIG_SOURCE_VDD = 1U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN0 = 2U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN1 = 3U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN2 = 4U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN3 = 5U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN4 = 6U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN5 = 7U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN6 = 8U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN7 = 9U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN8 = 10U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN9 = 11U, + TRGMUX_TRIG_SOURCE_CMP0_OUT = 14U, + TRGMUX_TRIG_SOURCE_LPIT_CH0 = 17U, + TRGMUX_TRIG_SOURCE_LPIT_CH1 = 18U, + TRGMUX_TRIG_SOURCE_LPIT_CH2 = 19U, + TRGMUX_TRIG_SOURCE_LPIT_CH3 = 20U, + TRGMUX_TRIG_SOURCE_LPTMR0 = 21U, + TRGMUX_TRIG_SOURCE_FTM0_INIT_TRIG = 22U, + TRGMUX_TRIG_SOURCE_FTM0_EXT_TRIG = 23U, + TRGMUX_TRIG_SOURCE_FTM1_INIT_TRIG = 24U, + TRGMUX_TRIG_SOURCE_FTM1_EXT_TRIG = 25U, + TRGMUX_TRIG_SOURCE_ADC0_SC1A_COCO = 30U, + TRGMUX_TRIG_SOURCE_ADC0_SC1B_COCO = 31U, + TRGMUX_TRIG_SOURCE_PDB0_CH0_TRIG = 34U, + TRGMUX_TRIG_SOURCE_PDB0_PULSE_OUT = 36U, + TRGMUX_TRIG_SOURCE_RTC_ALARM = 43U, + TRGMUX_TRIG_SOURCE_RTC_SECOND = 44U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG0 = 45U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG1 = 46U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG2 = 47U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG3 = 48U, + TRGMUX_TRIG_SOURCE_LPUART0_RX_DATA = 49U, + TRGMUX_TRIG_SOURCE_LPUART0_TX_DATA = 50U, + TRGMUX_TRIG_SOURCE_LPUART0_RX_IDLE = 51U, + TRGMUX_TRIG_SOURCE_LPUART1_RX_DATA = 52U, + TRGMUX_TRIG_SOURCE_LPUART1_TX_DATA = 53U, + TRGMUX_TRIG_SOURCE_LPUART1_RX_IDLE = 54U, + TRGMUX_TRIG_SOURCE_LPI2C0_MASTER_TRIG = 55U, + TRGMUX_TRIG_SOURCE_LPI2C0_SLAVE_TRIG = 56U, + TRGMUX_TRIG_SOURCE_LPSPI0_FRAME = 59U, + TRGMUX_TRIG_SOURCE_LPSPI0_RX_DATA = 60U, + TRGMUX_TRIG_SOURCE_LPSPI1_FRAME = 61U, + TRGMUX_TRIG_SOURCE_LPSPI1_RX_DATA = 62U, + TRGMUX_TRIG_SOURCE_SIM_SW_TRIG = 63U, +}; + +/*! + * @brief Enumeration for target module of TRGMUX + * + * Describes all possible outputs (target modules) of the TRGMUX IP + * This enumeration depends on the supported instances in device + */ +enum trgmux_target_module_e +{ + TRGMUX_TARGET_MODULE_DMA_CH0 = 0U, + TRGMUX_TARGET_MODULE_DMA_CH1 = 1U, + TRGMUX_TARGET_MODULE_DMA_CH2 = 2U, + TRGMUX_TARGET_MODULE_DMA_CH3 = 3U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT0 = 4U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT1 = 5U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT2 = 6U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT3 = 7U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT4 = 8U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT5 = 9U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA0 = 12U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA1 = 13U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA2 = 14U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA3 = 15U, + TRGMUX_TARGET_MODULE_CMP0_SAMPLE = 28U, + TRGMUX_TARGET_MODULE_FTM0_HWTRIG0 = 40U, + TRGMUX_TARGET_MODULE_FTM0_FAULT0 = 41U, + TRGMUX_TARGET_MODULE_FTM0_FAULT1 = 42U, + TRGMUX_TARGET_MODULE_FTM0_FAULT2 = 43U, + TRGMUX_TARGET_MODULE_FTM1_HWTRIG0 = 44U, + TRGMUX_TARGET_MODULE_FTM1_FAULT0 = 45U, + TRGMUX_TARGET_MODULE_FTM1_FAULT1 = 46U, + TRGMUX_TARGET_MODULE_FTM1_FAULT2 = 47U, + TRGMUX_TARGET_MODULE_PDB0_TRG_IN = 56U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM0 = 68U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM1 = 69U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM2 = 70U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM3 = 71U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH0 = 72U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH1 = 73U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH2 = 74U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH3 = 75U, + TRGMUX_TARGET_MODULE_LPUART0_TRG = 76U, + TRGMUX_TARGET_MODULE_LPUART1_TRG = 80U, + TRGMUX_TARGET_MODULE_LPI2C0_TRG = 84U, + TRGMUX_TARGET_MODULE_LPSPI0_TRG = 92U, + TRGMUX_TARGET_MODULE_LPSPI1_TRG = 96U, + TRGMUX_TARGET_MODULE_LPTMR0_ALT0 = 100U, +}; + +/* @brief Constant array storing the value of all TRGMUX output(target module) identifiers */ +#define FEATURE_TRGMUX_TARGET_MODULE \ +{ \ + TRGMUX_TARGET_MODULE_DMA_CH0, \ + TRGMUX_TARGET_MODULE_DMA_CH1, \ + TRGMUX_TARGET_MODULE_DMA_CH2, \ + TRGMUX_TARGET_MODULE_DMA_CH3, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT0, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT1, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT2, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT3, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT4, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT5, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA0, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA1, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA2, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA3, \ + TRGMUX_TARGET_MODULE_CMP0_SAMPLE, \ + TRGMUX_TARGET_MODULE_FTM0_HWTRIG0, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT0, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT1, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT2, \ + TRGMUX_TARGET_MODULE_FTM1_HWTRIG0, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT0, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT1, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT2, \ + TRGMUX_TARGET_MODULE_PDB0_TRG_IN, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM0, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM1, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM2, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM3, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH0, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH1, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH2, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH3, \ + TRGMUX_TARGET_MODULE_LPUART0_TRG, \ + TRGMUX_TARGET_MODULE_LPUART1_TRG, \ + TRGMUX_TARGET_MODULE_LPI2C0_TRG, \ + TRGMUX_TARGET_MODULE_LPSPI0_TRG, \ + TRGMUX_TARGET_MODULE_LPSPI1_TRG, \ + TRGMUX_TARGET_MODULE_LPTMR0_ALT0 \ +} + + +/* LPSPI module features */ +/* @brief Initial value for state structure */ +#define FEATURE_LPSPI_STATE_STRUCTURES_NULL {NULL, NULL} +/* @brief Clock indexes for LPSPI clock */ +#define FEATURE_LPSPI_CLOCKS_NAMES {LPSPI0_CLK, LPSPI1_CLK}; + +/* FlexIO module features */ + +/* @brief Define the maximum number of shifters for any FlexIO instance. */ +#define FEATURE_FLEXIO_MAX_SHIFTER_COUNT (4U) +/* @brief Define DMA request names for Flexio. */ +#define FEATURE_FLEXIO_DMA_REQ_0 EDMA_REQ_FLEXIO_SHIFTER0 +#define FEATURE_FLEXIO_DMA_REQ_1 EDMA_REQ_FLEXIO_SHIFTER1 +#define FEATURE_FLEXIO_DMA_REQ_2 EDMA_REQ_FLEXIO_SHIFTER2 +#define FEATURE_FLEXIO_DMA_REQ_3 EDMA_REQ_FLEXIO_SHIFTER3 + +/* LPUART module features */ + +/* @brief Has extended data register ED. */ +#define FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FEATURE_LPUART_FIFO_SIZE (4U) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits. */ +#define FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Flag clearance mask for STAT register. */ +#define FEATURE_LPUART_STAT_REG_FLAGS_MASK (0xC01FC000U) +/* @brief Flag clearance mask for FIFO register. */ +#define FEATURE_LPUART_FIFO_REG_FLAGS_MASK (0x00030000U) +/* @brief Reset mask for FIFO register. */ +#define FEATURE_LPUART_FIFO_RESET_MASK (0x0003C000U) +/* @brief Default oversampling ratio. */ +#define FEATURE_LPUART_DEFAULT_OSR (0x0FUL) +/* @brief Default baud rate modulo divisor. */ +#define FEATURE_LPUART_DEFAULT_SBR (0x04UL) +/* @brief Clock names for LPUART. */ +#define LPUART_CLOCK_NAMES {LPUART0_CLK, LPUART1_CLK} + +/* ADC module features */ + +/*! @brief ADC feature flag for extended number of SC1 and R registers, + * generically named 'alias registers' */ +#define FEATURE_ADC_HAS_EXTRA_NUM_REGS (0) + +#define NUMBER_OF_ALT_CLOCKS ADC_CLK_ALT_1 +/*! @brief ADC feature flag for defining number of external ADC channels. + * If each ADC instance has different number of external channels, then + * this define is set with the maximum value. */ +#define FEATURE_ADC_MAX_NUM_EXT_CHANS (16) +#define FEATURE_ADC_HAS_CHANNEL_2 (1) +#define FEATURE_ADC_HAS_CHANNEL_8 (1) +#define ADC_CLOCKS {ADC0_CLK} +/*! @brief ADC number of control channels */ +#if FEATURE_ADC_HAS_EXTRA_NUM_REGS +#define ADC_CTRL_CHANS_COUNT ADC_aSC1_COUNT +#else +#define ADC_CTRL_CHANS_COUNT ADC_SC1_COUNT +#endif /* FEATURE_ADC_HAS_EXTRA_NUM_REGS */ + +/*! @brief ADC default Sample Time from RM */ +#define ADC_DEFAULT_SAMPLE_TIME (0x0CU) +/*! @brief ADC default User Gain from RM */ +#define ADC_DEFAULT_USER_GAIN (0x04U) +/* @brief Max of adc clock frequency */ +#define ADC_CLOCK_FREQ_MAX_RUNTIME (50000000u) +/* @brief Min of adc clock frequency */ +#define ADC_CLOCK_FREQ_MIN_RUNTIME (2000000u) + +/* CAN module features */ + +/* @brief Frames available in Rx FIFO flag shift */ +#define FEATURE_CAN_RXFIFO_FRAME_AVAILABLE (5U) +/* @brief Rx FIFO warning flag shift */ +#define FEATURE_CAN_RXFIFO_WARNING (6U) +/* @brief Rx FIFO overflow flag shift */ +#define FEATURE_CAN_RXFIFO_OVERFLOW (7U) +/* @brief Has Flexible Data Rate for CAN0 */ +#define FEATURE_CAN0_HAS_FD (1) +/* @brief Maximum number of Message Buffers supported for payload size 8 for CAN0 */ +#define FEATURE_CAN0_MAX_MB_NUM (32U) +/* @brief Has PE clock source select (bit field CAN_CTRL1[CLKSRC]). */ +#define FEATURE_CAN_HAS_PE_CLKSRC_SELECT (1) +/* @brief Has DMA enable (bit field MCR[DMA]). */ +#define FEATURE_CAN_HAS_DMA_ENABLE (1) +/* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */ +#define FEATURE_CAN_MAX_MB_NUM (32U) +/* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */ +#define FEATURE_CAN_MAX_MB_NUM_ARRAY { FEATURE_CAN0_MAX_MB_NUM } +/* @brief Has Pretending Networking mode */ +#define FEATURE_CAN_HAS_PRETENDED_NETWORKING (1) +/* @brief Has Stuff Bit Count Enable Bit */ +#define FEATURE_CAN_HAS_STFCNTEN_ENABLE (0) +/* @brief Has ISO CAN FD Enable Bit */ +#define FEATURE_CAN_HAS_ISOCANFDEN_ENABLE (1) +/* @brief Has Message Buffer Data Size Region 1 */ +#define FEATURE_CAN_HAS_MBDSR1 (0) +/* @brief Has Message Buffer Data Size Region 2 */ +#define FEATURE_CAN_HAS_MBDSR2 (0) +/* @brief DMA hardware requests for all FlexCAN instances */ +#define FEATURE_CAN_EDMA_REQUESTS { EDMA_REQ_FLEXCAN0 } + +/* @brief Maximum number of Message Buffers IRQs */ +#define FEATURE_CAN_MB_IRQS_MAX_COUNT (2U) +/* @brief Message Buffers IRQs */ +#define FEATURE_CAN_MB_IRQS { CAN_ORed_0_15_MB_IRQS, \ + CAN_ORed_16_31_MB_IRQS } +/* @brief Has Wake Up Irq channels (CAN_Wake_Up_IRQS_CH_COUNT > 0u) */ +#define FEATURE_CAN_HAS_WAKE_UP_IRQ (1) +/* @brief Has Self Wake Up mode */ +#define FEATURE_CAN_HAS_SELF_WAKE_UP (0) +/* @brief Has Flexible Data Rate */ +#define FEATURE_CAN_HAS_FD (1) +/* @brief Clock name for the PE oscillator clock source */ +#define FEATURE_CAN_PE_OSC_CLK_NAME SOSC_CLK +/* @bried FlexCAN has Detection And Correction of Memory Errors */ +#define FEATURE_CAN_HAS_MEM_ERR_DET (0) + +/* LPTMR module features */ + +/* @brief LPTMR pulse counter input options */ +#define FEATURE_LPTMR_HAS_INPUT_ALT1_SELECTION (1U) + +/* OSIF module features */ + +#define FEATURE_OSIF_USE_SYSTICK (1) +#define FEATURE_OSIF_USE_PIT (0) +#define FEATURE_OSIF_FREERTOS_ISR_CONTEXT_METHOD (1) /* Cortex M device */ + +/* PDB module features */ + +/* @brief PDB has back-to-back at instance level */ +#define FEATURE_PDB_HAS_INSTANCE_BACKTOBACK (0) + +#endif /* S32K118_FEATURES_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/devassert.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/devassert.h new file mode 100644 index 00000000..243c8d45 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/devassert.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DEVASSERT_H +#define DEVASSERT_H + +#include + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced. + * The macro is defined to be used by drivers to validate input parameters and can be disabled. + * + * @section [global] + * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro defined. + * The macros are used to validate input parameters to driver functions. + * + */ + +/** +\page Error_detection_and_reporting Error detection and reporting + +S32 SDK drivers can use a mechanism to validate data coming from upper software layers (application code) by performing +a number of checks on input parameters' range or other invariants that can be statically checked (not dependent on +runtime conditions). A failed validation is indicative of a software bug in application code, therefore it is important +to use this mechanism during development. + +The validation is performed by using DEV_ASSERT macro. +A default implementation of this macro is provided in this file. However, application developers can provide their own +implementation in a custom file. This requires defining the CUSTOM_DEVASSERT symbol with the specific file name in the +project configuration (for example: -DCUSTOM_DEVASSERT="custom_devassert.h") + +The default implementation accommodates two behaviors, based on DEV_ERROR_DETECT symbol: + - When DEV_ERROR_DETECT symbol is defined in the project configuration (for example: -DDEV_ERROR_DETECT), the validation + performed by the DEV_ASSERT macro is enabled, and a failed validation triggers a software breakpoint and further execution is + prevented (application spins in an infinite loop) + This configuration is recommended for development environments, as it prevents further execution and allows investigating + potential problems from the point of error detection. + - When DEV_ERROR_DETECT symbol is not defined, the DEV_ASSERT macro is implemented as no-op, therefore disabling all validations. + This configuration can be used to eliminate the overhead of development-time checks. + +It is the application developer's responsibility to decide the error detection strategy for production code: one can opt to +disable development-time checking altogether (by not defining DEV_ERROR_DETECT symbol), or one can opt to keep the checks +in place and implement a recovery mechanism in case of a failed validation, by defining CUSTOM_DEVASSERT to point +to the file containing the custom implementation. +*/ + +#if defined (CUSTOM_DEVASSERT) + /* If the CUSTOM_DEVASSERT symbol is defined, then add the custom implementation */ + #include CUSTOM_DEVASSERT +#elif defined (DEV_ERROR_DETECT) + /* Implement default assert macro */ +static inline void DevAssert(volatile bool x) +{ + if(x) { } else { BKPT_ASM; for(;;) {} } +} + #define DEV_ASSERT(x) DevAssert(x) +#else + /* Assert macro does nothing */ + #define DEV_ASSERT(x) ((void)0) +#endif + +#endif /* DEVASSERT_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/device_registers.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/device_registers.h new file mode 100644 index 00000000..583a35d5 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/device_registers.h @@ -0,0 +1,67 @@ +/* +** ################################################################### +** Abstract: +** Common include file for CMSIS register access layer headers. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** ################################################################### +*/ + +#ifndef DEVICE_REGISTERS_H +#define DEVICE_REGISTERS_H + +/** +* @page misra_violations MISRA-C:2012 violations +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced. +* The macro defines the device currently in use and may be used by components for specific checks. +* +*/ + + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ + +#if defined(CPU_S32K118) + + #define S32K11x_SERIES + + /* Specific core definitions */ + #include "s32_core_cm0.h" + /* Register definitions */ + #include "S32K118.h" + /* CPU specific feature definitions */ + #include "S32K118_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#include "devassert.h" + +#endif /* DEVICE_REGISTERS_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/s32_core_cm0.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/s32_core_cm0.h new file mode 100644 index 00000000..2dcd6e17 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/s32_core_cm0.h @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/*! + * @file s32_core_cm0.h + * + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro + * Function-like macros are used instead of inline functions in order to ensure + * that the performance will not be decreased if the functions will not be + * inlined by the compiler. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. + * The macros defined are used only on some of the drivers, so this might be reported + * when the analysis is made only on one driver. + */ + +/* + * Tool Chains: + * GNUC flag is defined also by ARM compiler - it shows the current major version of the compatible GCC version + * __GNUC__ : GNU Compiler Collection + * __ghs__ : Green Hills ARM Compiler + * __ICCARM__ : IAR ARM Compiler + * __DCC__ : Wind River Diab Compiler + * __ARMCC_VERSION : ARM Compiler + */ + +#if !defined (CORE_CM0_H) +#define CORE_CM0_H + + +#ifdef __cplusplus +extern "C" { +#endif + +/** \brief BKPT_ASM + * + * Macro to be used to trigger an debug interrupt + */ +#if defined ( __DCC__ ) +#define BKPT_ASM __asm ("BKPT 0\n\t") +#else +#define BKPT_ASM __asm ("BKPT #0\n\t") +#endif + +/** \brief Enable interrupts + */ +#if defined (__GNUC__) +#define ENABLE_INTERRUPTS() __asm volatile ("cpsie i" : : : "memory"); +#elif defined ( __DCC__ ) +#define ENABLE_INTERRUPTS() __asm (".short 0xb662"); +#else +#define ENABLE_INTERRUPTS() __asm("cpsie i") +#endif + + +/** \brief Disable interrupts + */ +#if defined (__GNUC__) +#define DISABLE_INTERRUPTS() __asm volatile ("cpsid i" : : : "memory"); +#elif defined ( __DCC__ ) +#define DISABLE_INTERRUPTS() __asm (".short 0xb672"); +#else +#define DISABLE_INTERRUPTS() __asm("cpsid i") +#endif + + +/** \brief Enter low-power standby state + * WFI (Wait For Interrupt) makes the processor suspend execution (Clock is stopped) until an IRQ interrupts. + */ +#if defined (__GNUC__) +#define STANDBY() __asm volatile ("wfi") +#elif defined ( __DCC__ ) +#define STANDBY() __asm (".short 0xbf30"); +#else +#define STANDBY() __asm ("wfi") +#endif + +/** \brief No-op + */ +#define NOP() __asm volatile ("nop") + + +/** \brief Reverse byte order in a word. + * ARM Documentation Cortex-M0 Devices Generic User Guide + * Accordingly to 3.5.7. REV, REV16, and REVSH + * Restriction "This function requires low registers R0-R7 register" + */ +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ARMCC_VERSION) +#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=l" (b) : "l" (a)) +#elif defined (__ghs__) +#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=r" (b) : "r" (a)) +#else +#define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \ + | ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U)) +#endif + +/** \brief Reverse byte order in each halfword independently. + * ARM Documentation Cortex-M0 Devices Generic User Guide + * Accordingly to 3.5.7. REV, REV16, and REVSH + * Restriction "This function requires low registers R0-R7 register" + */ +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ARMCC_VERSION) +#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=l" (b) : "l" (a)) +#elif defined (__ghs__) +#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=r" (b) : "r" (a)) +#else +#define REV_BYTES_16(a, b) (b = ((a & 0xFF000000U) >> 8U) | ((a & 0xFF0000U) << 8U) \ + | ((a & 0xFF00U) >> 8U) | ((a & 0xFFU) << 8U)) +#endif + +/** \brief Places a function in RAM. + */ +#if defined ( __GNUC__ ) || defined (__ARMCC_VERSION) + #define START_FUNCTION_DECLARATION_RAMSECTION + #define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram"))); +#elif defined ( __ghs__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("ghs callmode=far") + #define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));\ + _Pragma("ghs callmode=default") +#elif defined ( __ICCARM__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION __ramfunc + #define END_FUNCTION_DECLARATION_RAMSECTION ; +#elif defined ( __DCC__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("section CODE \".code_ram\" \"\" far-absolute") \ + _Pragma("use_section CODE") + #define END_FUNCTION_DECLARATION_RAMSECTION ; \ + _Pragma("section CODE \".text\"") +#else + /* Keep compatibility with software analysis tools */ + #define START_FUNCTION_DECLARATION_RAMSECTION + #define END_FUNCTION_DECLARATION_RAMSECTION ; +#endif + + /* For GCC, IAR, GHS, Diab and ARMC there is no need to specify the section when + defining a function, it is enough to specify it at the declaration. This + also enables compatibility with software analysis tools. */ + #define START_FUNCTION_DEFINITION_RAMSECTION + #define END_FUNCTION_DEFINITION_RAMSECTION + +#if defined (__ICCARM__) + #define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_suppress=Ta022") + #define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_default=Ta022") +#else + #define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL + #define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL +#endif + +/** \brief Get Core ID + * + * GET_CORE_ID returns the processor identification number for cm0 + */ +#define GET_CORE_ID() 0U + +/** \brief Data alignment. + */ +#if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION) + #define ALIGNED(x) __attribute__((aligned(x))) +#elif defined ( __ICCARM__ ) + #define stringify(s) tostring(s) + #define tostring(s) #s + #define ALIGNED(x) _Pragma(stringify(data_alignment=x)) +#else + /* Keep compatibility with software analysis tools */ + #define ALIGNED(x) +#endif + +/** \brief Endianness. + */ +#define CORE_LITTLE_ENDIAN + +#ifdef __cplusplus +} +#endif + +#endif /* CORE_CM0_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/startup.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/startup.c new file mode 100644 index 00000000..2d0efc61 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/startup.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * All variables with this problem are defined in the linker files. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.11, When an array with external linkage + * is declared, its size should be explicitly specified. + * The size of the arrays can not be explicitly determined. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed + * between a pointer to object and an integer type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed + * between pointer to void and an arithmetic type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 2.1, A project shall not contain unreachable + * code. + * The condition compares two address defined in linker files that can be different. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. + * Function is defined for usage by application code. + * + * @section [global] + * Violates MISRA 2012 Mandatory Rule 17.3, Symbol 'MFSPR' undeclared, assumed + * to return int. + * This is an e200 Power Architecture Assembly instruction used to retrieve + * the core number. + * + */ + +#include "startup.h" +#include + + +/******************************************************************************* + * Static Variables + ******************************************************************************/ +static volatile uint32_t * const s_vectors[NUMBER_OF_CORES] = FEATURE_INTERRUPT_INT_VECTORS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : init_data_bss + * Description : Make necessary initializations for RAM. + * - Copy the vector table from ROM to RAM. + * - Copy initialized data from ROM to RAM. + * - Copy code that should reside in RAM from ROM + * - Clear the zero-initialized data section. + * + * Tool Chains: + * __GNUC__ : GNU Compiler Collection + * __ghs__ : Green Hills ARM Compiler + * __ICCARM__ : IAR ARM Compiler + * __DCC__ : Wind River Diab Compiler + * __ARMCC_VERSION : ARMC Compiler + * + * Implements : init_data_bss_Activity + *END**************************************************************************/ +void init_data_bss(void) +{ + uint32_t n; + uint8_t coreId; +/* For ARMC we are using the library method of initializing DATA, Custom Section and + * Code RAM sections so the below variables are not needed */ +#if !defined(__ARMCC_VERSION) + /* Declare pointers for various data sections. These pointers + * are initialized using values pulled in from the linker file */ + uint8_t * data_ram; + uint8_t * code_ram; + uint8_t * bss_start; + uint8_t * custom_ram; + const uint8_t * data_rom, * data_rom_end; + const uint8_t * code_rom, * code_rom_end; + const uint8_t * bss_end; + const uint8_t * custom_rom, * custom_rom_end; +#endif + /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ + +#if defined(__ARMCC_VERSION) + extern uint32_t __RAM_VECTOR_TABLE_SIZE; + extern uint32_t __VECTOR_ROM; + extern uint32_t __VECTOR_RAM; +#else + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#endif + /* Get section information from linker files */ +#if defined(__ICCARM__) + /* Data */ + data_ram = __section_begin(".data"); + data_rom = __section_begin(".data_init"); + data_rom_end = __section_end(".data_init"); + + /* CODE RAM */ + #pragma section = "__CODE_ROM" + #pragma section = "__CODE_RAM" + code_ram = __section_begin("__CODE_RAM"); + code_rom = __section_begin("__CODE_ROM"); + code_rom_end = __section_end("__CODE_ROM"); + + /* BSS */ + bss_start = __section_begin(".bss"); + bss_end = __section_end(".bss"); + + custom_ram = __section_begin(".customSection"); + custom_rom = __section_begin(".customSection_init"); + custom_rom_end = __section_end(".customSection_init"); + +#elif defined (__ARMCC_VERSION) + /* VECTOR TABLE*/ + uint8_t * vector_table_size = (uint8_t *)__RAM_VECTOR_TABLE_SIZE; + uint32_t * vector_rom = (uint32_t *)__VECTOR_ROM; + uint32_t * vector_ram = (uint32_t *)__VECTOR_RAM; +#else + extern uint32_t __DATA_ROM[]; + extern uint32_t __DATA_RAM[]; + extern uint32_t __DATA_END[]; + + extern uint32_t __CODE_RAM[]; + extern uint32_t __CODE_ROM[]; + extern uint32_t __CODE_END[]; + + extern uint32_t __BSS_START[]; + extern uint32_t __BSS_END[]; + + extern uint32_t __CUSTOM_ROM[]; + extern uint32_t __CUSTOM_END[]; + + /* Data */ + data_ram = (uint8_t *)__DATA_RAM; + data_rom = (uint8_t *)__DATA_ROM; + data_rom_end = (uint8_t *)__DATA_END; + /* CODE RAM */ + code_ram = (uint8_t *)__CODE_RAM; + code_rom = (uint8_t *)__CODE_ROM; + code_rom_end = (uint8_t *)__CODE_END; + /* BSS */ + bss_start = (uint8_t *)__BSS_START; + bss_end = (uint8_t *)__BSS_END; + + /* Custom section */ + custom_ram = CUSTOMSECTION_SECTION_START; + custom_rom = (uint8_t *)__CUSTOM_ROM; + custom_rom_end = (uint8_t *)__CUSTOM_END; + +#endif + +#if !defined(__ARMCC_VERSION) + /* Copy initialized data from ROM to RAM */ + while (data_rom_end != data_rom) + { + *data_ram = *data_rom; + data_ram++; + data_rom++; + } + + /* Copy functions from ROM to RAM */ + while (code_rom_end != code_rom) + { + *code_ram = *code_rom; + code_ram++; + code_rom++; + } + + /* Clear the zero-initialized data section */ + while(bss_end != bss_start) + { + *bss_start = 0; + bss_start++; + } + + /* Copy customsection rom to ram */ + while(custom_rom_end != custom_rom) + { + *custom_ram = *custom_rom; + custom_rom++; + custom_ram++; + } +#endif + coreId = (uint8_t)GET_CORE_ID(); +#if defined (__ARMCC_VERSION) + /* Copy the vector table from ROM to RAM */ + /* Workaround */ + for (n = 0; n < (((uint32_t)(vector_table_size))/sizeof(uint32_t)); n++) + { + vector_ram[n] = vector_rom[n]; + } + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t) __VECTOR_RAM; +#else + /* Check if VECTOR_TABLE copy is needed */ + if (__VECTOR_RAM != __VECTOR_TABLE) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < (((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t)); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t)__VECTOR_RAM; + } + else + { + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t)__VECTOR_TABLE; + } +#endif + +} + +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/startup.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/startup.h new file mode 100644 index 00000000..8384b7db --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/startup.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef STARTUP_H +#define STARTUP_H + +#include +#include "device_registers.h" +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, Local macro not referenced. + * The defined macro is used as include guard. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * All variables with this problem are defined in the linker files. + * + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief define symbols that specific start and end addres of some basic sections. + */ +#if (defined(S32K14x_SERIES) || defined(S32K11x_SERIES) || defined(S32V234_SERIES) || defined(MPC574x_SERIES) || defined(S32R_SERIES) || defined(S32MTV_SERIES) || defined(SJA1110_SERIES)) || defined (S32K144W_M4_SERIES) + #if (defined(__ICCARM__)) + #define INTERRUPTS_SECTION_START __section_begin(".intvec") + #define INTERRUPTS_SECTION_END __section_end(".intvec") + #define BSS_SECTION_START __section_begin(".bss") + #define BSS_SECTION_END __section_end(".bss") + #define DATA_SECTION_START __section_begin(".data") + #define DATA_SECTION_END __section_end(".data") + #define CUSTOMSECTION_SECTION_START __section_begin(".customSection") + #define CUSTOMSECTION_SECTION_END __section_end(".customSection") + #define CODE_RAM_SECTION_START __section_begin("__CODE_RAM") + #define CODE_RAM_SECTION_END __section_end("__CODE_RAM") + #define DATA_INIT_SECTION_START __section_begin(".data_init") + #define DATA_INIT_SECTION_END __section_end(".data_init") + #define CODE_ROM_SECTION_START __section_begin("__CODE_ROM") + #define CODE_ROM_SECTION_END __section_end("__CODE_ROM") + + #elif (defined(__ARMCC_VERSION)) + #define INTERRUPTS_SECTION_START (uint8_t *)__VECTOR_ROM_START + #define INTERRUPTS_SECTION_END (uint8_t *)__VECTOR_ROM_END + #define BSS_SECTION_START (uint8_t *)__BSS_START + #define BSS_SECTION_END (uint8_t *)__BSS_END + #define DATA_SECTION_START (uint8_t *)__DATA_RAM_START + #define DATA_SECTION_END (uint8_t *)__DATA_RAM_END + #define CUSTOMSECTION_SECTION_START (uint8_t *)__CUSTOM_SECTION_START + #define CUSTOMSECTION_SECTION_END (uint8_t *)__CUSTOM_SECTION_END + #define CODE_RAM_SECTION_START (uint8_t *)__CODE_RAM_START + #define CODE_RAM_SECTION_END (uint8_t *)__CODE_RAM_END + + extern uint32_t __VECTOR_ROM_START; + extern uint32_t __VECTOR_ROM_END; + extern uint32_t __BSS_START; + extern uint32_t __BSS_END; + extern uint32_t __DATA_RAM_START; + extern uint32_t __DATA_RAM_END; + extern uint32_t __CUSTOM_SECTION_START; + extern uint32_t __CUSTOM_SECTION_END; + extern uint32_t __CODE_RAM_START; + extern uint32_t __CODE_RAM_END; + #else + #define INTERRUPTS_SECTION_START (uint8_t *)&__interrupts_start__ + #define INTERRUPTS_SECTION_END (uint8_t *)&__interrupts_end__ + #define BSS_SECTION_START (uint8_t *)&__bss_start__ + #define BSS_SECTION_END (uint8_t *)&__bss_end__ + #define DATA_SECTION_START (uint8_t *)&__data_start__ + #define DATA_SECTION_END (uint8_t *)&__data_end__ + #define CUSTOMSECTION_SECTION_START (uint8_t *)&__customSection_start__ + #define CUSTOMSECTION_SECTION_END (uint8_t *)&__customSection_end__ + #define CODE_RAM_SECTION_START (uint8_t *)&__code_ram_start__ + #define CODE_RAM_SECTION_END (uint8_t *)&__code_ram_end__ + + extern uint32_t __interrupts_start__; + extern uint32_t __interrupts_end__; + extern uint32_t __bss_start__; + extern uint32_t __bss_end__; + extern uint32_t __data_start__; + extern uint32_t __data_end__; + extern uint32_t __customSection_start__; + extern uint32_t __customSection_end__; + extern uint32_t __code_ram_start__; + extern uint32_t __code_ram_end__; + #endif +#endif + +#if (defined(__ICCARM__)) + #pragma section = ".data" + #pragma section = ".data_init" + #pragma section = ".bss" + #pragma section = ".intvec" + #pragma section = ".customSection" + #pragma section = ".customSection_init" + #pragma section = "__CODE_RAM" + #pragma section = "__CODE_ROM" +#endif + +/*! + * @brief Make necessary initializations for RAM. + * + * - Copy initialized data from ROM to RAM. + * - Clear the zero-initialized data section. + * - Copy the vector table from ROM to RAM. This could be an option. + */ +void init_data_bss(void); + +#endif /* STARTUP_H*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/system_S32K118.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/system_S32K118.c new file mode 100644 index 00000000..868b365b --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/system_S32K118.c @@ -0,0 +1,176 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * An object with static storage duration declared at block scope cannot be + * accessed directly from outside the block. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed + * between a pointer to object and an integer type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed + * between pointer to void and an arithmetic type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. + * Function is defined for usage by application code. + * + */ + +#include "device_registers.h" +#include "system_S32K118.h" +#include "stdbool.h" + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/*FUNCTION********************************************************************** + * + * Function Name : SystemInit + * Description : This function disables the watchdog, enables FPU + * and the power mode protection if the corresponding feature macro + * is enabled. SystemInit is called from startup_device file. + * + * Implements : SystemInit_Activity + *END**************************************************************************/ +void SystemInit(void) +{ +/**************************************************************************/ +/* WDOG DISABLE*/ +/**************************************************************************/ + +#if (DISABLE_WDOG) + /* Write of the WDOG unlock key to CNT register, must be done in order to allow any modifications*/ + WDOG->CNT = (uint32_t ) FEATURE_WDOG_UNLOCK_VALUE; + /* The dummy read is used in order to make sure that the WDOG registers will be configured only + * after the write of the unlock value was completed. */ + (void)WDOG->CNT; + + /* Initial write of WDOG configuration register: + * enables support for 32-bit refresh/unlock command write words, + * clock select from LPO, update enable, watchdog disabled */ + WDOG->CS = (uint32_t ) ( (1UL << WDOG_CS_CMD32EN_SHIFT) | + (FEATURE_WDOG_CLK_FROM_LPO << WDOG_CS_CLK_SHIFT) | + (0U << WDOG_CS_EN_SHIFT) | + (1U << WDOG_CS_UPDATE_SHIFT) ); + + /* Configure timeout */ + WDOG->TOVAL = (uint32_t )0xFFFF; +#endif /* (DISABLE_WDOG) */ +} + +/*FUNCTION********************************************************************** + * + * Function Name : SystemCoreClockUpdate + * Description : This function must be called whenever the core clock is changed + * during program execution. It evaluates the clock register settings and calculates + * the current core clock. + * + * Implements : SystemCoreClockUpdate_Activity + *END**************************************************************************/ +void SystemCoreClockUpdate(void) +{ + uint32_t SCGOUTClock = 0U; /* Variable to store output clock frequency of the SCG module */ + uint32_t regValue; /* Temporary variable */ + uint32_t divider; + bool validSystemClockSource = true; + + divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U; + + switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) + { + case 0x1: + /* System OSC */ + SCGOUTClock = CPU_XTAL_CLK_HZ; + break; + case 0x2: + /* Slow IRC */ + regValue = (SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT; + if (regValue != 0UL) + { + SCGOUTClock = FEATURE_SCG_SIRC_HIGH_RANGE_FREQ; + } + else + { + validSystemClockSource = false; + } + break; + case 0x3: + /* Fast IRC */ + regValue = (SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT; + if (regValue == 0x0UL) + { + SCGOUTClock = FEATURE_SCG_FIRC_FREQ0; + } + else + { + validSystemClockSource = false; + } + break; + default: + validSystemClockSource = false; + break; + } + + if (validSystemClockSource == true) + { + SystemCoreClock = (SCGOUTClock / divider); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : SystemSoftwareReset + * Description : This function is used to initiate a system reset + * + * Implements : SystemSoftwareReset_Activity + *END**************************************************************************/ +void SystemSoftwareReset(void) +{ + uint32_t regValue; + + /* Read Application Interrupt and Reset Control Register */ + regValue = S32_SCB->AIRCR; + + /* Clear register key */ + regValue &= ~( S32_SCB_AIRCR_VECTKEY_MASK); + + /* Configure System reset request bit and Register Key */ + regValue |= S32_SCB_AIRCR_VECTKEY(FEATURE_SCB_VECTKEY); + regValue |= S32_SCB_AIRCR_SYSRESETREQ(0x1u); + + /* Write computed register value */ + S32_SCB->AIRCR = regValue; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/system_S32K118.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/system_S32K118.h new file mode 100644 index 00000000..6e98f97f --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/system_S32K118.h @@ -0,0 +1,105 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*! @addtogroup soc_support_S32K118*/ +/*! @{*/ + +/*! + * @file system_S32K118.h + * @brief Device specific configuration file for S32K118 + */ + +#ifndef SYSTEM_S32K118_H_ +#define SYSTEM_S32K118_H_ /**< Symbol preventing repeated inclusion */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** + * CPU Settings. + *****************************************************************************/ + +/* Watchdog disable */ +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +/* Value of the external crystal or oscillator clock frequency in Hz */ +#ifndef CPU_XTAL_CLK_HZ + #define CPU_XTAL_CLK_HZ 8000000u +#endif + +/* Value of the fast internal oscillator clock frequency in Hz */ +#ifndef CPU_INT_FAST_CLK_HZ + #define CPU_INT_FAST_CLK_HZ 48000000u +#endif + +/* Default System clock value */ +#ifndef DEFAULT_SYSTEM_CLOCK + #define DEFAULT_SYSTEM_CLOCK 48000000u +#endif + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the SoC. + * + * This function disables the watchdog. + * if the corresponding feature macro is enabled. + * SystemInit is called from startup_device file. + */ +void SystemInit(void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + * This function must be called when user does not want to use clock manager component. + * If clock manager is used, the CLOCK_SYS_GetFreq function must be used with CORE_CLOCK + * parameter. + * + */ +void SystemCoreClockUpdate(void); + +/** + * @brief Initiates a system reset. + * + * This function is used to initiate a system reset + */ +void SystemSoftwareReset(void); + +#ifdef __cplusplus +} +#endif + +/*! @}*/ +#endif /* #if !defined(SYSTEM_S32K118_H_) */ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/main.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/main.c new file mode 100644 index 00000000..a2a5cb42 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/main.c @@ -0,0 +1,186 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/main.c +* \brief Bootloader application source file. +* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "device_registers.h" /* device registers */ +#include "system_S32K118.h" /* device sconfiguration */ + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static void Init(void); +static void SystemClockConfig(void); + + +/************************************************************************************//** +** \brief This is the entry point for the bootloader application and is called +** by the reset interrupt vector after the C-startup routines executed. +** \return none. +** +****************************************************************************************/ +void main(void) +{ + /* Initialize the microcontroller. */ + Init(); + /* Initialize the bootloader. */ + BootInit(); + + /* Start the infinite program loop. */ + while (1) + { + /* Run the bootloader task. */ + BootTask(); + } +} /*** end of main ***/ + + +/************************************************************************************//** +** \brief Initializes the microcontroller. +** \return none. +** +****************************************************************************************/ +static void Init(void) +{ + /* Configure the system clock. */ + SystemClockConfig(); + /* Enable the peripheral clock for the ports that are used. */ + PCC->PCCn[PCC_PORTB_INDEX] |= PCC_PCCn_CGC_MASK; + PCC->PCCn[PCC_PORTD_INDEX] |= PCC_PCCn_CGC_MASK; + PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK; + + /* Configure SW2 (PD3) GPIO pin for (optional) backdoor entry input. */ + /* Input GPIO pin configuration. PD3 = GPIO, MUX = ALT1. */ + PORTD->PCR[3] |= PORT_PCR_MUX(1); + /* Disable pull device, as SW2 already has a pull down resistor on the board. */ + PORTD->PCR[3] &= ~PORT_PCR_PE(1); + /* Configure and enable Port D pin 3 GPIO as digital input */ + PTD->PDDR &= ~GPIO_PDDR_PDD(1 << 3U); + PTD->PIDR &= ~GPIO_PIDR_PID(1 << 3U); +#if (BOOT_COM_RS232_ENABLE > 0) + /* UART RX GPIO pin configuration. PB0 = UART0 RX, MUX = ALT2. */ + PORTB->PCR[0] |= PORT_PCR_MUX(2); + /* UART TX GPIO pin configuration. PB1 = UART0 TX, MUX = ALT2. */ + PORTB->PCR[1] |= PORT_PCR_MUX(2); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) + /* CAN RX GPIO pin configuration. PE4 = CAN0 RX, MUX = ALT5. */ + PORTE->PCR[4] |= PORT_PCR_MUX(5); + /* CAN TX GPIO pin configuration. PE5 = CAN0 TX, MUX = ALT5. */ + PORTE->PCR[5] |= PORT_PCR_MUX(5); +#endif +} /*** end of Init ***/ + + +/************************************************************************************//** +** \brief System Clock Configuration. This code was derived from a S32 Design Studio +** example program. It enables the SOCS (40 MHz external crystal), FIRC (48 +** MHz internal) and SIRC (8 MHz internal). The FIRC is used as a source for +** the system clock and configures the normal RUN mode for the following clock +** settings: +** - CORE_CLK = 48 MHz +** - SYS_CLK = 48 MHz +** - BUS_CLK = 48 MHz +** - FLASH_CLK = 24 MHz +** - SOSCDIV1_CLK = 40 MHz +** - SOSCDIV2_CLK = 40 MHz +** - FIRCDIV1_CLK = 48 MHz +** - FIRCDIV2_CLK = 48 MHz +** - SIRCDIV1_CLK = 8 MHz +** - SIRCDIV2_CLK = 8 MHz +** \return none. +** +****************************************************************************************/ +static void SystemClockConfig(void) +{ + /* --------- SOSC Initialization (40 MHz) ------------------------------------------ */ + /* SOSCDIV1 & SOSCDIV2 =1: divide by 1. */ + SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1) | SCG_SOSCDIV_SOSCDIV2(1); + /* Range=3: High freq (SOSC betw 8MHz - 40MHz). + * HGO=0: Config xtal osc for low power. + * EREFS=1: Input is external XTAL. + */ + SCG->SOSCCFG = SCG_SOSCCFG_RANGE(3) | SCG_SOSCCFG_EREFS_MASK; + /* Ensure SOSCCSR unlocked. */ + while (SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK) + { + ; + } + + /* LK=0: SOSCCSR can be written. + * SOSCCMRE=0: OSC CLK monitor IRQ if enabled. + * SOSCCM=0: OSC CLK monitor disabled. + * SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled. + * SOSCLPEN=0: Sys OSC disabled in VLP modes. + * SOSCSTEN=0: Sys OSC disabled in Stop modes. + * SOSCEN=1: Enable oscillator. + */ + SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK; + /* Wait for system OSC clock to become valid. */ + while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK)) + { + ; + } + + /* --------- FIRC Initialization --------------------------------------------------- */ + /* Fast IRC is enabled and trimmed to 48 MHz in reset (default). Enable FIRCDIV2_CLK + * and FIRCDIV1_CLK, divide by 1 = 48 MHz. + */ + SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV1(1) | SCG_FIRCDIV_FIRCDIV2(1); + + /* --------- SIRC Initialization --------------------------------------------------- */ + /* Slow IRC is enabled with high range (8 MHz) in reset. Enable SIRCDIV2_CLK and + * SIRCDIV1_CLK, divide by 1 = 8MHz asynchronous clock source. + */ + SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1) | SCG_SIRCDIV_SIRCDIV2(1); + + /* --------- Change to normal RUN mode with 48MHz FIRC ----------------------------- */ + /* Select FIRC as clock source. + * DIVCORE=0, div. by 1: Core clock = 48 MHz. + * DIVBUS=0, div. by 1: bus clock = 48 MHz. + * DIVSLOW=1, div. by 2: SCG slow, flash clock= 24 MHz + */ + SCG->RCCR = SCG_RCCR_SCS(3) | SCG_RCCR_DIVCORE(0) | SCG_RCCR_DIVBUS(0) | + SCG_RCCR_DIVSLOW(1); + + /* Wait until system clock source is FIRC. */ + while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 3U) + { + ; + } + /* Evaluate the clock register settings and calculates the current core clock. This + * function must be called when the clock manager component is not used. + */ + SystemCoreClockUpdate(); +} /*** end of SystemClockConfig ***/ + + +/*********************************** end of main.c *************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/startup_S32K118.s b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/startup_S32K118.s new file mode 100644 index 00000000..68f775b7 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/startup_S32K118.s @@ -0,0 +1,287 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_S32K118.s +; @purpose: IAR Startup File +; S32K118 +; @version: 1.0 +; @date: 2018-1-22 +; @build: b170107 +; --------------------------------------------------------------------------------------- +; +; Copyright 2018 NXP +; All rights reserved. +; +; THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +; OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +; IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +; INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +; STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +; IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:ROOT(2) + + EXTERN main + EXTERN SystemInit + EXTERN init_data_bss + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; Non Maskable Interrupt + DCD HardFault_Handler ; Cortex-M0 SV Hard Fault Interrupt + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler ; Cortex-M0 SV Call Interrupt + DCD 0 + DCD 0 + DCD PendSV_Handler ; Cortex-M0 Pend SV Interrupt + DCD SysTick_Handler ; Cortex-M0 System Tick Interrupt + + + DCD DMA0_IRQHandler ; DMA channel 0 transfer complete + DCD DMA1_IRQHandler ; DMA channel 1 transfer complete + DCD DMA2_IRQHandler ; DMA channel 2 transfer complete + DCD DMA3_IRQHandler ; DMA channel 3 transfer complete + DCD DMA_Error_IRQHandler ; DMA error interrupt channels 0-3 + DCD ERM_fault_IRQHandler ; ERM single and double bit error correction + DCD RTC_IRQHandler ; RTC alarm interrupt + DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt + DCD LPTMR0_IRQHandler ; LPTIMER interrupt request + DCD PORT_IRQHandler ; Port A, B, C, D and E pin detect interrupt + DCD CAN0_ORed_Err_Wakeup_IRQHandler ; OR’ed [Bus Off OR Bus Off Done OR Transmit Warning OR Receive Warning], Interrupt indicating that errors were detected on the CAN bus, Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode + DCD CAN0_ORed_0_31_MB_IRQHandler ; OR’ed Message buffer (0-15, 16-31) + DCD FTM0_Ch0_7_IRQHandler ; FTM0 Channel 0 to 7 interrupt + DCD FTM0_Fault_IRQHandler ; FTM0 Fault interrupt + DCD FTM0_Ovf_Reload_IRQHandler ; FTM0 Counter overflow and Reload interrupt + DCD FTM1_Ch0_7_IRQHandler ; FTM1 Channel 0 to 7 interrupt + DCD FTM1_Fault_IRQHandler ; FTM1 Fault interrupt + DCD FTM1_Ovf_Reload_IRQHandler ; FTM1 Counter overflow and Reload interrupt + DCD FTFC_IRQHandler ; FTFC Command complete, Read collision and Double bit fault detect + DCD PDB0_IRQHandler ; PDB0 interrupt + DCD LPIT0_IRQHandler ; LPIT interrupt + DCD SCG_CMU_LVD_LVWSCG_IRQHandler ; PMC Low voltage detect interrupt, SCG bus interrupt request and CMU loss of range interrupt + DCD WDOG_IRQHandler ; WDOG interrupt request out before wdg reset out + DCD RCM_IRQHandler ; RCM Asynchronous Interrupt + DCD LPI2C0_Master_Slave_IRQHandler ; LPI2C0 Master Interrupt and Slave Interrupt + DCD FLEXIO_IRQHandler ; FlexIO Interrupt + DCD LPSPI0_IRQHandler ; LPSPI0 Interrupt + DCD LPSPI1_IRQHandler ; LPSPI1 Interrupt + DCD ADC0_IRQHandler ; ADC0 interrupt request. + DCD CMP0_IRQHandler ; CMP0 interrupt request + DCD LPUART1_RxTx_IRQHandler ; LPUART1 Transmit / Receive Interrupt + DCD LPUART0_RxTx_IRQHandler ; LPUART0 Transmit / Receive Interrupt +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF ; 8 bytes backdoor comparison key + DCD 0xFFFFFFFF ; + DCD 0xFFFFFFFF ; 4 bytes program flash protection bytes + DCD 0xFFFF7FFE ; FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured) +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + ;; Init the rest of the registers + LDR R1,=0 + LDR R2,=0 + LDR R3,=0 + LDR R4,=0 + LDR R5,=0 + LDR R6,=0 + LDR R7,=0 + MOV R8,R7 + MOV R9,R7 + MOV R10,R7 + MOV R11,R7 + MOV R12,R7 + +#ifdef START_FROM_FLASH + IMPORT __RAM_START, __RAM_END + ;; INIT ECC RAM + + LDR R1, =__RAM_START + LDR R2, =__RAM_END + + SUBS R2, R2, R1 + SUBS R2, #1 + BLE .LC5 + + MOVS R0, #0 + MOVS R3, #4 + .LC4: + STR R0, [R1] + ADD R1, R1, R3 + SUBS R2, #4 + BGE .LC4 + .LC5: +#endif + ;; Initialize the stack pointer + LDR R0, =sfe(CSTACK) + MOV R13,R0 + +#ifndef __NO_SYSTEM_INIT + ;; Call the CMSIS system init routine + LDR R0, =SystemInit + BLX R0 +#endif + + ;; Init .data and .bss sections + LDR R0, =init_data_bss + BLX R0 + CPSIE I ; Unmask interrupts + + BL main +JumpToSelf + B JumpToSelf + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA3_IRQHandler + PUBWEAK DMA_Error_IRQHandler + PUBWEAK ERM_fault_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK PORT_IRQHandler + PUBWEAK CAN0_ORed_Err_Wakeup_IRQHandler + PUBWEAK CAN0_ORed_0_31_MB_IRQHandler + PUBWEAK FTM0_Ch0_7_IRQHandler + PUBWEAK FTM0_Fault_IRQHandler + PUBWEAK FTM0_Ovf_Reload_IRQHandler + PUBWEAK FTM1_Ch0_7_IRQHandler + PUBWEAK FTM1_Fault_IRQHandler + PUBWEAK FTM1_Ovf_Reload_IRQHandler + PUBWEAK FTFC_IRQHandler + PUBWEAK PDB0_IRQHandler + PUBWEAK LPIT0_IRQHandler + PUBWEAK SCG_CMU_LVD_LVWSCG_IRQHandler + PUBWEAK WDOG_IRQHandler + PUBWEAK RCM_IRQHandler + PUBWEAK LPI2C0_Master_Slave_IRQHandler + PUBWEAK FLEXIO_IRQHandler + PUBWEAK LPSPI0_IRQHandler + PUBWEAK LPSPI1_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK LPUART1_RxTx_IRQHandler + PUBWEAK LPUART0_RxTx_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler +HardFault_Handler +SVC_Handler +PendSV_Handler +SysTick_Handler +DMA0_IRQHandler +DMA1_IRQHandler +DMA2_IRQHandler +DMA3_IRQHandler +DMA_Error_IRQHandler +ERM_fault_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +LPTMR0_IRQHandler +PORT_IRQHandler +CAN0_ORed_Err_Wakeup_IRQHandler +CAN0_ORed_0_31_MB_IRQHandler +FTM0_Ch0_7_IRQHandler +FTM0_Fault_IRQHandler +FTM0_Ovf_Reload_IRQHandler +FTM1_Ch0_7_IRQHandler +FTM1_Fault_IRQHandler +FTM1_Ovf_Reload_IRQHandler +FTFC_IRQHandler +PDB0_IRQHandler +LPIT0_IRQHandler +SCG_CMU_LVD_LVWSCG_IRQHandler +WDOG_IRQHandler +RCM_IRQHandler +LPI2C0_Master_Slave_IRQHandler +FLEXIO_IRQHandler +LPSPI0_IRQHandler +LPSPI1_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +LPUART1_RxTx_IRQHandler +LPUART0_RxTx_IRQHandler +DefaultISR + B DefaultISR + + END diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/S32K118_25_flash.icf b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/S32K118_25_flash.icf new file mode 100644 index 00000000..611257c3 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/S32K118_25_flash.icf @@ -0,0 +1,125 @@ +/* +** ################################################################### +** Processor: S32K118 with 25 KB SRAM +** Compiler: IAR ANSI C/C++ Compiler for ARM +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2018 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +/* If symbol __flash_vector_table__=1 is defined at link time + * the interrupt vector will not be copied to RAM. + * Warning: Using the interrupt vector from FLASH will not allow + * INT_SYS_InstallHandler because the section is Read Only. + */ +define symbol __ram_vector_table_size__ = isdefinedsymbol(__flash_vector_table__) ? 0 : 0x000000C0; +define symbol __ram_vector_table_offset__ = isdefinedsymbol(__flash_vector_table__) ? 0 : 0x000000BF; + +/* Flash */ +define symbol m_interrupts_start = 0x00002000; +define symbol m_interrupts_end = 0x000020C3; + +define symbol m_flash_config_start = 0x00002400; +define symbol m_flash_config_end = 0x0000240F; + +define symbol m_text_start = 0x00002410; +define symbol m_text_end = 0x0003FFFF; + +/* SRAM_L */ +define symbol m_custom_start = 0x1FFFFC00; +define symbol m_custom_end = 0x1FFFFFFF; + +/* SRAM_U */ +define symbol m_interrupts_ram_start = 0x20000000; +define symbol m_interrupts_ram_end = 0x20000000 + __ram_vector_table_offset__; + +define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__; +define symbol m_data_end = 0x200030BF; + +define symbol m_data_2_start = 0x200030C0; +define symbol m_data_2_end = 0x200057FF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x00000200; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x00000200; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = isdefinedsymbol(__flash_vector_table__) ? m_interrupts_start : m_interrupts_ram_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__; + +define exported symbol __RAM_START = m_interrupts_ram_start; +define exported symbol __RAM_END = m_data_2_end; + +define memory mem with size = 4G; +define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end]; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA_region_2 = mem:[from m_data_2_start to m_data_2_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end]; +define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; +define region CUSTOM_region = mem:[from m_custom_start to m_custom_end]; + + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +/* Custom Section Block that can be used to place data at absolute address. */ +/* Use __attribute__((section (".customSection"))) to place data here. */ +/* Use this section only when MTB (Micro Trace Buffer) is not used, because MTB uses the same RAM area, as described in S32K Reference Manual. */ +define block customSectionBlock { section .customSection }; + +define block __CODE_ROM { section .textrw_init }; +define block __CODE_RAM { section .textrw }; + +initialize manually { section .textrw }; +initialize manually { section .bss }; +initialize manually { section .customSection }; +initialize manually { section .data }; +initialize manually { section __DLIB_PERTHREAD }; +do not initialize { section .noinit, section .bss, section .data, section __DLIB_PERTHREAD, section .customSection }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in m_flash_config_region { section FlashConfig }; +place in TEXT_region { readonly }; +place in TEXT_region { block __CODE_ROM }; +place in DATA_region { block RW }; +place in DATA_region { block __CODE_RAM }; +place in CUSTOM_region { first block customSectionBlock }; +place in DATA_region_2 { block ZI }; +place in DATA_region_2 { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in m_interrupts_ram_region { section m_interrupts_ram }; + + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/bin/demoprog_s32k118.out b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/bin/demoprog_s32k118.out new file mode 100644 index 00000000..451e2f91 Binary files /dev/null and b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/bin/demoprog_s32k118.out differ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/bin/demoprog_s32k118.srec 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+S10F2F300810204008ED00E0006CDC02FA +S9032F19B4 diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/boot.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/boot.c new file mode 100644 index 00000000..65095b5b --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/boot.c @@ -0,0 +1,772 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/boot.c +* \brief Demo program bootloader interface source file. +* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +#if (BOOT_COM_RS232_ENABLE > 0) +static void BootComRs232Init(void); +static void BootComRs232CheckActivationRequest(void); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) +static void BootComCanInit(void); +static void BootComCanCheckActivationRequest(void); +#endif + + +/************************************************************************************//** +** \brief Initializes the communication interface. +** \return none. +** +****************************************************************************************/ +void BootComInit(void) +{ +#if (BOOT_COM_RS232_ENABLE > 0) + BootComRs232Init(); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) + BootComCanInit(); +#endif +} /*** end of BootComInit ***/ + + +/************************************************************************************//** +** \brief Receives the CONNECT request from the host, which indicates that the +** bootloader should be activated and, if so, activates it. +** \return none. +** +****************************************************************************************/ +void BootComCheckActivationRequest(void) +{ +#if (BOOT_COM_RS232_ENABLE > 0) + BootComRs232CheckActivationRequest(); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) + BootComCanCheckActivationRequest(); +#endif +} /*** end of BootComCheckActivationRequest ***/ + + +/************************************************************************************//** +** \brief Bootloader activation function. +** \return none. +** +****************************************************************************************/ +void BootActivate(void) +{ + /* Activate the bootloader by performing a software reset. */ + SystemSoftwareReset(); +} /*** end of BootActivate ***/ + + +#if (BOOT_COM_RS232_ENABLE > 0) +/**************************************************************************************** +* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E +****************************************************************************************/ + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Timeout time for the reception of a CTO packet. The timer is started upon + * reception of the first packet byte. + */ +#define RS232_CTO_RX_PACKET_TIMEOUT_MS (100u) +/** \brief Set the peripheral LPUART base pointer. */ +#define LPUARTx (LPUART0) +/** \brief Set the PCC index offset for LPUART. */ +#define PCC_LPUARTx_INDEX (PCC_LPUART0_INDEX) + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static unsigned char Rs232ReceiveByte(unsigned char *data); + + +/************************************************************************************//** +** \brief Initializes the UART communication interface. +** \return none. +** +****************************************************************************************/ +static void BootComRs232Init(void) +{ + unsigned long sourceClockFreqHz; + unsigned long div2RegValue; + unsigned short baudrateSbr0_12; + unsigned char const div2DividerLookup[] = + { + 0U, /* 0b000. Output disabled. */ + 1U, /* 0b001. Divide by 1. */ + 2U, /* 0b010. Divide by 2. */ + 4U, /* 0b011. Divide by 4. */ + 8U, /* 0b100. Divide by 8. */ + 16U, /* 0b101. Divide by 16. */ + 32U, /* 0b110. Divide by 32. */ + 64U, /* 0b111. Divide by 64. */ + }; + + /* Make sure the UART peripheral clock is disabled before configuring its source + * clock. + */ + PCC->PCCn[PCC_LPUARTx_INDEX] &= ~PCC_PCCn_CGC_MASK; + /* Select option 2 as the UART peripheral source clock and enable the clock. Option 2 + * is the SIRCDIV2_CLK, which is available on all peripherals and configurations. + */ + PCC->PCCn[PCC_LPUARTx_INDEX] |= PCC_PCCn_PCS(2) | PCC_PCCn_CGC_MASK; + /* Obtain the DIV2 divider value of the SIRC_CLK. */ + div2RegValue = (SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT; + /* Check if the DIV2 register value for SIRC is 0. In this case SIRCDIV2_CLK is + * currently disabled. + */ + if (div2RegValue == 0U) + { + /* Configure the DIV2 for a default divide by 1 to make sure the SIRCDIV2_CLK is + * actually enabled. + */ + div2RegValue = 1U; + SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV2(div2RegValue); + } + /* Determine the SIRC clock frequency. If SIRC high range is enabled, it is 8 MHz. If + * SIRC low range is enabled, it is 2 MHz. + */ + sourceClockFreqHz = 8000000U; + if ((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) == SCG_SIRCCFG_RANGE(0)) + { + sourceClockFreqHz = 2000000U; + } + /* Now process the configured DIV2 divider factor to get the actual frequency of the + * UART peripheral source clock. + */ + sourceClockFreqHz /= div2DividerLookup[div2RegValue]; + /* Configure the baudrate from BOOT_COM_RS232_BAUDRATE, taking into account that an + * oversampling of 8 will be configured. Default 8,n,1 format is used. Integer + * rounding is used to get the best value for baudrateSbr0_12. Actual baudrate equals + * sourceClockFreqHz / 8 / baudrateSbr0_12. + */ + baudrateSbr0_12 = (((sourceClockFreqHz / BOOT_COM_RS232_BAUDRATE) + (8U - 1U)) / 8U) & + LPUART_BAUD_SBR_MASK; + /* OSR=7: Over sampling ratio = 7+1=8. + * SBNS=0: One stop bit. + * BOTHEDGE=0: receiver samples only on rising edge. + * M10=0: Rx and Tx use 7 to 9 bit data characters. + * RESYNCDIS=0: Resync during rec'd data word supported. + * LBKDIE, RXEDGIE=0: interrupts disable. + * TDMAE, RDMAE, TDMAE=0: DMA requests disabled. + * MAEN1, MAEN2, MATCFG=0: Match disabled. + */ + LPUARTx->BAUD = LPUART_BAUD_SBR(baudrateSbr0_12) | LPUART_BAUD_OSR(7); + /* Clear the error/interrupt flags */ + LPUARTx->STAT = FEATURE_LPUART_STAT_REG_FLAGS_MASK; + /* Reset all features/interrupts by default */ + LPUARTx->CTRL = 0x00000000; + /* Reset match addresses */ + LPUARTx->MATCH = 0x00000000; +#if FEATURE_LPUART_HAS_MODEM_SUPPORT + /* Reset IrDA modem features */ + LPUARTx->MODIR = 0x00000000; +#endif +#if FEATURE_LPUART_FIFO_SIZE > 0U + /* Reset FIFO feature */ + LPUARTx->FIFO = FEATURE_LPUART_FIFO_RESET_MASK; + /* Enable the transmit and receive FIFOs. */ + LPUARTx->FIFO |= LPUART_FIFO_TXFE(1) | LPUART_FIFO_RXFE(1); + /* Set the reception water mark to 0 and the transmitter water mark to 1. */ + LPUARTx->WATER = LPUART_WATER_TXWATER(1) | LPUART_WATER_RXWATER(0); +#endif + /* Enable transmitter and receiver, no parity, 8 bit char: + * RE=1: Receiver enabled. + * TE=1: Transmitter enabled. + * PE,PT=0: No hw parity generation or checking. + * M7,M,R8T9,R9T8=0: 8-bit data characters. + * DOZEEN=0: LPUART enabled in Doze mode. + * ORIE,NEIE,FEIE,PEIE,TIE,TCIE,RIE,ILIE,MA1IE,MA2IE=0: no IRQ. + * TxDIR=0: TxD pin is input if in single-wire mode. + * TXINV=0: Transmit data not inverted. + * RWU,WAKE=0: normal operation; rcvr not in standby. + * IDLCFG=0: one idle character. + * ILT=0: Idle char bit count starts after start bit. + * SBK=0: Normal transmitter operation - no break char. + * LOOPS,RSRC=0: no loop back. + */ + LPUARTx->CTRL = LPUART_CTRL_RE_MASK | LPUART_CTRL_TE_MASK; +} /*** end of BootComRs232Init ***/ + + +/************************************************************************************//** +** \brief Receives the CONNECT request from the host, which indicates that the +** bootloader should be activated and, if so, activates it. +** \return none. +** +****************************************************************************************/ +static void BootComRs232CheckActivationRequest(void) +{ + static unsigned char xcpCtoReqPacket[BOOT_COM_RS232_RX_MAX_DATA+1]; + static unsigned char xcpCtoRxLength; + static unsigned char xcpCtoRxInProgress = 0; + static unsigned long xcpCtoRxStartTime = 0; + + /* start of cto packet received? */ + if (xcpCtoRxInProgress == 0) + { + /* store the message length when received */ + if (Rs232ReceiveByte(&xcpCtoReqPacket[0]) == 1) + { + /* check that the length has a valid value. it should not be 0 */ + if ( (xcpCtoReqPacket[0] > 0) && + (xcpCtoReqPacket[0] <= BOOT_COM_RS232_RX_MAX_DATA) ) + { + /* store the start time */ + xcpCtoRxStartTime = TimerGet(); + /* indicate that a cto packet is being received */ + xcpCtoRxInProgress = 1; + /* reset packet data count */ + xcpCtoRxLength = 0; + } + } + } + else + { + /* store the next packet byte */ + if (Rs232ReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1) + { + /* increment the packet data count */ + xcpCtoRxLength++; + + /* check to see if the entire packet was received */ + if (xcpCtoRxLength == xcpCtoReqPacket[0]) + { + /* done with cto packet reception */ + xcpCtoRxInProgress = 0; + + /* check if this was an XCP CONNECT command */ + if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00)) + { + /* connection request received so start the bootloader */ + BootActivate(); + } + } + } + else + { + /* check packet reception timeout */ + if (TimerGet() > (xcpCtoRxStartTime + RS232_CTO_RX_PACKET_TIMEOUT_MS)) + { + /* cancel cto packet reception due to timeout. note that this automatically + * discards the already received packet bytes, allowing the host to retry. + */ + xcpCtoRxInProgress = 0; + } + } + } +} /*** end of BootComRs232CheckActivationRequest ***/ + + +/************************************************************************************//** +** \brief Receives a communication interface byte if one is present. +** \param data Pointer to byte where the data is to be stored. +** \return 1 if a byte was received, 0 otherwise. +** +****************************************************************************************/ +static unsigned char Rs232ReceiveByte(unsigned char *data) +{ + unsigned char result = 0; + + /* Check if a new byte was received by means of the RDRF-bit. */ + if (((LPUARTx->STAT & LPUART_STAT_RDRF_MASK) >> LPUART_STAT_RDRF_SHIFT) != 0U) + { + /* Retrieve and store the newly received byte. */ + *data = LPUARTx->DATA; + /* Update the result. */ + result = 1; + } + + /* Give the result back to the caller. */ + return result; +} /*** end of Rs232ReceiveByte ***/ +#endif /* BOOT_COM_RS232_ENABLE > 0 */ + + +#if (BOOT_COM_CAN_ENABLE > 0) +/**************************************************************************************** +* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E +****************************************************************************************/ + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Timeout for entering/leaving CAN initialization mode in milliseconds. */ +#define CAN_INIT_TIMEOUT_MS (250U) + +/** \brief Set the peripheral CAN0 base pointer. */ +#define CANx (CAN0) +/** \brief Set the PCC index offset for CAN0. */ +#define PCC_FlexCANx_INDEX (PCC_FlexCAN0_INDEX) +/** \brief Set the number of message boxes supported by CAN0. */ +#define CANx_MAX_MB_NUM (FEATURE_CAN0_MAX_MB_NUM) + +/** \brief The mailbox used for receiving the XCP command message. */ +#define CAN_RX_MSGBOX_NUM (9U) + + +/**************************************************************************************** +* Type definitions +****************************************************************************************/ +/** \brief Structure type for grouping CAN bus timing related information. */ +typedef struct t_can_bus_timing +{ + unsigned char timeQuanta; /**< Total number of time quanta */ + unsigned char propSeg; /**< CAN propagation segment */ + unsigned char phaseSeg1; /**< CAN phase segment 1 */ + unsigned char phaseSeg2; /**< CAN phase segment 2 */ +} tCanBusTiming; + + +/**************************************************************************************** +* Local constant declarations +****************************************************************************************/ +/** \brief CAN bit timing table for dynamically calculating the bittiming settings. + * \details According to the CAN protocol 1 bit-time can be made up of between 8..25 + * time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC + * always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + TSEG2) + * * 100%. This array contains possible and valid time quanta configurations + * with a sample point between 68..78%. A visual representation of the TQ in + * a bit is: + * | SYNCSEG | TIME1SEG | TIME2SEG | + * Or with an alternative representation: + * | SYNCSEG | PROPSEG | PHASE1SEG | PHASE2SEG | + * With the alternative representation TIME1SEG = PROPSEG + PHASE1SEG. + * + */ +static const tCanBusTiming canTiming[] = +{ + /* Time-Quanta | PROPSEG | PSEG1 | PSEG2 | Sample-Point */ + /* ---------------------------------------------------- */ + { 8U, 3U, 2U, 2U }, /*1+3+2+1=8 | 3 | 2 | 2 | 75% */ + { 9U, 3U, 3U, 2U }, /* 9 | 3 | 3 | 2 | 78% */ + { 10U, 3U, 3U, 3U }, /* 10 | 3 | 3 | 3 | 70% */ + { 11U, 4U, 3U, 3U }, /* 11 | 4 | 3 | 3 | 73% */ + { 12U, 4U, 4U, 3U }, /* 12 | 4 | 4 | 3 | 75% */ + { 13U, 5U, 4U, 3U }, /* 13 | 5 | 4 | 3 | 77% */ + { 14U, 5U, 4U, 4U }, /* 14 | 5 | 4 | 4 | 71% */ + { 15U, 6U, 4U, 4U }, /* 15 | 6 | 4 | 4 | 73% */ + { 16U, 6U, 5U, 4U }, /* 16 | 6 | 5 | 4 | 75% */ + { 17U, 7U, 5U, 4U }, /* 17 | 7 | 5 | 4 | 76% */ + { 18U, 7U, 5U, 5U }, /* 18 | 7 | 5 | 5 | 72% */ + { 19U, 8U, 5U, 5U }, /* 19 | 8 | 5 | 5 | 74% */ + { 20U, 8U, 6U, 5U }, /* 20 | 8 | 6 | 5 | 75% */ + { 21U, 8U, 7U, 5U }, /* 21 | 8 | 7 | 5 | 76% */ + { 22U, 8U, 7U, 6U }, /* 22 | 8 | 7 | 6 | 73% */ + { 23U, 8U, 8U, 6U }, /* 23 | 8 | 8 | 6 | 74% */ + { 24U, 8U, 8U, 7U }, /* 24 | 8 | 8 | 7 | 71% */ + { 25U, 8U, 8U, 8U } /* 25 | 8 | 8 | 8 | 68% */ +}; + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Dummy variable to store the CAN controller's free running timer value in. + * This is needed at the end of a CAN message reception to unlock the mailbox + * again. If this variable is declared locally within the function, it generates + * an unwanted compiler warning about assigning a value and not using it. + * For this reason this dummy variabled is declare here as a module global. + */ +static volatile unsigned long dummyTimerVal; + + +/************************************************************************************//** +** \brief Search algorithm to match the desired baudrate to a possible bus +** timing configuration. +** \param baud The desired baudrate in kbps. Valid values are 10..1000. +** \param prescaler Pointer to where the value for the prescaler will be stored. +** \param busTimingCfg Pointer to where the bus timing values will be stored. +** \return 1 if the CAN bustiming register values were found, 0 otherwise. +** +****************************************************************************************/ +static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned short * prescaler, + tCanBusTiming * busTimingCfg) +{ + unsigned char cnt; + unsigned long canClockFreqkHz; + unsigned long div2RegValue; + unsigned char const div2DividerLookup[] = + { + 0U, /* 0b000. Output disabled. */ + 1U, /* 0b001. Divide by 1. */ + 2U, /* 0b010. Divide by 2. */ + 4U, /* 0b011. Divide by 4. */ + 8U, /* 0b100. Divide by 8. */ + 16U, /* 0b101. Divide by 16. */ + 32U, /* 0b110. Divide by 32. */ + 64U, /* 0b111. Divide by 64. */ + }; + + /* Obtain the DIV2 divider value of the SOSC_CLK. */ + div2RegValue = (SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV2_MASK) >> SCG_SOSCDIV_SOSCDIV2_SHIFT; + /* Check if the DIV2 register value for SOSC is 0. In this case SOSCDIV2_CLK is + * currently disabled. + */ + if (div2RegValue == 0U) + { + /* Configure the DIV2 for a default divide by 1 to make sure the SOSCDIV2_CLK is + * actually enabled. + */ + div2RegValue = 1U; + SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(div2RegValue); + } + /* Determine the SOSC clock frequency. */ + canClockFreqkHz = BOOT_CPU_XTAL_SPEED_KHZ; + /* Now process the configured DIV2 divider factor to get the actual frequency of the + * CAN peripheral source clock. + */ + canClockFreqkHz /= div2DividerLookup[div2RegValue]; + + /* Loop through all possible time quanta configurations to find a match. */ + for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++) + { + if ((canClockFreqkHz % (baud * canTiming[cnt].timeQuanta)) == 0U) + { + /* Compute the prescaler that goes with this TQ configuration. */ + *prescaler = canClockFreqkHz/(baud * canTiming[cnt].timeQuanta); + + /* Make sure the prescaler is valid. */ + if ((*prescaler > 0U) && (*prescaler <= 256U)) + { + /* Store the bustiming configuration. */ + *busTimingCfg = canTiming[cnt]; + /* Found a good bus timing configuration. */ + return 1U; + } + } + } + /* Could not find a good bus timing configuration. */ + return 0U; +} /*** end of CanGetSpeedConfig ***/ + + +/************************************************************************************//** +** \brief Places the CAN controller in freeze mode. Note that the CAN controller +** can only be placed in freeze mode, if it is actually enabled. +** \return none. +** +****************************************************************************************/ +static void CanFreezeModeEnter(void) +{ + unsigned long timeout; + + /* Request to enter freeze mode. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(1U); + CANx->MCR = (CANx->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(1U); + /* Set timeout time for entering freeze mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for freeze mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_FRZACK_MASK)) == 0U) + { + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } +} /*** end of CanFreezeModeEnter ***/ + + +/************************************************************************************//** +** \brief Leaves the CAN controller's freeze mode. Note that this operation can +** only be done, if it is actually enabled. +** \return none. +** +****************************************************************************************/ +static void CanFreezeModeExit(void) +{ + unsigned long timeout; + + /* Request to leave freeze mode. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(0U); + CANx->MCR = (CANx->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(0U); + /* Set timeout time for leaving freeze mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for non freeze mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_FRZACK_MASK)) != 0U) + { + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } +} /*** end of CanFreezeModeExit ***/ + + +/************************************************************************************//** +** \brief Places the CAN controller in disabled mode. +** \return none. +** +****************************************************************************************/ +static void CanDisabledModeEnter(void) +{ + unsigned long timeout; + + /* Only continue if the CAN controller is currently enabled. */ + if ((CANx->MCR & CAN_MCR_MDIS_MASK) == 0U) + { + /* Request disabled mode. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(1U); + /* Set timeout time for entering disabled mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for disabled mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_LPMACK_MASK)) == 0U) + { + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } + } +} /*** end of CanDisabledModeEnter ***/ + +/************************************************************************************//** +** \brief Places the CAN controller in enabled mode. +** \return none. +** +****************************************************************************************/ +static void CanDisabledModeExit(void) +{ + unsigned long timeout; + + /* Only continue if the CAN controller is currently disabled. */ + if ((CANx->MCR & CAN_MCR_MDIS_MASK) != 0U) + { + /* Request enabled mode. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(0U); + /* Set timeout time for leaving disabled mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for disabled mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_LPMACK_MASK)) != 0U) + { + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } + } +} /*** end of CanDisabledModeExit ***/ + + +/************************************************************************************//** +** \brief Initializes the CAN communication interface. +** \return none. +** +****************************************************************************************/ +static void BootComCanInit(void) +{ + unsigned short prescaler = 0; + tCanBusTiming timingCfg = { 0 }; + unsigned char rjw; + unsigned short idx; + unsigned long timeout; + unsigned long rxMsgId = BOOT_COM_CAN_RX_MSG_ID; + + /* Enable the CAN peripheral clock. */ + PCC->PCCn[PCC_FlexCANx_INDEX] |= PCC_PCCn_CGC_MASK; + + /* The source clock needs to be configured first. For this the CAN controller must be + * in disabled mode, but that can only be entered after first entering freeze mode, + * which in turn can only be in enabled mode. So first enable the module, then goto + * freeze mode and finally enter disabled mode. + */ + CanDisabledModeExit(); + CanFreezeModeEnter(); + CanDisabledModeEnter(); + /* Configure SOSCDIV2 as the source clock. This assumes that an external oscillator + * is available, which is typically the case to meet the clock tolerance requirements + * of the CAN 2.0B secification. + */ + CANx->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK; + /* Leave disabled mode. */ + CanDisabledModeExit(); + /* Make sure freeze mode is active to be able to initialize the CAN controller. */ + CanFreezeModeEnter(); + + /* Obtain bittiming configuration information. */ + (void)CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &timingCfg); + + /* Reset the current bittiming configuration. */ + CANx->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_PROPSEG_MASK | + CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | CAN_CTRL1_RJW_MASK | + CAN_CTRL1_SMP_MASK); + /* Configure the baudrate prescaler. */ + CANx->CTRL1 |= CAN_CTRL1_PRESDIV(prescaler - 1U); + /* Configure the propagation segment. */ + CANx->CTRL1 |= CAN_CTRL1_PROPSEG(timingCfg.propSeg - 1U); + /* Configure the phase segments. */ + CANx->CTRL1 |= CAN_CTRL1_PSEG1(timingCfg.phaseSeg1 - 1U); + CANx->CTRL1 |= CAN_CTRL1_PSEG2(timingCfg.phaseSeg2 - 1U); + /* The resynchronization jump width (RJW) can be 1 - 4 TQ, yet should never be larger + * than pseg1. Configure the longest possible value for RJW. + */ + rjw = (timingCfg.phaseSeg1 < 4) ? timingCfg.phaseSeg1 : 4; + CANx->CTRL1 |= CAN_CTRL1_RJW(rjw - 1U); + /* All the entries in canTiming[] have a PSEG1 >= 2, so three samples can be used to + * determine the value of the received bit, instead of the default one. + */ + CANx->CTRL1 |= CAN_CTRL1_SMP(1U); + + /* Clear the message box RAM. Each message box covers 4 words (1 word = 32-bits. */ + for (idx = 0; idx < (CANx_MAX_MB_NUM * 4U); idx++) + { + CANx->RAMn[idx] = 0U; + } + /* Clear the reception mask register for each message box. */ + for (idx = 0; idx < CANx_MAX_MB_NUM; idx++) + { + CANx->RXIMR[idx] = 0U; + } + /* Configure the maximum number of message boxes. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB(CANx_MAX_MB_NUM - 1U); + /* Disable the self reception feature. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_SRXDIS_MASK) | CAN_MCR_SRXDIS(1U); + + /* Enable individual reception masking. This disables the legacy support for the + * global reception mask and the mailbox 14/15 individual reception mask. + */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_IRMQ_MASK) | CAN_MCR_IRMQ(1U); + /* Disable the reception FIFO. This driver only needs to receive one CAN message + * identifier. It is sufficient to use just one dedicated mailbox for this. + */ + CANx->MCR &= ~CAN_MCR_RFEN_MASK; + /* Configure the mask of the invididual message reception mailbox to check all ID bits + * and also the IDE bit. + */ + CANx->RXIMR[CAN_RX_MSGBOX_NUM] = 0x40000000U | 0x1FFFFFFFU; + /* Configure the reception mailbox to receive just the CAN message configured with + * BOOT_COM_CAN_RX_MSG_ID. + * EDL, BRS, ESI=0: CANFD not used. + * CODE=0b0100: mailbox set to active and empty. + * IDE=0: 11-bit CAN identifier. + * SRR, RTR, TIME STAMP=0: not applicable. + */ + CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] = 0x04000000; + /* Store the message identifier to receive in the mailbox RAM. */ + if ((rxMsgId & 0x80000000U) != 0U) + { + /* It is a 29-bit extended CAN identifier. */ + rxMsgId &= ~0x80000000U; + /* Set the IDE bit to configure the message for a 29-bit identifier. */ + CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] |= CAN_WMBn_CS_IDE_MASK; + /* Store the 29-bit CAN identifier. */ + CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(rxMsgId); + } + else + { + /* Store the 11-bit CAN identifier. */ + CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(rxMsgId << 18U); + } + + /* Disable all message box interrupts. */ + CANx->IMASK1 = 0U; + /* Clear all mesasge box interrupt flags. */ + CANx->IFLAG1 = CAN_IMASK1_BUF31TO0M_MASK; + /* Clear all error interrupt flags */ + CANx->ESR1 = CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK | + CAN_ESR1_TWRNINT_MASK | CAN_ESR1_BOFFDONEINT_MASK | + CAN_ESR1_ERRINT_FAST_MASK | CAN_ESR1_ERROVR_MASK; + + /* Switch to normal user mode. */ + CANx->MCR &= ~CAN_MCR_SUPV_MASK; + CANx->CTRL1 &= ~(CAN_CTRL1_LOM_MASK | CAN_CTRL1_LPB_MASK); + /* Exit freeze mode. */ + CanFreezeModeExit(); + /* Set timeout time for entering normal user mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for normal user mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_NOTRDY_MASK)) != 0U) + { + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } +} /*** end of BootComCanInit ***/ + + +/************************************************************************************//** +** \brief Receives the CONNECT request from the host, which indicates that the +** bootloader should be activated and, if so, activates it. +** \return none. +** +****************************************************************************************/ +static void BootComCanCheckActivationRequest(void) +{ + unsigned char * pMsgBoxData; + unsigned char byteIdx; + unsigned char rxMsgData[8]; + unsigned char rxMsgLen; + + /* Check if a message was received in the individual mailbox configured to receive + * the BOOT_COM_CAN_RX_MSG_ID message. + */ + if ((CANx->IFLAG1 & (1U << CAN_RX_MSGBOX_NUM)) != 0U) + { + /* Note that there is no need to verify the identifier of the CAN message because the + * mailbox is configured to only receive the BOOT_COM_CAN_TX_MSG_ID message. Start + * by reading out the DLC of the newly received CAN message. + */ + rxMsgLen = (CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] & CAN_WMBn_CS_DLC_MASK) >> CAN_WMBn_CS_DLC_SHIFT; + /* Read the data bytes of the CAN message from the mailbox RAM. */ + pMsgBoxData = (unsigned char *)(&CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 2U]); + for (byteIdx = 0; byteIdx < rxMsgLen; byteIdx++) + { + rxMsgData[byteIdx] = pMsgBoxData[((byteIdx) & ~3U) + (3U - ((byteIdx) & 3U))]; + } + /* Clear the mailbox interrupt flag by writing a 1 to the corresponding box. */ + CANx->IFLAG1 = (1U << CAN_RX_MSGBOX_NUM); + /* Read the free running timer to unlock the mailbox. */ + dummyTimerVal = CANx->TIMER; + + /* check if this was an XCP CONNECT command */ + if ((rxMsgData[0] == 0xff) && (rxMsgLen == 2)) + { + /* connection request received so start the bootloader */ + BootActivate(); + } + } +} /*** end of BootComCanCheckActivationRequest ***/ +#endif /* BOOT_COM_CAN_ENABLE > 0 */ + + +/*********************************** end of boot.c *************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/boot.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/boot.h new file mode 100644 index 00000000..897be52f --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/boot.h @@ -0,0 +1,40 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/boot.h +* \brief Demo program bootloader interface header file. +* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef BOOT_H +#define BOOT_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void BootComInit(void); +void BootComCheckActivationRequest(void); +void BootActivate(void); + + +#endif /* BOOT_H */ +/*********************************** end of boot.h *************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/header.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/header.h new file mode 100644 index 00000000..d5404645 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/header.h @@ -0,0 +1,42 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/header.h +* \brief Generic header file. +* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef HEADER_H +#define HEADER_H + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "../Boot/blt_conf.h" /* bootloader configuration */ +#include "boot.h" /* bootloader interface driver */ +#include "led.h" /* LED driver */ +#include "timer.h" /* Timer driver */ +#include "device_registers.h" /* Device registers */ +#include "system_S32K118.h" /* Device sconfiguration */ + +#endif /* HEADER_H */ +/*********************************** end of header.h ***********************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.dep b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.dep new file mode 100644 index 00000000..b10e1d58 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.dep @@ -0,0 +1,247 @@ + + + 4 + 544470611 + + Debug + + $PROJ_DIR$\..\obj\timer.__cstat.et + $PROJ_DIR$\..\obj\led.xcl + $TOOLKIT_DIR$\inc\c\yvals.h + $PROJ_DIR$\..\boot.h + $PROJ_DIR$\..\boot.c + $PROJ_DIR$\..\header.h + $PROJ_DIR$\..\timer.c + $PROJ_DIR$\..\obj\s32k118.pbd + $PROJ_DIR$\..\led.c + $PROJ_DIR$\..\obj\startup.__cstat.et + $PROJ_DIR$\..\obj\system_S32K118.o + $PROJ_DIR$\..\obj\system_S32K118.__cstat.et + $PROJ_DIR$\..\obj\timer.xcl + $PROJ_DIR$\..\lib\S32K118_features.h + $PROJ_DIR$\..\lib\system_S32K118.h + $PROJ_DIR$\..\obj\system_S32K118.xcl + $PROJ_DIR$\..\obj\startup.xcl + $PROJ_DIR$\..\obj\boot.xcl + $PROJ_DIR$\..\timer.h + $PROJ_DIR$\..\lib\startup.h + $PROJ_DIR$\..\obj\boot.o + $PROJ_DIR$\..\obj\startup_S32K118.o + $PROJ_DIR$\..\obj\main.xcl + $PROJ_DIR$\..\main.c + $PROJ_DIR$\..\lib\startup.c + $PROJ_DIR$\..\obj\main.o + $PROJ_DIR$\..\bin\demoprog_s32k118.out + $PROJ_DIR$\..\startup_S32K118.s + $PROJ_DIR$\..\obj\led.o + $PROJ_DIR$\..\lib\system_S32K118.c + $PROJ_DIR$\..\led.h + $PROJ_DIR$\..\obj\timer.o + $PROJ_DIR$\..\lib\s32_core_cm0.h + $PROJ_DIR$\..\lib\S32K118.h + $PROJ_DIR$\..\lib\devassert.h + $PROJ_DIR$\..\lib\device_registers.h + $PROJ_DIR$\..\obj\startup.o + $TOOLKIT_DIR$\inc\c\DLib_Product.h + $TOOLKIT_DIR$\inc\c\stdint.h + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + $TOOLKIT_DIR$\lib\m6M_tl.a + $TOOLKIT_DIR$\lib\shb_l.a + $PROJ_DIR$\..\obj\main.__cstat.et + $PROJ_DIR$\..\obj\boot.__cstat.et + $PROJ_DIR$\..\obj\led.__cstat.et + $PROJ_DIR$\..\obj\demoprog_s32k118.map + $PROJ_DIR$\..\S32K118_25_flash.icf + $TOOLKIT_DIR$\lib\rt6M_tl.a + $PROJ_DIR$\..\..\Boot\blt_conf.h + $PROJ_DIR$\..\bin\demoprog_s32k118.srec + $TOOLKIT_DIR$\inc\c\stdbool.h + $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h + $TOOLKIT_DIR$\lib\dl6M_tln.a + $TOOLKIT_DIR$\inc\c\ycheck.h + + + [ROOT_NODE] + + + ILINK + 26 45 + + + + + $PROJ_DIR$\..\boot.c + + + ICCARM + 20 + + + BICOMP + 17 + + + __cstat + 43 + + + + + ICCARM + 5 48 3 30 18 35 32 33 38 53 2 39 51 37 13 34 50 14 + + + + + $PROJ_DIR$\..\timer.c + + + ICCARM + 31 + + + BICOMP + 12 + + + __cstat + 0 + + + + + ICCARM + 5 48 3 30 18 35 32 33 38 53 2 39 51 37 13 34 50 14 + + + + + $PROJ_DIR$\..\led.c + + + ICCARM + 28 + + + BICOMP + 1 + + + __cstat + 44 + + + + + ICCARM + 5 48 3 30 18 35 32 33 38 53 2 39 51 37 13 34 50 14 + + + + + $PROJ_DIR$\..\main.c + + + ICCARM + 25 + + + BICOMP + 22 + + + __cstat + 42 + + + + + ICCARM + 5 48 3 30 18 35 32 33 38 53 2 39 51 37 13 34 50 14 + + + + + $PROJ_DIR$\..\lib\startup.c + + + ICCARM + 36 + + + BICOMP + 16 + + + __cstat + 9 + + + + + ICCARM + 19 38 53 2 39 51 37 35 32 33 13 34 50 + + + + + $PROJ_DIR$\..\bin\demoprog_s32k118.out + + + OBJCOPY + 49 + + + ILINK + 45 + + + + + ILINK + 46 20 28 25 36 21 10 31 41 47 40 52 + + + + + $PROJ_DIR$\..\startup_S32K118.s + + + AARM + 21 + + + + + $PROJ_DIR$\..\lib\system_S32K118.c + + + ICCARM + 10 + + + BICOMP + 15 + + + __cstat + 11 + + + + + ICCARM + 35 32 33 38 53 2 39 51 37 13 34 50 14 + + + + + + Release + + + [MULTI_TOOL] + ILINK + + + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.ewd b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.ewd new file mode 100644 index 00000000..42f98615 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.ewd @@ -0,0 +1,2966 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + 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$PROJ_DIR$\..\startup_S32K118.s + + + $PROJ_DIR$\..\timer.c + + + $PROJ_DIR$\..\timer.h + + + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.ewt b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.ewt new file mode 100644 index 00000000..405ef8f9 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.ewt @@ -0,0 +1,2432 @@ + + + 3 + + Debug + + ARM + + 1 + + C-STAT + 261 + + 261 + + 0 + + 1 + 600 + 1 + 2 + 0 + 1 + 100 + + + 1.5.5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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RuntimeChecking + 0 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + Prog + + lib + + $PROJ_DIR$\..\lib\devassert.h + + + $PROJ_DIR$\..\lib\device_registers.h + + + $PROJ_DIR$\..\lib\s32_core_cm0.h + + + $PROJ_DIR$\..\lib\S32K118.h + + + $PROJ_DIR$\..\lib\S32K118_features.h + + + $PROJ_DIR$\..\lib\startup.c + + + $PROJ_DIR$\..\lib\startup.h + + + $PROJ_DIR$\..\lib\system_S32K118.c + + + $PROJ_DIR$\..\lib\system_S32K118.h + + + + $PROJ_DIR$\..\boot.c + + + $PROJ_DIR$\..\boot.h + + + $PROJ_DIR$\..\header.h + + + $PROJ_DIR$\..\led.c + + + $PROJ_DIR$\..\led.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\startup_S32K118.s + + + $PROJ_DIR$\..\timer.c + + + $PROJ_DIR$\..\timer.h + + + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.eww b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.eww new file mode 100644 index 00000000..ca137aad --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\s32k118.ewp + + + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/led.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/led.c new file mode 100644 index 00000000..07031dec --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/led.c @@ -0,0 +1,96 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/led.c +* \brief LED driver source file. +* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Toggle interval time in milliseconds. */ +#define LED_TOGGLE_MS (500U) + + +/************************************************************************************//** +** \brief Initializes the LED. +** \return none. +** +****************************************************************************************/ +void LedInit(void) +{ + /* LED GPIO pin configuration. PE8 = GPIO, MUX = ALT1. */ + PORTE->PCR[8] = PORT_PCR_MUX(1); + /* Configure Port E pin 8 GPIO as digital output. */ + PTE->PDDR |= GPIO_PDDR_PDD(1 << 8U); + /* Turn the LED off on Port E pin 8. */ + PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U); +} /*** end of LedInit ***/ + + +/************************************************************************************//** +** \brief Toggles the LED at a fixed time interval. +** \return none. +** +****************************************************************************************/ +void LedToggle(void) +{ + static unsigned char led_toggle_state = 0; + static unsigned long timer_counter_last = 0; + unsigned long timer_counter_now; + + /* Check if toggle interval time passed. */ + timer_counter_now = TimerGet(); + if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS) + { + /* Not yet time to toggle. */ + return; + } + + /* Determine toggle action. */ + if (led_toggle_state == 0) + { + led_toggle_state = 1; + /* Turn the LED on. */ + PTE->PSOR |= GPIO_PSOR_PTSO(1 << 8U); + } + else + { + led_toggle_state = 0; + /* Turn the LED off. */ + PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U); + } + + /* Store toggle time to determine next toggle interval. */ + timer_counter_last = timer_counter_now; +} /*** end of LedToggle ***/ + + +/*********************************** end of led.c **************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/led.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/led.h new file mode 100644 index 00000000..5365c03f --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/led.h @@ -0,0 +1,39 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/led.h +* \brief LED driver header file. +* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef LED_H +#define LED_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void LedInit(void); +void LedToggle(void); + + +#endif /* LED_H */ +/*********************************** end of led.h **************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/S32K118.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/S32K118.h new file mode 100644 index 00000000..d1f10a17 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/S32K118.h @@ -0,0 +1,10438 @@ +/* +** ################################################################### +** Processor: S32K118 +** Reference manual: S32K1XXRM Rev. 9, 09/2018 +** Version: rev. 1.3, 2019-02-19 +** Build: b190219 +** +** Abstract: +** Peripheral Access Layer for S32K118 +** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2017-12-14) - Mihai Volmer +** Initial version based on S32K1XXRM Rev. 6, 12/2017. +** - rev. 1.1 (2018-02-08) - Mihai Volmer +** Renamed the NVIC register array IP to IPR to reflect the register access difference from Cortex-M4 NVIC registers +** Fixed CSE_PRAM base address +** - rev. 1.2 (2018-07-19) - Dan Nastasa +** Updated the header based on S32K1XXRM Rev. 8, 06/2018. +** Added MTB_DWT peripheral to the header file +** - rev. 1.3 (2019-02-19) - Ionut Pavel +** Updated the header based on S32K1XXRM Rev. 9, 09/2018. +** Removed LMEM_LMDR2 register from the header file. +** Modified LMEM_LMPECR register to Read-Only. +** +** ################################################################### +*/ + +/*! + * @file S32K118.h + * @version 1.3 + * @date 2019-02-19 + * @brief Peripheral Access Layer for S32K118 + * + * This file contains register definitions and macros for easy access to their + * bit fields. + * + * This file assumes LITTLE endian system. + */ + +/** +* @page misra_violations MISRA-C:2012 violations +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced +* The SoC header defines typedef for all modules. +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced +* The SoC header defines macros for all modules and registers. +* +* @section [global] +* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro +* These are generated macros used for accessing the bit-fields from registers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.1, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.2, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.4, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.5, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler +* This type qualifier is needed to ensure correct I/O access and addressing. +*/ + +/* ---------------------------------------------------------------------------- + -- MCU activation + ---------------------------------------------------------------------------- */ + +/* Prevention from multiple including the same memory map */ +#if !defined(S32K118_H_) /* Check if memory map has not been already included */ +#define S32K118_H_ +#define MCU_S32K118 + +/* Check if another memory map has not been also included */ +#if (defined(MCU_ACTIVE)) + #error S32K118 memory map: There is already included another memory map. Only one memory map can be included. +#endif /* (defined(MCU_ACTIVE)) */ +#define MCU_ACTIVE + +#include + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0003u + +/* ---------------------------------------------------------------------------- + -- Generic macros + ---------------------------------------------------------------------------- */ + +/* IO definitions (access restrictions to peripheral registers) */ +/** +* IO Type Qualifiers are used +* \li to specify the access to peripheral variables. +* \li for automatic generation of peripheral register debug information. +*/ +#ifndef __IO +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ +#endif + + +/** +* @brief 32 bits memory read macro. +*/ +#if !defined(REG_READ32) + #define REG_READ32(address) (*(volatile uint32_t*)(address)) +#endif + +/** +* @brief 32 bits memory write macro. +*/ +#if !defined(REG_WRITE32) + #define REG_WRITE32(address, value) ((*(volatile uint32_t*)(address))= (uint32_t)(value)) +#endif + +/** +* @brief 32 bits bits setting macro. +*/ +#if !defined(REG_BIT_SET32) + #define REG_BIT_SET32(address, mask) ((*(volatile uint32_t*)(address))|= (uint32_t)(mask)) +#endif + +/** +* @brief 32 bits bits clearing macro. +*/ +#if !defined(REG_BIT_CLEAR32) + #define REG_BIT_CLEAR32(address, mask) ((*(volatile uint32_t*)(address))&= ((uint32_t)~((uint32_t)(mask)))) +#endif + +/** +* @brief 32 bit clear bits and set with new value +* @note It is user's responsability to make sure that value has only "mask" bits set - (value&~mask)==0 +*/ +#if !defined(REG_RMW32) + #define REG_RMW32(address, mask, value) (REG_WRITE32((address), ((REG_READ32(address)& ((uint32_t)~((uint32_t)(mask))))| ((uint32_t)(value))))) +#endif + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers for S32K118 + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers_S32K118 Interrupt vector numbers for S32K118 + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 48u /**< Number of interrupts in the Vector table */ + +/** + * @brief Defines the Interrupt Numbers definitions + * + * This enumeration is used to configure the interrupts. + * + * Implements : IRQn_Type_Class + */ +typedef enum +{ + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_IRQn = 0u, /**< DMA channel 0 transfer complete */ + DMA1_IRQn = 1u, /**< DMA channel 1 transfer complete */ + DMA2_IRQn = 2u, /**< DMA channel 2 transfer complete */ + DMA3_IRQn = 3u, /**< DMA channel 3 transfer complete */ + DMA_Error_IRQn = 4u, /**< DMA error interrupt channels 0-3 */ + ERM_fault_IRQn = 5u, /**< ERM single and double bit error correction */ + RTC_IRQn = 6u, /**< RTC alarm interrupt */ + RTC_Seconds_IRQn = 7u, /**< RTC seconds interrupt */ + LPTMR0_IRQn = 8u, /**< LPTIMER interrupt request */ + PORT_IRQn = 9u, /**< Port A, B, C, D and E pin detect interrupt */ + CAN0_ORed_Err_Wakeup_IRQn = 10u, /**< OR’ed [Bus Off OR Bus Off Done OR Transmit Warning OR Receive Warning], Interrupt indicating that errors were detected on the CAN bus, Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode */ + CAN0_ORed_0_31_MB_IRQn = 11u, /**< OR'ed Message buffer (0-15, 16-31) */ + FTM0_Ch0_7_IRQn = 12u, /**< FTM0 Channel 0 to 7 interrupt */ + FTM0_Fault_IRQn = 13u, /**< FTM0 Fault interrupt */ + FTM0_Ovf_Reload_IRQn = 14u, /**< FTM0 Counter overflow and Reload interrupt */ + FTM1_Ch0_7_IRQn = 15u, /**< FTM1 Channel 0 to 7 interrupt */ + FTM1_Fault_IRQn = 16u, /**< FTM1 Fault interrupt */ + FTM1_Ovf_Reload_IRQn = 17u, /**< FTM1 Counter overflow and Reload interrupt */ + FTFC_IRQn = 18u, /**< FTFC Command complete, Read collision and Double bit fault detect */ + PDB0_IRQn = 19u, /**< PDB0 interrupt */ + LPIT0_IRQn = 20u, /**< LPIT interrupt */ + SCG_CMU_LVD_LVWSCG_IRQn = 21u, /**< PMC Low voltage detect interrupt, SCG bus interrupt request and CMU loss of range interrupt */ + WDOG_IRQn = 22u, /**< WDOG interrupt request out before wdg reset out */ + RCM_IRQn = 23u, /**< RCM Asynchronous Interrupt */ + LPI2C0_Master_Slave_IRQn = 24u, /**< LPI2C0 Master Interrupt and Slave Interrupt */ + FLEXIO_IRQn = 25u, /**< FlexIO Interrupt */ + LPSPI0_IRQn = 26u, /**< LPSPI0 Interrupt */ + LPSPI1_IRQn = 27u, /**< LPSPI1 Interrupt */ + ADC0_IRQn = 28u, /**< ADC0 interrupt request. */ + CMP0_IRQn = 29u, /**< CMP0 interrupt request */ + LPUART1_RxTx_IRQn = 30u, /**< LPUART1 Transmit / Receive Interrupt */ + LPUART0_RxTx_IRQn = 31u /**< LPUART0 Transmit / Receive Interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers_S32K118 */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer for S32K118 + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer_S32K118 Device Peripheral Access Layer for S32K118 + * @{ + */ + +/* @brief This module covers memory mapped registers available on SoC */ + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + + +/** ADC - Size of Registers Arrays */ +#define ADC_SC1_COUNT 16u +#define ADC_R_COUNT 16u +#define ADC_CV_COUNT 2u + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[ADC_SC1_COUNT]; /**< ADC Status and Control Register 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ + __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x44 */ + __I uint32_t R[ADC_R_COUNT]; /**< ADC Data Result Registers, array offset: 0x48, array step: 0x4 */ + __IO uint32_t CV[ADC_CV_COUNT]; /**< Compare Value Registers, array offset: 0x88, array step: 0x4 */ + __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x90 */ + __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x94 */ + __IO uint32_t BASE_OFS; /**< BASE Offset Register, offset: 0x98 */ + __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x9C */ + __IO uint32_t USR_OFS; /**< USER Offset Correction Register, offset: 0xA0 */ + __IO uint32_t XOFS; /**< ADC X Offset Correction Register, offset: 0xA4 */ + __IO uint32_t YOFS; /**< ADC Y Offset Correction Register, offset: 0xA8 */ + __IO uint32_t G; /**< ADC Gain Register, offset: 0xAC */ + __IO uint32_t UG; /**< ADC User Gain Register, offset: 0xB0 */ + __IO uint32_t CLPS; /**< ADC General Calibration Value Register S, offset: 0xB4 */ + __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register 3, offset: 0xB8 */ + __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register 2, offset: 0xBC */ + __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register 1, offset: 0xC0 */ + __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register 0, offset: 0xC4 */ + __IO uint32_t CLPX; /**< ADC Plus-Side General Calibration Value Register X, offset: 0xC8 */ + __IO uint32_t CLP9; /**< ADC Plus-Side General Calibration Value Register 9, offset: 0xCC */ + __IO uint32_t CLPS_OFS; /**< ADC General Calibration Offset Value Register S, offset: 0xD0 */ + __IO uint32_t CLP3_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 3, offset: 0xD4 */ + __IO uint32_t CLP2_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 2, offset: 0xD8 */ + __IO uint32_t CLP1_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 1, offset: 0xDC */ + __IO uint32_t CLP0_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 0, offset: 0xE0 */ + __IO uint32_t CLPX_OFS; /**< ADC Plus-Side General Calibration Offset Value Register X, offset: 0xE4 */ + __IO uint32_t CLP9_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 9, offset: 0xE8 */ +} ADC_Type, *ADC_MemMapPtr; + + /** Number of instances of the ADC module. */ +#define ADC_INSTANCE_COUNT (1u) + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x4003B000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0 } + /** Number of interrupt vector arrays for the ADC module. */ +#define ADC_IRQS_ARR_COUNT (1u) + /** Number of interrupt channels for the ADC module. */ +#define ADC_IRQS_CH_COUNT (1u) +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* SC1 Bit Fields */ +#define ADC_SC1_ADCH_MASK 0x1Fu +#define ADC_SC1_ADCH_SHIFT 0u +#define ADC_SC1_ADCH_WIDTH 5u +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<VTOR} + +/* FTM module features */ + +/* @brief Number of PWM channels */ +#define FEATURE_FTM_CHANNEL_COUNT (8U) +/* @brief Number of fault channels */ +#define FTM_FEATURE_FAULT_CHANNELS (4U) +/* @brief Width of control channel */ +#define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH (8U) +/* @brief Output channel offset */ +#define FTM_FEATURE_OUTPUT_CHANNEL_OFFSET (16U) +/* @brief Max counter value */ +#define FTM_FEATURE_CNT_MAX_VALUE_U32 (0x0000FFFFU) +/* @brief Input capture for single shot */ +#define FTM_FEATURE_INPUT_CAPTURE_SINGLE_SHOT (2U) +/* @brief Dithering has supported on the generated PWM signals */ +#define FEATURE_FTM_HAS_SUPPORTED_DITHERING (1U) +/* @brief Number of interrupt vector for channels of the FTM module. */ +#define FEATURE_FTM_HAS_NUM_IRQS_CHANS (1U) + +/* LPIT module features */ + +/*! @brief Number of interrupt vector for channels of the LPIT module. */ +#define FEATURE_LPIT_HAS_NUM_IRQS_CHANS (1U) +/*! @brief Clock names for LPIT. */ +#define LPIT_CLOCK_NAMES {LPIT0_CLK} + +/* LPI2C module features */ + +/* @brief DMA instance used for LPI2C module */ +#define LPI2C_DMA_INSTANCE 0U + +/* @brief EDMA requests for LPI2C module. */ +#define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}} +/* @brief PCC clocks for LPI2C module. */ +#define LPI2C_PCC_CLOCKS {LPI2C0_CLK} + +/* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */ +#define LPI2C_HAS_FAST_PLUS_MODE (0U) +#define LPI2C_HAS_HIGH_SPEED_MODE (0U) +#define LPI2C_HAS_ULTRA_FAST_MODE (0U) + +/* LPI2C module features */ + +/* @brief DMA instance used for LPI2C module */ +#define LPI2C_DMA_INSTANCE 0U + +/* @brief EDMA requests for LPI2C module. */ +#define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}} +/* @brief PCC clocks for LPI2C module. */ +#define LPI2C_PCC_CLOCKS {LPI2C0_CLK} + +/* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */ +#define LPI2C_HAS_FAST_PLUS_MODE (0U) +#define LPI2C_HAS_HIGH_SPEED_MODE (0U) +#define LPI2C_HAS_ULTRA_FAST_MODE (0U) + +/* MSCM module features */ + +/* @brief Has interrupt router control registers (IRSPRCn). */ +#define FEATURE_MSCM_HAS_INTERRUPT_ROUTER (0) +/* @brief Has directed CPU interrupt routerregisters (IRCPxxx). */ +#define FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER (0) + +/* CSEc module features */ + +/*! @brief CSE_PRAM offset of the page length parameter used by the following +commands: CMD_ENC_ECB, CMD_ENC_CBC, CMD_DEC_ECB, CMD_DEC_CBC, CMD_MP_COMPRESS */ +#define FEATURE_CSEC_PAGE_LENGTH_OFFSET (0xEU) +/*! @brief CSE_PRAM offset of the message length parameter used by the following +commands: CMD_GENERATE_MAC, CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_MESSAGE_LENGTH_OFFSET (0xCU) +/*! @brief CSE_PRAM offset of the MAC length parameter used by the following +commands: CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_MAC_LENGTH_OFFSET (0x8U) +/*! @brief CSE_PRAM offset of the boot size parameter used by the following +commands: CMD_BOOT_DEFINE */ +#define FEATURE_CSEC_BOOT_SIZE_OFFSET (0x1CU) +/*! @brief CSE_PRAM offset of the boot flavor parameter used by the following +commands: CMD_BOOT_DEFINE */ +#define FEATURE_CSEC_BOOT_FLAVOR_OFFSET (0x1BU) +/*! @brief CSE_PRAM offset of the Flash start address parameter used by the +following commands: CMD_GENERATE_MAC, CMD_VERIFY_MAC (pointer method) */ +#define FEATURE_CSEC_FLASH_START_ADDRESS_OFFSET (0x10U) +/*! @brief CSE_PRAM offset of the verification status parameter used by the +following commands: CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_VERIFICATION_STATUS_OFFSET (0x14U) +/*! @brief CSE_PRAM offset of the error bits field contained by all commands */ +#define FEATURE_CSEC_ERROR_BITS_OFFSET (0x4U) +/*! @brief CSE_PRAM offset of the SREG parameter used by the following commands: +CMD_GET_ID */ +#define FEATURE_CSEC_SREG_OFFSET (0x2FU) + +/*! @brief CSE_PRAM offset of page 0 */ +#define FEATURE_CSEC_PAGE_0_OFFSET (0x0U) +/*! @brief CSE_PRAM offset of page 1 */ +#define FEATURE_CSEC_PAGE_1_OFFSET (0x10U) +/*! @brief CSE_PRAM offset of page 2 */ +#define FEATURE_CSEC_PAGE_2_OFFSET (0x20U) +/*! @brief CSE_PRAM offset of page 3 */ +#define FEATURE_CSEC_PAGE_3_OFFSET (0x30U) +/*! @brief CSE_PRAM offset of page 4 */ +#define FEATURE_CSEC_PAGE_4_OFFSET (0x40U) +/*! @brief CSE_PRAM offset of page 5 */ +#define FEATURE_CSEC_PAGE_5_OFFSET (0x50U) +/*! @brief CSE_PRAM offset of page 6 */ +#define FEATURE_CSEC_PAGE_6_OFFSET (0x60U) +/*! @brief CSE_PRAM offset of page 7 */ +#define FEATURE_CSEC_PAGE_7_OFFSET (0x70U) + +/* CRC module features */ + +/* @brief CRC module use for S32K. */ +#define FEATURE_CRC_DRIVER_SOFT_POLYNOMIAL +/* @brief Default CRC bit width */ +#define FEATURE_CRC_DEFAULT_WIDTH CRC_BITS_16 +/* @brief Default CRC read transpose */ +#define FEATURE_CRC_DEFAULT_READ_TRANSPOSE CRC_TRANSPOSE_NONE +/* @brief Default CRC write transpose */ +#define FEATURE_CRC_DEFAULT_WRITE_TRANSPOSE CRC_TRANSPOSE_NONE +/* @brief Default polynomial 0x1021U */ +#define FEATURE_CRC_DEFAULT_POLYNOMIAL (0x1021U) +/* @brief Default seed value is 0xFFFFU */ +#define FEATURE_CRC_DEFAULT_SEED (0xFFFFU) + +/* PORT module features */ +/*! @brief PORT Used for setting Pins */ +#define FEATURE_PINS_DRIVER_USING_PORT (1) +/* @brief Has control lock (register bit PCR[LK]). */ +#define FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FEATURE_PINS_HAS_OPEN_DRAIN (0) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FEATURE_PORT_HAS_DIGITAL_FILTER (1) +/* @brief Has trigger output to trigger other peripherals (register bit field PCR[IRQC] values). */ +#define FEATURE_PORT_HAS_TRIGGER_OUT (0) +/* @brief Has setting flag only (register bit field PCR[IRQC] values). */ +#define FEATURE_PORT_HAS_FLAG_SET_ONLY (0) +/* @brief Has over-current feature (register bit field PCR[OCIE] values). */ +#define FEATURE_PINS_HAS_OVER_CURRENT (0) +/* @brief Has pull resistor selection available. */ +#define FEATURE_PINS_HAS_PULL_SELECTION (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FEATURE_PINS_HAS_SLEW_RATE (0) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength (register bit PCR[DSE]). */ +#define FEATURE_PINS_HAS_DRIVE_STRENGTH (1) +/* @brief Has drive strength control bits*/ +#define FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL (0) +/* @brief Has port input disable control bits*/ +#define FEATURE_PORT_HAS_INPUT_DISABLE (0) +/* @brief SIM_CHIPCTL_ADC_INTERLEAVE_EN bit is not available */ +#define FEATURE_PINS_HAS_ADC_INTERLEAVE_EN (0) + +/* MPU module features */ + +/* @brief Specifies hardware revision level. */ +#define FEATURE_MPU_HARDWARE_REVISION_LEVEL (1U) +/* @brief Has process identifier support. */ +#define FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1U) +/* @brief Specifies total number of bus masters. */ +#define FEATURE_MPU_MASTER_COUNT (3U) +/* @brief Specifies maximum number of masters which have separated +privilege rights for user and supervisor mode accesses (e.g. master0~3 in S32K1xx). +*/ +#define FEATURE_MPU_MAX_LOW_MASTER_NUMBER (3U) +/* @brief Specifies maximum number of masters which have only +read and write permissions (e.g. master4~7 in S32K1xx). +*/ +#define FEATURE_MPU_MAX_HIGH_MASTER_NUMBER (7U) + +/* @brief Specifies number of set access control right bits for + masters which have separated privilege rights for user and + supervisor mode accesses (e.g. master0~3 in S32K1xx). +*/ +#define FEATURE_MPU_LOW_MASTER_CONTROL_WIDTH (6U) +/* @brief Specifies number of set access control right bits for + masters which have only read and write permissions(e.g. master4~7 in S32K1xx). +*/ +#define FEATURE_MPU_HIGH_MASTER_CONTROL_WIDTH (2U) + +/* @brief The MPU Logical Bus Master Number for core bus master. */ +#define FEATURE_MPU_MASTER_CORE (0U) +/* @brief The MPU Logical Bus Master Number for Debugger master. */ +#define FEATURE_MPU_MASTER_DEBUGGER (1U) +/* @brief The MPU Logical Bus Master Number for DMA master. */ +#define FEATURE_MPU_MASTER_DMA (2U) +/* @brief Specifies master number. */ +#define FEATURE_MPU_MASTER \ +{ \ + FEATURE_MPU_MASTER_CORE, /*!< CORE */ \ + FEATURE_MPU_MASTER_DEBUGGER, /*!< DEBUGGER */ \ + FEATURE_MPU_MASTER_DMA, /*!< DMA */ \ +} + +/* @brief Specifies total number of slave ports. */ +#define FEATURE_MPU_SLAVE_COUNT (2U) +/* @brief The MPU Slave Port Assignment for Flash Controller and boot ROM. */ +#define FEATURE_MPU_SLAVE_FLASH_BOOTROM (0U) +/* @brief The MPU Slave Port Assignment for SRAM, MTB, DWT and MCM. */ +#define FEATURE_MPU_SLAVE_SRAM_MTB_DWT_MCM (1U) +/* @brief The MPU Slave Port mask. */ +#define FEATURE_MPU_SLAVE_MASK (0xC0000000U) +#define FEATURE_MPU_SLAVE_SHIFT (30u) +#define FEATURE_MPU_SLAVE_WIDTH (2u) +#define FEATURE_MPU_SLAVE(x) (((uint32_t)(((uint32_t)(x))<> (uint32_t)FEATURE_DMA_CH_WIDTH) +/* @brief DMA virtual channel to channel */ +#define FEATURE_DMA_VCH_TO_CH(x) ((x) & ((uint32_t)FEATURE_DMA_CHANNELS - 1U)) +/* @brief DMA supports the following particular channel priorities: */ +#define FEATURE_DMA_4_CH_PRIORITIES +/* @brief DMA supports bus bandwidth control. */ +#define FEATURE_DMA_ENGINE_STALL + +/* DMAMUX module features */ + +/* @brief DMAMUX peripheral is available in silicon. */ +#define FEATURE_DMAMUX_AVAILABLE +/* @brief Number of DMA channels. */ +#define FEATURE_DMAMUX_CHANNELS (4U) +/* @brief Has the periodic trigger capability */ +#define FEATURE_DMAMUX_HAS_TRIG (1) +/* @brief Conversion from request source to the actual DMAMUX channel */ +#define FEATURE_DMAMUX_REQ_SRC_TO_CH(x) (x) +/* @brief Mapping between request source and DMAMUX instance */ +#define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x) (0U) +/* @brief Conversion from eDMA channel index to DMAMUX channel. */ +#define FEATURE_DMAMUX_DMA_CH_TO_CH(x) (x) +/* @brief Conversion from DMAMUX channel DMAMUX register index. */ +#define FEATURE_DMAMUX_CHN_REG_INDEX(x) (x) +/* @brief Clock names for DMAMUX. */ +#define FEATURE_DMAMUX_CLOCK_NAMES {DMAMUX0_CLK} + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum { + EDMA_REQ_DISABLED = 0U, + EDMA_REQ_LPUART0_RX = 2U, + EDMA_REQ_LPUART0_TX = 3U, + EDMA_REQ_LPUART1_RX = 4U, + EDMA_REQ_LPUART1_TX = 5U, + EDMA_REQ_FLEXIO_SHIFTER0 = 10U, + EDMA_REQ_FLEXIO_SHIFTER1 = 11U, + EDMA_REQ_FLEXIO_SHIFTER2 = 12U, + EDMA_REQ_FLEXIO_SHIFTER3 = 13U, + EDMA_REQ_LPSPI0_RX = 14U, + EDMA_REQ_LPSPI0_TX = 15U, + EDMA_REQ_LPSPI1_RX = 16U, + EDMA_REQ_LPSPI1_TX = 17U, + EDMA_REQ_FTM1_CHANNEL_0 = 20U, + EDMA_REQ_FTM1_CHANNEL_1 = 21U, + EDMA_REQ_FTM1_CHANNEL_2 = 22U, + EDMA_REQ_FTM1_CHANNEL_3 = 23U, + EDMA_REQ_FTM1_CHANNEL_4 = 24U, + EDMA_REQ_FTM1_CHANNEL_5 = 25U, + EDMA_REQ_FTM1_CHANNEL_6 = 26U, + EDMA_REQ_FTM1_CHANNEL_7 = 27U, + EDMA_REQ_FTM0_OR_CH0_CH7 = 36U, + EDMA_REQ_ADC0 = 42U, + EDMA_REQ_LPI2C0_RX = 44U, + EDMA_REQ_LPI2C0_TX = 45U, + EDMA_REQ_PDB0 = 46U, + EDMA_REQ_CMP0 = 48U, + EDMA_REQ_PORTA = 49U, + EDMA_REQ_PORTB = 50U, + EDMA_REQ_PORTC = 51U, + EDMA_REQ_PORTD = 52U, + EDMA_REQ_PORTE = 53U, + EDMA_REQ_FLEXCAN0 = 54U, + EDMA_REQ_LPTMR0 = 59U, + EDMA_REQ_DMAMUX_ALWAYS_ENABLED0 = 62U, + EDMA_REQ_DMAMUX_ALWAYS_ENABLED1 = 63U +} dma_request_source_t; + + +/* TRGMUX module features */ +/*! + * @brief Enumeration for trigger source module of TRGMUX + * + * Describes all possible inputs (trigger sources) of the TRGMUX IP + * This enumeration depends on the supported instances in device + */ +enum trgmux_trigger_source_e +{ + TRGMUX_TRIG_SOURCE_DISABLED = 0U, + TRGMUX_TRIG_SOURCE_VDD = 1U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN0 = 2U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN1 = 3U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN2 = 4U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN3 = 5U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN4 = 6U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN5 = 7U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN6 = 8U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN7 = 9U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN8 = 10U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN9 = 11U, + TRGMUX_TRIG_SOURCE_CMP0_OUT = 14U, + TRGMUX_TRIG_SOURCE_LPIT_CH0 = 17U, + TRGMUX_TRIG_SOURCE_LPIT_CH1 = 18U, + TRGMUX_TRIG_SOURCE_LPIT_CH2 = 19U, + TRGMUX_TRIG_SOURCE_LPIT_CH3 = 20U, + TRGMUX_TRIG_SOURCE_LPTMR0 = 21U, + TRGMUX_TRIG_SOURCE_FTM0_INIT_TRIG = 22U, + TRGMUX_TRIG_SOURCE_FTM0_EXT_TRIG = 23U, + TRGMUX_TRIG_SOURCE_FTM1_INIT_TRIG = 24U, + TRGMUX_TRIG_SOURCE_FTM1_EXT_TRIG = 25U, + TRGMUX_TRIG_SOURCE_ADC0_SC1A_COCO = 30U, + TRGMUX_TRIG_SOURCE_ADC0_SC1B_COCO = 31U, + TRGMUX_TRIG_SOURCE_PDB0_CH0_TRIG = 34U, + TRGMUX_TRIG_SOURCE_PDB0_PULSE_OUT = 36U, + TRGMUX_TRIG_SOURCE_RTC_ALARM = 43U, + TRGMUX_TRIG_SOURCE_RTC_SECOND = 44U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG0 = 45U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG1 = 46U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG2 = 47U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG3 = 48U, + TRGMUX_TRIG_SOURCE_LPUART0_RX_DATA = 49U, + TRGMUX_TRIG_SOURCE_LPUART0_TX_DATA = 50U, + TRGMUX_TRIG_SOURCE_LPUART0_RX_IDLE = 51U, + TRGMUX_TRIG_SOURCE_LPUART1_RX_DATA = 52U, + TRGMUX_TRIG_SOURCE_LPUART1_TX_DATA = 53U, + TRGMUX_TRIG_SOURCE_LPUART1_RX_IDLE = 54U, + TRGMUX_TRIG_SOURCE_LPI2C0_MASTER_TRIG = 55U, + TRGMUX_TRIG_SOURCE_LPI2C0_SLAVE_TRIG = 56U, + TRGMUX_TRIG_SOURCE_LPSPI0_FRAME = 59U, + TRGMUX_TRIG_SOURCE_LPSPI0_RX_DATA = 60U, + TRGMUX_TRIG_SOURCE_LPSPI1_FRAME = 61U, + TRGMUX_TRIG_SOURCE_LPSPI1_RX_DATA = 62U, + TRGMUX_TRIG_SOURCE_SIM_SW_TRIG = 63U, +}; + +/*! + * @brief Enumeration for target module of TRGMUX + * + * Describes all possible outputs (target modules) of the TRGMUX IP + * This enumeration depends on the supported instances in device + */ +enum trgmux_target_module_e +{ + TRGMUX_TARGET_MODULE_DMA_CH0 = 0U, + TRGMUX_TARGET_MODULE_DMA_CH1 = 1U, + TRGMUX_TARGET_MODULE_DMA_CH2 = 2U, + TRGMUX_TARGET_MODULE_DMA_CH3 = 3U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT0 = 4U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT1 = 5U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT2 = 6U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT3 = 7U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT4 = 8U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT5 = 9U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA0 = 12U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA1 = 13U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA2 = 14U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA3 = 15U, + TRGMUX_TARGET_MODULE_CMP0_SAMPLE = 28U, + TRGMUX_TARGET_MODULE_FTM0_HWTRIG0 = 40U, + TRGMUX_TARGET_MODULE_FTM0_FAULT0 = 41U, + TRGMUX_TARGET_MODULE_FTM0_FAULT1 = 42U, + TRGMUX_TARGET_MODULE_FTM0_FAULT2 = 43U, + TRGMUX_TARGET_MODULE_FTM1_HWTRIG0 = 44U, + TRGMUX_TARGET_MODULE_FTM1_FAULT0 = 45U, + TRGMUX_TARGET_MODULE_FTM1_FAULT1 = 46U, + TRGMUX_TARGET_MODULE_FTM1_FAULT2 = 47U, + TRGMUX_TARGET_MODULE_PDB0_TRG_IN = 56U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM0 = 68U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM1 = 69U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM2 = 70U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM3 = 71U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH0 = 72U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH1 = 73U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH2 = 74U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH3 = 75U, + TRGMUX_TARGET_MODULE_LPUART0_TRG = 76U, + TRGMUX_TARGET_MODULE_LPUART1_TRG = 80U, + TRGMUX_TARGET_MODULE_LPI2C0_TRG = 84U, + TRGMUX_TARGET_MODULE_LPSPI0_TRG = 92U, + TRGMUX_TARGET_MODULE_LPSPI1_TRG = 96U, + TRGMUX_TARGET_MODULE_LPTMR0_ALT0 = 100U, +}; + +/* @brief Constant array storing the value of all TRGMUX output(target module) identifiers */ +#define FEATURE_TRGMUX_TARGET_MODULE \ +{ \ + TRGMUX_TARGET_MODULE_DMA_CH0, \ + TRGMUX_TARGET_MODULE_DMA_CH1, \ + TRGMUX_TARGET_MODULE_DMA_CH2, \ + TRGMUX_TARGET_MODULE_DMA_CH3, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT0, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT1, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT2, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT3, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT4, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT5, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA0, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA1, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA2, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA3, \ + TRGMUX_TARGET_MODULE_CMP0_SAMPLE, \ + TRGMUX_TARGET_MODULE_FTM0_HWTRIG0, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT0, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT1, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT2, \ + TRGMUX_TARGET_MODULE_FTM1_HWTRIG0, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT0, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT1, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT2, \ + TRGMUX_TARGET_MODULE_PDB0_TRG_IN, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM0, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM1, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM2, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM3, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH0, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH1, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH2, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH3, \ + TRGMUX_TARGET_MODULE_LPUART0_TRG, \ + TRGMUX_TARGET_MODULE_LPUART1_TRG, \ + TRGMUX_TARGET_MODULE_LPI2C0_TRG, \ + TRGMUX_TARGET_MODULE_LPSPI0_TRG, \ + TRGMUX_TARGET_MODULE_LPSPI1_TRG, \ + TRGMUX_TARGET_MODULE_LPTMR0_ALT0 \ +} + + +/* LPSPI module features */ +/* @brief Initial value for state structure */ +#define FEATURE_LPSPI_STATE_STRUCTURES_NULL {NULL, NULL} +/* @brief Clock indexes for LPSPI clock */ +#define FEATURE_LPSPI_CLOCKS_NAMES {LPSPI0_CLK, LPSPI1_CLK}; + +/* FlexIO module features */ + +/* @brief Define the maximum number of shifters for any FlexIO instance. */ +#define FEATURE_FLEXIO_MAX_SHIFTER_COUNT (4U) +/* @brief Define DMA request names for Flexio. */ +#define FEATURE_FLEXIO_DMA_REQ_0 EDMA_REQ_FLEXIO_SHIFTER0 +#define FEATURE_FLEXIO_DMA_REQ_1 EDMA_REQ_FLEXIO_SHIFTER1 +#define FEATURE_FLEXIO_DMA_REQ_2 EDMA_REQ_FLEXIO_SHIFTER2 +#define FEATURE_FLEXIO_DMA_REQ_3 EDMA_REQ_FLEXIO_SHIFTER3 + +/* LPUART module features */ + +/* @brief Has extended data register ED. */ +#define FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FEATURE_LPUART_FIFO_SIZE (4U) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits. */ +#define FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Flag clearance mask for STAT register. */ +#define FEATURE_LPUART_STAT_REG_FLAGS_MASK (0xC01FC000U) +/* @brief Flag clearance mask for FIFO register. */ +#define FEATURE_LPUART_FIFO_REG_FLAGS_MASK (0x00030000U) +/* @brief Reset mask for FIFO register. */ +#define FEATURE_LPUART_FIFO_RESET_MASK (0x0003C000U) +/* @brief Default oversampling ratio. */ +#define FEATURE_LPUART_DEFAULT_OSR (0x0FUL) +/* @brief Default baud rate modulo divisor. */ +#define FEATURE_LPUART_DEFAULT_SBR (0x04UL) +/* @brief Clock names for LPUART. */ +#define LPUART_CLOCK_NAMES {LPUART0_CLK, LPUART1_CLK} + +/* ADC module features */ + +/*! @brief ADC feature flag for extended number of SC1 and R registers, + * generically named 'alias registers' */ +#define FEATURE_ADC_HAS_EXTRA_NUM_REGS (0) + +#define NUMBER_OF_ALT_CLOCKS ADC_CLK_ALT_1 +/*! @brief ADC feature flag for defining number of external ADC channels. + * If each ADC instance has different number of external channels, then + * this define is set with the maximum value. */ +#define FEATURE_ADC_MAX_NUM_EXT_CHANS (16) +#define FEATURE_ADC_HAS_CHANNEL_2 (1) +#define FEATURE_ADC_HAS_CHANNEL_8 (1) +#define ADC_CLOCKS {ADC0_CLK} +/*! @brief ADC number of control channels */ +#if FEATURE_ADC_HAS_EXTRA_NUM_REGS +#define ADC_CTRL_CHANS_COUNT ADC_aSC1_COUNT +#else +#define ADC_CTRL_CHANS_COUNT ADC_SC1_COUNT +#endif /* FEATURE_ADC_HAS_EXTRA_NUM_REGS */ + +/*! @brief ADC default Sample Time from RM */ +#define ADC_DEFAULT_SAMPLE_TIME (0x0CU) +/*! @brief ADC default User Gain from RM */ +#define ADC_DEFAULT_USER_GAIN (0x04U) +/* @brief Max of adc clock frequency */ +#define ADC_CLOCK_FREQ_MAX_RUNTIME (50000000u) +/* @brief Min of adc clock frequency */ +#define ADC_CLOCK_FREQ_MIN_RUNTIME (2000000u) + +/* CAN module features */ + +/* @brief Frames available in Rx FIFO flag shift */ +#define FEATURE_CAN_RXFIFO_FRAME_AVAILABLE (5U) +/* @brief Rx FIFO warning flag shift */ +#define FEATURE_CAN_RXFIFO_WARNING (6U) +/* @brief Rx FIFO overflow flag shift */ +#define FEATURE_CAN_RXFIFO_OVERFLOW (7U) +/* @brief Has Flexible Data Rate for CAN0 */ +#define FEATURE_CAN0_HAS_FD (1) +/* @brief Maximum number of Message Buffers supported for payload size 8 for CAN0 */ +#define FEATURE_CAN0_MAX_MB_NUM (32U) +/* @brief Has PE clock source select (bit field CAN_CTRL1[CLKSRC]). */ +#define FEATURE_CAN_HAS_PE_CLKSRC_SELECT (1) +/* @brief Has DMA enable (bit field MCR[DMA]). */ +#define FEATURE_CAN_HAS_DMA_ENABLE (1) +/* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */ +#define FEATURE_CAN_MAX_MB_NUM (32U) +/* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */ +#define FEATURE_CAN_MAX_MB_NUM_ARRAY { FEATURE_CAN0_MAX_MB_NUM } +/* @brief Has Pretending Networking mode */ +#define FEATURE_CAN_HAS_PRETENDED_NETWORKING (1) +/* @brief Has Stuff Bit Count Enable Bit */ +#define FEATURE_CAN_HAS_STFCNTEN_ENABLE (0) +/* @brief Has ISO CAN FD Enable Bit */ +#define FEATURE_CAN_HAS_ISOCANFDEN_ENABLE (1) +/* @brief Has Message Buffer Data Size Region 1 */ +#define FEATURE_CAN_HAS_MBDSR1 (0) +/* @brief Has Message Buffer Data Size Region 2 */ +#define FEATURE_CAN_HAS_MBDSR2 (0) +/* @brief DMA hardware requests for all FlexCAN instances */ +#define FEATURE_CAN_EDMA_REQUESTS { EDMA_REQ_FLEXCAN0 } + +/* @brief Maximum number of Message Buffers IRQs */ +#define FEATURE_CAN_MB_IRQS_MAX_COUNT (2U) +/* @brief Message Buffers IRQs */ +#define FEATURE_CAN_MB_IRQS { CAN_ORed_0_15_MB_IRQS, \ + CAN_ORed_16_31_MB_IRQS } +/* @brief Has Wake Up Irq channels (CAN_Wake_Up_IRQS_CH_COUNT > 0u) */ +#define FEATURE_CAN_HAS_WAKE_UP_IRQ (1) +/* @brief Has Self Wake Up mode */ +#define FEATURE_CAN_HAS_SELF_WAKE_UP (0) +/* @brief Has Flexible Data Rate */ +#define FEATURE_CAN_HAS_FD (1) +/* @brief Clock name for the PE oscillator clock source */ +#define FEATURE_CAN_PE_OSC_CLK_NAME SOSC_CLK +/* @bried FlexCAN has Detection And Correction of Memory Errors */ +#define FEATURE_CAN_HAS_MEM_ERR_DET (0) + +/* LPTMR module features */ + +/* @brief LPTMR pulse counter input options */ +#define FEATURE_LPTMR_HAS_INPUT_ALT1_SELECTION (1U) + +/* OSIF module features */ + +#define FEATURE_OSIF_USE_SYSTICK (1) +#define FEATURE_OSIF_USE_PIT (0) +#define FEATURE_OSIF_FREERTOS_ISR_CONTEXT_METHOD (1) /* Cortex M device */ + +/* PDB module features */ + +/* @brief PDB has back-to-back at instance level */ +#define FEATURE_PDB_HAS_INSTANCE_BACKTOBACK (0) + +#endif /* S32K118_FEATURES_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/devassert.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/devassert.h new file mode 100644 index 00000000..243c8d45 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/devassert.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DEVASSERT_H +#define DEVASSERT_H + +#include + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced. + * The macro is defined to be used by drivers to validate input parameters and can be disabled. + * + * @section [global] + * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro defined. + * The macros are used to validate input parameters to driver functions. + * + */ + +/** +\page Error_detection_and_reporting Error detection and reporting + +S32 SDK drivers can use a mechanism to validate data coming from upper software layers (application code) by performing +a number of checks on input parameters' range or other invariants that can be statically checked (not dependent on +runtime conditions). A failed validation is indicative of a software bug in application code, therefore it is important +to use this mechanism during development. + +The validation is performed by using DEV_ASSERT macro. +A default implementation of this macro is provided in this file. However, application developers can provide their own +implementation in a custom file. This requires defining the CUSTOM_DEVASSERT symbol with the specific file name in the +project configuration (for example: -DCUSTOM_DEVASSERT="custom_devassert.h") + +The default implementation accommodates two behaviors, based on DEV_ERROR_DETECT symbol: + - When DEV_ERROR_DETECT symbol is defined in the project configuration (for example: -DDEV_ERROR_DETECT), the validation + performed by the DEV_ASSERT macro is enabled, and a failed validation triggers a software breakpoint and further execution is + prevented (application spins in an infinite loop) + This configuration is recommended for development environments, as it prevents further execution and allows investigating + potential problems from the point of error detection. + - When DEV_ERROR_DETECT symbol is not defined, the DEV_ASSERT macro is implemented as no-op, therefore disabling all validations. + This configuration can be used to eliminate the overhead of development-time checks. + +It is the application developer's responsibility to decide the error detection strategy for production code: one can opt to +disable development-time checking altogether (by not defining DEV_ERROR_DETECT symbol), or one can opt to keep the checks +in place and implement a recovery mechanism in case of a failed validation, by defining CUSTOM_DEVASSERT to point +to the file containing the custom implementation. +*/ + +#if defined (CUSTOM_DEVASSERT) + /* If the CUSTOM_DEVASSERT symbol is defined, then add the custom implementation */ + #include CUSTOM_DEVASSERT +#elif defined (DEV_ERROR_DETECT) + /* Implement default assert macro */ +static inline void DevAssert(volatile bool x) +{ + if(x) { } else { BKPT_ASM; for(;;) {} } +} + #define DEV_ASSERT(x) DevAssert(x) +#else + /* Assert macro does nothing */ + #define DEV_ASSERT(x) ((void)0) +#endif + +#endif /* DEVASSERT_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/device_registers.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/device_registers.h new file mode 100644 index 00000000..583a35d5 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/device_registers.h @@ -0,0 +1,67 @@ +/* +** ################################################################### +** Abstract: +** Common include file for CMSIS register access layer headers. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** ################################################################### +*/ + +#ifndef DEVICE_REGISTERS_H +#define DEVICE_REGISTERS_H + +/** +* @page misra_violations MISRA-C:2012 violations +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced. +* The macro defines the device currently in use and may be used by components for specific checks. +* +*/ + + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ + +#if defined(CPU_S32K118) + + #define S32K11x_SERIES + + /* Specific core definitions */ + #include "s32_core_cm0.h" + /* Register definitions */ + #include "S32K118.h" + /* CPU specific feature definitions */ + #include "S32K118_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#include "devassert.h" + +#endif /* DEVICE_REGISTERS_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/s32_core_cm0.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/s32_core_cm0.h new file mode 100644 index 00000000..2dcd6e17 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/s32_core_cm0.h @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/*! + * @file s32_core_cm0.h + * + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro + * Function-like macros are used instead of inline functions in order to ensure + * that the performance will not be decreased if the functions will not be + * inlined by the compiler. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. + * The macros defined are used only on some of the drivers, so this might be reported + * when the analysis is made only on one driver. + */ + +/* + * Tool Chains: + * GNUC flag is defined also by ARM compiler - it shows the current major version of the compatible GCC version + * __GNUC__ : GNU Compiler Collection + * __ghs__ : Green Hills ARM Compiler + * __ICCARM__ : IAR ARM Compiler + * __DCC__ : Wind River Diab Compiler + * __ARMCC_VERSION : ARM Compiler + */ + +#if !defined (CORE_CM0_H) +#define CORE_CM0_H + + +#ifdef __cplusplus +extern "C" { +#endif + +/** \brief BKPT_ASM + * + * Macro to be used to trigger an debug interrupt + */ +#if defined ( __DCC__ ) +#define BKPT_ASM __asm ("BKPT 0\n\t") +#else +#define BKPT_ASM __asm ("BKPT #0\n\t") +#endif + +/** \brief Enable interrupts + */ +#if defined (__GNUC__) +#define ENABLE_INTERRUPTS() __asm volatile ("cpsie i" : : : "memory"); +#elif defined ( __DCC__ ) +#define ENABLE_INTERRUPTS() __asm (".short 0xb662"); +#else +#define ENABLE_INTERRUPTS() __asm("cpsie i") +#endif + + +/** \brief Disable interrupts + */ +#if defined (__GNUC__) +#define DISABLE_INTERRUPTS() __asm volatile ("cpsid i" : : : "memory"); +#elif defined ( __DCC__ ) +#define DISABLE_INTERRUPTS() __asm (".short 0xb672"); +#else +#define DISABLE_INTERRUPTS() __asm("cpsid i") +#endif + + +/** \brief Enter low-power standby state + * WFI (Wait For Interrupt) makes the processor suspend execution (Clock is stopped) until an IRQ interrupts. + */ +#if defined (__GNUC__) +#define STANDBY() __asm volatile ("wfi") +#elif defined ( __DCC__ ) +#define STANDBY() __asm (".short 0xbf30"); +#else +#define STANDBY() __asm ("wfi") +#endif + +/** \brief No-op + */ +#define NOP() __asm volatile ("nop") + + +/** \brief Reverse byte order in a word. + * ARM Documentation Cortex-M0 Devices Generic User Guide + * Accordingly to 3.5.7. REV, REV16, and REVSH + * Restriction "This function requires low registers R0-R7 register" + */ +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ARMCC_VERSION) +#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=l" (b) : "l" (a)) +#elif defined (__ghs__) +#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=r" (b) : "r" (a)) +#else +#define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \ + | ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U)) +#endif + +/** \brief Reverse byte order in each halfword independently. + * ARM Documentation Cortex-M0 Devices Generic User Guide + * Accordingly to 3.5.7. REV, REV16, and REVSH + * Restriction "This function requires low registers R0-R7 register" + */ +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ARMCC_VERSION) +#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=l" (b) : "l" (a)) +#elif defined (__ghs__) +#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=r" (b) : "r" (a)) +#else +#define REV_BYTES_16(a, b) (b = ((a & 0xFF000000U) >> 8U) | ((a & 0xFF0000U) << 8U) \ + | ((a & 0xFF00U) >> 8U) | ((a & 0xFFU) << 8U)) +#endif + +/** \brief Places a function in RAM. + */ +#if defined ( __GNUC__ ) || defined (__ARMCC_VERSION) + #define START_FUNCTION_DECLARATION_RAMSECTION + #define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram"))); +#elif defined ( __ghs__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("ghs callmode=far") + #define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));\ + _Pragma("ghs callmode=default") +#elif defined ( __ICCARM__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION __ramfunc + #define END_FUNCTION_DECLARATION_RAMSECTION ; +#elif defined ( __DCC__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("section CODE \".code_ram\" \"\" far-absolute") \ + _Pragma("use_section CODE") + #define END_FUNCTION_DECLARATION_RAMSECTION ; \ + _Pragma("section CODE \".text\"") +#else + /* Keep compatibility with software analysis tools */ + #define START_FUNCTION_DECLARATION_RAMSECTION + #define END_FUNCTION_DECLARATION_RAMSECTION ; +#endif + + /* For GCC, IAR, GHS, Diab and ARMC there is no need to specify the section when + defining a function, it is enough to specify it at the declaration. This + also enables compatibility with software analysis tools. */ + #define START_FUNCTION_DEFINITION_RAMSECTION + #define END_FUNCTION_DEFINITION_RAMSECTION + +#if defined (__ICCARM__) + #define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_suppress=Ta022") + #define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_default=Ta022") +#else + #define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL + #define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL +#endif + +/** \brief Get Core ID + * + * GET_CORE_ID returns the processor identification number for cm0 + */ +#define GET_CORE_ID() 0U + +/** \brief Data alignment. + */ +#if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION) + #define ALIGNED(x) __attribute__((aligned(x))) +#elif defined ( __ICCARM__ ) + #define stringify(s) tostring(s) + #define tostring(s) #s + #define ALIGNED(x) _Pragma(stringify(data_alignment=x)) +#else + /* Keep compatibility with software analysis tools */ + #define ALIGNED(x) +#endif + +/** \brief Endianness. + */ +#define CORE_LITTLE_ENDIAN + +#ifdef __cplusplus +} +#endif + +#endif /* CORE_CM0_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/startup.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/startup.c new file mode 100644 index 00000000..2d0efc61 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/startup.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * All variables with this problem are defined in the linker files. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.11, When an array with external linkage + * is declared, its size should be explicitly specified. + * The size of the arrays can not be explicitly determined. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed + * between a pointer to object and an integer type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed + * between pointer to void and an arithmetic type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 2.1, A project shall not contain unreachable + * code. + * The condition compares two address defined in linker files that can be different. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. + * Function is defined for usage by application code. + * + * @section [global] + * Violates MISRA 2012 Mandatory Rule 17.3, Symbol 'MFSPR' undeclared, assumed + * to return int. + * This is an e200 Power Architecture Assembly instruction used to retrieve + * the core number. + * + */ + +#include "startup.h" +#include + + +/******************************************************************************* + * Static Variables + ******************************************************************************/ +static volatile uint32_t * const s_vectors[NUMBER_OF_CORES] = FEATURE_INTERRUPT_INT_VECTORS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : init_data_bss + * Description : Make necessary initializations for RAM. + * - Copy the vector table from ROM to RAM. + * - Copy initialized data from ROM to RAM. + * - Copy code that should reside in RAM from ROM + * - Clear the zero-initialized data section. + * + * Tool Chains: + * __GNUC__ : GNU Compiler Collection + * __ghs__ : Green Hills ARM Compiler + * __ICCARM__ : IAR ARM Compiler + * __DCC__ : Wind River Diab Compiler + * __ARMCC_VERSION : ARMC Compiler + * + * Implements : init_data_bss_Activity + *END**************************************************************************/ +void init_data_bss(void) +{ + uint32_t n; + uint8_t coreId; +/* For ARMC we are using the library method of initializing DATA, Custom Section and + * Code RAM sections so the below variables are not needed */ +#if !defined(__ARMCC_VERSION) + /* Declare pointers for various data sections. These pointers + * are initialized using values pulled in from the linker file */ + uint8_t * data_ram; + uint8_t * code_ram; + uint8_t * bss_start; + uint8_t * custom_ram; + const uint8_t * data_rom, * data_rom_end; + const uint8_t * code_rom, * code_rom_end; + const uint8_t * bss_end; + const uint8_t * custom_rom, * custom_rom_end; +#endif + /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ + +#if defined(__ARMCC_VERSION) + extern uint32_t __RAM_VECTOR_TABLE_SIZE; + extern uint32_t __VECTOR_ROM; + extern uint32_t __VECTOR_RAM; +#else + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#endif + /* Get section information from linker files */ +#if defined(__ICCARM__) + /* Data */ + data_ram = __section_begin(".data"); + data_rom = __section_begin(".data_init"); + data_rom_end = __section_end(".data_init"); + + /* CODE RAM */ + #pragma section = "__CODE_ROM" + #pragma section = "__CODE_RAM" + code_ram = __section_begin("__CODE_RAM"); + code_rom = __section_begin("__CODE_ROM"); + code_rom_end = __section_end("__CODE_ROM"); + + /* BSS */ + bss_start = __section_begin(".bss"); + bss_end = __section_end(".bss"); + + custom_ram = __section_begin(".customSection"); + custom_rom = __section_begin(".customSection_init"); + custom_rom_end = __section_end(".customSection_init"); + +#elif defined (__ARMCC_VERSION) + /* VECTOR TABLE*/ + uint8_t * vector_table_size = (uint8_t *)__RAM_VECTOR_TABLE_SIZE; + uint32_t * vector_rom = (uint32_t *)__VECTOR_ROM; + uint32_t * vector_ram = (uint32_t *)__VECTOR_RAM; +#else + extern uint32_t __DATA_ROM[]; + extern uint32_t __DATA_RAM[]; + extern uint32_t __DATA_END[]; + + extern uint32_t __CODE_RAM[]; + extern uint32_t __CODE_ROM[]; + extern uint32_t __CODE_END[]; + + extern uint32_t __BSS_START[]; + extern uint32_t __BSS_END[]; + + extern uint32_t __CUSTOM_ROM[]; + extern uint32_t __CUSTOM_END[]; + + /* Data */ + data_ram = (uint8_t *)__DATA_RAM; + data_rom = (uint8_t *)__DATA_ROM; + data_rom_end = (uint8_t *)__DATA_END; + /* CODE RAM */ + code_ram = (uint8_t *)__CODE_RAM; + code_rom = (uint8_t *)__CODE_ROM; + code_rom_end = (uint8_t *)__CODE_END; + /* BSS */ + bss_start = (uint8_t *)__BSS_START; + bss_end = (uint8_t *)__BSS_END; + + /* Custom section */ + custom_ram = CUSTOMSECTION_SECTION_START; + custom_rom = (uint8_t *)__CUSTOM_ROM; + custom_rom_end = (uint8_t *)__CUSTOM_END; + +#endif + +#if !defined(__ARMCC_VERSION) + /* Copy initialized data from ROM to RAM */ + while (data_rom_end != data_rom) + { + *data_ram = *data_rom; + data_ram++; + data_rom++; + } + + /* Copy functions from ROM to RAM */ + while (code_rom_end != code_rom) + { + *code_ram = *code_rom; + code_ram++; + code_rom++; + } + + /* Clear the zero-initialized data section */ + while(bss_end != bss_start) + { + *bss_start = 0; + bss_start++; + } + + /* Copy customsection rom to ram */ + while(custom_rom_end != custom_rom) + { + *custom_ram = *custom_rom; + custom_rom++; + custom_ram++; + } +#endif + coreId = (uint8_t)GET_CORE_ID(); +#if defined (__ARMCC_VERSION) + /* Copy the vector table from ROM to RAM */ + /* Workaround */ + for (n = 0; n < (((uint32_t)(vector_table_size))/sizeof(uint32_t)); n++) + { + vector_ram[n] = vector_rom[n]; + } + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t) __VECTOR_RAM; +#else + /* Check if VECTOR_TABLE copy is needed */ + if (__VECTOR_RAM != __VECTOR_TABLE) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < (((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t)); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t)__VECTOR_RAM; + } + else + { + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t)__VECTOR_TABLE; + } +#endif + +} + +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/startup.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/startup.h new file mode 100644 index 00000000..8384b7db --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/startup.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef STARTUP_H +#define STARTUP_H + +#include +#include "device_registers.h" +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, Local macro not referenced. + * The defined macro is used as include guard. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * All variables with this problem are defined in the linker files. + * + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief define symbols that specific start and end addres of some basic sections. + */ +#if (defined(S32K14x_SERIES) || defined(S32K11x_SERIES) || defined(S32V234_SERIES) || defined(MPC574x_SERIES) || defined(S32R_SERIES) || defined(S32MTV_SERIES) || defined(SJA1110_SERIES)) || defined (S32K144W_M4_SERIES) + #if (defined(__ICCARM__)) + #define INTERRUPTS_SECTION_START __section_begin(".intvec") + #define INTERRUPTS_SECTION_END __section_end(".intvec") + #define BSS_SECTION_START __section_begin(".bss") + #define BSS_SECTION_END __section_end(".bss") + #define DATA_SECTION_START __section_begin(".data") + #define DATA_SECTION_END __section_end(".data") + #define CUSTOMSECTION_SECTION_START __section_begin(".customSection") + #define CUSTOMSECTION_SECTION_END __section_end(".customSection") + #define CODE_RAM_SECTION_START __section_begin("__CODE_RAM") + #define CODE_RAM_SECTION_END __section_end("__CODE_RAM") + #define DATA_INIT_SECTION_START __section_begin(".data_init") + #define DATA_INIT_SECTION_END __section_end(".data_init") + #define CODE_ROM_SECTION_START __section_begin("__CODE_ROM") + #define CODE_ROM_SECTION_END __section_end("__CODE_ROM") + + #elif (defined(__ARMCC_VERSION)) + #define INTERRUPTS_SECTION_START (uint8_t *)__VECTOR_ROM_START + #define INTERRUPTS_SECTION_END (uint8_t *)__VECTOR_ROM_END + #define BSS_SECTION_START (uint8_t *)__BSS_START + #define BSS_SECTION_END (uint8_t *)__BSS_END + #define DATA_SECTION_START (uint8_t *)__DATA_RAM_START + #define DATA_SECTION_END (uint8_t *)__DATA_RAM_END + #define CUSTOMSECTION_SECTION_START (uint8_t *)__CUSTOM_SECTION_START + #define CUSTOMSECTION_SECTION_END (uint8_t *)__CUSTOM_SECTION_END + #define CODE_RAM_SECTION_START (uint8_t *)__CODE_RAM_START + #define CODE_RAM_SECTION_END (uint8_t *)__CODE_RAM_END + + extern uint32_t __VECTOR_ROM_START; + extern uint32_t __VECTOR_ROM_END; + extern uint32_t __BSS_START; + extern uint32_t __BSS_END; + extern uint32_t __DATA_RAM_START; + extern uint32_t __DATA_RAM_END; + extern uint32_t __CUSTOM_SECTION_START; + extern uint32_t __CUSTOM_SECTION_END; + extern uint32_t __CODE_RAM_START; + extern uint32_t __CODE_RAM_END; + #else + #define INTERRUPTS_SECTION_START (uint8_t *)&__interrupts_start__ + #define INTERRUPTS_SECTION_END (uint8_t *)&__interrupts_end__ + #define BSS_SECTION_START (uint8_t *)&__bss_start__ + #define BSS_SECTION_END (uint8_t *)&__bss_end__ + #define DATA_SECTION_START (uint8_t *)&__data_start__ + #define DATA_SECTION_END (uint8_t *)&__data_end__ + #define CUSTOMSECTION_SECTION_START (uint8_t *)&__customSection_start__ + #define CUSTOMSECTION_SECTION_END (uint8_t *)&__customSection_end__ + #define CODE_RAM_SECTION_START (uint8_t *)&__code_ram_start__ + #define CODE_RAM_SECTION_END (uint8_t *)&__code_ram_end__ + + extern uint32_t __interrupts_start__; + extern uint32_t __interrupts_end__; + extern uint32_t __bss_start__; + extern uint32_t __bss_end__; + extern uint32_t __data_start__; + extern uint32_t __data_end__; + extern uint32_t __customSection_start__; + extern uint32_t __customSection_end__; + extern uint32_t __code_ram_start__; + extern uint32_t __code_ram_end__; + #endif +#endif + +#if (defined(__ICCARM__)) + #pragma section = ".data" + #pragma section = ".data_init" + #pragma section = ".bss" + #pragma section = ".intvec" + #pragma section = ".customSection" + #pragma section = ".customSection_init" + #pragma section = "__CODE_RAM" + #pragma section = "__CODE_ROM" +#endif + +/*! + * @brief Make necessary initializations for RAM. + * + * - Copy initialized data from ROM to RAM. + * - Clear the zero-initialized data section. + * - Copy the vector table from ROM to RAM. This could be an option. + */ +void init_data_bss(void); + +#endif /* STARTUP_H*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/system_S32K118.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/system_S32K118.c new file mode 100644 index 00000000..868b365b --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/system_S32K118.c @@ -0,0 +1,176 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * An object with static storage duration declared at block scope cannot be + * accessed directly from outside the block. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed + * between a pointer to object and an integer type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed + * between pointer to void and an arithmetic type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. + * Function is defined for usage by application code. + * + */ + +#include "device_registers.h" +#include "system_S32K118.h" +#include "stdbool.h" + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/*FUNCTION********************************************************************** + * + * Function Name : SystemInit + * Description : This function disables the watchdog, enables FPU + * and the power mode protection if the corresponding feature macro + * is enabled. SystemInit is called from startup_device file. + * + * Implements : SystemInit_Activity + *END**************************************************************************/ +void SystemInit(void) +{ +/**************************************************************************/ +/* WDOG DISABLE*/ +/**************************************************************************/ + +#if (DISABLE_WDOG) + /* Write of the WDOG unlock key to CNT register, must be done in order to allow any modifications*/ + WDOG->CNT = (uint32_t ) FEATURE_WDOG_UNLOCK_VALUE; + /* The dummy read is used in order to make sure that the WDOG registers will be configured only + * after the write of the unlock value was completed. */ + (void)WDOG->CNT; + + /* Initial write of WDOG configuration register: + * enables support for 32-bit refresh/unlock command write words, + * clock select from LPO, update enable, watchdog disabled */ + WDOG->CS = (uint32_t ) ( (1UL << WDOG_CS_CMD32EN_SHIFT) | + (FEATURE_WDOG_CLK_FROM_LPO << WDOG_CS_CLK_SHIFT) | + (0U << WDOG_CS_EN_SHIFT) | + (1U << WDOG_CS_UPDATE_SHIFT) ); + + /* Configure timeout */ + WDOG->TOVAL = (uint32_t )0xFFFF; +#endif /* (DISABLE_WDOG) */ +} + +/*FUNCTION********************************************************************** + * + * Function Name : SystemCoreClockUpdate + * Description : This function must be called whenever the core clock is changed + * during program execution. It evaluates the clock register settings and calculates + * the current core clock. + * + * Implements : SystemCoreClockUpdate_Activity + *END**************************************************************************/ +void SystemCoreClockUpdate(void) +{ + uint32_t SCGOUTClock = 0U; /* Variable to store output clock frequency of the SCG module */ + uint32_t regValue; /* Temporary variable */ + uint32_t divider; + bool validSystemClockSource = true; + + divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U; + + switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) + { + case 0x1: + /* System OSC */ + SCGOUTClock = CPU_XTAL_CLK_HZ; + break; + case 0x2: + /* Slow IRC */ + regValue = (SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT; + if (regValue != 0UL) + { + SCGOUTClock = FEATURE_SCG_SIRC_HIGH_RANGE_FREQ; + } + else + { + validSystemClockSource = false; + } + break; + case 0x3: + /* Fast IRC */ + regValue = (SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT; + if (regValue == 0x0UL) + { + SCGOUTClock = FEATURE_SCG_FIRC_FREQ0; + } + else + { + validSystemClockSource = false; + } + break; + default: + validSystemClockSource = false; + break; + } + + if (validSystemClockSource == true) + { + SystemCoreClock = (SCGOUTClock / divider); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : SystemSoftwareReset + * Description : This function is used to initiate a system reset + * + * Implements : SystemSoftwareReset_Activity + *END**************************************************************************/ +void SystemSoftwareReset(void) +{ + uint32_t regValue; + + /* Read Application Interrupt and Reset Control Register */ + regValue = S32_SCB->AIRCR; + + /* Clear register key */ + regValue &= ~( S32_SCB_AIRCR_VECTKEY_MASK); + + /* Configure System reset request bit and Register Key */ + regValue |= S32_SCB_AIRCR_VECTKEY(FEATURE_SCB_VECTKEY); + regValue |= S32_SCB_AIRCR_SYSRESETREQ(0x1u); + + /* Write computed register value */ + S32_SCB->AIRCR = regValue; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/system_S32K118.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/system_S32K118.h new file mode 100644 index 00000000..6e98f97f --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/system_S32K118.h @@ -0,0 +1,105 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*! @addtogroup soc_support_S32K118*/ +/*! @{*/ + +/*! + * @file system_S32K118.h + * @brief Device specific configuration file for S32K118 + */ + +#ifndef SYSTEM_S32K118_H_ +#define SYSTEM_S32K118_H_ /**< Symbol preventing repeated inclusion */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** + * CPU Settings. + *****************************************************************************/ + +/* Watchdog disable */ +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +/* Value of the external crystal or oscillator clock frequency in Hz */ +#ifndef CPU_XTAL_CLK_HZ + #define CPU_XTAL_CLK_HZ 8000000u +#endif + +/* Value of the fast internal oscillator clock frequency in Hz */ +#ifndef CPU_INT_FAST_CLK_HZ + #define CPU_INT_FAST_CLK_HZ 48000000u +#endif + +/* Default System clock value */ +#ifndef DEFAULT_SYSTEM_CLOCK + #define DEFAULT_SYSTEM_CLOCK 48000000u +#endif + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the SoC. + * + * This function disables the watchdog. + * if the corresponding feature macro is enabled. + * SystemInit is called from startup_device file. + */ +void SystemInit(void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + * This function must be called when user does not want to use clock manager component. + * If clock manager is used, the CLOCK_SYS_GetFreq function must be used with CORE_CLOCK + * parameter. + * + */ +void SystemCoreClockUpdate(void); + +/** + * @brief Initiates a system reset. + * + * This function is used to initiate a system reset + */ +void SystemSoftwareReset(void); + +#ifdef __cplusplus +} +#endif + +/*! @}*/ +#endif /* #if !defined(SYSTEM_S32K118_H_) */ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/main.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/main.c new file mode 100644 index 00000000..1ef5439f --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/main.c @@ -0,0 +1,184 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/main.c +* \brief Demo program application source file. +* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static void Init(void); +static void SystemClockConfig(void); + + +/************************************************************************************//** +** \brief This is the entry point for the bootloader application and is called +** by the reset interrupt vector after the C-startup routines executed. +** \return none. +** +****************************************************************************************/ +void main(void) +{ + /* Initialize the microcontroller. */ + Init(); + /* Initialize the bootloader interface */ + BootComInit(); + + /* Start the infinite program loop. */ + while (1) + { + /* Toggle LED with a fixed frequency. */ + LedToggle(); + /* Check for bootloader activation request */ + BootComCheckActivationRequest(); + } +} /*** end of main ***/ + + +/************************************************************************************//** +** \brief Initializes the microcontroller. +** \return none. +** +****************************************************************************************/ +static void Init(void) +{ + /* Configure the system clock. */ + SystemClockConfig(); + /* Enable the peripheral clock for the ports that are used. */ + PCC->PCCn[PCC_PORTB_INDEX] |= PCC_PCCn_CGC_MASK; + PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK; + +#if (BOOT_COM_RS232_ENABLE > 0) + /* UART RX GPIO pin configuration. PB0 = UART0 RX, MUX = ALT2. */ + PORTB->PCR[0] |= PORT_PCR_MUX(2); + /* UART TX GPIO pin configuration. PB1 = UART0 TX, MUX = ALT2. */ + PORTB->PCR[1] |= PORT_PCR_MUX(2); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) + /* CAN RX GPIO pin configuration. PE4 = CAN0 RX, MUX = ALT5. */ + PORTE->PCR[4] |= PORT_PCR_MUX(5); + /* CAN TX GPIO pin configuration. PE5 = CAN0 TX, MUX = ALT5. */ + PORTE->PCR[5] |= PORT_PCR_MUX(5); +#endif + + /* Initialize the timer driver. */ + TimerInit(); + /* Initialize the led driver. */ + LedInit(); + /* Enable the global interrupts. */ + ENABLE_INTERRUPTS(); +} /*** end of Init ***/ + + +/************************************************************************************//** +** \brief System Clock Configuration. This code was derived from a S32 Design Studio +** example program. It enables the SOCS (40 MHz external crystal), FIRC (48 +** MHz internal) and SIRC (8 MHz internal). The FIRC is used as a source for +** the system clock and configures the normal RUN mode for the following clock +** settings: +** - CORE_CLK = 48 MHz +** - SYS_CLK = 48 MHz +** - BUS_CLK = 48 MHz +** - FLASH_CLK = 24 MHz +** - SOSCDIV1_CLK = 40 MHz +** - SOSCDIV2_CLK = 40 MHz +** - FIRCDIV1_CLK = 48 MHz +** - FIRCDIV2_CLK = 48 MHz +** - SIRCDIV1_CLK = 8 MHz +** - SIRCDIV2_CLK = 8 MHz +** \return none. +** +****************************************************************************************/ +static void SystemClockConfig(void) +{ + /* --------- SOSC Initialization (40 MHz) ------------------------------------------ */ + /* SOSCDIV1 & SOSCDIV2 =1: divide by 1. */ + SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1) | SCG_SOSCDIV_SOSCDIV2(1); + /* Range=3: High freq (SOSC betw 8MHz - 40MHz). + * HGO=0: Config xtal osc for low power. + * EREFS=1: Input is external XTAL. + */ + SCG->SOSCCFG = SCG_SOSCCFG_RANGE(3) | SCG_SOSCCFG_EREFS_MASK; + /* Ensure SOSCCSR unlocked. */ + while (SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK) + { + ; + } + + /* LK=0: SOSCCSR can be written. + * SOSCCMRE=0: OSC CLK monitor IRQ if enabled. + * SOSCCM=0: OSC CLK monitor disabled. + * SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled. + * SOSCLPEN=0: Sys OSC disabled in VLP modes. + * SOSCSTEN=0: Sys OSC disabled in Stop modes. + * SOSCEN=1: Enable oscillator. + */ + SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK; + /* Wait for system OSC clock to become valid. */ + while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK)) + { + ; + } + + /* --------- FIRC Initialization --------------------------------------------------- */ + /* Fast IRC is enabled and trimmed to 48 MHz in reset (default). Enable FIRCDIV2_CLK + * and FIRCDIV1_CLK, divide by 1 = 48 MHz. + */ + SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV1(1) | SCG_FIRCDIV_FIRCDIV2(1); + + /* --------- SIRC Initialization --------------------------------------------------- */ + /* Slow IRC is enabled with high range (8 MHz) in reset. Enable SIRCDIV2_CLK and + * SIRCDIV1_CLK, divide by 1 = 8MHz asynchronous clock source. + */ + SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1) | SCG_SIRCDIV_SIRCDIV2(1); + + /* --------- Change to normal RUN mode with 48MHz FIRC ----------------------------- */ + /* Select FIRC as clock source. + * DIVCORE=0, div. by 1: Core clock = 48 MHz. + * DIVBUS=0, div. by 1: bus clock = 48 MHz. + * DIVSLOW=1, div. by 2: SCG slow, flash clock= 24 MHz + */ + SCG->RCCR = SCG_RCCR_SCS(3) | SCG_RCCR_DIVCORE(0) | SCG_RCCR_DIVBUS(0) | + SCG_RCCR_DIVSLOW(1); + + /* Wait until system clock source is FIRC. */ + while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 3U) + { + ; + } + /* Evaluate the clock register settings and calculates the current core clock. This + * function must be called when the clock manager component is not used. + */ + SystemCoreClockUpdate(); +} /*** end of SystemClockConfig ***/ + + +/*********************************** end of main.c *************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/prog.dox b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/prog.dox new file mode 100644 index 00000000..a63f202e --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/prog.dox @@ -0,0 +1,13 @@ +/** +\defgroup Prog_ARMCM0_S32K14_S32K118EVB_IAR User Program +\ingroup ARMCM0_S32K14_S32K118EVB_IAR +\brief User Program. +\details The intention of the demo user program is two-fold. (1) To test the + bootloader, you need some sort of firmware to see if you can perform a + firmware update with the bootloader. This program can be used for this + purpose. (2) To make firmware programmable by the bootloader, a few + adjustments to the firmware are required. The demo user program serves as an + example for how these adjustments can be implemented. This demo user program + is a template that can be used as a starting point for creating your own + demo user program. +*/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/startup_S32K118.s b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/startup_S32K118.s new file mode 100644 index 00000000..24552fbc --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/startup_S32K118.s @@ -0,0 +1,288 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_S32K118.s +; @purpose: IAR Startup File +; S32K118 +; @version: 1.0 +; @date: 2018-1-22 +; @build: b170107 +; --------------------------------------------------------------------------------------- +; +; Copyright 2018 NXP +; All rights reserved. +; +; THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +; OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +; IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +; INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +; STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +; IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:ROOT(2) + + EXTERN main + EXTERN SystemInit + EXTERN init_data_bss + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; Non Maskable Interrupt + DCD HardFault_Handler ; Cortex-M0 SV Hard Fault Interrupt + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler ; Cortex-M0 SV Call Interrupt + DCD 0 + DCD 0 + DCD PendSV_Handler ; Cortex-M0 Pend SV Interrupt + DCD SysTick_Handler ; Cortex-M0 System Tick Interrupt + + + DCD DMA0_IRQHandler ; DMA channel 0 transfer complete + DCD DMA1_IRQHandler ; DMA channel 1 transfer complete + DCD DMA2_IRQHandler ; DMA channel 2 transfer complete + DCD DMA3_IRQHandler ; DMA channel 3 transfer complete + DCD DMA_Error_IRQHandler ; DMA error interrupt channels 0-3 + DCD ERM_fault_IRQHandler ; ERM single and double bit error correction + DCD RTC_IRQHandler ; RTC alarm interrupt + DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt + DCD LPTMR0_IRQHandler ; LPTIMER interrupt request + DCD PORT_IRQHandler ; Port A, B, C, D and E pin detect interrupt + DCD CAN0_ORed_Err_Wakeup_IRQHandler ; OR’ed [Bus Off OR Bus Off Done OR Transmit Warning OR Receive Warning], Interrupt indicating that errors were detected on the CAN bus, Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode + DCD CAN0_ORed_0_31_MB_IRQHandler ; OR’ed Message buffer (0-15, 16-31) + DCD FTM0_Ch0_7_IRQHandler ; FTM0 Channel 0 to 7 interrupt + DCD FTM0_Fault_IRQHandler ; FTM0 Fault interrupt + DCD FTM0_Ovf_Reload_IRQHandler ; FTM0 Counter overflow and Reload interrupt + DCD FTM1_Ch0_7_IRQHandler ; FTM1 Channel 0 to 7 interrupt + DCD FTM1_Fault_IRQHandler ; FTM1 Fault interrupt + DCD FTM1_Ovf_Reload_IRQHandler ; FTM1 Counter overflow and Reload interrupt + DCD FTFC_IRQHandler ; FTFC Command complete, Read collision and Double bit fault detect + DCD PDB0_IRQHandler ; PDB0 interrupt + DCD LPIT0_IRQHandler ; LPIT interrupt + DCD SCG_CMU_LVD_LVWSCG_IRQHandler ; PMC Low voltage detect interrupt, SCG bus interrupt request and CMU loss of range interrupt + DCD WDOG_IRQHandler ; WDOG interrupt request out before wdg reset out + DCD RCM_IRQHandler ; RCM Asynchronous Interrupt + DCD LPI2C0_Master_Slave_IRQHandler ; LPI2C0 Master Interrupt and Slave Interrupt + DCD FLEXIO_IRQHandler ; FlexIO Interrupt + DCD LPSPI0_IRQHandler ; LPSPI0 Interrupt + DCD LPSPI1_IRQHandler ; LPSPI1 Interrupt + DCD ADC0_IRQHandler ; ADC0 interrupt request. + DCD CMP0_IRQHandler ; CMP0 interrupt request + DCD LPUART1_RxTx_IRQHandler ; LPUART1 Transmit / Receive Interrupt + DCD LPUART0_RxTx_IRQHandler ; LPUART0 Transmit / Receive Interrupt + DCD 0x55AA11EE ; Reserved for OpenBLT checksum +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF ; 8 bytes backdoor comparison key + DCD 0xFFFFFFFF ; + DCD 0xFFFFFFFF ; 4 bytes program flash protection bytes + DCD 0xFFFF7FFE ; FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured) +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + ;; Init the rest of the registers + LDR R1,=0 + LDR R2,=0 + LDR R3,=0 + LDR R4,=0 + LDR R5,=0 + LDR R6,=0 + LDR R7,=0 + MOV R8,R7 + MOV R9,R7 + MOV R10,R7 + MOV R11,R7 + MOV R12,R7 + +#ifdef START_FROM_FLASH + IMPORT __RAM_START, __RAM_END + ;; INIT ECC RAM + + LDR R1, =__RAM_START + LDR R2, =__RAM_END + + SUBS R2, R2, R1 + SUBS R2, #1 + BLE .LC5 + + MOVS R0, #0 + MOVS R3, #4 + .LC4: + STR R0, [R1] + ADD R1, R1, R3 + SUBS R2, #4 + BGE .LC4 + .LC5: +#endif + ;; Initialize the stack pointer + LDR R0, =sfe(CSTACK) + MOV R13,R0 + +#ifndef __NO_SYSTEM_INIT + ;; Call the CMSIS system init routine + LDR R0, =SystemInit + BLX R0 +#endif + + ;; Init .data and .bss sections + LDR R0, =init_data_bss + BLX R0 + CPSIE I ; Unmask interrupts + + BL main +JumpToSelf + B JumpToSelf + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA3_IRQHandler + PUBWEAK DMA_Error_IRQHandler + PUBWEAK ERM_fault_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK PORT_IRQHandler + PUBWEAK CAN0_ORed_Err_Wakeup_IRQHandler + PUBWEAK CAN0_ORed_0_31_MB_IRQHandler + PUBWEAK FTM0_Ch0_7_IRQHandler + PUBWEAK FTM0_Fault_IRQHandler + PUBWEAK FTM0_Ovf_Reload_IRQHandler + PUBWEAK FTM1_Ch0_7_IRQHandler + PUBWEAK FTM1_Fault_IRQHandler + PUBWEAK FTM1_Ovf_Reload_IRQHandler + PUBWEAK FTFC_IRQHandler + PUBWEAK PDB0_IRQHandler + PUBWEAK LPIT0_IRQHandler + PUBWEAK SCG_CMU_LVD_LVWSCG_IRQHandler + PUBWEAK WDOG_IRQHandler + PUBWEAK RCM_IRQHandler + PUBWEAK LPI2C0_Master_Slave_IRQHandler + PUBWEAK FLEXIO_IRQHandler + PUBWEAK LPSPI0_IRQHandler + PUBWEAK LPSPI1_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK LPUART1_RxTx_IRQHandler + PUBWEAK LPUART0_RxTx_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler +HardFault_Handler +SVC_Handler +PendSV_Handler +SysTick_Handler +DMA0_IRQHandler +DMA1_IRQHandler +DMA2_IRQHandler +DMA3_IRQHandler +DMA_Error_IRQHandler +ERM_fault_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +LPTMR0_IRQHandler +PORT_IRQHandler +CAN0_ORed_Err_Wakeup_IRQHandler +CAN0_ORed_0_31_MB_IRQHandler +FTM0_Ch0_7_IRQHandler +FTM0_Fault_IRQHandler +FTM0_Ovf_Reload_IRQHandler +FTM1_Ch0_7_IRQHandler +FTM1_Fault_IRQHandler +FTM1_Ovf_Reload_IRQHandler +FTFC_IRQHandler +PDB0_IRQHandler +LPIT0_IRQHandler +SCG_CMU_LVD_LVWSCG_IRQHandler +WDOG_IRQHandler +RCM_IRQHandler +LPI2C0_Master_Slave_IRQHandler +FLEXIO_IRQHandler +LPSPI0_IRQHandler +LPSPI1_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +LPUART1_RxTx_IRQHandler +LPUART0_RxTx_IRQHandler +DefaultISR + B DefaultISR + + END diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/timer.c b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/timer.c new file mode 100644 index 00000000..0eaaf6da --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/timer.c @@ -0,0 +1,88 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/timer.c +* \brief Timer driver source file. +* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Local variable for storing the number of milliseconds that have elapsed since + * startup. + */ +static unsigned long millisecond_counter; + + +/************************************************************************************//** +** \brief Initializes the timer. +** \return none. +** +****************************************************************************************/ +void TimerInit(void) +{ + /* Configure the systick frequency as a 1 ms event generator. */ + S32_SysTick->RVR = (SystemCoreClock / 1000U) - 1U; + /* Reset the current counter value. */ + S32_SysTick->CVR = 0U; + /* Select core clock as source and enable the timer. */ + S32_SysTick->CSR = S32_SysTick_CSR_ENABLE_MASK | + S32_SysTick_CSR_TICKINT_MASK | + S32_SysTick_CSR_CLKSOURCE_MASK; + /* Reset the millisecond counter value. */ + millisecond_counter = 0U; +} /*** end of TimerInit ***/ + + +/************************************************************************************//** +** \brief Obtains the counter value of the millisecond timer. +** \return Current value of the millisecond timer. +** +****************************************************************************************/ +unsigned long TimerGet(void) +{ + /* Read and return the tick counter value. */ + return millisecond_counter; +} /*** end of TimerGet ***/ + + +/************************************************************************************//** +** \brief Interrupt service routine of the timer. +** \return none. +** +****************************************************************************************/ +void SysTick_Handler(void) +{ + /* Increment the millisecond counter. */ + millisecond_counter++; +} /*** end of SysTick_Handler ***/ + + +/*********************************** end of timer.c ************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/timer.h b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/timer.h new file mode 100644 index 00000000..cb46f881 --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/timer.h @@ -0,0 +1,38 @@ +/************************************************************************************//** +* \file Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/timer.h +* \brief Timer driver header file. +* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef TIMER_H +#define TIMER_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void TimerInit(void); +unsigned long TimerGet(void); + +#endif /* TIMER_H */ +/*********************************** end of timer.h ************************************/ diff --git a/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/demo.dox b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/demo.dox new file mode 100644 index 00000000..f24879cf --- /dev/null +++ b/Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/demo.dox @@ -0,0 +1,8 @@ +/** +\defgroup ARMCM0_S32K14_S32K118EVB_IAR Demo for S32K118EVB/IAR +\ingroup Demos +\brief Preconfigured programs for the NXP S32K118EVB board and the IAR Embedded + Workbench for ARM. +*/ + + diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/Debug/openblt_s32k144.elf b/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/Debug/openblt_s32k144.elf index c57a777a..1d29f293 100644 Binary files a/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/Debug/openblt_s32k144.elf and b/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/Debug/openblt_s32k144.elf differ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/Debug/openblt_s32k144.srec b/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/Debug/openblt_s32k144.srec index 35deb67d..96221e7b 100644 --- a/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/Debug/openblt_s32k144.srec +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/Debug/openblt_s32k144.srec @@ -417,7 +417,7 @@ S11319E0081C0000081C0000081C00000C1C00005F S11319F002440346934200D1704703F8011BF9E700 S1131A00FEE70000433A2F576F726B2F736F6674B3 S1131A10776172652F4F70656E424C545F53333259 -S1131A204B31342F5461726765742F536F75726331 +S1131A204B31312F5461726765742F536F75726334 S1131A30652F41524D434D345F5333324B31342F74 S1131A4063616E2E630000000803020209030302AF S1131A500A0303030B0403030C0404030D0504032A @@ -441,7 +441,7 @@ S1131B6000800000130000000080060000800000D8 S1131B7014000000000007000080000015000000B1 S1131B80008007000080000016000000433A2F5731 S1131B906F726B2F736F6674776172652F4F706508 -S1131BA06E424C545F5333324B31342F546172675D +S1131BA06E424C545F5333324B31312F5461726760 S1131BB065742F536F757263652F41524D434D34D5 S1131BC05F5333324B31342F72733233322E63000E S1131BD04F70656E424C54000884FF1FF8B500BF77 diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/main.c b/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/main.c index c2644ac6..0d5397d2 100644 --- a/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/main.c +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Boot/main.c @@ -194,8 +194,8 @@ static void SystemClockConfig(void) * DIVBUS=1, div. by 2: bus clock = 40 MHz. * DIVSLOW=2, div. by 2: SCG slow, flash clock= 26 2/3 MHz. */ - SCG->RCCR= SCG_RCCR_SCS(6) | SCG_RCCR_DIVCORE(0b01) | SCG_RCCR_DIVBUS(0b01) | - SCG_RCCR_DIVSLOW(0b10); + SCG->RCCR= SCG_RCCR_SCS(6) | SCG_RCCR_DIVCORE(1) | SCG_RCCR_DIVBUS(1) | + SCG_RCCR_DIVSLOW(2); /* Wait until system clock source is SPLL. */ while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 6U) { diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/Debug/demoprog_s32k144.elf b/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/Debug/demoprog_s32k144.elf index f0b3d461..a87f5e9c 100644 Binary files a/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/Debug/demoprog_s32k144.elf and b/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/Debug/demoprog_s32k144.elf differ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/boot.c b/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/boot.c index 0a9d85ae..d2fc02e2 100644 --- a/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/boot.c +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/boot.c @@ -143,7 +143,7 @@ static void BootComRs232Init(void) /* Select option 2 as the UART peripheral source clock and enable the clock. Option 2 * is the SIRCDIV2_CLK, which is available on all peripherals and configurations. */ - PCC->PCCn[PCC_LPUARTx_INDEX] |= PCC_PCCn_PCS(0b010) | PCC_PCCn_CGC_MASK; + PCC->PCCn[PCC_LPUARTx_INDEX] |= PCC_PCCn_PCS(2) | PCC_PCCn_CGC_MASK; /* Obtain the DIV2 divider value of the SIRC_CLK. */ div2RegValue = (SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT; /* Check if the DIV2 register value for SIRC is 0. In this case SIRCDIV2_CLK is diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/main.c b/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/main.c index 49f4795b..4b31b787 100644 --- a/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/main.c +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_GCC/Prog/main.c @@ -190,8 +190,8 @@ static void SystemClockConfig(void) * DIVBUS=1, div. by 2: bus clock = 40 MHz. * DIVSLOW=2, div. by 2: SCG slow, flash clock= 26 2/3 MHz. */ - SCG->RCCR= SCG_RCCR_SCS(6) | SCG_RCCR_DIVCORE(0b01) | SCG_RCCR_DIVBUS(0b01) | - SCG_RCCR_DIVSLOW(0b10); + SCG->RCCR= SCG_RCCR_SCS(6) | SCG_RCCR_DIVCORE(1) | SCG_RCCR_DIVBUS(1) | + SCG_RCCR_DIVSLOW(2); /* Wait until system clock source is SPLL. */ while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 6U) { diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/main.c b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/main.c index fe8a10cd..c2f4a5b0 100644 --- a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/main.c +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/main.c @@ -47,7 +47,7 @@ static void SystemClockConfig(void); ** \return none. ** ****************************************************************************************/ -int main(void) +void main(void) { /* Initialize the microcontroller. */ Init(); diff --git a/Target/Source/ARMCM0_S32K11/GCC/cpu_comp.c b/Target/Source/ARMCM0_S32K11/GCC/cpu_comp.c new file mode 100644 index 00000000..66d6722f --- /dev/null +++ b/Target/Source/ARMCM0_S32K11/GCC/cpu_comp.c @@ -0,0 +1,59 @@ +/************************************************************************************//** +* \file Source/ARMCM0_S32K11/GCC/cpu_comp.c +* \brief Bootloader cpu module source file. +* \ingroup Target_ARMCM0_S32K11 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ + + +/************************************************************************************//** +** \brief Disable global interrupts. +** \return none. +** +****************************************************************************************/ +void CpuIrqDisable(void) +{ + /* Disable the global interrupts. */ + __asm volatile ("cpsid i" : : : "memory"); +} /*** end of CpuIrqDisable ***/ + + +/************************************************************************************//** +** \brief Enable global interrupts. +** \return none. +** +****************************************************************************************/ +void CpuIrqEnable(void) +{ + /* Enable the global interrupts. */ + __asm volatile ("cpsie i" : : : "memory"); +} /*** end of CpuIrqEnable ***/ + + +/*********************************** end of cpu_comp.c *********************************/ diff --git a/Target/Source/ARMCM0_S32K11/IAR/cpu_comp.c b/Target/Source/ARMCM0_S32K11/IAR/cpu_comp.c new file mode 100644 index 00000000..f98214dc --- /dev/null +++ b/Target/Source/ARMCM0_S32K11/IAR/cpu_comp.c @@ -0,0 +1,59 @@ +/************************************************************************************//** +* \file Source/ARMCM0_S32K11/IAR/cpu_comp.c +* \brief Bootloader cpu module source file. +* \ingroup Target_ARMCM0_S32K11 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ + + +/************************************************************************************//** +** \brief Disable global interrupts. +** \return none. +** +****************************************************************************************/ +void CpuIrqDisable(void) +{ + /* Disable the global interrupts. */ + __asm("cpsie i"); +} /*** end of CpuIrqDisable ***/ + + +/************************************************************************************//** +** \brief Enable global interrupts. +** \return none. +** +****************************************************************************************/ +void CpuIrqEnable(void) +{ + /* Enable the global interrupts. */ + __asm("cpsie i"); +} /*** end of CpuIrqEnable ***/ + + +/*********************************** end of cpu_comp.c *********************************/ diff --git a/Target/Source/ARMCM0_S32K11/can.c b/Target/Source/ARMCM0_S32K11/can.c new file mode 100644 index 00000000..9c09366d --- /dev/null +++ b/Target/Source/ARMCM0_S32K11/can.c @@ -0,0 +1,600 @@ +/************************************************************************************//** +* \file Source/ARMCM0_S32K11/can.c +* \brief Bootloader CAN communication interface source file. +* \ingroup Target_ARMCM0_S32K11 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#if (BOOT_COM_CAN_ENABLE > 0) +#include "device_registers.h" /* device registers */ + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Timeout for entering/leaving CAN initialization mode in milliseconds. */ +#define CAN_INIT_TIMEOUT_MS (250U) +/** \brief Timeout for transmitting a CAN message in milliseconds. */ +#define CAN_MSG_TX_TIMEOUT_MS (50U) + +#if (BOOT_COM_CAN_CHANNEL_INDEX == 0) +/** \brief Set the peripheral CAN0 base pointer. */ +#define CANx (CAN0) +/** \brief Set the PCC index offset for CAN0. */ +#define PCC_FlexCANx_INDEX (PCC_FlexCAN0_INDEX) +/** \brief Set the number of message boxes supported by CAN0. */ +#define CANx_MAX_MB_NUM (FEATURE_CAN0_MAX_MB_NUM) +#endif + +/** \brief The mailbox used for transmitting the XCP respond message. */ +#define CAN_TX_MSGBOX_NUM (8U) +/** \brief The mailbox used for receiving the XCP command message. */ +#define CAN_RX_MSGBOX_NUM (9U) + + +/**************************************************************************************** +* Type definitions +****************************************************************************************/ +/** \brief Structure type for grouping CAN bus timing related information. */ +typedef struct t_can_bus_timing +{ + blt_int8u timeQuanta; /**< Total number of time quanta */ + blt_int8u propSeg; /**< CAN propagation segment */ + blt_int8u phaseSeg1; /**< CAN phase segment 1 */ + blt_int8u phaseSeg2; /**< CAN phase segment 2 */ +} tCanBusTiming; + + +/**************************************************************************************** +* Local constant declarations +****************************************************************************************/ +/** \brief CAN bit timing table for dynamically calculating the bittiming settings. + * \details According to the CAN protocol 1 bit-time can be made up of between 8..25 + * time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC + * always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + TSEG2) + * * 100%. This array contains possible and valid time quanta configurations + * with a sample point between 68..78%. A visual representation of the TQ in + * a bit is: + * | SYNCSEG | TIME1SEG | TIME2SEG | + * Or with an alternative representation: + * | SYNCSEG | PROPSEG | PHASE1SEG | PHASE2SEG | + * With the alternative representation TIME1SEG = PROPSEG + PHASE1SEG. + * + */ +static const tCanBusTiming canTiming[] = +{ + /* Time-Quanta | PROPSEG | PSEG1 | PSEG2 | Sample-Point */ + /* ---------------------------------------------------- */ + { 8U, 3U, 2U, 2U }, /*1+3+2+1=8 | 3 | 2 | 2 | 75% */ + { 9U, 3U, 3U, 2U }, /* 9 | 3 | 3 | 2 | 78% */ + { 10U, 3U, 3U, 3U }, /* 10 | 3 | 3 | 3 | 70% */ + { 11U, 4U, 3U, 3U }, /* 11 | 4 | 3 | 3 | 73% */ + { 12U, 4U, 4U, 3U }, /* 12 | 4 | 4 | 3 | 75% */ + { 13U, 5U, 4U, 3U }, /* 13 | 5 | 4 | 3 | 77% */ + { 14U, 5U, 4U, 4U }, /* 14 | 5 | 4 | 4 | 71% */ + { 15U, 6U, 4U, 4U }, /* 15 | 6 | 4 | 4 | 73% */ + { 16U, 6U, 5U, 4U }, /* 16 | 6 | 5 | 4 | 75% */ + { 17U, 7U, 5U, 4U }, /* 17 | 7 | 5 | 4 | 76% */ + { 18U, 7U, 5U, 5U }, /* 18 | 7 | 5 | 5 | 72% */ + { 19U, 8U, 5U, 5U }, /* 19 | 8 | 5 | 5 | 74% */ + { 20U, 8U, 6U, 5U }, /* 20 | 8 | 6 | 5 | 75% */ + { 21U, 8U, 7U, 5U }, /* 21 | 8 | 7 | 5 | 76% */ + { 22U, 8U, 7U, 6U }, /* 22 | 8 | 7 | 6 | 73% */ + { 23U, 8U, 8U, 6U }, /* 23 | 8 | 8 | 6 | 74% */ + { 24U, 8U, 8U, 7U }, /* 24 | 8 | 8 | 7 | 71% */ + { 25U, 8U, 8U, 8U } /* 25 | 8 | 8 | 8 | 68% */ +}; + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Dummy variable to store the CAN controller's free running timer value in. + * This is needed at the end of a CAN message reception to unlock the mailbox + * again. If this variable is declared locally within the function, it generates + * an unwanted compiler warning about assigning a value and not using it. + * For this reason this dummy variabled is declare here as a module global. + */ +static volatile blt_int32u dummyTimerVal; + + +/************************************************************************************//** +** \brief Search algorithm to match the desired baudrate to a possible bus +** timing configuration. +** \param baud The desired baudrate in kbps. Valid values are 10..1000. +** \param prescaler Pointer to where the value for the prescaler will be stored. +** \param busTimingCfg Pointer to where the bus timing values will be stored. +** \return BLT_TRUE if the CAN bustiming register values were found, BLT_FALSE +** otherwise. +** +****************************************************************************************/ +static blt_bool CanGetSpeedConfig(blt_int16u baud, blt_int16u * prescaler, + tCanBusTiming * busTimingCfg) +{ + blt_int8u cnt; + blt_int32u canClockFreqkHz; + blt_int32u div2RegValue; + blt_int8u const div2DividerLookup[] = + { + 0U, /* 0b000. Output disabled. */ + 1U, /* 0b001. Divide by 1. */ + 2U, /* 0b010. Divide by 2. */ + 4U, /* 0b011. Divide by 4. */ + 8U, /* 0b100. Divide by 8. */ + 16U, /* 0b101. Divide by 16. */ + 32U, /* 0b110. Divide by 32. */ + 64U, /* 0b111. Divide by 64. */ + }; + + /* Obtain the DIV2 divider value of the SOSC_CLK. */ + div2RegValue = (SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV2_MASK) >> SCG_SOSCDIV_SOSCDIV2_SHIFT; + /* Check if the DIV2 register value for SOSC is 0. In this case SOSCDIV2_CLK is + * currently disabled. + */ + if (div2RegValue == 0U) + { + /* Configure the DIV2 for a default divide by 1 to make sure the SOSCDIV2_CLK is + * actually enabled. + */ + div2RegValue = 1U; + SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(div2RegValue); + } + /* Determine the SOSC clock frequency. */ + canClockFreqkHz = BOOT_CPU_XTAL_SPEED_KHZ; + /* Now process the configured DIV2 divider factor to get the actual frequency of the + * CAN peripheral source clock. + */ + canClockFreqkHz /= div2DividerLookup[div2RegValue]; + + /* Loop through all possible time quanta configurations to find a match. */ + for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++) + { + if ((canClockFreqkHz % (baud * canTiming[cnt].timeQuanta)) == 0U) + { + /* Compute the prescaler that goes with this TQ configuration. */ + *prescaler = canClockFreqkHz/(baud * canTiming[cnt].timeQuanta); + + /* Make sure the prescaler is valid. */ + if ((*prescaler > 0U) && (*prescaler <= 256U)) + { + /* Store the bustiming configuration. */ + *busTimingCfg = canTiming[cnt]; + /* Found a good bus timing configuration. */ + return BLT_TRUE; + } + } + } + /* Could not find a good bus timing configuration. */ + return BLT_FALSE; +} /*** end of CanGetSpeedConfig ***/ + + +/************************************************************************************//** +** \brief Places the CAN controller in freeze mode. Note that the CAN controller +** can only be placed in freeze mode, if it is actually enabled. +** \return none. +** +****************************************************************************************/ +static void CanFreezeModeEnter(void) +{ + blt_int32u timeout; + + /* This function should only be called with the module enabled. */ + ASSERT_RT((CANx->MCR & CAN_MCR_MDIS_MASK) == 0U); + + /* Request to enter freeze mode. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(1U); + CANx->MCR = (CANx->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(1U); + /* Set timeout time for entering freeze mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for freeze mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_FRZACK_MASK)) == 0U) + { + /* Keep the watchdog happy. */ + CopService(); + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } +} /*** end of CanFreezeModeEnter ***/ + + +/************************************************************************************//** +** \brief Leaves the CAN controller's freeze mode. Note that this operation can +** only be done, if it is actually enabled. +** \return none. +** +****************************************************************************************/ +static void CanFreezeModeExit(void) +{ + blt_int32u timeout; + + /* This function should only be called with the module enabled. */ + ASSERT_RT((CANx->MCR & CAN_MCR_MDIS_MASK) == 0U); + + /* Request to leave freeze mode. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(0U); + CANx->MCR = (CANx->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(0U); + /* Set timeout time for leaving freeze mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for non freeze mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_FRZACK_MASK)) != 0U) + { + /* Keep the watchdog happy. */ + CopService(); + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } +} /*** end of CanFreezeModeExit ***/ + + +/************************************************************************************//** +** \brief Places the CAN controller in disabled mode. +** \return none. +** +****************************************************************************************/ +static void CanDisabledModeEnter(void) +{ + blt_int32u timeout; + + /* Only continue if the CAN controller is currently enabled. */ + if ((CANx->MCR & CAN_MCR_MDIS_MASK) == 0U) + { + /* Request disabled mode. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(1U); + /* Set timeout time for entering disabled mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for disabled mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_LPMACK_MASK)) == 0U) + { + /* Keep the watchdog happy. */ + CopService(); + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } + } +} /*** end of CanDisabledModeEnter ***/ + +/************************************************************************************//** +** \brief Places the CAN controller in enabled mode. +** \return none. +** +****************************************************************************************/ +static void CanDisabledModeExit(void) +{ + blt_int32u timeout; + + /* Only continue if the CAN controller is currently disabled. */ + if ((CANx->MCR & CAN_MCR_MDIS_MASK) != 0U) + { + /* Request enabled mode. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(0U); + /* Set timeout time for leaving disabled mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for disabled mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_LPMACK_MASK)) != 0U) + { + /* Keep the watchdog happy. */ + CopService(); + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } + } +} /*** end of CanDisabledModeExit ***/ + + +/************************************************************************************//** +** \brief Initializes the CAN controller and synchronizes it to the CAN bus. +** \return none. +** +****************************************************************************************/ +void CanInit(void) +{ + blt_int16u prescaler = 0; + tCanBusTiming timingCfg = { 0 }; + blt_int8u rjw; + blt_int16u idx; + blt_int32u timeout; + blt_int32u rxMsgId = BOOT_COM_CAN_RX_MSG_ID; + + /* Perform compile time assertion to check that the configured CAN channel is actually + * supported by this driver. + */ + ASSERT_CT(BOOT_COM_CAN_CHANNEL_INDEX == 0); + + /* Verify the correct configuration of the transmit and receive mailboxes. */ + ASSERT_CT(CAN_TX_MSGBOX_NUM < CANx_MAX_MB_NUM); + ASSERT_CT(CAN_RX_MSGBOX_NUM < CANx_MAX_MB_NUM); + + /* Enable the CAN peripheral clock. */ + PCC->PCCn[PCC_FlexCANx_INDEX] |= PCC_PCCn_CGC_MASK; + + /* The source clock needs to be configured first. For this the CAN controller must be + * in disabled mode, but that can only be entered after first entering freeze mode, + * which in turn can only be in enabled mode. So first enable the module, then goto + * freeze mode and finally enter disabled mode. + */ + CanDisabledModeExit(); + CanFreezeModeEnter(); + CanDisabledModeEnter(); + /* Configure SOSCDIV2 as the source clock. This assumes that an external oscillator + * is available, which is typically the case to meet the clock tolerance requirements + * of the CAN 2.0B secification. + */ + CANx->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK; + /* Leave disabled mode. */ + CanDisabledModeExit(); + /* Make sure freeze mode is active to be able to initialize the CAN controller. */ + CanFreezeModeEnter(); + + /* Obtain bittiming configuration information. */ + if (CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &timingCfg) == BLT_FALSE) + { + /* Incorrect configuration. The specified baudrate is not supported for the given + * clock configuration. Verify the following settings in blt_conf.h: + * - BOOT_COM_CAN_BAUDRATE + * - BOOT_CPU_XTAL_SPEED_KHZ + * - BOOT_CPU_SYSTEM_SPEED_KHZ + */ + ASSERT_RT(BLT_FALSE); + } + + /* Reset the current bittiming configuration. */ + CANx->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_PROPSEG_MASK | + CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | CAN_CTRL1_RJW_MASK | + CAN_CTRL1_SMP_MASK); + /* Configure the baudrate prescaler. */ + CANx->CTRL1 |= CAN_CTRL1_PRESDIV(prescaler - 1U); + /* Configure the propagation segment. */ + CANx->CTRL1 |= CAN_CTRL1_PROPSEG(timingCfg.propSeg - 1U); + /* Configure the phase segments. */ + CANx->CTRL1 |= CAN_CTRL1_PSEG1(timingCfg.phaseSeg1 - 1U); + CANx->CTRL1 |= CAN_CTRL1_PSEG2(timingCfg.phaseSeg2 - 1U); + /* The resynchronization jump width (RJW) can be 1 - 4 TQ, yet should never be larger + * than pseg1. Configure the longest possible value for RJW. + */ + rjw = (timingCfg.phaseSeg1 < 4) ? timingCfg.phaseSeg1 : 4; + CANx->CTRL1 |= CAN_CTRL1_RJW(rjw - 1U); + /* All the entries in canTiming[] have a PSEG1 >= 2, so three samples can be used to + * determine the value of the received bit, instead of the default one. + */ + CANx->CTRL1 |= CAN_CTRL1_SMP(1U); + + /* Clear the message box RAM. Each message box covers 4 words (1 word = 32-bits. */ + for (idx = 0; idx < (CANx_MAX_MB_NUM * 4U); idx++) + { + CANx->RAMn[idx] = 0U; + } + /* Clear the reception mask register for each message box. */ + for (idx = 0; idx < CANx_MAX_MB_NUM; idx++) + { + CANx->RXIMR[idx] = 0U; + } + /* Configure the maximum number of message boxes. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB(CANx_MAX_MB_NUM - 1U); + /* Disable the self reception feature. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_SRXDIS_MASK) | CAN_MCR_SRXDIS(1U); + + /* Enable individual reception masking. This disables the legacy support for the + * global reception mask and the mailbox 14/15 individual reception mask. + */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_IRMQ_MASK) | CAN_MCR_IRMQ(1U); + /* Disable the reception FIFO. This driver only needs to receive one CAN message + * identifier. It is sufficient to use just one dedicated mailbox for this. + */ + CANx->MCR &= ~CAN_MCR_RFEN_MASK; + /* Configure the mask of the invididual message reception mailbox to check all ID bits + * and also the IDE bit. + */ + CANx->RXIMR[CAN_RX_MSGBOX_NUM] = 0x40000000U | 0x1FFFFFFFU; + /* Configure the reception mailbox to receive just the CAN message configured with + * BOOT_COM_CAN_RX_MSG_ID. + * EDL, BRS, ESI=0: CANFD not used. + * CODE=0b0100: mailbox set to active and empty. + * IDE=0: 11-bit CAN identifier. + * SRR, RTR, TIME STAMP=0: not applicable. + */ + CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] = 0x04000000; + /* Store the message identifier to receive in the mailbox RAM. */ + if ((rxMsgId & 0x80000000U) != 0U) + { + /* It is a 29-bit extended CAN identifier. */ + rxMsgId &= ~0x80000000U; + /* Set the IDE bit to configure the message for a 29-bit identifier. */ + CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] |= CAN_WMBn_CS_IDE_MASK; + /* Store the 29-bit CAN identifier. */ + CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(rxMsgId); + } + else + { + /* Store the 11-bit CAN identifier. */ + CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(rxMsgId << 18U); + } + + /* Disable all message box interrupts. */ + CANx->IMASK1 = 0U; + /* Clear all mesasge box interrupt flags. */ + CANx->IFLAG1 = CAN_IMASK1_BUF31TO0M_MASK; + /* Clear all error interrupt flags */ + CANx->ESR1 = CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK | + CAN_ESR1_TWRNINT_MASK | CAN_ESR1_BOFFDONEINT_MASK | + CAN_ESR1_ERRINT_FAST_MASK | CAN_ESR1_ERROVR_MASK; + + /* Switch to normal user mode. */ + CANx->MCR &= ~CAN_MCR_SUPV_MASK; + CANx->CTRL1 &= ~(CAN_CTRL1_LOM_MASK | CAN_CTRL1_LPB_MASK); + /* Exit freeze mode. */ + CanFreezeModeExit(); + /* Set timeout time for entering normal user mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for normal user mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_NOTRDY_MASK)) != 0U) + { + /* Keep the watchdog happy. */ + CopService(); + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } +} /*** end of CanInit ***/ + + +/************************************************************************************//** +** \brief Transmits a packet formatted for the communication interface. +** \param data Pointer to byte array with data that it to be transmitted. +** \param len Number of bytes that are to be transmitted. +** \return none. +** +****************************************************************************************/ +void CanTransmitPacket(blt_int8u *data, blt_int8u len) +{ + blt_int32u timeout; + blt_bool isExtId = BLT_FALSE; + blt_int32u txMsgId = BOOT_COM_CAN_TX_MSG_ID; + blt_int8u * pMsgBoxData; + blt_int8u byteIdx; + + /* Prepare information about the message identifier. */ + if ((txMsgId & 0x80000000U) != 0U) + { + /* It is a 29-bit extended CAN identifier. */ + txMsgId &= ~0x80000000U; + isExtId = BLT_TRUE; + } + + /* Clear the mailbox interrupt flag by writing a 1 to the corresponding box. */ + CANx->IFLAG1 = (1U << CAN_TX_MSGBOX_NUM); + + /* Prepare the mailbox RAM for a basic CAN message. + * EDL,BRS,ESI=0: CANFD not used. + */ + CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 0U] &= ~0xE0000000U; + /* Configure SRR, IDE, RTR bits for a standard 11-bit transmit frame. */ + CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 0U] &= ~(CAN_WMBn_CS_IDE_MASK | + CAN_WMBn_CS_RTR_MASK); + CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 0U] |= CAN_WMBn_CS_SRR_MASK; + /* Configure the DLC. */ + CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 0U] &= ~CAN_WMBn_CS_DLC_MASK; + CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 0U] |= CAN_WMBn_CS_DLC(len); + /* Write the data bytes of the CAN message to the mailbox RAM. */ + pMsgBoxData = (blt_int8u * )(&CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 2U]); + for (byteIdx = 0; byteIdx < len; byteIdx++) + { + pMsgBoxData[((byteIdx) & ~3U) + (3U - ((byteIdx) & 3U))] = data[byteIdx]; + } + /* Store the CAN message identifier in the mailbox RAM. */ + if (isExtId == BLT_FALSE) + { + /* Store the 11-bit CAN identifier. */ + CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(txMsgId << 18U); + } + else + { + /* Set the IDE bit to configure the message for a 29-bit identifier. */ + CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 0U] |= CAN_WMBn_CS_IDE_MASK; + /* Store the 29-bit CAN identifier. */ + CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(txMsgId); + } + /* Activate the mailbox to start the transmission by writing 0x0C to the CODE field. */ + CANx->RAMn[(CAN_TX_MSGBOX_NUM * 4U) + 0U] |= (0x0CU << 24U) & 0x0F000000U; + + /* Determine timeout time for the transmit completion. */ + timeout = TimerGet() + CAN_MSG_TX_TIMEOUT_MS; + /* Poll for completion of the transmit operation. */ + while ((CANx->IFLAG1 & (1U << CAN_TX_MSGBOX_NUM)) == 0U) + { + /* Service the watchdog. */ + CopService(); + /* Break loop upon timeout. this would indicate a hardware failure or no other + * nodes connected to the bus. + */ + if (TimerGet() > timeout) + { + break; + } + } +} /*** end of CanTransmitPacket ***/ + + +/************************************************************************************//** +** \brief Receives a communication interface packet if one is present. +** \param data Pointer to byte array where the data is to be stored. +** \param len Pointer where the length of the packet is to be stored. +** \return BLT_TRUE is a packet was received, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool CanReceivePacket(blt_int8u *data, blt_int8u *len) +{ + blt_bool result = BLT_FALSE; + blt_int8u * pMsgBoxData; + blt_int8u byteIdx; + + /* Check if a message was received in the individual mailbox configured to receive + * the BOOT_COM_CAN_RX_MSG_ID message. + */ + if ((CANx->IFLAG1 & (1U << CAN_RX_MSGBOX_NUM)) != 0U) + { + /* Note that there is no need to verify the identifier of the CAN message because the + * mailbox is configured to only receive the BOOT_COM_CAN_TX_MSG_ID message. Start + * by reading out the DLC of the newly received CAN message. + */ + *len = (CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] & CAN_WMBn_CS_DLC_MASK) >> CAN_WMBn_CS_DLC_SHIFT; + /* Read the data bytes of the CAN message from the mailbox RAM. */ + pMsgBoxData = (blt_int8u *)(&CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 2U]); + for (byteIdx = 0; byteIdx < *len; byteIdx++) + { + data[byteIdx] = pMsgBoxData[((byteIdx) & ~3U) + (3U - ((byteIdx) & 3U))]; + } + /* Clear the mailbox interrupt flag by writing a 1 to the corresponding box. */ + CANx->IFLAG1 = (1U << CAN_RX_MSGBOX_NUM); + /* Read the free running timer to unlock the mailbox. */ + dummyTimerVal = CANx->TIMER; + /* Update the result. */ + result = BLT_TRUE; + } + + /* Give the result back to the caller. */ + return result; +} /*** end of CanReceivePacket ***/ +#endif /* BOOT_COM_CAN_ENABLE > 0 */ + + +/*********************************** end of can.c **************************************/ diff --git a/Target/Source/ARMCM0_S32K11/cpu.c b/Target/Source/ARMCM0_S32K11/cpu.c new file mode 100644 index 00000000..ea785d7f --- /dev/null +++ b/Target/Source/ARMCM0_S32K11/cpu.c @@ -0,0 +1,192 @@ +/************************************************************************************//** +* \file Source/ARMCM0_S32K11/cpu.c +* \brief Bootloader cpu module source file. +* \ingroup Target_ARMCM0_S32K11 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "device_registers.h" /* device registers */ + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Pointer to the user program's reset vector. */ +#define CPU_USER_PROGRAM_STARTADDR_PTR ((blt_addr)(NvmGetUserProgBaseAddress() + 0x00000004)) +/** \brief Pointer to the user program's vector table. */ +#define CPU_USER_PROGRAM_VECTABLE_OFFSET ((blt_addr)NvmGetUserProgBaseAddress()) + + +/**************************************************************************************** +* Hook functions +****************************************************************************************/ +#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0) +extern blt_bool CpuUserProgramStartHook(void); +#endif + + +/************************************************************************************//** +** \brief Initializes the CPU module. +** \return none. +** +****************************************************************************************/ +void CpuInit(void) +{ + /* bootloader runs in polling mode so disable the global interrupts. this is done for + * safety reasons. if the bootloader was started from a running user program, it could + * be that the user program did not properly disable the interrupt generation of + * peripherals. */ + CpuIrqDisable(); +} /*** end of CpuInit ***/ + + +/************************************************************************************//** +** \brief Starts the user program, if one is present. In this case this function +** does not return. +** \return none. +** +****************************************************************************************/ +void CpuStartUserProgram(void) +{ + void (*pProgResetHandler)(void); + + /* check if a user program is present by verifying the checksum */ + if (NvmVerifyChecksum() == BLT_FALSE) + { +#if (BOOT_COM_DEFERRED_INIT_ENABLE > 0) && (BOOT_COM_ENABLE > 0) + /* bootloader will stay active so perform deferred initialization to make sure + * the communication interface that were not yet initialized are now initialized. + * this is needed to make sure firmware updates via these communication interfaces + * will be possible. + */ + ComDeferredInit(); +#endif + /* not a valid user program so it cannot be started */ + return; + } +#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0) + /* invoke callback */ + if (CpuUserProgramStartHook() == BLT_FALSE) + { + #if (BOOT_COM_DEFERRED_INIT_ENABLE > 0) && (BOOT_COM_ENABLE > 0) + /* bootloader will stay active so perform deferred initialization to make sure + * the communication interface that were not yet initialized are now initialized. + * this is needed to make sure firmware updates via these communication interfaces + * will be possible. + */ + ComDeferredInit(); + #endif + /* callback requests the user program to not be started */ + return; + } +#endif +#if (BOOT_COM_ENABLE > 0) + /* release the communication interface */ + ComFree(); +#endif + /* reset the timer */ + TimerReset(); + /* remap user program's vector table */ + S32_SCB->VTOR = CPU_USER_PROGRAM_VECTABLE_OFFSET & (blt_int32u)0x1FFFFF80; + /* The Cortex-M4 core has interrupts enabled out of reset. the bootloader + * explicitly disables these for security reasons. Enable them here again, so it does + * not have to be done by the user program. + */ + CpuIrqEnable(); + /* set the address where the bootloader needs to jump to. this is the address of + * the 2nd entry in the user program's vector table. this address points to the + * user program's reset handler. + */ + pProgResetHandler = (void(*)(void))(*((blt_addr *)CPU_USER_PROGRAM_STARTADDR_PTR)); + /* start the user program by calling its reset interrupt service routine */ + pProgResetHandler(); +#if (BOOT_COM_DEFERRED_INIT_ENABLE > 0) && (BOOT_COM_ENABLE > 0) + /* theoretically, the code never gets here because the user program should now be + * running and the previous function call should not return. In case it did return + * for whatever reason, make sure all communication interfaces are initialized so that + * firmware updates can be started. + */ + ComDeferredInit(); +#endif +} /*** end of CpuStartUserProgram ***/ + + +/************************************************************************************//** +** \brief Copies data from the source to the destination address. +** \param dest Destination address for the data. +** \param src Source address of the data. +** \param len length of the data in bytes. +** \return none. +** +****************************************************************************************/ +void CpuMemCopy(blt_addr dest, blt_addr src, blt_int16u len) +{ + blt_int8u *from, *to; + + /* set casted pointers */ + from = (blt_int8u *)src; + to = (blt_int8u *)dest; + + /* copy all bytes from source address to destination address */ + while (len-- > 0) + { + /* store byte value from source to destination */ + *to++ = *from++; + /* keep the watchdog happy */ + CopService(); + } +} /*** end of CpuMemCopy ***/ + + +/************************************************************************************//** +** \brief Sets the bytes at the destination address to the specified value. +** \param dest Destination address for the data. +** \param value Value to write. +** \param len Number of bytes to write. +** \return none. +** +****************************************************************************************/ +void CpuMemSet(blt_addr dest, blt_int8u value, blt_int16u len) +{ + blt_int8u *to; + + /* set casted pointer */ + to = (blt_int8u *)dest; + + /* set all bytes at the destination address to the specified value */ + while (len-- > 0) + { + /* set byte value */ + *to++ = value; + /* keep the watchdog happy */ + CopService(); + } +} /*** end of CpuMemSet ***/ + + +/*********************************** end of cpu.c **************************************/ diff --git a/Target/Source/ARMCM0_S32K11/flash.c b/Target/Source/ARMCM0_S32K11/flash.c new file mode 100644 index 00000000..591a8d1e --- /dev/null +++ b/Target/Source/ARMCM0_S32K11/flash.c @@ -0,0 +1,1018 @@ +/************************************************************************************//** +* \file Source/ARMCM0_S32K11/flash.c +* \brief Bootloader flash driver source file. +* \ingroup Target_ARMCM0_S32K11 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "device_registers.h" /* device registers */ + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Value for an invalid sector entry index into flashLayout[]. */ +#define FLASH_INVALID_SECTOR_IDX (0xff) +/** \brief Value for an invalid flash address. */ +#define FLASH_INVALID_ADDRESS (0xffffffff) +/** \brief Standard size of a flash block for writing. */ +#define FLASH_WRITE_BLOCK_SIZE (256) +/** \brief Standard size of a flash block for erasing. This is either 2 or 4 kb depending + * on the microcontroller derivative. + */ +#define FLASH_ERASE_BLOCK_SIZE (FEATURE_FLS_PF_BLOCK_SECTOR_SIZE) +/** \brief Total numbers of sectors in array flashLayout[]. */ +#define FLASH_TOTAL_SECTORS (sizeof(flashLayout)/sizeof(flashLayout[0])) +/** \brief End address of the bootloader programmable flash. */ +#define FLASH_END_ADDRESS (flashLayout[FLASH_TOTAL_SECTORS-1].sector_start + \ + flashLayout[FLASH_TOTAL_SECTORS-1].sector_size - 1) +/** \brief FTFC program phrase command code. */ +#define FLASH_FTFC_CMD_PROGRAM_PHRASE (0x07U) +/** \brief FTFC erase sector command code. */ +#define FLASH_FTFC_CMD_ERASE_SECTOR (0x09U) + +/** \brief Offset into the user program's vector table where the checksum is located. + * Note that the value can be overriden in blt_conf.h, because the size of the + * vector table could vary. When changing this value, don't forget to update the + * location of the checksum in the user program accordingly. Otherwise the + * checksum verification will always fail. + */ +#ifndef BOOT_FLASH_VECTOR_TABLE_CS_OFFSET +#define BOOT_FLASH_VECTOR_TABLE_CS_OFFSET (0xC0) +#endif + + +/**************************************************************************************** +* Plausibility checks +****************************************************************************************/ +#if (BOOT_FLASH_VECTOR_TABLE_CS_OFFSET >= FLASH_WRITE_BLOCK_SIZE) +#error "BOOT_FLASH_VECTOR_TABLE_CS_OFFSET is set too high. It must be located in the first writable block." +#endif + +#ifndef BOOT_FLASH_CUSTOM_LAYOUT_ENABLE +#define BOOT_FLASH_CUSTOM_LAYOUT_ENABLE (0u) +#endif + + +/**************************************************************************************** +* Type definitions +****************************************************************************************/ +/** \brief Flash sector descriptor type. */ +typedef struct +{ + blt_addr sector_start; /**< sector start address */ + blt_int32u sector_size; /**< sector size in bytes */ + blt_int8u sector_num; /**< sector number */ +} tFlashSector; + +/** \brief Structure type for grouping flash block information. + * \details Programming is done per block of max FLASH_WRITE_BLOCK_SIZE. for this a + * flash block manager is implemented in this driver. this flash block manager + * depends on this flash block info structure. It holds the base address of + * the flash block and the data that should be programmed into the flash + * block. The .base_addr must be a multiple of FLASH_WRITE_BLOCK_SIZE. + */ +typedef struct +{ + blt_addr base_addr; + blt_int8u data[FLASH_WRITE_BLOCK_SIZE]; +} tFlashBlockInfo; + + +/**************************************************************************************** +* Hook functions +****************************************************************************************/ +#if (BOOT_FLASH_CRYPTO_HOOKS_ENABLE > 0) +extern blt_bool FlashCryptoDecryptDataHook(blt_int8u * data, blt_int32u size); +#endif + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static blt_bool FlashInitBlock(tFlashBlockInfo *block, blt_addr address); +static tFlashBlockInfo *FlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr); +static blt_bool FlashAddToBlock(tFlashBlockInfo *block, blt_addr address, + blt_int8u *data, blt_int32u len); +static blt_bool FlashWriteBlock(tFlashBlockInfo *block); +static blt_bool FlashEraseSectors(blt_int8u first_sector_idx, + blt_int8u last_sector_idx); +static blt_int8u FlashGetSectorIdx(blt_addr address); +START_FUNCTION_DECLARATION_RAMSECTION +static void FlashCommandSequence(void) +END_FUNCTION_DECLARATION_RAMSECTION + + +/**************************************************************************************** +* Local constant declarations +****************************************************************************************/ +/** \brief If desired, it is possible to set BOOT_FLASH_CUSTOM_LAYOUT_ENABLE to > 0 + * in blt_conf.h and then implement your own version of the flashLayout[] table + * in a source-file with the name flash_layout.c. This way you customize the + * flash memory size reserved for the bootloader, without having to modify + * the flashLayout[] table in this file directly. This file will then include + * flash_layout.c so there is no need to compile it additionally with your + * project. + */ +#if (BOOT_FLASH_CUSTOM_LAYOUT_ENABLE == 0) +/** \brief Array wit the layout of the flash memory. + * \details Also controls what part of the flash memory is reserved for the bootloader. + * If the bootloader size changes, the reserved sectors for the bootloader + * might need adjustment to make sure the bootloader doesn't get overwritten. + */ +static const tFlashSector flashLayout[] = +{ + /* Update the contents of this array with the erase sector sizes as defined in the + * microcontroller's reference manual. The flash sector erase sizes are hardware + * specific and must therefore match, otherwise erase operations cannot be performed + * properly. + * Besides controlling the flash erase size, this array also controls which sectors + * are reserved for the bootloader and will therefore never be erased. Note the for the + * S32K11x, the flash sector erase size is 2kb. It was decided to create entries that + * are equal or a multiple of 2kb to simplify the flash layout array and to keep it + * from getting unnecessarily large. + */ + /*{ 0x00000000, 0x00800, 0}, flash sector 0 - reserved for bootloader */ + /*{ 0x00000800, 0x01000, 1}, flash sector 1 - reserved for bootloader */ + /*{ 0x00001000, 0x00800, 2}, flash sector 2 - reserved for bootloader */ + /*{ 0x00001800, 0x00800, 3}, flash sector 3 - reserved for bootloader */ + { 0x00002000, 0x00800, 4}, /* flash sector 4 - 2kb */ + { 0x00002800, 0x00800, 5}, /* flash sector 5 - 2kb */ + { 0x00003000, 0x00800, 6}, /* flash sector 6 - 2kb */ + { 0x00003800, 0x00800, 7}, /* flash sector 7 - 2kb */ + { 0x00004000, 0x00800, 8}, /* flash sector 8 - 2kb */ + { 0x00004800, 0x00800, 9}, /* flash sector 9 - 2kb */ + { 0x00005000, 0x00800, 10}, /* flash sector 10 - 2kb */ + { 0x00005800, 0x00800, 11}, /* flash sector 11 - 2kb */ + { 0x00006000, 0x00800, 12}, /* flash sector 12 - 2kb */ + { 0x00006800, 0x00800, 13}, /* flash sector 13 - 2kb */ + { 0x00007000, 0x00800, 14}, /* flash sector 14 - 2kb */ + { 0x00007800, 0x00800, 15}, /* flash sector 15 - 2kb */ + { 0x00008000, 0x08000, 16}, /* flash sector 16 - 32kb */ + { 0x00010000, 0x08000, 17}, /* flash sector 17 - 32kb */ + { 0x00018000, 0x08000, 18}, /* flash sector 18 - 32kb */ + #if (BOOT_NVM_SIZE_KB > 128) + { 0x00020000, 0x08000, 19}, /* flash sector 19 - 32kb */ + { 0x00028000, 0x08000, 20}, /* flash sector 20 - 32kb */ + { 0x00030000, 0x08000, 21}, /* flash sector 21 - 32kb */ + { 0x00038000, 0x08000, 22}, /* flash sector 22 - 32kb */ + #endif + #if (BOOT_NVM_SIZE_KB > 256) + #error "BOOT_NVM_SIZE_KB > 256 is currently not supported." + #endif +}; +#else +#include "flash_layout.c" +#endif /* BOOT_FLASH_CUSTOM_LAYOUT_ENABLE == 0 */ + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Local variable with information about the flash block that is currently + * being operated on. + * \details The smallest amount of flash that can be programmed is + * FLASH_WRITE_BLOCK_SIZE. A flash block manager is implemented in this driver + * and stores info in this variable. Whenever new data should be flashed, it + * is first added to a RAM buffer, which is part of this variable. Whenever + * the RAM buffer, which has the size of a flash block, is full or data needs + * to be written to a different block, the contents of the RAM buffer are + * programmed to flash. The flash block manager requires some software + * overhead, yet results is faster flash programming because data is first + * harvested, ideally until there is enough to program an entire flash block, + * before the flash device is actually operated on. + */ +static tFlashBlockInfo blockInfo; + +/** \brief Local variable with information about the flash boot block. + * \details The first block of the user program holds the vector table, which on the + * STM32 is also the where the checksum is written to. Is it likely that + * the vector table is first flashed and then, at the end of the programming + * sequence, the checksum. This means that this flash block need to be written + * to twice. Normally this is not a problem with flash memory, as long as you + * write the same values to those bytes that are not supposed to be changed + * and the locations where you do write to are still in the erased 0xFF state. + * Unfortunately, writing twice to flash this way, does not work reliably on + * all micros. This is why we need to have an extra block, the bootblock, + * placed under the management of the block manager. This way is it possible + * to implement functionality so that the bootblock is only written to once + * at the end of the programming sequence. + */ +static tFlashBlockInfo bootBlockInfo; + + +/************************************************************************************//** +** \brief Initializes the flash driver. +** \return none. +** +****************************************************************************************/ +void FlashInit(void) +{ + /* init the flash block info structs by setting the address to an invalid address */ + blockInfo.base_addr = FLASH_INVALID_ADDRESS; + bootBlockInfo.base_addr = FLASH_INVALID_ADDRESS; +} /*** end of FlashInit ***/ + + +/************************************************************************************//** +** \brief Reinitializes the flash driver. +** \return none. +** +****************************************************************************************/ +void FlashReinit(void) +{ + /* init the flash block info structs by setting the address to an invalid address */ + blockInfo.base_addr = FLASH_INVALID_ADDRESS; + bootBlockInfo.base_addr = FLASH_INVALID_ADDRESS; +} /*** end of FlashReinit ***/ + + +/************************************************************************************//** +** \brief Writes the data to flash through a flash block manager. Note that this +** function also checks that no data is programmed outside the flash +** memory region, so the bootloader can never be overwritten. +** \param addr Start address. +** \param len Length in bytes. +** \param data Pointer to the data buffer. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data) +{ + blt_bool result = BLT_TRUE; + blt_addr base_addr; + + /* validate the len parameter */ + if ((len - 1) > (FLASH_END_ADDRESS - addr)) + { + result = BLT_FALSE; + } + + /* only continue if all is okay so far */ + if (result == BLT_TRUE) + { + /* make sure the addresses are within the flash device */ + if ((FlashGetSectorIdx(addr) == FLASH_INVALID_SECTOR_IDX) || \ + (FlashGetSectorIdx(addr+len-1) == FLASH_INVALID_SECTOR_IDX)) + { + result = BLT_FALSE; + } + } + + /* only continue if all is okay so far */ + if (result == BLT_TRUE) + { + /* if this is the bootblock, then let the boot block manager handle it */ + base_addr = (addr/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE; + if (base_addr == flashLayout[0].sector_start) + { + /* let the boot block manager handle it */ + result = FlashAddToBlock(&bootBlockInfo, addr, data, len); + } + else + { + /* let the block manager handle it */ + result = FlashAddToBlock(&blockInfo, addr, data, len); + } + } + + /* give the result back to the caller */ + return result; +} /*** end of FlashWrite ***/ + + +/************************************************************************************//** +** \brief Erases the flash memory. Note that this function also checks that no +** data is erased outside the flash memory region, so the bootloader can +** never be erased. +** \param addr Start address. +** \param len Length in bytes. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool FlashErase(blt_addr addr, blt_int32u len) +{ + blt_bool result = BLT_TRUE; + blt_int8u first_sector_idx; + blt_int8u last_sector_idx; + + /* validate the len parameter */ + if ((len - 1) > (FLASH_END_ADDRESS - addr)) + { + result = BLT_FALSE; + } + + /* only continue if all is okay so far */ + if (result == BLT_TRUE) + { + /* obtain the first and last sector entry indices to the flashLayout[] array. */ + first_sector_idx = FlashGetSectorIdx(addr); + last_sector_idx = FlashGetSectorIdx(addr+len-1); + /* check them */ + if ((first_sector_idx == FLASH_INVALID_SECTOR_IDX) || + (last_sector_idx == FLASH_INVALID_SECTOR_IDX)) + { + result = BLT_FALSE; + } + } + + /* only continue if all is okay so far */ + if (result == BLT_TRUE) + { + /* erase the sectors */ + result = FlashEraseSectors(first_sector_idx, last_sector_idx); + } + + /* give the result back to the caller */ + return result; +} /*** end of FlashErase ***/ + + +/************************************************************************************//** +** \brief Writes a checksum of the user program to non-volatile memory. This is +** performed once the entire user program has been programmed. Through +** the checksum, the bootloader can check if the programming session +** was completed, which indicates that a valid user programming is +** present and can be started. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool FlashWriteChecksum(void) +{ + blt_bool result = BLT_TRUE; + blt_int32u signature_checksum = 0; + + /* first check that the bootblock contains valid data. if not, this means the + * bootblock is not part of the reprogramming this time and therefore no + * new checksum needs to be written + */ + if (bootBlockInfo.base_addr != FLASH_INVALID_ADDRESS) + { +#if (BOOT_FLASH_CRYPTO_HOOKS_ENABLE > 0) + /* perform decryption of the bootblock, before calculating the checksum and writing it + * to flash memory. + */ + if (FlashCryptoDecryptDataHook(bootBlockInfo.data, FLASH_WRITE_BLOCK_SIZE) == BLT_FALSE) + { + result = BLT_FALSE; + } +#endif + + /* only continue if all is okay so far */ + if (result == BLT_TRUE) + { + /* compute the checksum. note that the user program's vectors are not yet written + * to flash but are present in the bootblock data structure at this point. + */ + signature_checksum += *((blt_int32u *)(&bootBlockInfo.data[0+0x00])); + signature_checksum += *((blt_int32u *)(&bootBlockInfo.data[0+0x04])); + signature_checksum += *((blt_int32u *)(&bootBlockInfo.data[0+0x08])); + signature_checksum += *((blt_int32u *)(&bootBlockInfo.data[0+0x0C])); + signature_checksum += *((blt_int32u *)(&bootBlockInfo.data[0+0x10])); + signature_checksum += *((blt_int32u *)(&bootBlockInfo.data[0+0x14])); + signature_checksum += *((blt_int32u *)(&bootBlockInfo.data[0+0x18])); + signature_checksum = ~signature_checksum; /* one's complement */ + signature_checksum += 1; /* two's complement */ + + /* write the checksum */ + result = FlashWrite(flashLayout[0].sector_start+BOOT_FLASH_VECTOR_TABLE_CS_OFFSET, + sizeof(blt_addr), (blt_int8u *)&signature_checksum); + } + } + + /* give the result back to the caller */ + return result; +} /*** end of FlashWriteChecksum ***/ + + +/************************************************************************************//** +** \brief Verifies the checksum, which indicates that a valid user program is +** present and can be started. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool FlashVerifyChecksum(void) +{ + blt_bool result = BLT_TRUE; + blt_int32u signature_checksum = 0; + + /* verify the checksum based on how it was written by FlashWriteChecksum(). */ + signature_checksum += *((blt_int32u *)(flashLayout[0].sector_start)); + signature_checksum += *((blt_int32u *)(flashLayout[0].sector_start+0x04)); + signature_checksum += *((blt_int32u *)(flashLayout[0].sector_start+0x08)); + signature_checksum += *((blt_int32u *)(flashLayout[0].sector_start+0x0C)); + signature_checksum += *((blt_int32u *)(flashLayout[0].sector_start+0x10)); + signature_checksum += *((blt_int32u *)(flashLayout[0].sector_start+0x14)); + signature_checksum += *((blt_int32u *)(flashLayout[0].sector_start+0x18)); + /* add the checksum value that was written by FlashWriteChecksum(). Since this was a + * Two complement's value, the resulting value should equal 0. + */ + signature_checksum += *((blt_int32u *)(flashLayout[0].sector_start+BOOT_FLASH_VECTOR_TABLE_CS_OFFSET)); + /* sum should add up to an unsigned 32-bit value of 0 */ + if (signature_checksum != 0) + { + /* checksum not okay */ + result = BLT_FALSE; + } + + /* give the result back to the caller */ + return result; +} /*** end of FlashVerifyChecksum ***/ + + +/************************************************************************************//** +** \brief Finalizes the flash driver operations. There could still be data in +** the currently active block that needs to be flashed. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool FlashDone(void) +{ + blt_bool result = BLT_TRUE; + + /* check if there is still data waiting to be programmed in the boot block */ + if (bootBlockInfo.base_addr != FLASH_INVALID_ADDRESS) + { + if (FlashWriteBlock(&bootBlockInfo) == BLT_FALSE) + { + /* update the result value to flag the error */ + result = BLT_FALSE; + } + } + + /* only continue if all is okay so far */ + if (result == BLT_TRUE) + { + /* check if there is still data waiting to be programmed */ + if (blockInfo.base_addr != FLASH_INVALID_ADDRESS) + { + if (FlashWriteBlock(&blockInfo) == BLT_FALSE) + { + /* update the result value to flag the error */ + result = BLT_FALSE; + } + } + } + + /* give the result back to the caller */ + return result; +} /*** end of FlashDone ***/ + + +/************************************************************************************//** +** \brief Obtains the base address of the flash memory available to the user program. +** This is basically the first address in the flashLayout table. +** \return Base address. +** +****************************************************************************************/ +blt_addr FlashGetUserProgBaseAddress(void) +{ + blt_addr result; + + result = flashLayout[0].sector_start; + + /* give the result back to the caller */ + return result; +} /*** end of FlashGetUserProgBaseAddress ***/ + + +/************************************************************************************//** +** \brief Copies data currently in flash to the block->data and sets the +** base address. +** \param block Pointer to flash block info structure to operate on. +** \param address Base address of the block data. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +static blt_bool FlashInitBlock(tFlashBlockInfo *block, blt_addr address) +{ + blt_bool result = BLT_TRUE; + + /* check address alignment */ + if ((address % FLASH_WRITE_BLOCK_SIZE) != 0) + { + /* update the result value to flag the error */ + result = BLT_FALSE; + } + + /* only continue if all is okay so far */ + if (result == BLT_TRUE) + { + /* make sure that we are initializing a new block and not the same one */ + if (block->base_addr != address) + { + /* set the base address and copies the current data from flash */ + block->base_addr = address; + CpuMemCopy((blt_addr)block->data, address, FLASH_WRITE_BLOCK_SIZE); + } + } + + /* give the result back to the caller */ + return result; +} /*** end of FlashInitBlock ***/ + + +/************************************************************************************//** +** \brief Switches blocks by programming the current one and initializing the +** next. +** \param block Pointer to flash block info structure to operate on. +** \param base_addr Base address of the next block. +** \return The pointer of the block info struct that is now being used, or a NULL +** pointer in case of error. +** +****************************************************************************************/ +static tFlashBlockInfo *FlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr) +{ + tFlashBlockInfo * result = BLT_NULL; + + /* check if a switch needs to be made away from the boot block. in this case the boot + * block shouldn't be written yet, because this is done at the end of the programming + * session by FlashDone(), this is right after the checksum was written. + */ + if (block == &bootBlockInfo) + { + /* switch from the boot block to the generic block info structure */ + block = &blockInfo; + result = block; + } + /* check if a switch back into the bootblock is needed. in this case the generic block + * doesn't need to be written here yet. + */ + else if (base_addr == flashLayout[0].sector_start) + { + /* switch from the generic block to the boot block info structure */ + block = &bootBlockInfo; + base_addr = flashLayout[0].sector_start; + result = block; + } + /* no switching between the generic block and the bootblock needed. it is a switch + * within a generic block. the current block needs to be first programmed before a + * switch to the new one can be make. + */ + else + { + /* start by initializing the result to success */ + result = block; + /* need to switch to a new block, so program the current one and init the next */ + if (FlashWriteBlock(block) == BLT_FALSE) + { + /* invalidate the result value to flag the error */ + result = BLT_NULL; + } + } + + /* only continue if all is okay sofar */ + if (result != BLT_NULL) + { + /* initialize the new block when necessary */ + if (FlashInitBlock(block, base_addr) == BLT_FALSE) + { + /* invalidate the result value to flag the error */ + result = BLT_NULL; + } + } + + /* Give the result back to the caller. */ + return result; +} /*** end of FlashSwitchBlock ***/ + + +/************************************************************************************//** +** \brief Programming is done per block. This function adds data to the block +** that is currently collecting data to be written to flash. If the +** address is outside of the current block, the current block is written +** to flash an a new block is initialized. +** \param block Pointer to flash block info structure to operate on. +** \param address Flash destination address. +** \param data Pointer to the byte array with data. +** \param len Number of bytes to add to the block. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +static blt_bool FlashAddToBlock(tFlashBlockInfo *block, blt_addr address, + blt_int8u *data, blt_int32u len) +{ + blt_bool result = BLT_TRUE; + blt_addr current_base_addr; + blt_int8u *dst; + blt_int8u *src; + + /* determine the current base address */ + current_base_addr = (address/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE; + + /* make sure the blockInfo is not uninitialized */ + if (block->base_addr == FLASH_INVALID_ADDRESS) + { + /* initialize the blockInfo struct for the current block */ + if (FlashInitBlock(block, current_base_addr) == BLT_FALSE) + { + result = BLT_FALSE; + } + } + + /* only continue if all is okay so far */ + if (result == BLT_TRUE) + { + /* check if the new data fits in the current block */ + if (block->base_addr != current_base_addr) + { + /* need to switch to a new block, so program the current one and init the next */ + block = FlashSwitchBlock(block, current_base_addr); + if (block == BLT_NULL) + { + result = BLT_FALSE; + } + } + } + + /* only continue if all is okay so far */ + if (result == BLT_TRUE) + { + /* add the data to the current block, but check for block overflow */ + dst = &(block->data[address - block->base_addr]); + src = data; + do + { + /* keep the watchdog happy */ + CopService(); + /* buffer overflow? */ + if ((blt_addr)(dst-&(block->data[0])) >= FLASH_WRITE_BLOCK_SIZE) + { + /* need to switch to a new block, so program the current one and init the next */ + block = FlashSwitchBlock(block, current_base_addr+FLASH_WRITE_BLOCK_SIZE); + if (block == BLT_NULL) + { + /* flag error and stop looping */ + result = BLT_FALSE; + break; + } + /* reset destination pointer */ + dst = &(block->data[0]); + } + /* write the data to the buffer */ + *dst = *src; + /* update pointers */ + dst++; + src++; + /* decrement byte counter */ + len--; + } + while (len > 0); + } + + /* give the result back to the caller */ + return result; +} /*** end of FlashAddToBlock ***/ + + +/************************************************************************************//** +** \brief Programs FLASH_WRITE_BLOCK_SIZE bytes to flash from the block->data +** array. +** \param block Pointer to flash block info structure to operate on. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +static blt_bool FlashWriteBlock(tFlashBlockInfo *block) +{ + blt_bool result = BLT_TRUE; + blt_addr prog_addr; + blt_int8u * prog_data; + blt_int8u const * flash_data; + blt_int32u phrase_cnt; + blt_int8u const phrase_size = FEATURE_FLS_PF_BLOCK_WRITE_UNIT_SIZE; + blt_int8u phrase_byte_idx; + + /* check that the address is actually within flash */ + if (FlashGetSectorIdx(block->base_addr) == FLASH_INVALID_SECTOR_IDX) + { + result = BLT_FALSE; + } + +#if (BOOT_FLASH_CRYPTO_HOOKS_ENABLE > 0) + #if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE == 0) + /* note that the bootblock is already decrypted in FlashWriteChecksum(), if the + * internal checksum mechanism is used. Therefore don't decrypt it again. + */ + if (block != &bootBlockInfo) + #endif + { + /* perform decryption of the program data before writing it to flash memory. */ + if (FlashCryptoDecryptDataHook(block->data, FLASH_WRITE_BLOCK_SIZE) == BLT_FALSE) + { + result = BLT_FALSE; + } + } +#endif + + /* only continue if all is okay so far */ + if (result == BLT_TRUE) + { + /* program all phrases in the block one by one */ + for (phrase_cnt=0; phrase_cnt<(FLASH_WRITE_BLOCK_SIZE/phrase_size); phrase_cnt++) + { + prog_addr = block->base_addr + (phrase_cnt * phrase_size); + prog_data = &block->data[phrase_cnt * phrase_size]; + /* keep the watchdog happy */ + CopService(); + /* check CCIF to verify that the previous command is completed. */ + if ((FTFC->FSTAT & FTFC_FSTAT_CCIF_MASK) == FTFC_FSTAT_CCIF(0)) + { + /* FTFC module should not be busy anymore. flag error and abort. */ + result = BLT_FALSE; + break; + } + /* clear the old errors that might still be set from a previous operation. */ + FTFC->FSTAT = FTFC_FSTAT_FPVIOL_MASK | FTFC_FSTAT_ACCERR_MASK | FTFC_FSTAT_RDCOLERR_MASK; + /* prepare the program phrase command. + * FTFC->FCCOB[3] = FCCOB0 + */ + FTFC->FCCOB[3] = FLASH_FTFC_CMD_PROGRAM_PHRASE; + /* set the program base address. + * FTFC->FCCOB[2] = FCCOB1 + * FTFC->FCCOB[1] = FCCOB2 + * FTFC->FCCOB[0] = FCCOB3 + */ + FTFC->FCCOB[2] = (blt_int8u)(((blt_addr)(prog_addr >> 16U)) & 0xFFU); + FTFC->FCCOB[1] = (blt_int8u)(((blt_addr)(prog_addr >> 8U)) & 0xFFU); + FTFC->FCCOB[0] = (blt_int8u)(prog_addr & 0xFFU); + /* set the phrase bytes that should be programmed. + * FTFC->FCCOB[7] = FCCOB4 + * FTFC->FCCOB[6] = FCCOB5 + * FTFC->FCCOB[5] = FCCOB6 + * FTFC->FCCOB[4] = FCCOB7 + * FTFC->FCCOB[11] = FCCOB8 + * FTFC->FCCOB[10] = FCCOB9 + * FTFC->FCCOB[9] = FCCOBA + * FTFC->FCCOB[8] = FCCOBB + */ + FTFC->FCCOB[4] = prog_data[0]; + FTFC->FCCOB[5] = prog_data[1]; + FTFC->FCCOB[6] = prog_data[2]; + FTFC->FCCOB[7] = prog_data[3]; + FTFC->FCCOB[8] = prog_data[4]; + FTFC->FCCOB[9] = prog_data[5]; + FTFC->FCCOB[10] = prog_data[6]; + FTFC->FCCOB[11] = prog_data[7]; + /* Execute the command. Note that it needs to run from RAM. */ + FlashCommandSequence(); + /* Check the results. */ + if ((FTFC->FSTAT & (FTFC_FSTAT_MGSTAT0_MASK | FTFC_FSTAT_FPVIOL_MASK | + FTFC_FSTAT_ACCERR_MASK | FTFC_FSTAT_RDCOLERR_MASK)) != 0U) + { + /* could not perform program operation */ + result = BLT_FALSE; + /* error detected so don't bother continuing with the loop */ + break; + } + /* verify that the written data is actually there. */ + flash_data = ((blt_int8u const *)prog_addr); + for (phrase_byte_idx = 0; phrase_byte_idx < phrase_size; phrase_byte_idx++) + { + /* check that the byte in flash has the same value as what was programmed. */ + if (flash_data[phrase_byte_idx] != prog_data[phrase_byte_idx]) + { + /* verification of programmed data failed. */ + result = BLT_FALSE; + /* error detected so don't bother continuing with the loop */ + break; + + } + } + } + } + + /* Give the result back to the caller. */ + return result; +} /*** end of FlashWriteBlock ***/ + + +/************************************************************************************//** +** \brief Erases the flash sectors from indices first_sector_idx up until +** last_sector_idx into the flashLayout[] array. +** \param first_sector_idx First flash sector number index into flashLayout[]. +** \param last_sector_idx Last flash sector number index into flashLayout[]. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +static blt_bool FlashEraseSectors(blt_int8u first_sector_idx, blt_int8u last_sector_idx) +{ + blt_bool result = BLT_TRUE; + blt_int8u sectorIdx; + blt_addr sectorBaseAddr; + blt_int32u sectorSize; + blt_int8u blockIdx; + blt_addr blockBaseAddr; + blt_int8u totalBlocks; + + /* validate the sector numbers */ + if (first_sector_idx > last_sector_idx) + { + result = BLT_FALSE; + } + + /* only continue if all is okay so far */ + if (result == BLT_TRUE) + { + if (last_sector_idx > (FLASH_TOTAL_SECTORS-1)) + { + result = BLT_FALSE; + } + } + + /* only continue if all is okay so far */ + if (result == BLT_TRUE) + { + /* erase the sectors one by one */ + for (sectorIdx = first_sector_idx; sectorIdx <= last_sector_idx; sectorIdx++) + { + /* service the watchdog */ + CopService(); + /* get information about the sector */ + sectorBaseAddr = flashLayout[sectorIdx].sector_start; + sectorSize = flashLayout[sectorIdx].sector_size; + /* validate the sector information */ + if ( (sectorBaseAddr == FLASH_INVALID_ADDRESS) || (sectorSize == 0) ) + { + /* invalid sector information. flag error and abort erase operation */ + result = BLT_FALSE; + break; + } + + /* each sector could contain more than just one block. make sure the base address + * of the sector is block aligned. + */ + if ((sectorBaseAddr % FLASH_ERASE_BLOCK_SIZE) != 0) + { + /* sector base address not aligned to the start of a block. flag error and abort + * erase operation + */ + result = BLT_FALSE; + break; + } + + /* make sure the sector size is an exact multiple of the block size. */ + if ((sectorSize % FLASH_ERASE_BLOCK_SIZE) != 0) + { + /* sector base address not aligned to the start of a block. flag error and abort + * erase operation + */ + result = BLT_FALSE; + break; + } + + /* erase the sector one block at a time. */ + totalBlocks = sectorSize / FLASH_ERASE_BLOCK_SIZE; + for (blockIdx = 0; blockIdx < totalBlocks; blockIdx++) + { + /* service the watchdog */ + CopService(); + /* store the block base address. */ + blockBaseAddr = sectorBaseAddr + (blockIdx * FLASH_ERASE_BLOCK_SIZE); + /* check CCIF to verify that the previous command is completed. */ + if ((FTFC->FSTAT & FTFC_FSTAT_CCIF_MASK) == FTFC_FSTAT_CCIF(0)) + { + /* FTFC module should not be busy anymore. flag error and abort. */ + result = BLT_FALSE; + break; + } + /* clear the old errors that might still be set from a previous operation. */ + FTFC->FSTAT = FTFC_FSTAT_FPVIOL_MASK | FTFC_FSTAT_ACCERR_MASK | FTFC_FSTAT_RDCOLERR_MASK; + /* prepare the sector erase command. + * FTFC->FCCOB[3] = FCCOB0 + */ + FTFC->FCCOB[3] = FLASH_FTFC_CMD_ERASE_SECTOR; + /* set the erase sector base address. note that in this function that means the + * block base address. + * FTFC->FCCOB[2] = FCCOB1 + * FTFC->FCCOB[1] = FCCOB2 + * FTFC->FCCOB[0] = FCCOB3 + */ + FTFC->FCCOB[2] = (blt_int8u)(((blt_addr)(blockBaseAddr >> 16U)) & 0xFFU); + FTFC->FCCOB[1] = (blt_int8u)(((blt_addr)(blockBaseAddr >> 8U)) & 0xFFU); + FTFC->FCCOB[0] = (blt_int8u)(blockBaseAddr & 0xFFU); + /* Execute the command. Note that it needs to run from RAM. */ + FlashCommandSequence(); + /* Check the results. */ + if ((FTFC->FSTAT & (FTFC_FSTAT_MGSTAT0_MASK | FTFC_FSTAT_FPVIOL_MASK | + FTFC_FSTAT_ACCERR_MASK | FTFC_FSTAT_RDCOLERR_MASK)) != 0U) + { + /* could not perform erase operation */ + result = BLT_FALSE; + /* error detected so don't bother continuing with the loop */ + break; + } + } + + /* Only continue with the next sector if all is okay so far. */ + if (result == BLT_FALSE) + { + break; + } + } + } + + /* give the result back to the caller */ + return result; +} /*** end of FlashEraseSectors ***/ + + +/************************************************************************************//** +** \brief Determines the index into the flashLayout[] array of the flash sector that +** the specified address is in. +** \param address Address in the flash sector. +** \return Flash sector index in flashLayout[] or FLASH_INVALID_SECTOR_IDX. +** +****************************************************************************************/ +static blt_int8u FlashGetSectorIdx(blt_addr address) +{ + blt_int8u result = FLASH_INVALID_SECTOR_IDX; + blt_int8u sectorIdx; + + /* search through the sectors to find the right one */ + for (sectorIdx = 0; sectorIdx < FLASH_TOTAL_SECTORS; sectorIdx++) + { + /* keep the watchdog happy */ + CopService(); + /* is the address in this sector? */ + if ((address >= flashLayout[sectorIdx].sector_start) && \ + (address < (flashLayout[sectorIdx].sector_start + \ + flashLayout[sectorIdx].sector_size))) + { + /* update the result value and stop looping */ + result = sectorIdx; + break; + } + } + + /* give the result back to the caller */ + return result; +} /*** end of FlashGetSectorIdx ***/ + + +/************************************************************************************//** +** \brief Use the FTFC module to run the flash command sequence. It is assumed that +** that command and its necessary parameters were already written to the +** correct FTFC registers. +** \attention This function needs to run from RAM. It is configured such that the C +** start-up code automatically copies it from ROM to RAM in function +** init_data_bss(), which is called by the reset handler. +** \return None. +** +****************************************************************************************/ +START_FUNCTION_DEFINITION_RAMSECTION +static void FlashCommandSequence(void) +{ + /* Clear CCIF to launch command. This is done by writing a 1 to the bit. */ + FTFC->FSTAT |= FTFC_FSTAT_CCIF_MASK; + + /* Wait for operation to complete. + * From S32K Reference Manual: + * While executing from a particular PFLASH read partition , FTFC commands (except + * parallel boot) cannot run over that PFLASH read partition. + * + * The S32K series up to 512kB only have 1 partition, meaning we cannot return from + * this (ram based) function until the operation completes. We don't have to worry + * about a potentially endless loop, as if an error occurs during the command, the + * operation will return and set an error flag, which can be evaluated after this + * function call. If an operation hangs we have a processor hardware error, and have + * more to worry about than a hanging while loop. + */ + while ((FTFC->FSTAT & FTFC_FSTAT_CCIF_MASK) == 0U) + { + /* Ideally, the watchdog is serviced in this function. But function CopService() is + * located in the flash partition and can therefore not be accessed. This does mean + * that the watchdog timeout period should be configured to be longer that the worst + * case execution time of the flash phrase program / sector erase commands. + */ + ; + } +} /*** end of FlashCommandSequence ***/ +END_FUNCTION_DEFINITION_RAMSECTION + + +/*********************************** end of flash.c ************************************/ diff --git a/Target/Source/ARMCM0_S32K11/flash.h b/Target/Source/ARMCM0_S32K11/flash.h new file mode 100644 index 00000000..7d870911 --- /dev/null +++ b/Target/Source/ARMCM0_S32K11/flash.h @@ -0,0 +1,45 @@ +/************************************************************************************//** +* \file Source/ARMCM0_S32K11/flash.h +* \brief Bootloader flash driver header file. +* \ingroup Target_ARMCM0_S32K11 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef FLASH_H +#define FLASH_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void FlashInit(void); +void FlashReinit(void); +blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data); +blt_bool FlashErase(blt_addr addr, blt_int32u len); +blt_bool FlashWriteChecksum(void); +blt_bool FlashVerifyChecksum(void); +blt_bool FlashDone(void); +blt_addr FlashGetUserProgBaseAddress(void); + + +#endif /* FLASH_H */ +/*********************************** end of flash.h ************************************/ diff --git a/Target/Source/ARMCM0_S32K11/nvm.c b/Target/Source/ARMCM0_S32K11/nvm.c new file mode 100644 index 00000000..9e6c39f0 --- /dev/null +++ b/Target/Source/ARMCM0_S32K11/nvm.c @@ -0,0 +1,245 @@ +/************************************************************************************//** +* \file Source/ARMCM0_S32K11/nvm.c +* \brief Bootloader non-volatile memory driver source file. +* \ingroup Target_ARMCM0_S32K11 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "flash.h" + + +/**************************************************************************************** +* Hook functions +****************************************************************************************/ +#if (BOOT_NVM_HOOKS_ENABLE > 0) +extern void NvmInitHook(void); +extern void NvmReinitHook(void); +extern blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data); +extern blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len); +extern blt_bool NvmDoneHook(void); +#endif + +#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0) +extern blt_bool NvmWriteChecksumHook(void); +extern blt_bool NvmVerifyChecksumHook(void); +#endif + + +/************************************************************************************//** +** \brief Initializes the NVM driver. +** \return none. +** +****************************************************************************************/ +void NvmInit(void) +{ +#if (BOOT_NVM_HOOKS_ENABLE > 0) + /* give the application a chance to initialize a driver for operating on NVM + * that is not by default supported by this driver. + */ + NvmInitHook(); +#endif + + /* init the internal driver */ + FlashInit(); +} /*** end of NvmInit ***/ + + +/************************************************************************************//** +** \brief Reinitializes the NVM driver. This function is called at the start of each +** firmware update as opposed to NvmInit, which is only called once during +** power on. +** \return none. +** +****************************************************************************************/ +void NvmReinit(void) +{ +#if (BOOT_NVM_HOOKS_ENABLE > 0) + /* give the application a chance to re-initialize a driver for operating on NVM + * that is not by default supported by this driver. + */ + NvmReinitHook(); +#endif + + /* reinitialize the internal driver */ + FlashReinit(); +} /*** end of NvmReinit ***/ + + +/************************************************************************************//** +** \brief Programs the non-volatile memory. +** \param addr Start address. +** \param len Length in bytes. +** \param data Pointer to the data buffer. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmWrite(blt_addr addr, blt_int32u len, blt_int8u *data) +{ +#if (BOOT_NVM_HOOKS_ENABLE > 0) + blt_int8u result = BLT_NVM_NOT_IN_RANGE; +#endif + +#if (BOOT_NVM_HOOKS_ENABLE > 0) + /* give the application a chance to operate on memory that is not by default supported + * by this driver. + */ + result = NvmWriteHook(addr, len, data); + + /* process the return code */ + if (result == BLT_NVM_OKAY) + { + /* data was within range of the additionally supported memory and succesfully + * programmed, so we are all done. + */ + return BLT_TRUE; + } + else if (result == BLT_NVM_ERROR) + { + /* data was within range of the additionally supported memory and attempted to be + * programmed, but an error occurred, so we can't continue. + */ + return BLT_FALSE; + } +#endif + + /* still here so the internal driver should try and perform the program operation */ + return FlashWrite(addr, len, data); +} /*** end of NvmWrite ***/ + + +/************************************************************************************//** +** \brief Erases the non-volatile memory. +** \param addr Start address. +** \param len Length in bytes. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmErase(blt_addr addr, blt_int32u len) +{ +#if (BOOT_NVM_HOOKS_ENABLE > 0) + blt_int8u result = BLT_NVM_NOT_IN_RANGE; +#endif + +#if (BOOT_NVM_HOOKS_ENABLE > 0) + /* give the application a chance to operate on memory that is not by default supported + * by this driver. + */ + result = NvmEraseHook(addr, len); + + /* process the return code */ + if (result == BLT_NVM_OKAY) + { + /* address was within range of the additionally supported memory and succesfully + * erased, so we are all done. + */ + return BLT_TRUE; + } + else if (result == BLT_NVM_ERROR) + { + /* address was within range of the additionally supported memory and attempted to be + * erased, but an error occurred, so we can't continue. + */ + return BLT_FALSE; + } +#endif + + /* still here so the internal driver should try and perform the erase operation */ + return FlashErase(addr, len); +} /*** end of NvmErase ***/ + + +/************************************************************************************//** +** \brief Verifies the checksum, which indicates that a valid user program is +** present and can be started. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmVerifyChecksum(void) +{ +#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0) + /* check checksum using the application specific method. */ + return NvmVerifyChecksumHook(); +#else + /* check checksum using the interally supported method. */ + return FlashVerifyChecksum(); +#endif +} /*** end of NvmVerifyChecksum ***/ + + +/************************************************************************************//** +** \brief Obtains the base address of the non-volatile memory available to the user +** program. This is typically that start of the vector table. +** \return Base address. +** +****************************************************************************************/ +blt_addr NvmGetUserProgBaseAddress(void) +{ + return FlashGetUserProgBaseAddress(); +} /*** end of NvmGetUserProgBaseAddress ***/ + + +/************************************************************************************//** +** \brief Once all erase and programming operations are completed, this +** function is called, so at the end of the programming session and +** right before a software reset is performed. It is used to calculate +** a checksum and program this into flash. This checksum is later used +** to determine if a valid user program is present in flash. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmDone(void) +{ +#if (BOOT_NVM_HOOKS_ENABLE > 0) + /* give the application's NVM driver a chance to finish up */ + if (NvmDoneHook() == BLT_FALSE) + { + /* error so no need to continue */ + return BLT_FALSE; + } +#endif + +#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0) + /* compute and write checksum, using the application specific method. */ + if (NvmWriteChecksumHook() == BLT_FALSE) + { + return BLT_FALSE; + } +#else + /* compute and write checksum, which is programmed by the internal driver. */ + if (FlashWriteChecksum() == BLT_FALSE) + { + return BLT_FALSE; + } +#endif + + /* finish up internal driver operations */ + return FlashDone(); +} /*** end of NvmDone ***/ + + +/*********************************** end of nvm.c **************************************/ diff --git a/Target/Source/ARMCM0_S32K11/rs232.c b/Target/Source/ARMCM0_S32K11/rs232.c new file mode 100644 index 00000000..755779cf --- /dev/null +++ b/Target/Source/ARMCM0_S32K11/rs232.c @@ -0,0 +1,335 @@ +/************************************************************************************//** +* \file Source/ARMCM0_S32K11/uart.c +* \brief Bootloader RS232 communication interface source file. +* \ingroup Target_ARMCM0_S32K11 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#if (BOOT_COM_RS232_ENABLE > 0) +#include "device_registers.h" /* device registers */ + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Timeout time for the reception of a CTO packet. The timer is started upon + * reception of the first packet byte. + */ +#define RS232_CTO_RX_PACKET_TIMEOUT_MS (100U) +/** \brief Timeout for transmitting a byte in milliseconds. */ +#define RS232_BYTE_TX_TIMEOUT_MS (10U) + +#if (BOOT_COM_RS232_CHANNEL_INDEX == 0) +/** \brief Set the peripheral LPUART0 base pointer. */ +#define LPUARTx (LPUART0) +/** \brief Set the PCC index offset for LPUART0. */ +#define PCC_LPUARTx_INDEX (PCC_LPUART0_INDEX) +#elif (BOOT_COM_RS232_CHANNEL_INDEX == 1) +/** \brief Set the peripheral LPUART1 base pointer. */ +#define LPUARTx (LPUART1) +/** \brief Set the PCC index offset for LPUART1. */ +#define PCC_LPUARTx_INDEX (PCC_LPUART1_INDEX) +#endif + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static blt_bool Rs232ReceiveByte(blt_int8u *data); +static void Rs232TransmitByte(blt_int8u data); + + +/************************************************************************************//** +** \brief Initializes the RS232 communication interface. +** \return none. +** +****************************************************************************************/ +void Rs232Init(void) +{ + blt_int32u sourceClockFreqHz; + blt_int32u div2RegValue; + blt_int16u baudrateSbr0_12; + blt_int8u const div2DividerLookup[] = + { + 0U, /* 0b000. Output disabled. */ + 1U, /* 0b001. Divide by 1. */ + 2U, /* 0b010. Divide by 2. */ + 4U, /* 0b011. Divide by 4. */ + 8U, /* 0b100. Divide by 8. */ + 16U, /* 0b101. Divide by 16. */ + 32U, /* 0b110. Divide by 32. */ + 64U, /* 0b111. Divide by 64. */ + }; + + /* Perform compile time assertion to check that the configured UART channel is actually + * supported by this driver. + */ + ASSERT_CT((BOOT_COM_RS232_CHANNEL_INDEX == 0) || + (BOOT_COM_RS232_CHANNEL_INDEX == 1)); + + /* Make sure the UART peripheral clock is disabled before configuring its source + * clock. + */ + PCC->PCCn[PCC_LPUARTx_INDEX] &= ~PCC_PCCn_CGC_MASK; + /* Select option 2 as the UART peripheral source clock and enable the clock. Option 2 + * is the SIRCDIV2_CLK, which is available on all peripherals and configurations. + */ + PCC->PCCn[PCC_LPUARTx_INDEX] |= PCC_PCCn_PCS(2) | PCC_PCCn_CGC_MASK; + /* Obtain the DIV2 divider value of the SIRC_CLK. */ + div2RegValue = (SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT; + /* Check if the DIV2 register value for SIRC is 0. In this case SIRCDIV2_CLK is + * currently disabled. + */ + if (div2RegValue == 0U) + { + /* Configure the DIV2 for a default divide by 1 to make sure the SIRCDIV2_CLK is + * actually enabled. + */ + div2RegValue = 1U; + SCG->SIRCDIV |= SCG_SIRCDIV_SIRCDIV2(div2RegValue); + } + /* Determine the SIRC clock frequency. If SIRC high range is enabled, it is 8 MHz. If + * SIRC low range is enabled, it is 2 MHz. + */ + sourceClockFreqHz = 8000000U; + if ((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) == SCG_SIRCCFG_RANGE(0)) + { + sourceClockFreqHz = 2000000U; + } + /* Now process the configured DIV2 divider factor to get the actual frequency of the + * UART peripheral source clock. + */ + sourceClockFreqHz /= div2DividerLookup[div2RegValue]; + /* Configure the baudrate from BOOT_COM_RS232_BAUDRATE, taking into account that an + * oversampling of 8 will be configured. Default 8,n,1 format is used. Integer + * rounding is used to get the best value for baudrateSbr0_12. Actual baudrate equals + * sourceClockFreqHz / 8 / baudrateSbr0_12. + */ + baudrateSbr0_12 = (((sourceClockFreqHz / BOOT_COM_RS232_BAUDRATE) + (8U - 1U)) / 8U) & + LPUART_BAUD_SBR_MASK; + /* OSR=7: Over sampling ratio = 7+1=8. + * SBNS=0: One stop bit. + * BOTHEDGE=0: receiver samples only on rising edge. + * M10=0: Rx and Tx use 7 to 9 bit data characters. + * RESYNCDIS=0: Resync during rec'd data word supported. + * LBKDIE, RXEDGIE=0: interrupts disable. + * TDMAE, RDMAE, TDMAE=0: DMA requests disabled. + * MAEN1, MAEN2, MATCFG=0: Match disabled. + */ + LPUARTx->BAUD = LPUART_BAUD_SBR(baudrateSbr0_12) | LPUART_BAUD_OSR(7); + /* Clear the error/interrupt flags */ + LPUARTx->STAT = FEATURE_LPUART_STAT_REG_FLAGS_MASK; + /* Reset all features/interrupts by default */ + LPUARTx->CTRL = 0x00000000; + /* Reset match addresses */ + LPUARTx->MATCH = 0x00000000; +#if FEATURE_LPUART_HAS_MODEM_SUPPORT + /* Reset IrDA modem features */ + LPUARTx->MODIR = 0x00000000; +#endif +#if FEATURE_LPUART_FIFO_SIZE > 0U + /* Reset FIFO feature */ + LPUARTx->FIFO = FEATURE_LPUART_FIFO_RESET_MASK; + /* Enable the transmit and receive FIFOs. */ + LPUARTx->FIFO |= LPUART_FIFO_TXFE(1) | LPUART_FIFO_RXFE(1); + /* Set the reception water mark to 0 and the transmitter water mark to 1. */ + LPUARTx->WATER = LPUART_WATER_TXWATER(1) | LPUART_WATER_RXWATER(0); +#endif + /* Enable transmitter and receiver, no parity, 8 bit char: + * RE=1: Receiver enabled. + * TE=1: Transmitter enabled. + * PE,PT=0: No hw parity generation or checking. + * M7,M,R8T9,R9T8=0: 8-bit data characters. + * DOZEEN=0: LPUART enabled in Doze mode. + * ORIE,NEIE,FEIE,PEIE,TIE,TCIE,RIE,ILIE,MA1IE,MA2IE=0: no IRQ. + * TxDIR=0: TxD pin is input if in single-wire mode. + * TXINV=0: Transmit data not inverted. + * RWU,WAKE=0: normal operation; rcvr not in standby. + * IDLCFG=0: one idle character. + * ILT=0: Idle char bit count starts after start bit. + * SBK=0: Normal transmitter operation - no break char. + * LOOPS,RSRC=0: no loop back. + */ + LPUARTx->CTRL = LPUART_CTRL_RE_MASK | LPUART_CTRL_TE_MASK; +} /*** end of Rs232Init ***/ + + +/************************************************************************************//** +** \brief Transmits a packet formatted for the communication interface. +** \param data Pointer to byte array with data that it to be transmitted. +** \param len Number of bytes that are to be transmitted. +** \return none. +** +****************************************************************************************/ +void Rs232TransmitPacket(blt_int8u *data, blt_int8u len) +{ + blt_int16u data_index; + + /* Verify validity of the len-paramenter. */ + ASSERT_RT(len <= BOOT_COM_RS232_TX_MAX_DATA); + + /* First transmit the length of the packet. */ + Rs232TransmitByte(len); + + /* Transmit all the packet bytes one-by-one. */ + for (data_index = 0U; data_index < len; data_index++) + { + /* Keep the watchdog happy. */ + CopService(); + /* Write byte. */ + Rs232TransmitByte(data[data_index]); + } +} /*** end of Rs232TransmitPacket ***/ + + +/************************************************************************************//** +** \brief Receives a communication interface packet if one is present. +** \param data Pointer to byte array where the data is to be stored. +** \param len Pointer where the length of the packet is to be stored. +** \return BLT_TRUE if a packet was received, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool Rs232ReceivePacket(blt_int8u *data, blt_int8u *len) +{ + static blt_int8u xcpCtoReqPacket[BOOT_COM_RS232_RX_MAX_DATA+1U]; /* One extra for length. */ + static blt_int8u xcpCtoRxLength; + static blt_bool xcpCtoRxInProgress = BLT_FALSE; + static blt_int32u xcpCtoRxStartTime = 0U; + + /* Start of cto packet received? */ + if (xcpCtoRxInProgress == BLT_FALSE) + { + /* Store the message length when received. */ + if (Rs232ReceiveByte(&xcpCtoReqPacket[0]) == BLT_TRUE) + { + if ( (xcpCtoReqPacket[0] > 0U) && + (xcpCtoReqPacket[0] <= BOOT_COM_RS232_RX_MAX_DATA) ) + { + /* Store the start time. */ + xcpCtoRxStartTime = TimerGet(); + /* Reset packet data count. */ + xcpCtoRxLength = 0U; + /* Indicate that a cto packet is being received. */ + xcpCtoRxInProgress = BLT_TRUE; + } + } + } + else + { + /* Store the next packet byte. */ + if (Rs232ReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1U]) == BLT_TRUE) + { + /* Increment the packet data count. */ + xcpCtoRxLength++; + + /* Check to see if the entire packet was received. */ + if (xcpCtoRxLength == xcpCtoReqPacket[0]) + { + /* Copy the packet data. */ + CpuMemCopy((blt_int32u)data, (blt_int32u)&xcpCtoReqPacket[1], xcpCtoRxLength); + /* Done with cto packet reception. */ + xcpCtoRxInProgress = BLT_FALSE; + /* Set the packet length. */ + *len = xcpCtoRxLength; + /* Packet reception complete. */ + return BLT_TRUE; + } + } + else + { + /* Check packet reception timeout. */ + if (TimerGet() > (xcpCtoRxStartTime + RS232_CTO_RX_PACKET_TIMEOUT_MS)) + { + /* Cancel cto packet reception due to timeout. Note that that automaticaly + * discards the already received packet bytes, allowing the host to retry. + */ + xcpCtoRxInProgress = BLT_FALSE; + } + } + } + /* Packet reception not yet complete. */ + return BLT_FALSE; +} /*** end of Rs232ReceivePacket ***/ + + +/************************************************************************************//** +** \brief Receives a communication interface byte if one is present. +** \param data Pointer to byte where the data is to be stored. +** \return BLT_TRUE if a byte was received, BLT_FALSE otherwise. +** +****************************************************************************************/ +static blt_bool Rs232ReceiveByte(blt_int8u *data) +{ + blt_bool result = BLT_FALSE; + + /* Check if a new byte was received by means of the RDRF-bit. */ + if (((LPUARTx->STAT & LPUART_STAT_RDRF_MASK) >> LPUART_STAT_RDRF_SHIFT) != 0U) + { + /* Retrieve and store the newly received byte. */ + *data = LPUARTx->DATA; + /* Update the result. */ + result = BLT_TRUE; + } + + /* Give the result back to the caller. */ + return result; +} /*** end of Rs232ReceiveByte ***/ + + +/************************************************************************************//** +** \brief Transmits a communication interface byte. +** \param data Value of byte that is to be transmitted. +** \return none. +** +****************************************************************************************/ +static void Rs232TransmitByte(blt_int8u data) +{ + blt_int32u timeout; + + /* Write the byte value in 'data' to the transmit register of the UART peripheral such + * that the transmission of the byte value is started. + */ + LPUARTx->DATA = data; + /* Set timeout time to wait for transmit completion. */ + timeout = TimerGet() + RS232_BYTE_TX_TIMEOUT_MS; + /* Wait for tx holding register to be empty. */ + while (((LPUARTx->STAT & LPUART_STAT_TDRE_MASK) >> LPUART_STAT_TDRE_SHIFT) == 0U) + { + /* Keep the watchdog happy. */ + CopService(); + /* Break loop upon timeout. this would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } +} /*** end of Rs232TransmitByte ***/ +#endif /* BOOT_COM_RS232_ENABLE > 0 */ + + +/*********************************** end of rs232.c ************************************/ diff --git a/Target/Source/ARMCM0_S32K11/target.dox b/Target/Source/ARMCM0_S32K11/target.dox new file mode 100644 index 00000000..ee14b209 --- /dev/null +++ b/Target/Source/ARMCM0_S32K11/target.dox @@ -0,0 +1,9 @@ +/** +\defgroup Target_ARMCM0_S32K11 Target ARMCM0 S32K11 +\ingroup Ports +\brief Target dependent code for the NXP ARMCM0 S32K11x microcontroller family. +\details This module implements the bootloader's target dependent part for the + NXP ARMCM0 S32K11x microcontroller family. +*/ + + diff --git a/Target/Source/ARMCM0_S32K11/timer.c b/Target/Source/ARMCM0_S32K11/timer.c new file mode 100644 index 00000000..82e5b234 --- /dev/null +++ b/Target/Source/ARMCM0_S32K11/timer.c @@ -0,0 +1,110 @@ +/************************************************************************************//** +* \file Source/ARMCM0_S32K11/timer.c +* \brief Bootloader timer driver source file. +* \ingroup Target_ARMCM0_S32K11 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "device_registers.h" /* device registers */ + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Local variable for storing the number of milliseconds that have elapsed since + * startup. + */ +static blt_int32u millisecond_counter; + + +/************************************************************************************//** +** \brief Initializes the polling based millisecond timer driver. +** \return none. +** +****************************************************************************************/ +void TimerInit(void) +{ + /* Reset the timer configuration. */ + TimerReset(); + /* Configure the systick frequency as a 1 ms event generator. */ + S32_SysTick->RVR = BOOT_CPU_SYSTEM_SPEED_KHZ - 1; + /* Reset the current counter value. */ + S32_SysTick->CVR = 0u; + /* Select core clock as source and enable the timer. */ + S32_SysTick->CSR = S32_SysTick_CSR_ENABLE_MASK | S32_SysTick_CSR_CLKSOURCE_MASK; + /* Reset the millisecond counter value. */ + millisecond_counter = 0; +} /*** end of TimerInit ***/ + + +/************************************************************************************//** +** \brief Reset the timer by placing the timer back into it's default reset +** configuration. +** \return none. +** +****************************************************************************************/ +void TimerReset(void) +{ + /* Set the systick's status and control register back into the default reset value. */ + S32_SysTick->CSR = 0; +} /* end of TimerReset */ + + +/************************************************************************************//** +** \brief Updates the millisecond timer. +** \return none. +** +****************************************************************************************/ +void TimerUpdate(void) +{ + /* Check if the millisecond event occurred. */ + if ((S32_SysTick->CSR & S32_SysTick_CSR_COUNTFLAG_MASK) != 0) + { + /* Increment the millisecond counter. */ + millisecond_counter++; + } +} /*** end of TimerUpdate ***/ + + +/************************************************************************************//** +** \brief Obtains the counter value of the millisecond timer. +** \return Current value of the millisecond timer. +** +****************************************************************************************/ +blt_int32u TimerGet(void) +{ + /* Updating timer here allows this function to be called in a loop with timeout + * detection. + */ + TimerUpdate(); + /* Read and return the amount of milliseconds that passed since initialization. */ + return millisecond_counter; +} /*** end of TimerGet ***/ + + +/*********************************** end of timer.c ************************************/ diff --git a/Target/Source/ARMCM0_S32K11/types.h b/Target/Source/ARMCM0_S32K11/types.h new file mode 100644 index 00000000..7627865f --- /dev/null +++ b/Target/Source/ARMCM0_S32K11/types.h @@ -0,0 +1,57 @@ +/************************************************************************************//** +* \file Source/ARMCM0_S32K11/types.h +* \brief Bootloader types header file. +* \ingroup Target_ARMCM0_S32K11 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef TYPES_H +#define TYPES_H + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Boolean true value. */ +#define BLT_TRUE (1) +/** \brief Boolean false value. */ +#define BLT_FALSE (0) +/** \brief NULL pointer value. */ +#define BLT_NULL ((void *)0) + + +/**************************************************************************************** +* Type definitions +****************************************************************************************/ +typedef unsigned char blt_bool; /**< boolean type */ +typedef char blt_char; /**< character type */ +typedef unsigned long blt_addr; /**< memory address type */ +typedef unsigned char blt_int8u; /**< 8-bit unsigned integer */ +typedef signed char blt_int8s; /**< 8-bit signed integer */ +typedef unsigned short blt_int16u; /**< 16-bit unsigned integer */ +typedef signed short blt_int16s; /**< 16-bit signed integer */ +typedef unsigned int blt_int32u; /**< 32-bit unsigned integer */ +typedef signed int blt_int32s; /**< 32-bit signed integer */ + + +#endif /* TYPES_H */ +/*********************************** end of types.h ************************************/