diff --git a/Target/Source/ARMCM0_STM32C0/timer.c b/Target/Source/ARMCM0_STM32C0/timer.c
index 88406904..9f6ed4b1 100644
--- a/Target/Source/ARMCM0_STM32C0/timer.c
+++ b/Target/Source/ARMCM0_STM32C0/timer.c
@@ -73,6 +73,10 @@ void TimerInit(void)
   /* All STM32C0 derivatives support a TIM1 peripheral. Its free running counter will be
    * used to realize the polling based millisecond time reference in this module.
    * Start by enabling the periperhal.
+   *
+   * Note that the STM32C0 features one PCLK clock that drives both APB1 and APB2 busses.
+   * The RCC LL drivers call PCLK PCLK1 and APB APB1. Therefore the following lines
+   * use the PCLK1/APB1 APIs, even though TIM1 is actually on ABP2.
    */
   LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
   /* The TIM1 peripheral clock is derived from PCLK. Obtain the PCLK frequency. */
diff --git a/Target/Source/ARMCM0_STM32G0/timer.c b/Target/Source/ARMCM0_STM32G0/timer.c
index e1a3043d..e7e31e70 100644
--- a/Target/Source/ARMCM0_STM32G0/timer.c
+++ b/Target/Source/ARMCM0_STM32G0/timer.c
@@ -80,6 +80,10 @@ void TimerInit(void)
   /* All STM32G0 derivatives support a TIM1 peripheral. Its free running counter will be
    * used to realize the polling based millisecond time reference in this module.
    * Start by enabling the periperhal.
+   *
+   * Note that the STM32G0 features one PCLK clock that drives both APB1 and APB2 busses.
+   * The RCC LL drivers call PCLK PCLK1 and APB APB1. Therefore the following lines
+   * use the PCLK1/APB1 APIs, even though TIM1 is actually on ABP2.
    */
   LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
   /* The TIM1 peripheral clock is derived from PCLK. Obtain the PCLK frequency. */
diff --git a/Target/Source/ARMCM4_STM32G4/timer.c b/Target/Source/ARMCM4_STM32G4/timer.c
index 0da831fd..7b8f37e9 100644
--- a/Target/Source/ARMCM4_STM32G4/timer.c
+++ b/Target/Source/ARMCM4_STM32G4/timer.c
@@ -76,12 +76,12 @@ void TimerInit(void)
    */
   LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
   /* The TIM1 peripheral clock is derived from PCLK. Obtain the PCLK frequency. */
-  pclk_frequency = __LL_RCC_CALC_PCLK1_FREQ(SystemCoreClock, LL_RCC_GetAPB1Prescaler());
+  pclk_frequency = __LL_RCC_CALC_PCLK2_FREQ(SystemCoreClock, LL_RCC_GetAPB2Prescaler());
   /* According to the clock tree diagram in the RCC chapter of the reference manual,
    * the TPCLK frequency = PLCK * 1, when the APB1 prescaler is 1, otherwise it is
    * PCLK * 2.
    */
-  tim_multiplier = (LL_RCC_GetAPB1Prescaler() == LL_RCC_APB1_DIV_1) ? 1U : 2U;
+  tim_multiplier = (LL_RCC_GetAPB2Prescaler() == LL_RCC_APB2_DIV_1) ? 1U : 2U;
   /* Obtain the TPCLK frequency. */
   pclk_tim_frequency = pclk_frequency * tim_multiplier;
   /* Configure the free running counter as a 16-bit upwards counter that runs at the