mirror of https://github.com/rusefi/openblt.git
Refs #690. Added demo programs for the NXP DevKit-S12G128 board.
git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@700 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
Frank Voorburg
parent
7dcbeb6eda
commit
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/* This is a linker parameter file for the MC9S12G128 */
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NAMES END /* CodeWarrior will pass all the needed files to the linker by command line. But here you may add your own files too. */
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SEGMENTS /* Here all RAM/ROM areas of the device are listed. Used in PLACEMENT below. */
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/* Register space */
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/* IO_SEG = PAGED 0x0000 TO 0x03FF; intentionally not defined */
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/* RAM */
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RAM = READ_WRITE 0x2000 TO 0x3FFF;
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/* D-Flash */
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DFLASH = READ_ONLY 0x0400 TO 0x13FF;
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/* non-paged FLASHs */
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ROM_E800 = READ_ONLY 0xE800 TO 0xFEFF; /* Place bootloader in last 6kb */
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END
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PLACEMENT /* here all predefined and user segments are placed into the SEGMENTS defined above. */
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_PRESTART, /* Used in HIWARE format: jump to _Startup at the code start */
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STARTUP, /* startup data structures */
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ROM_VAR, /* constant variables */
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STRINGS, /* string literals */
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VIRTUAL_TABLE_SEGMENT, /* C++ virtual table segment */
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DEFAULT_ROM, NON_BANKED, /* runtime routines which must not be banked */
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COPY /* copy down information: how to initialize variables */
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/* in case you want to use ROM_4000 here as well, make sure
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that all files (incl. library files) are compiled with the
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option: -OnB=b */
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INTO ROM_E800;
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SSTACK, /* allocate stack first to avoid overwriting variables on overflow */
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DEFAULT_RAM INTO RAM;
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END
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ENTRIES /* keep the following unreferenced variables */
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_vectab
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END
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STACKSIZE 0x100
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|
||||
S22403F9E084E68487E3873BCC0000E988A987B7453A16FA1F37E685871A8E1AE633E1002707
|
||||
S22403FA00046A8B20086284E684C10825D4EE89086E898E00401825FF6AE68B1BF0153D3BB8
|
||||
S22403FA2034D61537EC8316FA3C5B15EC83EE8116FA48B745E600325A151B843D3B34C60E65
|
||||
S22403FA40ED8216FBED1B843D843FC380003D3BC787B74537E6E2EA0F6BE2259D3352C1162A
|
||||
S22403FA6025EECC259D6C8015F300003A3D6BAE6981C104230FCCEA583BCC0418CE00001663
|
||||
S22403FA80FB821B821E01068003C72052C6307B0106790102E687C403873BE68CB710C7EA8F
|
||||
S22403FAA081AA807C010AC6017B0102EC8A7C010AC71B82201537CB027B0102E6808759E386
|
||||
S22403FAC085B745EC007C010A3352E18025E716FA4E1F010630022004C6016B81E681303DD7
|
||||
S22403FAE006F4953BEC8A3BEC8A3BEC8A3BEC8A3BEC8816F5281B88303D3B34EC883BEC8827
|
||||
S22403FB003BEC8616F5DE1B841B843D16F70B3D16F7D13D16F6A40461013D16F7953D16FB19
|
||||
S22403FB203B4C4001C6015B4EDC44C35DC05C504C4680C7877C25B57C25B33D79004C790054
|
||||
S22403FB404679004D79004079004779004879004979004A79004B3D4F4E011AC6015B4EDCCD
|
||||
S22403FB6050C35DC05C50FC25B5FE25B316FC2C7C25B57E25B33D07DFFC25B5FE25B33D14EB
|
||||
S22403FB80103D16EE0D20FB7C25BC1D025C401C025A401C0258403D16FB76FD25BA35FD2567
|
||||
S22403FBA0B83516FBFE252FF625B7260BC6017B25B71D02584020077925B71C02584016FBD2
|
||||
S22403FBC076FD25BCF325BC7C25BACC0000B7C5C90089007C25B83D1C0258403D87D7B7C69C
|
||||
S22403FBE0270A59B7C55545B7C50436F63D87D7B7C6270AB7C549B7C546560436F63DAC84EE
|
||||
S22403FC00270E34B7C5E285A284B7C510FB302002AE82311B840540AC42270E34B7C5E24156
|
||||
S22403FC20A240B7C510FB302002AE403D04A401083D046401098300013D30E6E605E5303768
|
||||
S21D03FC40E1310460022504E61F2002E6E51AE533050000012101040000B2
|
||||
S22403FF80EB94EB9AEBA0EBA6EBACEBB2EBB8EBBEEBC4EBCAEBD0EBD6EBDCEBE2EBE8EBEE99
|
||||
S22403FFA0EBF4EBFAEC00EC06EC0CEC12EC18EC1EEC24EC2AEC30EC36EC3CEC42EC48EC4E6B
|
||||
S22403FFC0EC54EC5AEC60EC66EC6CEC72EC78EC7EEC84EC8AEC90EC96EC9CECA2ECA8ECAE49
|
||||
S22403FFE0ECB4ECBAECC0ECC6ECCCECD2ECD8ECDEECE4ECEAECF0ECF6ECFCE829ED02E829F4
|
||||
S9030000FC
|
||||
|
|
@ -0,0 +1,176 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo/HCS12_DevKit_S12G128_CodeWarrior/Boot/blt_conf.h
|
||||
* \brief Bootloader configuration header file.
|
||||
* \ingroup Boot_HCS12_DevKit_S12G128_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2019 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef BLT_CONF_H
|
||||
#define BLT_CONF_H
|
||||
|
||||
/****************************************************************************************
|
||||
* C P U D R I V E R C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* To properly initialize the baudrate clocks of the communication interface, typically
|
||||
* the speed of the crystal oscillator and/or the speed at which the system runs is
|
||||
* needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
|
||||
* BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
|
||||
* not dependent on the targets architecture, the byte ordering needs to be known.
|
||||
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects
|
||||
* little endian mode.
|
||||
*
|
||||
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
|
||||
* called the moment the user program is about to be started. This could be used to
|
||||
* de-initialize application specific parts, for example to stop blinking an LED, etc.
|
||||
*/
|
||||
/** \brief Frequency of the external crystal oscillator. */
|
||||
#define BOOT_CPU_XTAL_SPEED_KHZ (8000)
|
||||
/** \brief Desired system speed. */
|
||||
#define BOOT_CPU_SYSTEM_SPEED_KHZ (24000)
|
||||
/** \brief Motorola or Intel style byte ordering. */
|
||||
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (1)
|
||||
/** \brief Enable/disable hook function call right before user program start. */
|
||||
#define BOOT_CPU_USER_PROGRAM_START_HOOK (1)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE
|
||||
* configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed
|
||||
* in bits/second. Two CAN messages are reserved for communication with the host. The
|
||||
* message identifier for sending data from the target to the host is configured with
|
||||
* BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with
|
||||
* BOOT_COM_CAN_RXMSG_ID. Note that an extended 29-bit CAN identifier is configured by
|
||||
* OR-ing with mask 0x80000000. The maximum amount of data bytes in a message for data
|
||||
* transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and
|
||||
* BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more
|
||||
* than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the
|
||||
* CAN controller channel.
|
||||
*
|
||||
*/
|
||||
/** \brief Enable/disable CAN transport layer. */
|
||||
#define BOOT_COM_CAN_ENABLE (1)
|
||||
/** \brief Configure the desired CAN baudrate. */
|
||||
#define BOOT_COM_CAN_BAUDRATE (500000)
|
||||
/** \brief Configure CAN message ID target->host. */
|
||||
#define BOOT_COM_CAN_TX_MSG_ID (0x7E1 /*| 0x80000000*/)
|
||||
/** \brief Configure number of bytes in the target->host CAN message. */
|
||||
#define BOOT_COM_CAN_TX_MAX_DATA (8)
|
||||
/** \brief Configure CAN message ID host->target. */
|
||||
#define BOOT_COM_CAN_RX_MSG_ID (0x667 /*| 0x80000000*/)
|
||||
/** \brief Configure number of bytes in the host->target CAN message. */
|
||||
#define BOOT_COM_CAN_RX_MAX_DATA (8)
|
||||
/** \brief Select the desired CAN peripheral as a zero based index. */
|
||||
#define BOOT_COM_CAN_CHANNEL_INDEX (0)
|
||||
|
||||
/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE
|
||||
* configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed
|
||||
* in bits/second. The maximum amount of data bytes in a message for data transmission
|
||||
* and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA,
|
||||
* respectively. It is common for a microcontroller to have more than 1 UART interface
|
||||
* on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface.
|
||||
*
|
||||
*/
|
||||
/** \brief Enable/disable UART transport layer. */
|
||||
#define BOOT_COM_UART_ENABLE (0)
|
||||
/** \brief Configure the desired communication speed. */
|
||||
#define BOOT_COM_UART_BAUDRATE (57600)
|
||||
/** \brief Configure number of bytes in the target->host data packet. */
|
||||
#define BOOT_COM_UART_TX_MAX_DATA (64)
|
||||
/** \brief Configure number of bytes in the host->target data packet. */
|
||||
#define BOOT_COM_UART_RX_MAX_DATA (64)
|
||||
/** \brief Select the desired UART peripheral as a zero based index. */
|
||||
#define BOOT_COM_UART_CHANNEL_INDEX (0)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* B A C K D O O R E N T R Y C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* It is possible to implement an application specific method to force the bootloader to
|
||||
* stay active after a reset. Such a backdoor entry into the bootloader is desired in
|
||||
* situations where the user program does not run properly and therefore cannot
|
||||
* reactivate the bootloader. By enabling these hook functions, the application can
|
||||
* implement the backdoor, which overrides the default backdoor entry that is programmed
|
||||
* into the bootloader. When desired for security purposes, these hook functions can
|
||||
* also be implemented in a way that disables the backdoor entry altogether.
|
||||
*/
|
||||
/** \brief Enable/disable the backdoor override hook functions. */
|
||||
#define BOOT_BACKDOOR_HOOKS_ENABLE (0)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* The NVM driver typically supports erase and program operations of the internal memory
|
||||
* present on the microcontroller. Through these hook functions the NVM driver can be
|
||||
* extended to support additional memory types such as external flash memory and serial
|
||||
* eeproms. The size of the internal memory in kilobytes is specified with configurable
|
||||
* BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can
|
||||
* be overridden with a application specific method by enabling configuration switch
|
||||
* BOOT_NVM_CHECKSUM_HOOKS_ENABLE.
|
||||
*/
|
||||
/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */
|
||||
#define BOOT_NVM_HOOKS_ENABLE (0)
|
||||
/** \brief Configure the size of the default memory device (typically flash EEPROM). */
|
||||
#define BOOT_NVM_SIZE_KB (128)
|
||||
/** \brief Enable/disable hooks functions to override the user program checksum handling. */
|
||||
#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* W A T C H D O G D R I V E R C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* The COP driver cannot be configured internally in the bootloader, because its use
|
||||
* and configuration is application specific. The bootloader does need to service the
|
||||
* watchdog in case it is used. When the application requires the use of a watchdog,
|
||||
* set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
|
||||
* hook functions.
|
||||
*/
|
||||
/** \brief Enable/disable the hook functions for controlling the watchdog. */
|
||||
#define BOOT_COP_HOOKS_ENABLE (1)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* A security mechanism can be enabled in the bootloader's XCP module by setting configu-
|
||||
* rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming
|
||||
* operations can be performed, access to this resource need to be unlocked.
|
||||
* In the Microboot settings on tab "XCP Protection" you need to specify a DLL that
|
||||
* implements the unlocking algorithm. The demo programs are configured for the (simple)
|
||||
* algorithm in "libseednkey.dll". The source code for this DLL is available so it can be
|
||||
* customized to your needs.
|
||||
* During the unlock sequence, Microboot requests a seed from the bootloader, which is in
|
||||
* the format of a byte array. Using this seed the unlock algorithm in the DLL computes
|
||||
* a key, which is also a byte array, and sends this back to the bootloader. The
|
||||
* bootloader then verifies this key to determine if programming and erase operations are
|
||||
* permitted.
|
||||
* After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook()
|
||||
* are called by the bootloader to obtain the seed and to verify the key, respectively.
|
||||
*/
|
||||
#define BOOT_XCP_SEED_KEY_ENABLE (0)
|
||||
|
||||
|
||||
#endif /* BLT_CONF_H */
|
||||
/*********************************** end of blt_conf.h *********************************/
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
/**
|
||||
\defgroup Boot_HCS12_DevKit_S12G128_CodeWarrior Bootloader
|
||||
\brief Bootloader.
|
||||
\ingroup HCS12_DevKit_S12G128_CodeWarrior
|
||||
*/
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
// ver 0.1 (09-Mar-08)
|
||||
// HCS12P Core erasing + unsecuring command file:
|
||||
// These commands mass erase the chip then program the security byte to 0xFE (unsecured state).
|
||||
|
||||
DEFINEVALUEDLG "Information required to unsecure the device" "FCLKDIV" 17 "To unsecure the device, the command script needs \nthe correct value for the FCLKDIV onchip register.\n\nDatasheet proposed values:\n\noscillator frequency\tFCLKDIV value (decimal)\n\n 16 \tMHz\t\t17\n 12 \tMHz\t\t13\n 8 \tMHz\t\t9\n 4 \tMHz\t\t5\n"
|
||||
|
||||
FLASH RELEASE
|
||||
|
||||
reset
|
||||
wb 0x03c 0x00 //disable cop
|
||||
wait 20
|
||||
|
||||
|
||||
WB 0x100 FCLKDIV // clock divider
|
||||
|
||||
WB 0x106 0x30 // clear any error flags
|
||||
WB 0x102 0x00 // CCOBIX = 0
|
||||
WB 0x10A 0x08 // load erase all blocks command
|
||||
WB 0x106 0x80 // launch command
|
||||
WAIT 10
|
||||
|
||||
reset
|
||||
|
||||
WB 0x100 FCLKDIV // clock divider
|
||||
WB 0x106 0x30 // clear any error flags
|
||||
WB 0x102 0x00 // CCOBIX = 0
|
||||
WB 0x10A 0x06 // load program command
|
||||
WB 0x10B 0x03 // load GPAGE
|
||||
WB 0x102 0x01 // CCOBIX = 1
|
||||
WB 0x10A 0xFF // load addr hi
|
||||
WB 0x10B 0x08 // load addr lo
|
||||
WB 0x102 0x02 // CCOBIX = 2
|
||||
WB 0x10A 0xFF // load data
|
||||
WB 0x10B 0xFF // load data
|
||||
WB 0x102 0x03 // CCOBIX = 3
|
||||
WB 0x10A 0xFF // load data
|
||||
WB 0x10B 0xFF // load data
|
||||
WB 0x102 0x04 // CCOBIX = 4
|
||||
WB 0x10A 0xFF // load data
|
||||
WB 0x10B 0xFF // load data
|
||||
WB 0x102 0x05 // CCOBIX = 5
|
||||
WB 0x10A 0xFF // load data
|
||||
WB 0x10B 0xFE // load data
|
||||
WB 0x106 0x80 // launch command
|
||||
WAIT 1
|
||||
|
||||
undef FCLKDIV // undefine variable
|
||||
|
|
@ -0,0 +1 @@
|
|||
// After load the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// Before load the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// After reset the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// At startup the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// After programming the flash, the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// Before programming the flash, the commands written below will be executed
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/* s-record file with linear addresses for MicroBoot/OpenBLT */
|
||||
OPENFILE "%ABS_FILE%.sx"
|
||||
format = motorola
|
||||
busWidth = 1
|
||||
len = 0x4000
|
||||
|
||||
/* logical non banked flash at $4000 and $C000 to physical */
|
||||
origin = 0x004000
|
||||
destination = 0x34000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x00C000
|
||||
destination = 0x3C000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
/* logical 128 kB banked flash to physical */
|
||||
origin = 0x088000
|
||||
destination = 0x020000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x098000
|
||||
destination = 0x024000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x0A8000
|
||||
destination = 0x028000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x0B8000
|
||||
destination = 0x02C000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x0C8000
|
||||
destination = 0x030000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x0D8000
|
||||
destination = 0x034000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x0E8000
|
||||
destination = 0x038000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x0F8000
|
||||
destination = 0x03C000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
CLOSE
|
||||
|
||||
|
|
@ -0,0 +1,482 @@
|
|||
/*****************************************************
|
||||
start12.c - standard startup code
|
||||
The startup code may be optimized to special user requests
|
||||
----------------------------------------------------
|
||||
Copyright (c) Metrowerks, Basel, Switzerland
|
||||
All rights reserved
|
||||
|
||||
Note: ROM libraries are not implemented in this startup code
|
||||
Note: C++ destructors of global objects are NOT yet supported in the HIWARE Object File Format.
|
||||
To use this feature, please build your application with the ELF object file format.
|
||||
*****************************************************/
|
||||
/* these macros remove some unused fields in the startup descriptor */
|
||||
#define __NO_FLAGS_OFFSET /* we do not need the flags field in the startup data descriptor */
|
||||
#define __NO_MAIN_OFFSET /* we do not need the main field in the startup data descriptor */
|
||||
#define __NO_STACKOFFSET_OFFSET /* we do not need the stackOffset field in the startup data descriptor */
|
||||
|
||||
/*#define __BANKED_COPY_DOWN : allow to allocate .copy in flash area */
|
||||
#if defined(__BANKED_COPY_DOWN) && (!defined(__HCS12X__) || !defined(__ELF_OBJECT_FILE_FORMAT__))
|
||||
#error /* the __BANKED_COPY_DOWN switch is only supported for the HCS12X with ELF */
|
||||
/* (and not for the HC12, HCS12 or for the HIWARE object file format) */
|
||||
#endif
|
||||
|
||||
#include "hidef.h"
|
||||
#include "start12.h"
|
||||
|
||||
/***************************************************************************/
|
||||
/* Macros to control how the startup code handles the COP: */
|
||||
/* #define _DO_FEED_COP_ : do feed the COP */
|
||||
/* #define _DO_ENABLE_COP_: do enable the COP */
|
||||
/* #define _DO_DISABLE_COP_: disable the COP */
|
||||
/* Without defining any of these, the startup code does NOT handle the COP */
|
||||
/***************************************************************************/
|
||||
/* __ONLY_INIT_SP define: */
|
||||
/* This define selects an shorter version of the startup code */
|
||||
/* which only loads the stack pointer and directly afterwards calls */
|
||||
/* main. This version does however NOT initialized global variables */
|
||||
/* (So this version is not ANSI compliant!) */
|
||||
/***************************************************************************/
|
||||
/* __FAR_DATA define: */
|
||||
/* By default, the startup code only supports to initialize the default */
|
||||
/* kind of memory. If some memory is allocated far in the small or banked */
|
||||
/* memory model, then the startup code only supports to initialize this */
|
||||
/* memory blocks if __FAR_DATA is defined. If __FAR_DATA is not defined, */
|
||||
/* then the linker will issue a message like */
|
||||
/* "L1128: Cutting value _Range beg data member from 0xF01000 to 0x1000" */
|
||||
/* and this startup code writes to the cutted address */
|
||||
/***************************************************************************/
|
||||
/* __BANKED_COPY_DOWN define: */
|
||||
/* by default, the startup code assumes that the startup data structure */
|
||||
/* _startupData, the zero out areas and the .copy section are all */
|
||||
/* allocated in NON_BANKED memory. Especially the .copy section can be */
|
||||
/* huge if there are many or huge RAM areas to initialize. */
|
||||
/* For the HCS12X, which also copies the XGATE RAM located code via .copy */
|
||||
/* section, the startup code supports to allocate .copy in a banked flash */
|
||||
/* The placement of .copy in the prm file has to be adapted when adding or */
|
||||
/* removing the this macro. */
|
||||
/* Note: This macro is only supported for the HCS12X and when using ELF */
|
||||
/***************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define __EXTERN_C extern "C"
|
||||
#else
|
||||
#define __EXTERN_C
|
||||
#endif
|
||||
|
||||
/*lint -estring(961,"only preprocessor statements and comments before '#include'") , MISRA 19.1 ADV, non_bank.sgm and default.sgm each contain a conditionally compiled CODE_SEG pragma */
|
||||
|
||||
__EXTERN_C void main(void); /* prototype of main function */
|
||||
|
||||
#ifndef __ONLY_INIT_SP
|
||||
#pragma DATA_SEG __NEAR_SEG STARTUP_DATA /* _startupData can be accessed using 16 bit accesses. */
|
||||
/* This is needed because it contains the stack top, and without stack, far data cannot be accessed */
|
||||
struct _tagStartup _startupData; /* read-only: */
|
||||
/* _startupData is allocated in ROM and */
|
||||
/* initialized by the linker */
|
||||
#pragma DATA_SEG DEFAULT
|
||||
#endif /* __ONLY_INIT_SP */
|
||||
|
||||
#if defined(FAR_DATA) && (!defined(__HCS12X__) || defined(__BANKED_COPY_DOWN))
|
||||
/*lint -e451 non_bank.sgm contains a conditionally compiled CODE_SEG pragma */
|
||||
#include "non_bank.sgm"
|
||||
/*lint +e451 */
|
||||
|
||||
/* the init function must be in non banked memory if banked variables are used */
|
||||
/* because _SET_PAGE is called, which may change any page register. */
|
||||
|
||||
/*lint -esym(752,_SET_PAGE) , symbol '_SET_PAGE' is referenced in HLI */
|
||||
__EXTERN_C void _SET_PAGE(void); /* the inline assembler needs a prototype */
|
||||
/* this is a runtime routine with a special */
|
||||
/* calling convention, do not use it in c code! */
|
||||
#else
|
||||
/*lint -e451 default.sgm contains a conditionally compiled CODE_SEG pragma */
|
||||
#include "default.sgm"
|
||||
/*lint +e451 */
|
||||
#endif /* defined(FAR_DATA) && (!defined(__HCS12X__) || defined(__BANKED_COPY_DOWN)) */
|
||||
|
||||
|
||||
/* define value and bits for Windef Register */
|
||||
#ifdef HC812A4
|
||||
#define WINDEF (*(volatile unsigned char*) 0x37)
|
||||
#if defined( __BANKED__) || defined(__LARGE__) || defined(__PPAGE__)
|
||||
#define __ENABLE_PPAGE__ 0x40
|
||||
#else
|
||||
#define __ENABLE_PPAGE__ 0x0
|
||||
#endif
|
||||
#if defined(__DPAGE__)
|
||||
#define __ENABLE_DPAGE__ 0x80
|
||||
#else
|
||||
#define __ENABLE_DPAGE__ 0x0
|
||||
#endif
|
||||
#if defined(__EPAGE__)
|
||||
#define __ENABLE_EPAGE__ 0x20
|
||||
#else
|
||||
#define __ENABLE_EPAGE__ 0x0
|
||||
#endif
|
||||
#endif /* HC812A4 */
|
||||
|
||||
#ifdef _HCS12_SERIALMON
|
||||
/* for Monitor based software remap the RAM & EEPROM to adhere
|
||||
to EB386. Edit RAM and EEPROM sections in PRM file to match these. */
|
||||
#define ___INITRM (*(volatile unsigned char *) 0x0010)
|
||||
#define ___INITRG (*(volatile unsigned char *) 0x0011)
|
||||
#define ___INITEE (*(volatile unsigned char *) 0x0012)
|
||||
#endif
|
||||
|
||||
#if defined(_DO_FEED_COP_)
|
||||
#define __FEED_COP_IN_HLI() } asm movb #0x55, _COP_RST_ADR; asm movb #0xAA, _COP_RST_ADR; asm {
|
||||
#else
|
||||
#define __FEED_COP_IN_HLI() /* do nothing */
|
||||
#endif
|
||||
|
||||
#ifndef __ONLY_INIT_SP
|
||||
#if (!defined(FAR_DATA) || defined(__HCS12X__)) && (defined( __BANKED__) || defined(__LARGE__) || defined(__BANKED_COPY_DOWN))
|
||||
static void __far Init(void)
|
||||
#else
|
||||
static void Init(void)
|
||||
#endif
|
||||
{
|
||||
/* purpose: 1) zero out RAM-areas where data is allocated */
|
||||
/* 2) copy initialization data from ROM to RAM */
|
||||
/* 3) call global constructors in C++ */
|
||||
/* called from: _Startup, LibInits */
|
||||
asm {
|
||||
ZeroOut:
|
||||
#if defined(__HIWARE_OBJECT_FILE_FORMAT__) && defined(__LARGE__)
|
||||
LDX _startupData.pZeroOut:1 ; in the large memory model in the HIWARE format, pZeroOut is a 24 bit pointer
|
||||
#else
|
||||
LDX _startupData.pZeroOut ; *pZeroOut
|
||||
#endif
|
||||
LDY _startupData.nofZeroOuts ; nofZeroOuts
|
||||
BEQ CopyDown ; if nothing to zero out
|
||||
|
||||
NextZeroOut: PSHY ; save nofZeroOuts
|
||||
#if defined(FAR_DATA)
|
||||
LDAB 1,X+ ; load page of destination address
|
||||
LDY 2,X+ ; load offset of destination address
|
||||
#if defined(__HCS12X__)
|
||||
STAB __GPAGE_ADR__
|
||||
#else /* defined(__HCS12X__) */
|
||||
__PIC_JSR(_SET_PAGE) ; sets the page in the correct page register
|
||||
#endif /* defined(__HCS12X__) */
|
||||
#else /* FAR_DATA */
|
||||
LDY 2,X+ ; start address and advance *pZeroOut (X = X+4)
|
||||
#endif /* FAR_DATA */
|
||||
|
||||
#if defined(__HCS12X__) && defined(FAR_DATA)
|
||||
PSHX
|
||||
LDX 0,X ; byte count
|
||||
#if defined(__OPTIMIZE_FOR_SIZE__)
|
||||
CLRA
|
||||
NextWord: GSTAA 1,Y+ ; clear memory byte
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE X, NextWord ; dec byte count
|
||||
#else
|
||||
LDD #0
|
||||
LSRX
|
||||
BEQ LoopClrW1 ; do we copy more than 1 byte?
|
||||
NextWord: GSTD 2,Y+ ; clear memory word
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE X, NextWord ; dec word count
|
||||
LoopClrW1:
|
||||
BCC LastClr ; handle last byte
|
||||
GSTAA 1,Y+ ; handle last byte
|
||||
LastClr:
|
||||
#endif
|
||||
PULX
|
||||
LEAX 2,X
|
||||
#elif defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */
|
||||
LDD 2,X+ ; byte count
|
||||
NextWord: CLR 1,Y+ ; clear memory byte
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D, NextWord ; dec byte count
|
||||
#else /* __OPTIMIZE_FOR_TIME__ */
|
||||
LDD 2,X+ ; byte count
|
||||
LSRD ; /2 and save bit 0 in the carry
|
||||
BEQ LoopClrW1 ; do we copy more than 1 byte?
|
||||
PSHX
|
||||
LDX #0
|
||||
LoopClrW: STX 2,Y+ ; Word-Clear
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D, LoopClrW
|
||||
PULX
|
||||
LoopClrW1:
|
||||
BCC LastClr ; handle last byte
|
||||
CLR 1,Y+
|
||||
LastClr:
|
||||
#endif /* __OPTIMIZE_FOR_SIZE__/__OPTIMIZE_FOR_TIME__ */
|
||||
PULY ; restore nofZeroOuts
|
||||
DEY ; dec nofZeroOuts
|
||||
BNE NextZeroOut
|
||||
CopyDown:
|
||||
#if defined(__BANKED_COPY_DOWN)
|
||||
LDAA _startupData.toCopyDownBeg:0 ; get PAGE address of .copy section
|
||||
STAA __PPAGE_ADR__ ; set PPAGE address
|
||||
LDX _startupData.toCopyDownBeg:1 ; load address of copy down desc.
|
||||
#elif defined(__ELF_OBJECT_FILE_FORMAT__)
|
||||
LDX _startupData.toCopyDownBeg ; load address of copy down desc.
|
||||
#else
|
||||
LDX _startupData.toCopyDownBeg:2 ; load address of copy down desc.
|
||||
#endif
|
||||
NextBlock:
|
||||
LDD 2,X+ ; size of init-data -> D
|
||||
BEQ funcInits ; end of copy down desc.
|
||||
#ifdef FAR_DATA
|
||||
PSHD ; save counter
|
||||
LDAB 1,X+ ; load destination page
|
||||
LDY 2,X+ ; destination address
|
||||
#if defined(__HCS12X__)
|
||||
STAB __GPAGE_ADR__
|
||||
#else /* __HCS12X__ */
|
||||
__PIC_JSR(_SET_PAGE) ; sets the destinations page register
|
||||
#endif /* __HCS12X__ */
|
||||
PULD ; restore counter
|
||||
#else /* FAR_DATA */
|
||||
LDY 2,X+ ; load destination address
|
||||
#endif /* FAR_DATA */
|
||||
|
||||
#if defined(__HCS12X__) && defined(FAR_DATA)
|
||||
#if defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */
|
||||
Copy: PSHA
|
||||
LDAA 1,X+
|
||||
GSTAA 1,Y+ ; move a byte from ROM to the data area
|
||||
PULA
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D,Copy ; copy-byte loop
|
||||
#else
|
||||
LSRD ; /2 and save bit 0 in the carry
|
||||
BEQ Copy1 ; do we copy more than 1 byte?
|
||||
|
||||
Copy: PSHD
|
||||
LDD 2,X+
|
||||
GSTD 2,Y+ ; move a word from ROM to the data area
|
||||
PULD
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D,Copy ; copy-word loop
|
||||
Copy1:
|
||||
BCC NextBlock ; handle last byte?
|
||||
LDAA 1,X+
|
||||
GSTAA 1,Y+ ; move a byte from ROM to the data area
|
||||
#endif
|
||||
#elif defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */
|
||||
Copy: MOVB 1,X+,1,Y+ ; move a byte from ROM to the data area
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D,Copy ; copy-byte loop
|
||||
#else /* __OPTIMIZE_FOR_TIME__ */
|
||||
LSRD ; /2 and save bit 0 in the carry
|
||||
BEQ Copy1 ; do we copy more than 1 byte?
|
||||
Copy: MOVW 2,X+,2,Y+ ; move a word from ROM to the data area
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D,Copy ; copy-word loop
|
||||
Copy1:
|
||||
BCC NextBlock ; handle last byte?
|
||||
MOVB 1,X+,1,Y+ ; copy the last byte
|
||||
#endif /* __OPTIMIZE_FOR_SIZE__/__OPTIMIZE_FOR_TIME__ */
|
||||
BRA NextBlock
|
||||
funcInits: ; call of global construtors is only in c++ necessary
|
||||
#if defined(__cplusplus)
|
||||
#if defined(__ELF_OBJECT_FILE_FORMAT__)
|
||||
#if defined( __BANKED__) || defined(__LARGE__)
|
||||
LDY _startupData.nofInitBodies; load number of cpp.
|
||||
BEQ done ; if cppcount == 0, goto done
|
||||
LDX _startupData.initBodies ; load address of first module to initialize
|
||||
nextInit:
|
||||
LEAX 3,X ; increment to next init
|
||||
PSHX ; save address of next function to initialize
|
||||
PSHY ; save cpp counter
|
||||
CALL [-3,X] ; use double indirect call to load the page register also
|
||||
PULY ; restore cpp counter
|
||||
PULX ; restore actual address
|
||||
DEY ; decrement cpp counter
|
||||
BNE nextInit
|
||||
#else /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
|
||||
LDD _startupData.nofInitBodies; load number of cpp.
|
||||
BEQ done ; if cppcount == 0, goto done
|
||||
LDX _startupData.initBodies ; load address of first module to initialize
|
||||
nextInit:
|
||||
LDY 2,X+ ; load address of first module to initialize
|
||||
PSHD
|
||||
PSHX ; save actual address
|
||||
JSR 0,Y ; call initialization function
|
||||
PULX ; restore actual address
|
||||
PULD ; restore cpp counter
|
||||
DBNE D, nextInit
|
||||
#endif /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
#else /* __ELF_OBJECT_FILE_FORMAT__ */
|
||||
LDX _startupData.mInits ; load address of first module to initialize
|
||||
#if defined( __BANKED__) || defined(__LARGE__)
|
||||
nextInit: LDY 3,X+ ; load address of initialization function
|
||||
BEQ done ; stop when address == 0
|
||||
; in common environments the offset of a function is never 0, so this test could be avoided
|
||||
#ifdef __InitFunctionsMayHaveOffset0__
|
||||
BRCLR -1,X, done, 0xff ; stop when address == 0
|
||||
#endif /* __InitFunctionsMayHaveOffset0__ */
|
||||
PSHX ; save address of next function to initialize
|
||||
CALL [-3,X] ; use double indirect call to load the page register also
|
||||
#else /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
nextInit:
|
||||
LDY 2,X+ ; load address of first module to initialize
|
||||
BEQ done ; stop when address of function == 0
|
||||
PSHX ; save actual address
|
||||
JSR 0,Y ; call initialization function
|
||||
#endif /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
PULX ; restore actual address
|
||||
BRA nextInit
|
||||
#endif /* __ELF_OBJECT_FILE_FORMAT__ */
|
||||
done:
|
||||
#endif /* __cplusplus */
|
||||
}
|
||||
}
|
||||
#endif /* __ONLY_INIT_SP */
|
||||
|
||||
#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) && 0 /* the call to main does not support to return anymore */
|
||||
|
||||
#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__))
|
||||
static void __far Fini(void)
|
||||
#else
|
||||
static void Fini(void)
|
||||
#endif
|
||||
{
|
||||
/* purpose: 1) call global destructors in C++ */
|
||||
asm {
|
||||
#if defined( __BANKED__) || defined(__LARGE__)
|
||||
|
||||
LDY _startupData.nofFiniBodies; load number of cpp.
|
||||
BEQ done ; if cppcount == 0, goto done
|
||||
LDX _startupData.finiBodies ; load address of first module to finalize
|
||||
nextInit2:
|
||||
LEAX 3,X ; increment to next init
|
||||
PSHX ; save address of next function to finalize
|
||||
PSHY ; save cpp counter
|
||||
CALL [-3,X] ; use double indirect call to load the page register also
|
||||
PULY ; restore cpp counter
|
||||
PULX ; restore actual address
|
||||
DEY ; decrement cpp counter
|
||||
BNE nextInit2
|
||||
#else /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
|
||||
LDD _startupData.nofFiniBodies; load number of cpp.
|
||||
BEQ done ; if cppcount == 0, goto done
|
||||
LDX _startupData.finiBodies ; load address of first module to finalize
|
||||
nextInit2:
|
||||
LDY 2,X+ ; load address of first module to finalize
|
||||
PSHD
|
||||
PSHX ; save actual address
|
||||
JSR 0,Y ; call finalize function
|
||||
PULX ; restore actual address
|
||||
PULD ; restore cpp counter
|
||||
DBNE D, nextInit2
|
||||
#endif /* defined(__BANKED__) || defined(__LARGE__) */
|
||||
done:;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*lint -e451 non_bank.sgm contains a conditionally compiled CODE_SEG pragma */
|
||||
#include "non_bank.sgm"
|
||||
/*lint +e451 */
|
||||
|
||||
#pragma MESSAGE DISABLE C12053 /* Stack-pointer change not in debugging-information */
|
||||
#pragma NO_FRAME
|
||||
#pragma NO_ENTRY
|
||||
#if !defined(__SMALL__)
|
||||
#pragma NO_EXIT
|
||||
#endif
|
||||
|
||||
/* The function _Startup must be called in order to initialize global variables and to call main */
|
||||
/* You can adapt this function or call it from your startup code to implement a different startup */
|
||||
/* functionality. */
|
||||
|
||||
/* You should also setup the needed IO registers as WINDEF (HC12A4 only) or the COP registers to run */
|
||||
/* on hardware */
|
||||
|
||||
/* to set the reset vector several ways are possible : */
|
||||
/* 1. define the function with "interrupt 0" as done below in the first case */
|
||||
/* 2. add the following line to your prm file : VECTOR ADDRESS 0xfffe _Startup */
|
||||
/* of course, even more posibilities exists */
|
||||
/* the reset vector must be set so that the application has a defined entry point */
|
||||
|
||||
#if defined(__SET_RESET_VECTOR__)
|
||||
__EXTERN_C void __interrupt 0 _Startup(void) {
|
||||
#else
|
||||
__EXTERN_C void _Startup(void) {
|
||||
#endif
|
||||
/* purpose: 1) initialize the stack
|
||||
2) initialize the RAM, copy down init data etc (Init)
|
||||
3) call main;
|
||||
parameters: NONE
|
||||
called from: _PRESTART-code generated by the Linker
|
||||
or directly referenced by the reset vector */
|
||||
|
||||
/* initialize the stack pointer */
|
||||
/*lint -e{960} , MISRA 14.3 REQ, macro INIT_SP_FROM_STARTUP_DESC() expands to HLI code */
|
||||
/*lint -e{522} , MISRA 14.2 REQ, macro INIT_SP_FROM_STARTUP_DESC() expands to HLI code */
|
||||
INIT_SP_FROM_STARTUP_DESC(); /* HLI macro definition in hidef.h */
|
||||
#if defined(_HCS12_SERIALMON)
|
||||
/* for Monitor based software remap the RAM & EEPROM to adhere
|
||||
to EB386. Edit RAM and EEPROM sections in PRM file to match these. */
|
||||
___INITRG = 0x00; /* lock registers block to 0x0000 */
|
||||
___INITRM = 0x39; /* lock Ram to end at 0x3FFF */
|
||||
___INITEE = 0x09; /* lock EEPROM block to end at 0x0fff */
|
||||
#endif
|
||||
|
||||
/* Here user defined code could be inserted, the stack could be used */
|
||||
#if defined(_DO_DISABLE_COP_)
|
||||
_DISABLE_COP();
|
||||
#endif
|
||||
|
||||
/* Example : Set up WinDef Register to allow Paging */
|
||||
#ifdef HC812A4 /* HC12 A4 derivative needs WINDEF to configure which pages are available */
|
||||
#if (__ENABLE_EPAGE__ != 0 || __ENABLE_DPAGE__ != 0 || __ENABLE_PPAGE__ != 0)
|
||||
WINDEF= __ENABLE_EPAGE__ | __ENABLE_DPAGE__ | __ENABLE_PPAGE__;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(__MAP_RAM__) || defined(__MAP_FLASH__) || defined(__MAP_EXTERNAL__)) && !defined(__DO_SET_MMCTL1__)
|
||||
#define __DO_SET_MMCTL1__
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__DO_SET_MMCTL1__)
|
||||
/* Set the MMCTL1 byte. Please use for HCS12XE and change the bits according */
|
||||
/* to your configuration. */
|
||||
/* Note: MMCTL1 is write once therefore please adapt this initialization here. */
|
||||
/* This has to be done prior to the call to Init. */
|
||||
#define _MMCTL1_ADR (0x00000013)
|
||||
#define _MMCTL1_BIT_TGMRAMON (1<<7) /* EEE Tag RAM and FTM SCRATCH RAM visible in the memory map */
|
||||
#define _MMCTL1_BIT_EEEIFRON (1<<5) /* EEE IFR visible in the memory map */
|
||||
#define _MMCTL1_BIT_PGMIFRON (1<<4) /* Program IFR visible in the memory map */
|
||||
#define _MMCTL1_BIT_RAMHM (1<<3) /* RAM only in the higher half of the memory map */
|
||||
#define _MMCTL1_BIT_EROMON (1<<2) /* Enables emulated Flash or ROM memory in the memory map */
|
||||
#define _MMCTL1_BIT_ROMHM (1<<1) /* FLASH or ROM only in higher Half of Memory Map */
|
||||
#define _MMCTL1_BIT_ROMON (1<<0) /* Enable FLASH or ROM in the memory map */
|
||||
|
||||
#define _MMCTL1_SET(value) ((*(volatile unsigned char*)_MMCTL1_ADR)= (value))
|
||||
|
||||
#if defined(__MAP_FLASH__)
|
||||
_MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON);
|
||||
#elif defined(__MAP_EXTERNAL__)
|
||||
_MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON | _MMCTL1_BIT_ROMHM);
|
||||
#else /* RAM */
|
||||
_MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON | _MMCTL1_BIT_RAMHM | _MMCTL1_BIT_ROMHM);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __ONLY_INIT_SP
|
||||
/*lint -e{522} , MISRA 14.2 REQ, function Init() contains HLI only */
|
||||
Init(); /* zero out, copy down, call constructors */
|
||||
#endif
|
||||
|
||||
/* Here user defined code could be inserted, all global variables are initilized */
|
||||
#if defined(_DO_ENABLE_COP_)
|
||||
_ENABLE_COP(1);
|
||||
#endif
|
||||
|
||||
/* call main() */
|
||||
main();
|
||||
}
|
||||
|
||||
/*lint --e{766} , non_bank.sgm is not a regular header file, it contains a conditionally compiled CODE_SEG pragma */
|
||||
/*lint +estring(961,"only preprocessor statements and comments before '#include'") */
|
||||
/*lint +e451 */
|
||||
|
|
@ -0,0 +1,309 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo/HCS12_DevKit_S12G128_CodeWarrior/Boot/hooks.c
|
||||
* \brief Bootloader callback source file.
|
||||
* \ingroup Boot_HCS12_DevKit_S12G128_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2019 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include <hidef.h> /* common defines and macros */
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
#include "led.h" /* LED driver header */
|
||||
#include "derivative.h" /* derivative-specific definitions */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* C P U D R I V E R H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called when the bootloader is about to exit and
|
||||
** hand over control to the user program. This is the last moment that
|
||||
** some final checking can be performed and if necessary prevent the
|
||||
** bootloader from activiting the user program.
|
||||
** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
|
||||
** keep the bootloader active.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool CpuUserProgramStartHook(void)
|
||||
{
|
||||
/* additional and optional backdoor entry through the pushbutton SW3 on the board. to
|
||||
* force the bootloader to stay active after reset, keep the pushbutton pressed while
|
||||
* resetting the microcontroller.
|
||||
*/
|
||||
if (PTT_PTT6 != 0)
|
||||
{
|
||||
/* pushbutton pressed, so do not start the user program and keep the bootloader
|
||||
* active instead.
|
||||
*/
|
||||
return BLT_FALSE;
|
||||
}
|
||||
|
||||
/* clean up the LED driver */
|
||||
LedBlinkExit();
|
||||
|
||||
/* okay to start the user program */
|
||||
return BLT_TRUE;
|
||||
} /*** end of CpuUserProgramStartHook ***/
|
||||
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* W A T C H D O G D R I V E R H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_COP_HOOKS_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the end of the internal COP driver
|
||||
** initialization routine. It can be used to configure and enable the
|
||||
** watchdog.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void CopInitHook(void)
|
||||
{
|
||||
/* this function is called upon initialization. might as well use it to initialize
|
||||
* the LED driver. It is kind of a visual watchdog anyways.
|
||||
*/
|
||||
LedBlinkInit(100);
|
||||
} /*** end of CopInitHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the end of the internal COP driver
|
||||
** service routine. This gets called upon initialization and during
|
||||
** potential long lasting loops and routine. It can be used to service
|
||||
** the watchdog to prevent a watchdog reset.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void CopServiceHook(void)
|
||||
{
|
||||
/* run the LED blink task. this is a better place to do it than in the main() program
|
||||
* loop. certain operations such as flash erase can take a long time, which would cause
|
||||
* a blink interval to be skipped. this function is also called during such operations,
|
||||
* so no blink intervals will be skipped when calling the LED blink task here.
|
||||
*/
|
||||
LedBlinkTask();
|
||||
} /*** end of CopServiceHook ***/
|
||||
#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* B A C K D O O R E N T R Y H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the backdoor entry option.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void BackDoorInitHook(void)
|
||||
{
|
||||
} /*** end of BackDoorInitHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Checks if a backdoor entry is requested.
|
||||
** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool BackDoorEntryHook(void)
|
||||
{
|
||||
/* default implementation always activates the bootloader after a reset */
|
||||
return BLT_TRUE;
|
||||
} /*** end of BackDoorEntryHook ***/
|
||||
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the start of the internal NVM driver
|
||||
** initialization routine.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void NvmInitHook(void)
|
||||
{
|
||||
} /*** end of NvmInitHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the start of a firmware update to reinitialize
|
||||
** the NVM driver.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void NvmReinitHook(void)
|
||||
{
|
||||
} /*** end of NvmReinitHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the start of the NVM driver write
|
||||
** routine. It allows additional memory to be operated on. If the address
|
||||
** is not within the range of the additional memory, then
|
||||
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
|
||||
** been written yet.
|
||||
** \param addr Start address.
|
||||
** \param len Length in bytes.
|
||||
** \param data Pointer to the data buffer.
|
||||
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
|
||||
** not within the supported memory range, or BLT_NVM_ERROR is the write
|
||||
** operation failed.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
|
||||
{
|
||||
return BLT_NVM_NOT_IN_RANGE;
|
||||
} /*** end of NvmWriteHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the start of the NVM driver erase
|
||||
** routine. It allows additional memory to be operated on. If the address
|
||||
** is not within the range of the additional memory, then
|
||||
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory
|
||||
** hasn't been erased yet.
|
||||
** \param addr Start address.
|
||||
** \param len Length in bytes.
|
||||
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
|
||||
** not within the supported memory range, or BLT_NVM_ERROR is the erase
|
||||
** operation failed.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len)
|
||||
{
|
||||
return BLT_NVM_NOT_IN_RANGE;
|
||||
} /*** end of NvmEraseHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the end of the NVM programming session.
|
||||
** \return BLT_TRUE is successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmDoneHook(void)
|
||||
{
|
||||
return BLT_TRUE;
|
||||
} /*** end of NvmDoneHook ***/
|
||||
#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Verifies the checksum, which indicates that a valid user program is
|
||||
** present and can be started.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmVerifyChecksumHook(void)
|
||||
{
|
||||
return BLT_TRUE;
|
||||
} /*** end of NvmVerifyChecksum ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Writes a checksum of the user program to non-volatile memory. This is
|
||||
** performed once the entire user program has been programmed. Through
|
||||
** the checksum, the bootloader can check if a valid user programming is
|
||||
** present and can be started.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmWriteChecksumHook(void)
|
||||
{
|
||||
return BLT_TRUE;
|
||||
}
|
||||
#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_XCP_SEED_KEY_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Provides a seed to the XCP master that will be used for the key
|
||||
** generation when the master attempts to unlock the specified resource.
|
||||
** Called by the GET_SEED command.
|
||||
** \param resource Resource that the seed if requested for (XCP_RES_XXX).
|
||||
** \param seed Pointer to byte buffer wher the seed will be stored.
|
||||
** \return Length of the seed in bytes.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed)
|
||||
{
|
||||
/* request seed for unlocking ProGraMming resource */
|
||||
if ((resource & XCP_RES_PGM) != 0)
|
||||
{
|
||||
seed[0] = 0x55;
|
||||
}
|
||||
|
||||
/* return seed length */
|
||||
return 1;
|
||||
} /*** end of XcpGetSeedHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Called by the UNLOCK command and checks if the key to unlock the
|
||||
** specified resource was correct. If so, then the resource protection
|
||||
** will be removed.
|
||||
** \param resource resource to unlock (XCP_RES_XXX).
|
||||
** \param key pointer to the byte buffer holding the key.
|
||||
** \param len length of the key in bytes.
|
||||
** \return 1 if the key was correct, 0 otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len)
|
||||
{
|
||||
/* suppress compiler warning for unused parameter */
|
||||
len = len;
|
||||
|
||||
/* the example key algorithm in "libseednkey.dll" works as follows:
|
||||
* - PGM will be unlocked if key = seed - 1
|
||||
*/
|
||||
|
||||
/* check key for unlocking ProGraMming resource */
|
||||
if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1)))
|
||||
{
|
||||
/* correct key received for unlocking PGM resource */
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* still here so key incorrect */
|
||||
return 0;
|
||||
} /*** end of XcpVerifyKeyHook ***/
|
||||
#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */
|
||||
|
||||
|
||||
/*********************************** end of hooks.c ************************************/
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
OPEN source 0 0 60 39
|
||||
Source < attributes MARKS off
|
||||
OPEN assembly 60 0 40 31
|
||||
Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C
|
||||
OPEN procedure 0 39 60 17
|
||||
Procedure < attributes VALUES on,TYPES off
|
||||
OPEN register 60 31 40 25
|
||||
Register < attributes FORMAT AUTO,COMPLEMENT None
|
||||
OPEN memory 60 56 40 22
|
||||
Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80
|
||||
OPEN data 0 56 60 22
|
||||
Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16
|
||||
OPEN data 0 78 60 22
|
||||
Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16
|
||||
OPEN command 60 78 40 22
|
||||
Command < attributes CACHESIZE 1000
|
||||
bckcolor 50331647
|
||||
font 'Courier New' 9 BLACK
|
||||
AUTOSIZE on
|
||||
ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory
|
||||
Binary file not shown.
|
|
@ -0,0 +1,80 @@
|
|||
[STARTUP]
|
||||
CPUTARGETTYPE=0
|
||||
USE_CYCLONEPRO_RELAYS=0
|
||||
PORT=21
|
||||
interface_selection=1
|
||||
SHOWDIALOG=0
|
||||
IO_DELAY_SET=1
|
||||
frequency_has_changed_old_io_delay_cnt=7
|
||||
CyclonePro_poweroffonexit=0
|
||||
CyclonePro_currentvoltage=255
|
||||
CyclonePro_PowerDownDelay=250
|
||||
CyclonePro_PowerUpDelay=250
|
||||
IO_DELAY_CNT=7
|
||||
PCI_DELAY=0
|
||||
RESET_DELAY=0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
[Environment Variables]
|
||||
GENPATH={Project}Sources;{Compiler}lib\hc12c\src;{Compiler}lib\hc12c\include;{Compiler}lib\hc12c\lib;{Compiler}lib\xgatec\src;{Compiler}lib\xgatec\include;{Compiler}lib\xgatec\lib
|
||||
LIBPATH={Compiler}lib\hc12c\include;{Compiler}lib\xgatec\include
|
||||
OBJPATH={Project}bin
|
||||
TEXTPATH={Project}bin
|
||||
ABSPATH={Project}bin
|
||||
|
||||
[HI-WAVE]
|
||||
Target=icd12
|
||||
Layout=C_layout.hwl
|
||||
LoadDialogOptions=AUTOERASEANDFLASH RUNANDSTOPAFTERLOAD="main"
|
||||
CPU=HC12
|
||||
MainFrame=2,3,-1,-1,-1,-1,78,78,1518,845
|
||||
TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806
|
||||
AEFWarningDialog=FALSE
|
||||
|
||||
|
||||
|
||||
|
||||
[HC12MultilinkCyclonePro_GDI_SETTINGS]
|
||||
CMDFILE0=CMDFILE STARTUP ON ".\cmd\OpenSourceBDM_startup.cmd"
|
||||
CMDFILE1=CMDFILE RESET ON ".\cmd\OpenSourceBDM_reset.cmd"
|
||||
CMDFILE2=CMDFILE PRELOAD ON ".\cmd\OpenSourceBDM_preload.cmd"
|
||||
CMDFILE3=CMDFILE POSTLOAD ON ".\cmd\OpenSourceBDM_postload.cmd"
|
||||
CMDFILE4=CMDFILE VPPON ON ".\cmd\OpenSourceBDM_vppon.cmd"
|
||||
CMDFILE5=CMDFILE VPPOFF ON ".\cmd\OpenSourceBDM_vppoff.cmd"
|
||||
CMDFILE6=CMDFILE UNSECURE ON ".\cmd\OpenSourceBDM_erase_unsecure_hcs12p.cmd"
|
||||
MCUID=0x01C2
|
||||
CHIPSECURE=CHIPSECURE SETUP 0xFF0F 0x3 0x2
|
||||
DBG0=DBG GENERAL DISARM_ON PROTECT_OFF ANALYZE_ON STEPATRUN_ON
|
||||
DBG1=DBG PREDEFINED SELECT 0
|
||||
DBG2=DBG PREDEFINED DBGENGINE TRACE ENABLE RECORDAFTER PUREPC
|
||||
NV_PARAMETER_FILE=C:\Program Files (x86)\Freescale\CWS12v5.1\prog\FPP\mcu01C2.fpp
|
||||
NV_SAVE_WSP=0
|
||||
NV_AUTO_ID=1
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
[ICD12]
|
||||
COMSETTINGS=SETCOMM DRIVER NOPROTOCOL NOPERIODICAL
|
||||
SETCLKSW=0
|
||||
HOTPLUGGING=0
|
||||
DETECTRUNNING=0
|
||||
RESYNCONCOPRESET=0
|
||||
BDMAutoSpeed=0
|
||||
BDMClockSpeed=7
|
||||
HIGHIODELAYCONSTFORPLL=40
|
||||
|
||||
[PORT]
|
||||
IP=
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,107 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo/HCS12_DevKit_S12G128_CodeWarrior/Boot/led.c
|
||||
* \brief LED driver source file.
|
||||
* \ingroup Boot_HCS12_DevKit_S12G128_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2019 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include <hidef.h> /* common defines and macros */
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
#include "led.h" /* module header */
|
||||
#include "derivative.h" /* derivative-specific definitions */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Local data declarations
|
||||
****************************************************************************************/
|
||||
/** \brief Holds the desired LED blink interval time. */
|
||||
static blt_int16u ledBlinkIntervalMs;
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the LED blink driver.
|
||||
** \param interval_ms Specifies the desired LED blink interval time in milliseconds.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void LedBlinkInit(blt_int16u interval_ms)
|
||||
{
|
||||
/* store the interval time between LED toggles */
|
||||
ledBlinkIntervalMs = interval_ms;
|
||||
/* disable pull device for PP6 */
|
||||
PERP_PERP6 = 0;
|
||||
/* configure PP6 as a digital output */
|
||||
DDRP_DDRP6 = 1;
|
||||
/* turn off the LED by default */
|
||||
PTP_PTP6 = 1;
|
||||
} /*** end of LedBlinkInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Task function for blinking the LED as a fixed timer interval.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void LedBlinkTask(void)
|
||||
{
|
||||
static blt_bool ledOn = BLT_FALSE;
|
||||
static blt_int32u nextBlinkEvent = 0;
|
||||
|
||||
/* check for blink event */
|
||||
if (TimerGet() >= nextBlinkEvent)
|
||||
{
|
||||
/* toggle the LED state */
|
||||
if (ledOn == BLT_FALSE)
|
||||
{
|
||||
ledOn = BLT_TRUE;
|
||||
PTP_PTP6 = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
ledOn = BLT_FALSE;
|
||||
PTP_PTP6 = 1;
|
||||
}
|
||||
/* schedule the next blink event */
|
||||
nextBlinkEvent = TimerGet() + ledBlinkIntervalMs;
|
||||
}
|
||||
} /*** end of LedBlinkTask ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Cleans up the LED blink driver. This is intended to be used upon program
|
||||
** exit.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void LedBlinkExit(void)
|
||||
{
|
||||
/* turn the LED off */
|
||||
PTP_PTP6 = 1;
|
||||
} /*** end of LedBlinkExit ***/
|
||||
|
||||
|
||||
/*********************************** end of led.c **************************************/
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo/HCS12_DevKit_S12G128_CodeWarrior/Boot/led.h
|
||||
* \brief LED driver header file.
|
||||
* \ingroup Boot_HCS12_DevKit_S12G128_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2019 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef LED_H
|
||||
#define LED_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void LedBlinkInit(blt_int16u interval_ms);
|
||||
void LedBlinkTask(void);
|
||||
void LedBlinkExit(void);
|
||||
|
||||
|
||||
#endif /* LED_H */
|
||||
/*********************************** end of led.h **************************************/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Note: This file is recreated by the project wizard whenever the MCU is
|
||||
* changed and should not be edited by hand
|
||||
*/
|
||||
|
||||
/* Include the derivative-specific header file */
|
||||
#include <mc9s12g128.h>
|
||||
|
||||
#pragma LINK_INFO DERIVATIVE "mc9s12g128"
|
||||
|
||||
|
|
@ -0,0 +1,287 @@
|
|||
/* Based on CPU DB MC9S12G128_100, version 3.00.015 (RegistersPrg V2.32) */
|
||||
/* DataSheet : MC9S12GRMV1 Rev. 1.02 June 7, 2011 */
|
||||
|
||||
#include <mc9s12g128.h>
|
||||
|
||||
/*lint -save -esym(765, *) */
|
||||
|
||||
|
||||
/* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */
|
||||
volatile PORTESTR _PORTE; /* Port E Data Register; 0x00000008 */
|
||||
volatile DDRESTR _DDRE; /* Port E Data Direction Register; 0x00000009 */
|
||||
volatile MODESTR _MODE; /* Mode Register; 0x0000000B */
|
||||
volatile PUCRSTR _PUCR; /* Pull-Up Control Register; 0x0000000C */
|
||||
volatile DIRECTSTR _DIRECT; /* Direct Page Register; 0x00000011 */
|
||||
volatile MMCCTL1STR _MMCCTL1; /* MMC Control Register; 0x00000013 */
|
||||
volatile PPAGESTR _PPAGE; /* Program Page Index Register; 0x00000015 */
|
||||
volatile ECLKCTLSTR _ECLKCTL; /* ECLK Control Register; 0x0000001C */
|
||||
volatile IRQCRSTR _IRQCR; /* Interrupt Control Register; 0x0000001E */
|
||||
volatile DBGC1STR _DBGC1; /* Debug Control Register 1; 0x00000020 */
|
||||
volatile DBGSRSTR _DBGSR; /* Debug Status Register; 0x00000021 */
|
||||
volatile DBGTCRSTR _DBGTCR; /* Debug Trace Control Register; 0x00000022 */
|
||||
volatile DBGC2STR _DBGC2; /* Debug Control Register 2; 0x00000023 */
|
||||
volatile DBGCNTSTR _DBGCNT; /* Debug Count Register; 0x00000026 */
|
||||
volatile DBGSCRXSTR _DBGSCRX; /* Debug State Control Register; 0x00000027 */
|
||||
volatile DBGXCTLSTR _DBGXCTL; /* Debug Comparator Control Register; 0x00000028 */
|
||||
volatile DBGXAHSTR _DBGXAH; /* Debug Comparator Address High Register; 0x00000029 */
|
||||
volatile DBGXAMSTR _DBGXAM; /* Debug Comparator Address Mid Register; 0x0000002A */
|
||||
volatile DBGXALSTR _DBGXAL; /* Debug Comparator Address Low Register; 0x0000002B */
|
||||
volatile DBGADHSTR _DBGADH; /* Debug Comparator Data High Register; 0x0000002C */
|
||||
volatile DBGADLSTR _DBGADL; /* Debug Comparator Data Low Register; 0x0000002D */
|
||||
volatile DBGADHMSTR _DBGADHM; /* Debug Comparator Data High Mask Register; 0x0000002E */
|
||||
volatile DBGADLMSTR _DBGADLM; /* Debug Comparator Data Low Mask Register; 0x0000002F */
|
||||
volatile CPMUSYNRSTR _CPMUSYNR; /* S12CPMU Synthesizer Register; 0x00000034 */
|
||||
volatile CPMUREFDIVSTR _CPMUREFDIV; /* S12CPMU Reference Divider Register; 0x00000035 */
|
||||
volatile CPMUPOSTDIVSTR _CPMUPOSTDIV; /* S12CPMU Post Divider Register; 0x00000036 */
|
||||
volatile CPMUFLGSTR _CPMUFLG; /* S12CPMU Flags Register; 0x00000037 */
|
||||
volatile CPMUINTSTR _CPMUINT; /* S12CPMU Interrupt Enable Register; 0x00000038 */
|
||||
volatile CPMUCLKSSTR _CPMUCLKS; /* S12CPMU Clock Select Register; 0x00000039 */
|
||||
volatile CPMUPLLSTR _CPMUPLL; /* S12CPMU PLL Control Register; 0x0000003A */
|
||||
volatile CPMURTISTR _CPMURTI; /* CPMU RTI Control Register; 0x0000003B */
|
||||
volatile CPMUCOPSTR _CPMUCOP; /* CPMU COP Control Register; 0x0000003C */
|
||||
volatile CPMUARMCOPSTR _CPMUARMCOP; /* CPMU COP Timer Arm/Reset Register; 0x0000003F */
|
||||
volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select; 0x00000040 */
|
||||
volatile CFORCSTR _CFORC; /* Timer Compare Force Register; 0x00000041 */
|
||||
volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register; 0x00000042 */
|
||||
volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register; 0x00000043 */
|
||||
volatile TSCR1STR _TSCR1; /* Timer System Control Register1; 0x00000046 */
|
||||
volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register; 0x00000047 */
|
||||
volatile TCTL1STR _TCTL1; /* Timer Control Register 1; 0x00000048 */
|
||||
volatile TCTL2STR _TCTL2; /* Timer Control Register 2; 0x00000049 */
|
||||
volatile TCTL3STR _TCTL3; /* Timer Control Register 3; 0x0000004A */
|
||||
volatile TCTL4STR _TCTL4; /* Timer Control Register 4; 0x0000004B */
|
||||
volatile TIESTR _TIE; /* Timer Interrupt Enable Register; 0x0000004C */
|
||||
volatile TSCR2STR _TSCR2; /* Timer System Control Register 2; 0x0000004D */
|
||||
volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1; 0x0000004E */
|
||||
volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2; 0x0000004F */
|
||||
volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register; 0x00000060 */
|
||||
volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register; 0x00000061 */
|
||||
volatile OCPDSTR _OCPD; /* Output Compare Pin Disconnect Register; 0x0000006C */
|
||||
volatile PTPSRSTR _PTPSR; /* Precision Timer Prescaler Select Register; 0x0000006E */
|
||||
volatile ATDSTAT0STR _ATDSTAT0; /* ATD Status Register 0; 0x00000076 */
|
||||
volatile PWMESTR _PWME; /* PWM Enable Register; 0x000000A0 */
|
||||
volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register; 0x000000A1 */
|
||||
volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register; 0x000000A2 */
|
||||
volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register; 0x000000A3 */
|
||||
volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register; 0x000000A4 */
|
||||
volatile PWMCTLSTR _PWMCTL; /* PWM Control Register; 0x000000A5 */
|
||||
volatile PWMCLKABSTR _PWMCLKAB; /* PWM Clock Select Register; 0x000000A6 */
|
||||
volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register; 0x000000A8 */
|
||||
volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register; 0x000000A9 */
|
||||
volatile SCI0ACR2STR _SCI0ACR2; /* SCI 0 Alternative Control Register 2; 0x000000CA */
|
||||
volatile SCI0CR2STR _SCI0CR2; /* SCI 0 Control Register 2; 0x000000CB */
|
||||
volatile SCI0SR1STR _SCI0SR1; /* SCI 0 Status Register 1; 0x000000CC */
|
||||
volatile SCI0SR2STR _SCI0SR2; /* SCI 0 Status Register 2; 0x000000CD */
|
||||
volatile SCI0DRHSTR _SCI0DRH; /* SCI 0 Data Register High; 0x000000CE */
|
||||
volatile SCI0DRLSTR _SCI0DRL; /* SCI 0 Data Register Low; 0x000000CF */
|
||||
volatile SCI1ACR2STR _SCI1ACR2; /* SCI 1 Alternative Control Register 2; 0x000000D2 */
|
||||
volatile SCI1CR2STR _SCI1CR2; /* SCI 1 Control Register 2; 0x000000D3 */
|
||||
volatile SCI1SR1STR _SCI1SR1; /* SCI 1 Status Register 1; 0x000000D4 */
|
||||
volatile SCI1SR2STR _SCI1SR2; /* SCI 1 Status Register 2; 0x000000D5 */
|
||||
volatile SCI1DRHSTR _SCI1DRH; /* SCI 1 Data Register High; 0x000000D6 */
|
||||
volatile SCI1DRLSTR _SCI1DRL; /* SCI 1 Data Register Low; 0x000000D7 */
|
||||
volatile SPI0CR1STR _SPI0CR1; /* SPI 0 Control Register 1; 0x000000D8 */
|
||||
volatile SPI0CR2STR _SPI0CR2; /* SPI 0 Control Register 2; 0x000000D9 */
|
||||
volatile SPI0BRSTR _SPI0BR; /* SPI 0 Baud Rate Register; 0x000000DA */
|
||||
volatile SPI0SRSTR _SPI0SR; /* SPI 0 Status Register; 0x000000DB */
|
||||
volatile SCI2ACR2STR _SCI2ACR2; /* SCI 2 Alternative Control Register 2; 0x000000EA */
|
||||
volatile SCI2CR2STR _SCI2CR2; /* SCI 2 Control Register 2; 0x000000EB */
|
||||
volatile SCI2SR1STR _SCI2SR1; /* SCI 2 Status Register 1; 0x000000EC */
|
||||
volatile SCI2SR2STR _SCI2SR2; /* SCI 2 Status Register 2; 0x000000ED */
|
||||
volatile SCI2DRHSTR _SCI2DRH; /* SCI 2 Data Register High; 0x000000EE */
|
||||
volatile SCI2DRLSTR _SCI2DRL; /* SCI 2 Data Register Low; 0x000000EF */
|
||||
volatile SPI1CR1STR _SPI1CR1; /* SPI 1 Control Register 1; 0x000000F0 */
|
||||
volatile SPI1CR2STR _SPI1CR2; /* SPI 1 Control Register 2; 0x000000F1 */
|
||||
volatile SPI1BRSTR _SPI1BR; /* SPI 1 Baud Rate Register; 0x000000F2 */
|
||||
volatile SPI1SRSTR _SPI1SR; /* SPI 1 Status Register; 0x000000F3 */
|
||||
volatile SPI2CR1STR _SPI2CR1; /* SPI 2 Control Register 1; 0x000000F8 */
|
||||
volatile SPI2CR2STR _SPI2CR2; /* SPI 2 Control Register 2; 0x000000F9 */
|
||||
volatile SPI2BRSTR _SPI2BR; /* SPI 2 Baud Rate Register; 0x000000FA */
|
||||
volatile SPI2SRSTR _SPI2SR; /* SPI 2 Status Register; 0x000000FB */
|
||||
volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register; 0x00000100 */
|
||||
volatile FSECSTR _FSEC; /* Flash Security Register; 0x00000101 */
|
||||
volatile FCCOBIXSTR _FCCOBIX; /* Flash CCOB Index Register; 0x00000102 */
|
||||
volatile FCNFGSTR _FCNFG; /* Flash Configuration Register; 0x00000104 */
|
||||
volatile FERCNFGSTR _FERCNFG; /* Flash Error Configuration Register; 0x00000105 */
|
||||
volatile FSTATSTR _FSTAT; /* Flash Status Register; 0x00000106 */
|
||||
volatile FERSTATSTR _FERSTAT; /* Flash Error Status Register; 0x00000107 */
|
||||
volatile FPROTSTR _FPROT; /* P-Flash Protection Register; 0x00000108 */
|
||||
volatile DFPROTSTR _DFPROT; /* D-Flash Protection Register; 0x00000109 */
|
||||
volatile FOPTSTR _FOPT; /* Flash Option Register; 0x00000110 */
|
||||
volatile IVBRSTR _IVBR; /* Interrupt Vector Base Register; 0x00000120 */
|
||||
volatile CANCTL0STR _CANCTL0; /* MSCAN Control 0 Register; 0x00000140 */
|
||||
volatile CANCTL1STR _CANCTL1; /* MSCAN Control 1 Register; 0x00000141 */
|
||||
volatile CANBTR0STR _CANBTR0; /* MSCAN Bus Timing Register 0; 0x00000142 */
|
||||
volatile CANBTR1STR _CANBTR1; /* MSCAN Bus Timing Register 1; 0x00000143 */
|
||||
volatile CANRFLGSTR _CANRFLG; /* MSCAN Receiver Flag Register; 0x00000144 */
|
||||
volatile CANRIERSTR _CANRIER; /* MSCAN Receiver Interrupt Enable Register; 0x00000145 */
|
||||
volatile CANTFLGSTR _CANTFLG; /* MSCAN Transmitter Flag Register; 0x00000146 */
|
||||
volatile CANTIERSTR _CANTIER; /* MSCAN Transmitter Interrupt Enable Register; 0x00000147 */
|
||||
volatile CANTARQSTR _CANTARQ; /* MSCAN Transmitter Message Abort Request; 0x00000148 */
|
||||
volatile CANTAAKSTR _CANTAAK; /* MSCAN Transmitter Message Abort Acknowledge; 0x00000149 */
|
||||
volatile CANTBSELSTR _CANTBSEL; /* MSCAN Transmit Buffer Selection; 0x0000014A */
|
||||
volatile CANIDACSTR _CANIDAC; /* MSCAN Identifier Acceptance Control Register; 0x0000014B */
|
||||
volatile CANMISCSTR _CANMISC; /* MSCAN Miscellaneous Register; 0x0000014D */
|
||||
volatile CANRXERRSTR _CANRXERR; /* MSCAN Receive Error Counter Register; 0x0000014E */
|
||||
volatile CANTXERRSTR _CANTXERR; /* MSCAN Transmit Error Counter Register; 0x0000014F */
|
||||
volatile CANIDAR0STR _CANIDAR0; /* MSCAN Identifier Acceptance Register 0; 0x00000150 */
|
||||
volatile CANIDAR1STR _CANIDAR1; /* MSCAN Identifier Acceptance Register 1; 0x00000151 */
|
||||
volatile CANIDAR2STR _CANIDAR2; /* MSCAN Identifier Acceptance Register 2; 0x00000152 */
|
||||
volatile CANIDAR3STR _CANIDAR3; /* MSCAN Identifier Acceptance Register 3; 0x00000153 */
|
||||
volatile CANIDMR0STR _CANIDMR0; /* MSCAN Identifier Mask Register 0; 0x00000154 */
|
||||
volatile CANIDMR1STR _CANIDMR1; /* MSCAN Identifier Mask Register 1; 0x00000155 */
|
||||
volatile CANIDMR2STR _CANIDMR2; /* MSCAN Identifier Mask Register 2; 0x00000156 */
|
||||
volatile CANIDMR3STR _CANIDMR3; /* MSCAN Identifier Mask Register 3; 0x00000157 */
|
||||
volatile CANIDAR4STR _CANIDAR4; /* MSCAN Identifier Acceptance Register 4; 0x00000158 */
|
||||
volatile CANIDAR5STR _CANIDAR5; /* MSCAN Identifier Acceptance Register 5; 0x00000159 */
|
||||
volatile CANIDAR6STR _CANIDAR6; /* MSCAN Identifier Acceptance Register 6; 0x0000015A */
|
||||
volatile CANIDAR7STR _CANIDAR7; /* MSCAN Identifier Acceptance Register 7; 0x0000015B */
|
||||
volatile CANIDMR4STR _CANIDMR4; /* MSCAN Identifier Mask Register 4; 0x0000015C */
|
||||
volatile CANIDMR5STR _CANIDMR5; /* MSCAN Identifier Mask Register 5; 0x0000015D */
|
||||
volatile CANIDMR6STR _CANIDMR6; /* MSCAN Identifier Mask Register 6; 0x0000015E */
|
||||
volatile CANIDMR7STR _CANIDMR7; /* MSCAN Identifier Mask Register 7; 0x0000015F */
|
||||
volatile CANRXIDR0STR _CANRXIDR0; /* MSCAN Receive Identifier Register 0; 0x00000160 */
|
||||
volatile CANRXIDR1STR _CANRXIDR1; /* MSCAN Receive Identifier Register 1; 0x00000161 */
|
||||
volatile CANRXIDR2STR _CANRXIDR2; /* MSCAN Receive Identifier Register 2; 0x00000162 */
|
||||
volatile CANRXIDR3STR _CANRXIDR3; /* MSCAN Receive Identifier Register 3; 0x00000163 */
|
||||
volatile CANRXDSR0STR _CANRXDSR0; /* MSCAN Receive Data Segment Register 0; 0x00000164 */
|
||||
volatile CANRXDSR1STR _CANRXDSR1; /* MSCAN Receive Data Segment Register 1; 0x00000165 */
|
||||
volatile CANRXDSR2STR _CANRXDSR2; /* MSCAN Receive Data Segment Register 2; 0x00000166 */
|
||||
volatile CANRXDSR3STR _CANRXDSR3; /* MSCAN Receive Data Segment Register 3; 0x00000167 */
|
||||
volatile CANRXDSR4STR _CANRXDSR4; /* MSCAN Receive Data Segment Register 4; 0x00000168 */
|
||||
volatile CANRXDSR5STR _CANRXDSR5; /* MSCAN Receive Data Segment Register 5; 0x00000169 */
|
||||
volatile CANRXDSR6STR _CANRXDSR6; /* MSCAN Receive Data Segment Register 6; 0x0000016A */
|
||||
volatile CANRXDSR7STR _CANRXDSR7; /* MSCAN Receive Data Segment Register 7; 0x0000016B */
|
||||
volatile CANRXDLRSTR _CANRXDLR; /* MSCAN Receive Data Length Register; 0x0000016C */
|
||||
volatile CANTXIDR0STR _CANTXIDR0; /* MSCAN Transmit Identifier Register 0; 0x00000170 */
|
||||
volatile CANTXIDR1STR _CANTXIDR1; /* MSCAN Transmit Identifier Register 1; 0x00000171 */
|
||||
volatile CANTXIDR2STR _CANTXIDR2; /* MSCAN Transmit Identifier Register 2; 0x00000172 */
|
||||
volatile CANTXIDR3STR _CANTXIDR3; /* MSCAN Transmit Identifier Register 3; 0x00000173 */
|
||||
volatile CANTXDSR0STR _CANTXDSR0; /* MSCAN Transmit Data Segment Register 0; 0x00000174 */
|
||||
volatile CANTXDSR1STR _CANTXDSR1; /* MSCAN Transmit Data Segment Register 1; 0x00000175 */
|
||||
volatile CANTXDSR2STR _CANTXDSR2; /* MSCAN Transmit Data Segment Register 2; 0x00000176 */
|
||||
volatile CANTXDSR3STR _CANTXDSR3; /* MSCAN Transmit Data Segment Register 3; 0x00000177 */
|
||||
volatile CANTXDSR4STR _CANTXDSR4; /* MSCAN Transmit Data Segment Register 4; 0x00000178 */
|
||||
volatile CANTXDSR5STR _CANTXDSR5; /* MSCAN Transmit Data Segment Register 5; 0x00000179 */
|
||||
volatile CANTXDSR6STR _CANTXDSR6; /* MSCAN Transmit Data Segment Register 6; 0x0000017A */
|
||||
volatile CANTXDSR7STR _CANTXDSR7; /* MSCAN Transmit Data Segment Register 7; 0x0000017B */
|
||||
volatile CANTXDLRSTR _CANTXDLR; /* MSCAN Transmit Data Length Register; 0x0000017C */
|
||||
volatile CANTXTBPRSTR _CANTXTBPR; /* MSCAN Transmit Buffer Priority; 0x0000017D */
|
||||
volatile PTTSTR _PTT; /* Port T Data Register; 0x00000240 */
|
||||
volatile PTITSTR _PTIT; /* Port T Input Register; 0x00000241 */
|
||||
volatile DDRTSTR _DDRT; /* Port T Data Direction Register; 0x00000242 */
|
||||
volatile PERTSTR _PERT; /* Port T Pull Device Enable Register; 0x00000244 */
|
||||
volatile PPSTSTR _PPST; /* Port T Polarity Select Register; 0x00000245 */
|
||||
volatile PTSSTR _PTS; /* Port S Data Register; 0x00000248 */
|
||||
volatile PTISSTR _PTIS; /* Port S Input Register; 0x00000249 */
|
||||
volatile DDRSSTR _DDRS; /* Port S Data Direction Register; 0x0000024A */
|
||||
volatile PERSSTR _PERS; /* Port S Pull Device Enable Register; 0x0000024C */
|
||||
volatile PPSSSTR _PPSS; /* Port S Polarity Select Register; 0x0000024D */
|
||||
volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register; 0x0000024E */
|
||||
volatile PRR0STR _PRR0; /* Pin Routing Register 0; 0x0000024F */
|
||||
volatile PTMSTR _PTM; /* Port M Data Register; 0x00000250 */
|
||||
volatile PTIMSTR _PTIM; /* Port M Input Register; 0x00000251 */
|
||||
volatile DDRMSTR _DDRM; /* Port M Data Direction Register; 0x00000252 */
|
||||
volatile PERMSTR _PERM; /* Port M Pull Device Enable Register; 0x00000254 */
|
||||
volatile PPSMSTR _PPSM; /* Port M Polarity Select Register; 0x00000255 */
|
||||
volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register; 0x00000256 */
|
||||
volatile PKGCRSTR _PKGCR; /* Package Code Register; 0x00000257 */
|
||||
volatile PTPSTR _PTP; /* Port P Data Register; 0x00000258 */
|
||||
volatile PTIPSTR _PTIP; /* Port P Input Register; 0x00000259 */
|
||||
volatile DDRPSTR _DDRP; /* Port P Data Direction Register; 0x0000025A */
|
||||
volatile PERPSTR _PERP; /* Port P Pull Device Enable Register; 0x0000025C */
|
||||
volatile PPSPSTR _PPSP; /* Port P Polarity Select Register; 0x0000025D */
|
||||
volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register; 0x0000025E */
|
||||
volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register; 0x0000025F */
|
||||
volatile PTJSTR _PTJ; /* Port J Data Register; 0x00000268 */
|
||||
volatile PTIJSTR _PTIJ; /* Port J Input Register; 0x00000269 */
|
||||
volatile DDRJSTR _DDRJ; /* Port J Data Direction Register; 0x0000026A */
|
||||
volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register; 0x0000026C */
|
||||
volatile PPSJSTR _PPSJ; /* Port J Polarity Select Register; 0x0000026D */
|
||||
volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register; 0x0000026E */
|
||||
volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register; 0x0000026F */
|
||||
volatile CPMULVCTLSTR _CPMULVCTL; /* Low Voltage Control Register; 0x000002F1 */
|
||||
volatile CPMUAPICTLSTR _CPMUAPICTL; /* Autonomous Periodical Interrupt Control Register; 0x000002F2 */
|
||||
volatile CPMUACLKTRSTR _CPMUACLKTR; /* Autonomous Clock Trimming Register; 0x000002F3 */
|
||||
volatile CPMUOSCSTR _CPMUOSC; /* S12CPMU Oscillator Register; 0x000002FA */
|
||||
volatile CPMUPROTSTR _CPMUPROT; /* S12CPMUV1 Protection Register; 0x000002FB */
|
||||
/* NVFPROT - macro for reading non volatile register Non Volatile P-Flash Protection Register; 0x0000FF0C */
|
||||
/* NVDFPROT - macro for reading non volatile register Non Volatile D-Flash Protection Register; 0x0000FF0D */
|
||||
/* NVFOPT - macro for reading non volatile register Non Volatile Flash Option Register; 0x0000FF0E */
|
||||
/* NVFSEC - macro for reading non volatile register Non Volatile Flash Security Register; 0x0000FF0F */
|
||||
|
||||
|
||||
/* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */
|
||||
volatile PORTABSTR _PORTAB; /* Port AB Data Register; 0x00000000 */
|
||||
volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register; 0x00000002 */
|
||||
volatile PORTCDSTR _PORTCD; /* Port CD Data Register; 0x00000004 */
|
||||
volatile DDRCDSTR _DDRCD; /* Port CD Data Direction Register; 0x00000006 */
|
||||
volatile PARTIDSTR _PARTID; /* Part ID Register; 0x0000001A */
|
||||
volatile DBGTBSTR _DBGTB; /* Debug Trace Buffer Register; 0x00000024 */
|
||||
volatile TCNTSTR _TCNT; /* Timer Count Register; 0x00000044 */
|
||||
volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0; 0x00000050 */
|
||||
volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1; 0x00000052 */
|
||||
volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2; 0x00000054 */
|
||||
volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3; 0x00000056 */
|
||||
volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4; 0x00000058 */
|
||||
volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5; 0x0000005A */
|
||||
volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6; 0x0000005C */
|
||||
volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7; 0x0000005E */
|
||||
volatile PACNTSTR _PACNT; /* Pulse Accumulators Count Register; 0x00000062 */
|
||||
volatile ATDCTL01STR _ATDCTL01; /* ATD Control Register 01; 0x00000070 */
|
||||
volatile ATDCTL23STR _ATDCTL23; /* ATD Control Register 23; 0x00000072 */
|
||||
volatile ATDCTL45STR _ATDCTL45; /* ATD Control Register 45; 0x00000074 */
|
||||
volatile ATDCMPESTR _ATDCMPE; /* ATD Compare Enable Register; 0x00000078 */
|
||||
volatile ATDSTAT2STR _ATDSTAT2; /* ATD Status Register 2; 0x0000007A */
|
||||
volatile ATDDIENSTR _ATDDIEN; /* ATD Input Enable Register; 0x0000007C */
|
||||
volatile ATDCMPHTSTR _ATDCMPHT; /* ATD Compare Higher Than Register; 0x0000007E */
|
||||
volatile ATDDR0STR _ATDDR0; /* ATD Conversion Result Register 0; 0x00000080 */
|
||||
volatile ATDDR1STR _ATDDR1; /* ATD Conversion Result Register 1; 0x00000082 */
|
||||
volatile ATDDR2STR _ATDDR2; /* ATD Conversion Result Register 2; 0x00000084 */
|
||||
volatile ATDDR3STR _ATDDR3; /* ATD Conversion Result Register 3; 0x00000086 */
|
||||
volatile ATDDR4STR _ATDDR4; /* ATD Conversion Result Register 4; 0x00000088 */
|
||||
volatile ATDDR5STR _ATDDR5; /* ATD Conversion Result Register 5; 0x0000008A */
|
||||
volatile ATDDR6STR _ATDDR6; /* ATD Conversion Result Register 6; 0x0000008C */
|
||||
volatile ATDDR7STR _ATDDR7; /* ATD Conversion Result Register 7; 0x0000008E */
|
||||
volatile ATDDR8STR _ATDDR8; /* ATD Conversion Result Register 8; 0x00000090 */
|
||||
volatile ATDDR9STR _ATDDR9; /* ATD Conversion Result Register 9; 0x00000092 */
|
||||
volatile ATDDR10STR _ATDDR10; /* ATD Conversion Result Register 10; 0x00000094 */
|
||||
volatile ATDDR11STR _ATDDR11; /* ATD Conversion Result Register 11; 0x00000096 */
|
||||
volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register; 0x000000AC */
|
||||
volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register; 0x000000AE */
|
||||
volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register; 0x000000B0 */
|
||||
volatile PWMCNT67STR _PWMCNT67; /* PWM Channel Counter 67 Register; 0x000000B2 */
|
||||
volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register; 0x000000B4 */
|
||||
volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register; 0x000000B6 */
|
||||
volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register; 0x000000B8 */
|
||||
volatile PWMPER67STR _PWMPER67; /* PWM Channel Period 67 Register; 0x000000BA */
|
||||
volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register; 0x000000BC */
|
||||
volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register; 0x000000BE */
|
||||
volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register; 0x000000C0 */
|
||||
volatile PWMDTY67STR _PWMDTY67; /* PWM Channel Duty 67 Register; 0x000000C2 */
|
||||
volatile SCI0BDSTR _SCI0BD; /* SCI 0 Baud Rate Register; 0x000000C8 */
|
||||
volatile SCI1BDSTR _SCI1BD; /* SCI 1 Baud Rate Register; 0x000000D0 */
|
||||
volatile SPI0DRSTR _SPI0DR; /* SPI 0 Data Register; 0x000000DC */
|
||||
volatile SCI2BDSTR _SCI2BD; /* SCI 2 Baud Rate Register; 0x000000E8 */
|
||||
volatile SPI1DRSTR _SPI1DR; /* SPI 1 Data Register; 0x000000F4 */
|
||||
volatile SPI2DRSTR _SPI2DR; /* SPI 2 Data Register; 0x000000FC */
|
||||
volatile FCCOBSTR _FCCOB; /* Flash Common Command Object Register; 0x0000010A */
|
||||
volatile CANRXTSRSTR _CANRXTSR; /* MSCAN Receive Time Stamp Register; 0x0000016E */
|
||||
volatile CANTXTSRSTR _CANTXTSR; /* MSCAN Transmit Time Stamp Register; 0x0000017E */
|
||||
volatile PT01ADSTR _PT01AD; /* Port AD Data Register; 0x00000270 */
|
||||
volatile PTI01ADSTR _PTI01AD; /* Port AD Input Register; 0x00000272 */
|
||||
volatile DDR01ADSTR _DDR01AD; /* Port AD Data Direction Register; 0x00000274 */
|
||||
volatile PER01ADSTR _PER01AD; /* Port AD Pull Up Enable Register; 0x00000278 */
|
||||
volatile PPS01ADSTR _PPS01AD; /* Port AD Polarity Select Register; 0x0000027A */
|
||||
volatile PIE01ADSTR _PIE01AD; /* Port AD Interrupt Enable Register; 0x0000027C */
|
||||
volatile PIF01ADSTR _PIF01AD; /* Port AD Interrupt Flag Register; 0x0000027E */
|
||||
volatile CPMUAPIRSTR _CPMUAPIR; /* Autonomous Periodical Interrupt Rate Register; 0x000002F4 */
|
||||
volatile CPMUIRCTRIMSTR _CPMUIRCTRIM; /* S12CPMU IRC1M Trim Registers; 0x000002F8 */
|
||||
/* BAKEY0 - macro for reading non volatile register Backdoor Comparison Key 0; 0x0000FF00 */
|
||||
/* BAKEY1 - macro for reading non volatile register Backdoor Comparison Key 1; 0x0000FF02 */
|
||||
/* BAKEY2 - macro for reading non volatile register Backdoor Comparison Key 2; 0x0000FF04 */
|
||||
/* BAKEY3 - macro for reading non volatile register Backdoor Comparison Key 3; 0x0000FF06 */
|
||||
|
||||
/*lint -restore */
|
||||
|
||||
/* EOF */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,212 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo/HCS12_DevKit_S12G128_CodeWarrior/Boot/main.c
|
||||
* \brief Demo program application source file.
|
||||
* \ingroup Boot_HCS12_DevKit_S12G128_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2019 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include <hidef.h> /* common defines and macros */
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
#include "derivative.h" /* derivative-specific definitions */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
static void Init(void);
|
||||
static void SystemClockInit(void);
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief This is the entry point for the bootloader application and is called
|
||||
** by the reset interrupt vector after the C-startup routines executed.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void main(void)
|
||||
{
|
||||
/* initialize the microcontroller */
|
||||
Init();
|
||||
/* initialize the bootloader */
|
||||
BootInit();
|
||||
|
||||
/* start the infinite program loop */
|
||||
for (;;)
|
||||
{
|
||||
/* run the bootloader task */
|
||||
BootTask();
|
||||
}
|
||||
} /*** end of main ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the microcontroller.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void Init(void)
|
||||
{
|
||||
volatile unsigned long delayCnt;
|
||||
|
||||
/* ---- initialize the system clock ---- */
|
||||
SystemClockInit();
|
||||
|
||||
/* ---- configure SW3 digital input ---- */
|
||||
/* disable pull device for the pushbutton */
|
||||
PERT &= ~0x40;
|
||||
/* configure the pushbutton pin as a digital input */
|
||||
DDRT &= ~0x40;
|
||||
|
||||
/* ---- configure the CAN Tx and Rx pins ---- */
|
||||
/* configure pullup device for the CAN pins */
|
||||
PPSM &= ~0x03;
|
||||
/* enable the pull device for the CAN pins */
|
||||
PERM |= 0x03;
|
||||
/* configure the CAN tx pin as a push pull output */
|
||||
WOMM |= 0x02;
|
||||
|
||||
/* ---- configure the SPI pins for the SBC with CAN transceiver ---- */
|
||||
/* configure a pullup device for SPI MISO, MOSI, CLK and a pulldown for CS */
|
||||
PPSJ &= ~0x7;
|
||||
PPSJ |= 0x10;
|
||||
/* enabled the pull device for the SPI pins */
|
||||
PERJ |= 0x0F;
|
||||
/* disable interrupt on the SPI CS pin */
|
||||
PIEJ &= ~0x10;
|
||||
/* configure the SPI CS pin as a digital output and deselect the chip */
|
||||
PTJ |= 0x10;
|
||||
DDRJ |= 0x10;
|
||||
|
||||
/* ---- initialize the SPI peripheral ---- */
|
||||
/* disable the SPI1 module and clearing flags in SPISR register */
|
||||
SPI1CR1 = 0x00;
|
||||
/* set configuration in control register 2
|
||||
* XFRW=1,MODFEN=1, BIDIROE=0, SPISWAI=0, SPC0=0
|
||||
*/
|
||||
SPI1CR2 = 0x50;
|
||||
/* configure the communication speed */
|
||||
SPI1BR = 0x42;
|
||||
/* set the configuration in control register 1
|
||||
* SPIE=0, SPE=1, SPTIE=0, MSTR=1, CPOL=0, CPHA=1, SSOE=1, LSBFE=0
|
||||
*/
|
||||
SPI1CR1 = 0x56;
|
||||
|
||||
/* ---- communicate with SBC via SPI to enable CAN communication ---- */
|
||||
/* delay a bit to make sure the SBC is ready to receive new data */
|
||||
delayCnt = 300;
|
||||
while(delayCnt-- > 0);
|
||||
/* read Vreg register H */
|
||||
SPI1DRH = 0xDF;
|
||||
SPI1DRL = 0x80;
|
||||
/* wait for the SPI transmit data register to be empty */
|
||||
while(SPI1SR_SPTEF == 0);
|
||||
|
||||
/* delay a bit to make sure the SBC is ready to receive new data */
|
||||
delayCnt = 300;
|
||||
while(delayCnt-- > 0);
|
||||
/* enter in "normal mode" */
|
||||
SPI1DRH = 0x5A;
|
||||
SPI1DRL = 0x00;
|
||||
/* wait for the SPI transmit data register to be empty */
|
||||
while(SPI1SR_SPTEF == 0);
|
||||
|
||||
/* delay a bit to make sure the SBC is ready to receive new data */
|
||||
delayCnt = 300;
|
||||
while(delayCnt-- > 0);
|
||||
/* enable 5V-CAN and Vaux */
|
||||
SPI1DRH = 0x5E;
|
||||
SPI1DRL = 0x90;
|
||||
/* wait for the SPI transmit data register to be empty */
|
||||
while(SPI1SR_SPTEF == 0);
|
||||
|
||||
/* delay a bit to make sure the SBC is ready to receive new data */
|
||||
delayCnt = 300;
|
||||
while(delayCnt-- > 0);
|
||||
/* set CAN in Tx-Rx mode, fast slew rate */
|
||||
SPI1DRH = 0x60;
|
||||
SPI1DRL = 0xC0;
|
||||
/* wait for the SPI transmit data register to be empty */
|
||||
while(SPI1SR_SPTEF == 0);
|
||||
} /*** end of Init ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the clock configuration of the microcontroller.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void SystemClockInit(void)
|
||||
{
|
||||
/* system clock initialization in PEE mode. the external 8 MHz crystal oscillator is
|
||||
* used to drive the PLL such that the system clock (Fpll) is 24 MHz, with and Fvco
|
||||
* of 48 MHz and the bus clock is Fpll/2 = 12 MHz.
|
||||
*/
|
||||
/* disable the protection of the clock configuration registers */
|
||||
CPMUPROT = 0x26;
|
||||
/* configure the oscillator to be disabled in stop mode */
|
||||
CPMUCLKS_PSTP = 0;
|
||||
/* enable the PLL to allow write to divider registers */
|
||||
CPMUCLKS_PLLSEL = 1;
|
||||
/* configure Fref to be 4 MHz. REFDIV = 0, REFCLK = 2 - 6 MHz.
|
||||
* Fref = Fosc / (REFDIV + 1)
|
||||
*/
|
||||
CPMUREFDIV = 0x41;
|
||||
/* configure Fvco to be 48 MHz. SYNDIV = 11, VCOFRQ = 48 - 50 MHz.
|
||||
* Fvco = Fref * (SYNDIV + 1)
|
||||
*/
|
||||
CPMUSYNR = 0x4B;
|
||||
/* select Fpll (locked) to be 24 MHz. POSTDIV = 1.
|
||||
* Fpll = Fvco / (POSTDIV + 1)
|
||||
*/
|
||||
CPMUPOSTDIV = 0x01;
|
||||
/* set Fpll as the source of the system clocks */
|
||||
CPMUCLKS_PLLSEL = 1;
|
||||
/* wait for hardware handshake, which verifies a correct configuration of CPMUCLKS */
|
||||
while(CPMUCLKS_PLLSEL == 0)
|
||||
{
|
||||
;
|
||||
}
|
||||
/* enabled the external oscillator, since it is used to drive the PLL */
|
||||
CPMUOSC_OSCE = 1;
|
||||
/* wait for the oscillation to stabilize */
|
||||
while(CPMUFLG_UPOSC == 0)
|
||||
{
|
||||
;
|
||||
}
|
||||
/* configure the PLL frequency modulation */
|
||||
CPMUPLL = 0x00U;
|
||||
/* wait for the PLL to lock */
|
||||
while(CPMUFLG_LOCK == 0)
|
||||
{
|
||||
;
|
||||
}
|
||||
/* enable the protection of the clock configuration registers */
|
||||
CPMUPROT = 0x00;
|
||||
} /*** end of SystemClockInit ***/
|
||||
|
||||
|
||||
/*********************************** end of main.c *************************************/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,56 @@
|
|||
/* This is a linker parameter file for the MC9S12G128 */
|
||||
NAMES END /* CodeWarrior will pass all the needed files to the linker by command line. But here you may add your own files too. */
|
||||
|
||||
SEGMENTS /* Here all RAM/ROM areas of the device are listed. Used in PLACEMENT below. */
|
||||
|
||||
/* Register space */
|
||||
/* IO_SEG = PAGED 0x0000 TO 0x03FF; intentionally not defined */
|
||||
|
||||
/* RAM */
|
||||
RAM = READ_WRITE 0x2000 TO 0x3FFF;
|
||||
|
||||
/* D-Flash */
|
||||
DFLASH = READ_ONLY 0x0400 TO 0x13FF;
|
||||
|
||||
/* non-paged FLASHs */
|
||||
ROM_4000 = READ_ONLY 0x4000 TO 0x7FFF;
|
||||
ROM_C000 = READ_ONLY 0xC000 TO 0xE6FF;
|
||||
|
||||
/* paged FLASH: 0x8000 TO 0xBFFF; addressed through PPAGE */
|
||||
PAGE_08 = READ_ONLY 0x088000 TO 0x08BFFF;
|
||||
PAGE_09 = READ_ONLY 0x098000 TO 0x09BFFF;
|
||||
PAGE_0A = READ_ONLY 0x0A8000 TO 0x0ABFFF;
|
||||
PAGE_0B = READ_ONLY 0x0B8000 TO 0x0BBFFF;
|
||||
PAGE_0C = READ_ONLY 0x0C8000 TO 0x0CBFFF;
|
||||
/* PAGE_0D = READ_ONLY 0x0D8000 TO 0x0DBFFF; not used: equivalent to ROM_4000 */
|
||||
PAGE_0E = READ_ONLY 0x0E8000 TO 0x0EBFFF;
|
||||
PAGE_0F = READ_ONLY 0x0F8000 TO 0x0FA6FF; /* equivalent to ROM_C000. last part reserved for vector table and OpenBLT */
|
||||
END
|
||||
|
||||
PLACEMENT /* here all predefined and user segments are placed into the SEGMENTS defined above. */
|
||||
_PRESTART, /* Used in HIWARE format: jump to _Startup at the code start */
|
||||
STARTUP, /* startup data structures */
|
||||
ROM_VAR, /* constant variables */
|
||||
STRINGS, /* string literals */
|
||||
VIRTUAL_TABLE_SEGMENT, /* C++ virtual table segment */
|
||||
NON_BANKED, /* runtime routines which must not be banked */
|
||||
COPY /* copy down information: how to initialize variables */
|
||||
/* in case you want to use ROM_C000 here as well, make sure
|
||||
that all files (incl. library files) are compiled with the
|
||||
option: -OnB=b */
|
||||
INTO ROM_4000/*, ROM_C000*/;
|
||||
|
||||
DEFAULT_ROM INTO PAGE_08, PAGE_09, PAGE_0A, PAGE_0B, PAGE_0C, PAGE_0E, PAGE_0F;
|
||||
SSTACK, /* allocate stack first to avoid overwriting variables on overflow */
|
||||
DEFAULT_RAM INTO RAM;
|
||||
|
||||
|
||||
END
|
||||
|
||||
ENTRIES /* keep the following unreferenced variables */
|
||||
_vectab
|
||||
END
|
||||
|
||||
STACKSIZE 0x100
|
||||
|
||||
|
||||
Binary file not shown.
|
|
@ -0,0 +1,38 @@
|
|||
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|
||||
S224034000CF2100C6055B134A80F7084A800008000140154091210000090502060206030764
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
S9030000FC
|
||||
|
|
@ -0,0 +1,462 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/boot.c
|
||||
* \brief Demo program bootloader interface source file.
|
||||
* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
#if (BOOT_COM_UART_ENABLE > 0)
|
||||
static void BootComUartInit(void);
|
||||
static void BootComUartCheckActivationRequest(void);
|
||||
#endif
|
||||
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||
static void BootComCanInit(void);
|
||||
static void BootComCanCheckActivationRequest(void);
|
||||
#endif
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the communication interface.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void BootComInit(void)
|
||||
{
|
||||
#if (BOOT_COM_UART_ENABLE > 0)
|
||||
BootComUartInit();
|
||||
#endif
|
||||
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||
BootComCanInit();
|
||||
#endif
|
||||
} /*** end of BootComInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Receives the CONNECT request from the host, which indicates that the
|
||||
** bootloader should be activated and, if so, activates it.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void BootComCheckActivationRequest(void)
|
||||
{
|
||||
#if (BOOT_COM_UART_ENABLE > 0)
|
||||
BootComUartCheckActivationRequest();
|
||||
#endif
|
||||
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||
BootComCanCheckActivationRequest();
|
||||
#endif
|
||||
} /*** end of BootComCheckActivationRequest ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Bootloader activation function.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void BootActivate(void)
|
||||
{
|
||||
/* perform a software reset by letting the watchdog time out. make sure it is
|
||||
* enabled
|
||||
*/
|
||||
if ( (CPMUCOP & 0x07) == 0)
|
||||
{
|
||||
/* enable the watchdog */
|
||||
CPMUCOP = 0x41;
|
||||
}
|
||||
/* wait for the watchdog to time out which triggers a reset */
|
||||
for (;;)
|
||||
{
|
||||
;
|
||||
}
|
||||
} /*** end of BootActivate ***/
|
||||
|
||||
|
||||
#if (BOOT_COM_UART_ENABLE > 0)
|
||||
/****************************************************************************************
|
||||
* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Timeout time for the reception of a CTO packet. The timer is started upon
|
||||
* reception of the first packet byte.
|
||||
*/
|
||||
#define UART_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
static unsigned char UartReceiveByte(unsigned char *data);
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the UART communication interface.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void BootComUartInit(void)
|
||||
{
|
||||
unsigned short baudrate_sbr0_12;
|
||||
|
||||
/* reset the SCI subsystem's configuration, which automatically configures it for
|
||||
* 8,n,1 communication mode.
|
||||
*/
|
||||
SCI0CR2 = 0;
|
||||
SCI0CR1 = 0;
|
||||
SCI0BDH = 0;
|
||||
SCI0BDL = 0;
|
||||
/* configure the baudrate from BOOT_COM_UART_BAUDRATE */
|
||||
baudrate_sbr0_12 = (BOOT_CPU_SYSTEM_SPEED_KHZ * 1000ul) / 16 / BOOT_COM_UART_BAUDRATE;
|
||||
baudrate_sbr0_12 &= SCI0BD_SBR_MASK;
|
||||
/* write first MSB then LSB for the baudrate to latch */
|
||||
SCI0BDH = (unsigned char)(baudrate_sbr0_12 >> 8);
|
||||
SCI0BDL = (unsigned char)baudrate_sbr0_12;
|
||||
/* enable the receiver */
|
||||
SCI0CR2 |= (SCI0CR2_RE_MASK);
|
||||
} /*** end of BootComUartInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Receives the CONNECT request from the host, which indicates that the
|
||||
** bootloader should be activated and, if so, activates it.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void BootComUartCheckActivationRequest(void)
|
||||
{
|
||||
static unsigned char xcpCtoReqPacket[BOOT_COM_UART_RX_MAX_DATA+1];
|
||||
static unsigned char xcpCtoRxLength;
|
||||
static unsigned char xcpCtoRxInProgress = 0;
|
||||
static unsigned long xcpCtoRxStartTime = 0;
|
||||
|
||||
/* start of cto packet received? */
|
||||
if (xcpCtoRxInProgress == 0)
|
||||
{
|
||||
/* store the message length when received */
|
||||
if (UartReceiveByte(&xcpCtoReqPacket[0]) == 1)
|
||||
{
|
||||
/* check that the length has a valid value. it should not be 0 */
|
||||
if ( (xcpCtoReqPacket[0] > 0) &&
|
||||
(xcpCtoReqPacket[0] <= BOOT_COM_UART_RX_MAX_DATA) )
|
||||
{
|
||||
/* store the start time */
|
||||
xcpCtoRxStartTime = TimerGet();
|
||||
/* indicate that a cto packet is being received */
|
||||
xcpCtoRxInProgress = 1;
|
||||
/* reset packet data count */
|
||||
xcpCtoRxLength = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* store the next packet byte */
|
||||
if (UartReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1)
|
||||
{
|
||||
/* increment the packet data count */
|
||||
xcpCtoRxLength++;
|
||||
|
||||
/* check to see if the entire packet was received */
|
||||
if (xcpCtoRxLength == xcpCtoReqPacket[0])
|
||||
{
|
||||
/* done with cto packet reception */
|
||||
xcpCtoRxInProgress = 0;
|
||||
|
||||
/* check if this was an XCP CONNECT command */
|
||||
if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00))
|
||||
{
|
||||
/* connection request received so start the bootloader */
|
||||
BootActivate();
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* check packet reception timeout */
|
||||
if (TimerGet() > (xcpCtoRxStartTime + UART_CTO_RX_PACKET_TIMEOUT_MS))
|
||||
{
|
||||
/* cancel cto packet reception due to timeout. note that this automatically
|
||||
* discards the already received packet bytes, allowing the host to retry.
|
||||
*/
|
||||
xcpCtoRxInProgress = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
} /*** end of BootComUartCheckActivationRequest ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Receives a communication interface byte if one is present.
|
||||
** \param data Pointer to byte where the data is to be stored.
|
||||
** \return 1 if a byte was received, 0 otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static unsigned char UartReceiveByte(unsigned char *data)
|
||||
{
|
||||
/* check if a new byte was received by means of the RDRF-bit */
|
||||
if((SCI0SR1 & SCI0SR1_RDRF_MASK) != 0)
|
||||
{
|
||||
/* store the received byte */
|
||||
data[0] = SCI0DRL;
|
||||
/* inform caller of the newly received byte */
|
||||
return 1;
|
||||
}
|
||||
/* inform caller that no new data was received */
|
||||
return 0;
|
||||
} /*** end of UartReceiveByte ***/
|
||||
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
||||
|
||||
|
||||
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||
/****************************************************************************************
|
||||
* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Type definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Structure type with the layout of the CAN bus timing registers. */
|
||||
typedef struct
|
||||
{
|
||||
unsigned char tseg1; /**< CAN time segment 1 */
|
||||
unsigned char tseg2; /**< CAN time segment 2 */
|
||||
} tCanBusTiming;
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
#define CONVERT_STD_ID_TO_REG0(id) ((unsigned char)(((unsigned short)id & 0x07f8) >> 3))
|
||||
#define CONVERT_STD_ID_TO_REG1(id) ((unsigned char)(id & 0x07) << 5)
|
||||
#define CONVERT_STD_ID_TO_REG2(id) (0)
|
||||
#define CONVERT_STD_ID_TO_REG3(id) (0)
|
||||
#define CONVERT_EXT_ID_TO_REG0(id) ((unsigned char)(id >> 21))
|
||||
#define CONVERT_EXT_ID_TO_REG1(id) ((((unsigned char)(id >> 15)) & 0x07) | \
|
||||
(((unsigned char)(id >> 13)) & 0xe0) | CANRXIDR1_IDE_MASK)
|
||||
#define CONVERT_EXT_ID_TO_REG2(id) ((unsigned char)(((unsigned short)id & 0x7f80) >> 7))
|
||||
#define CONVERT_EXT_ID_TO_REG3(id) ((unsigned char)(id & 0x7f) << 1)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Local constant declarations
|
||||
****************************************************************************************/
|
||||
/**
|
||||
* \brief Array with possible time quanta configurations.
|
||||
* \details According to the CAN protocol 1 bit-time can be made up of between 8..25
|
||||
* time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
|
||||
* always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2)
|
||||
* * 100%. This array contains possible and valid time quanta configurations
|
||||
* with a sample point between 68..78%.
|
||||
*/
|
||||
static const tCanBusTiming canTiming[] =
|
||||
{ /* TQ | TSEG1 | TSEG2 | SP */
|
||||
/* ------------------------- */
|
||||
{ 5, 2 }, /* 8 | 5 | 2 | 75% */
|
||||
{ 6, 2 }, /* 9 | 6 | 2 | 78% */
|
||||
{ 6, 3 }, /* 10 | 6 | 3 | 70% */
|
||||
{ 7, 3 }, /* 11 | 7 | 3 | 73% */
|
||||
{ 8, 3 }, /* 12 | 8 | 3 | 75% */
|
||||
{ 9, 3 }, /* 13 | 9 | 3 | 77% */
|
||||
{ 9, 4 }, /* 14 | 9 | 4 | 71% */
|
||||
{ 10, 4 }, /* 15 | 10 | 4 | 73% */
|
||||
{ 11, 4 }, /* 16 | 11 | 4 | 75% */
|
||||
{ 12, 4 }, /* 17 | 12 | 4 | 76% */
|
||||
{ 12, 5 }, /* 18 | 12 | 5 | 72% */
|
||||
{ 13, 5 }, /* 19 | 13 | 5 | 74% */
|
||||
{ 14, 5 }, /* 20 | 14 | 5 | 75% */
|
||||
{ 15, 5 }, /* 21 | 15 | 5 | 76% */
|
||||
{ 15, 6 }, /* 22 | 15 | 6 | 73% */
|
||||
{ 16, 6 }, /* 23 | 16 | 6 | 74% */
|
||||
{ 16, 7 }, /* 24 | 16 | 7 | 71% */
|
||||
{ 16, 8 } /* 25 | 16 | 8 | 68% */
|
||||
};
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Search algorithm to match the desired baudrate to a possible bus timing
|
||||
** configuration.
|
||||
** \param baud The desired baudrate in kbps. Valid values are 10..1000.
|
||||
** \param btr0 Pointer to where the value for register CANxBTR0 will be stored.
|
||||
** \param btr1 Pointer to where the value for register CANxBTR1 will be stored.
|
||||
** \return 1 if the CAN bustiming register values were found, 0 otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned char *btr0, unsigned char *btr1)
|
||||
{
|
||||
unsigned char prescaler;
|
||||
unsigned char cnt;
|
||||
|
||||
/* loop through all possible time quanta configurations to find a match */
|
||||
for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
|
||||
{
|
||||
if ((BOOT_CPU_XTAL_SPEED_KHZ % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)
|
||||
{
|
||||
/* compute the prescaler that goes with this TQ configuration */
|
||||
prescaler = (unsigned char)(BOOT_CPU_XTAL_SPEED_KHZ/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1)));
|
||||
|
||||
/* make sure the prescaler is valid */
|
||||
if ( (prescaler > 0) && (prescaler <= 64) )
|
||||
{
|
||||
/* store the MSCAN bustiming register values */
|
||||
*btr0 = prescaler - 1;
|
||||
*btr1 = ((canTiming[cnt].tseg2 - 1) << 4) | (canTiming[cnt].tseg1 - 1);
|
||||
/* found a good bus timing configuration */
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* could not find a good bus timing configuration */
|
||||
return 0;
|
||||
} /*** end of CanGetSpeedConfig ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the CAN communication interface.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void BootComCanInit(void)
|
||||
{
|
||||
unsigned char btrRegValues[2];
|
||||
unsigned long accept_code;
|
||||
unsigned long accept_mask;
|
||||
|
||||
/* enter initialization mode. note that this automatically disables CAN interrupts */
|
||||
CANCTL0 = CANCTL0_INITRQ_MASK;
|
||||
/* wait for initialization mode entry handshake from the hardware */
|
||||
while ((CANCTL1 & CANCTL1_INITAK_MASK) == 0)
|
||||
{
|
||||
;
|
||||
}
|
||||
|
||||
/* enable the CAN controller, disable wake up and listen modes and set the
|
||||
* crystal oscillator as the clock source.
|
||||
*/
|
||||
CANCTL1 = CANCTL1_CANE_MASK;
|
||||
|
||||
/* configure baudrate */
|
||||
if (CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &btrRegValues[0], &btrRegValues[1]) == 1)
|
||||
{
|
||||
/* configure the baudrate */
|
||||
CANBTR0 = btrRegValues[0];
|
||||
CANBTR1 = btrRegValues[1];
|
||||
}
|
||||
|
||||
/* enable 2 32-bit acceptance filters. both will be configured for the same code and
|
||||
* mask. the only difference is that filter 0 will be setup to receive extended 29-bit
|
||||
* identifiers and filter 0 to receive standard 11-bit identifiers.
|
||||
*/
|
||||
CANIDAC_IDAM0 = 0;
|
||||
CANIDAC_IDAM1 = 0;
|
||||
|
||||
/* set the acceptance filter code and mask to receive all messages */
|
||||
accept_code = 0x00000000;
|
||||
accept_mask = 0x1fffffff;
|
||||
|
||||
/* configure acceptance filter 0 for 29-bit extended identifiers */
|
||||
CANIDAR0 = CONVERT_EXT_ID_TO_REG0(accept_code);
|
||||
CANIDAR1 = CONVERT_EXT_ID_TO_REG1(accept_code);
|
||||
CANIDAR2 = CONVERT_EXT_ID_TO_REG2(accept_code);
|
||||
CANIDAR3 = CONVERT_EXT_ID_TO_REG3(accept_code);
|
||||
CANIDMR0 = CONVERT_EXT_ID_TO_REG0(accept_mask);
|
||||
CANIDMR1 = (CONVERT_EXT_ID_TO_REG1(accept_mask) | 0x10) & (unsigned char)(~0x08);
|
||||
CANIDMR2 = CONVERT_EXT_ID_TO_REG2(accept_mask);
|
||||
CANIDMR3 = CONVERT_EXT_ID_TO_REG3(accept_mask);
|
||||
|
||||
/* configure acceptance filter 1 for 11-bit standard identifiers */
|
||||
CANIDAR4 = CONVERT_STD_ID_TO_REG0(accept_code);
|
||||
CANIDAR5 = CONVERT_STD_ID_TO_REG1(accept_code);
|
||||
CANIDAR6 = CONVERT_STD_ID_TO_REG2(accept_code);
|
||||
CANIDAR7 = CONVERT_STD_ID_TO_REG3(accept_code);
|
||||
CANIDMR4 = CONVERT_STD_ID_TO_REG0(accept_mask);
|
||||
CANIDMR5 = CONVERT_STD_ID_TO_REG1(accept_mask) | (0x04 | 0x02 | 0x01);
|
||||
CANIDMR6 = CONVERT_STD_ID_TO_REG2(accept_mask);
|
||||
CANIDMR7 = CONVERT_STD_ID_TO_REG3(accept_mask);
|
||||
|
||||
/* leave initialization mode and synchronize to the CAN bus */
|
||||
CANCTL0_INITRQ = 0;
|
||||
/* wait for CAN bus synchronization handshake from the hardware */
|
||||
while ((CANCTL1 & CANCTL1_INITAK_MASK) != 0)
|
||||
{
|
||||
;
|
||||
}
|
||||
} /*** end of BootComCanInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Receives the CONNECT request from the host, which indicates that the
|
||||
** bootloader should be activated and, if so, activates it.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void BootComCanCheckActivationRequest(void)
|
||||
{
|
||||
unsigned long rxMsgId;
|
||||
|
||||
/* check if a new message was received */
|
||||
if ((CANRFLG & CANRFLG_RXF_MASK) == CANRFLG_RXF_MASK)
|
||||
{
|
||||
/* check IDE-bit to determine if it is a 11-bit or 29-bit identifier */
|
||||
if ((CANRXIDR1 & CANRXIDR1_IDE_MASK) == 0)
|
||||
{
|
||||
/* 11-bit id */
|
||||
rxMsgId = (*(unsigned short*)(&CANRXIDR0)) >> 5;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 29-bit id */
|
||||
rxMsgId = (unsigned long)(((*(unsigned long*)(&CANRXIDR0)) & 0x0007ffff) >> 1) |
|
||||
(unsigned long)(((*(unsigned long*)(&CANRXIDR0)) & 0xffe00000) >> 3);
|
||||
rxMsgId |= 0x80000000;
|
||||
}
|
||||
/* is this the packet identifier? */
|
||||
if (rxMsgId == BOOT_COM_CAN_RX_MSG_ID)
|
||||
{
|
||||
/* check if this was an XCP CONNECT command */
|
||||
if ( (CANRXDSR0 == 0xff) && (CANRXDSR1 == 0x00) )
|
||||
{
|
||||
/* release the receive object by clearing the rx flag */
|
||||
CANRFLG &= CANRFLG_RXF_MASK;
|
||||
/* connection request received so start the bootloader */
|
||||
BootActivate();
|
||||
}
|
||||
}
|
||||
/* release the receive object by clearing the rx flag */
|
||||
CANRFLG &= CANRFLG_RXF_MASK;
|
||||
}
|
||||
} /*** end of BootComCanCheckActivationRequest ***/
|
||||
#endif /* BOOT_COM_CAN_ENABLE > 0 */
|
||||
|
||||
|
||||
/*********************************** end of boot.c *************************************/
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/boot.h
|
||||
* \brief Demo program bootloader interface header file.
|
||||
* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef BOOT_H
|
||||
#define BOOT_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void BootComInit(void);
|
||||
void BootComCheckActivationRequest(void);
|
||||
void BootActivate(void);
|
||||
|
||||
|
||||
#endif /* BOOT_H */
|
||||
/*********************************** end of boot.h *************************************/
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
// ver 0.1 (09-Mar-08)
|
||||
// HCS12P Core erasing + unsecuring command file:
|
||||
// These commands mass erase the chip then program the security byte to 0xFE (unsecured state).
|
||||
|
||||
DEFINEVALUEDLG "Information required to unsecure the device" "FCLKDIV" 17 "To unsecure the device, the command script needs \nthe correct value for the FCLKDIV onchip register.\n\nDatasheet proposed values:\n\noscillator frequency\tFCLKDIV value (decimal)\n\n 16 \tMHz\t\t17\n 12 \tMHz\t\t13\n 8 \tMHz\t\t9\n 4 \tMHz\t\t5\n"
|
||||
|
||||
FLASH RELEASE
|
||||
|
||||
reset
|
||||
wb 0x03c 0x00 //disable cop
|
||||
wait 20
|
||||
|
||||
|
||||
WB 0x100 FCLKDIV // clock divider
|
||||
|
||||
WB 0x106 0x30 // clear any error flags
|
||||
WB 0x102 0x00 // CCOBIX = 0
|
||||
WB 0x10A 0x08 // load erase all blocks command
|
||||
WB 0x106 0x80 // launch command
|
||||
WAIT 10
|
||||
|
||||
reset
|
||||
|
||||
WB 0x100 FCLKDIV // clock divider
|
||||
WB 0x106 0x30 // clear any error flags
|
||||
WB 0x102 0x00 // CCOBIX = 0
|
||||
WB 0x10A 0x06 // load program command
|
||||
WB 0x10B 0x03 // load GPAGE
|
||||
WB 0x102 0x01 // CCOBIX = 1
|
||||
WB 0x10A 0xFF // load addr hi
|
||||
WB 0x10B 0x08 // load addr lo
|
||||
WB 0x102 0x02 // CCOBIX = 2
|
||||
WB 0x10A 0xFF // load data
|
||||
WB 0x10B 0xFF // load data
|
||||
WB 0x102 0x03 // CCOBIX = 3
|
||||
WB 0x10A 0xFF // load data
|
||||
WB 0x10B 0xFF // load data
|
||||
WB 0x102 0x04 // CCOBIX = 4
|
||||
WB 0x10A 0xFF // load data
|
||||
WB 0x10B 0xFF // load data
|
||||
WB 0x102 0x05 // CCOBIX = 5
|
||||
WB 0x10A 0xFF // load data
|
||||
WB 0x10B 0xFE // load data
|
||||
WB 0x106 0x80 // launch command
|
||||
WAIT 1
|
||||
|
||||
undef FCLKDIV // undefine variable
|
||||
|
|
@ -0,0 +1 @@
|
|||
// After load the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// Before load the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// After reset the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// At startup the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// After programming the flash, the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// Before programming the flash, the commands written below will be executed
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/* s-record file with linear addresses for MicroBoot/OpenBLT */
|
||||
OPENFILE "%ABS_FILE%.sx"
|
||||
format = motorola
|
||||
busWidth = 1
|
||||
len = 0x4000
|
||||
|
||||
/* logical non banked flash at $4000 and $C000 to physical */
|
||||
origin = 0x004000
|
||||
destination = 0x34000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x00C000
|
||||
destination = 0x3C000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
/* logical 128 kB banked flash to physical */
|
||||
origin = 0x088000
|
||||
destination = 0x020000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x098000
|
||||
destination = 0x024000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x0A8000
|
||||
destination = 0x028000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x0B8000
|
||||
destination = 0x02C000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x0C8000
|
||||
destination = 0x030000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x0D8000
|
||||
destination = 0x034000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x0E8000
|
||||
destination = 0x038000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x0F8000
|
||||
destination = 0x03C000
|
||||
len = 0x4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
CLOSE
|
||||
|
||||
|
|
@ -0,0 +1,482 @@
|
|||
/*****************************************************
|
||||
start12.c - standard startup code
|
||||
The startup code may be optimized to special user requests
|
||||
----------------------------------------------------
|
||||
Copyright (c) Metrowerks, Basel, Switzerland
|
||||
All rights reserved
|
||||
|
||||
Note: ROM libraries are not implemented in this startup code
|
||||
Note: C++ destructors of global objects are NOT yet supported in the HIWARE Object File Format.
|
||||
To use this feature, please build your application with the ELF object file format.
|
||||
*****************************************************/
|
||||
/* these macros remove some unused fields in the startup descriptor */
|
||||
#define __NO_FLAGS_OFFSET /* we do not need the flags field in the startup data descriptor */
|
||||
#define __NO_MAIN_OFFSET /* we do not need the main field in the startup data descriptor */
|
||||
#define __NO_STACKOFFSET_OFFSET /* we do not need the stackOffset field in the startup data descriptor */
|
||||
|
||||
/*#define __BANKED_COPY_DOWN : allow to allocate .copy in flash area */
|
||||
#if defined(__BANKED_COPY_DOWN) && (!defined(__HCS12X__) || !defined(__ELF_OBJECT_FILE_FORMAT__))
|
||||
#error /* the __BANKED_COPY_DOWN switch is only supported for the HCS12X with ELF */
|
||||
/* (and not for the HC12, HCS12 or for the HIWARE object file format) */
|
||||
#endif
|
||||
|
||||
#include "hidef.h"
|
||||
#include "start12.h"
|
||||
|
||||
/***************************************************************************/
|
||||
/* Macros to control how the startup code handles the COP: */
|
||||
/* #define _DO_FEED_COP_ : do feed the COP */
|
||||
/* #define _DO_ENABLE_COP_: do enable the COP */
|
||||
/* #define _DO_DISABLE_COP_: disable the COP */
|
||||
/* Without defining any of these, the startup code does NOT handle the COP */
|
||||
/***************************************************************************/
|
||||
/* __ONLY_INIT_SP define: */
|
||||
/* This define selects an shorter version of the startup code */
|
||||
/* which only loads the stack pointer and directly afterwards calls */
|
||||
/* main. This version does however NOT initialized global variables */
|
||||
/* (So this version is not ANSI compliant!) */
|
||||
/***************************************************************************/
|
||||
/* __FAR_DATA define: */
|
||||
/* By default, the startup code only supports to initialize the default */
|
||||
/* kind of memory. If some memory is allocated far in the small or banked */
|
||||
/* memory model, then the startup code only supports to initialize this */
|
||||
/* memory blocks if __FAR_DATA is defined. If __FAR_DATA is not defined, */
|
||||
/* then the linker will issue a message like */
|
||||
/* "L1128: Cutting value _Range beg data member from 0xF01000 to 0x1000" */
|
||||
/* and this startup code writes to the cutted address */
|
||||
/***************************************************************************/
|
||||
/* __BANKED_COPY_DOWN define: */
|
||||
/* by default, the startup code assumes that the startup data structure */
|
||||
/* _startupData, the zero out areas and the .copy section are all */
|
||||
/* allocated in NON_BANKED memory. Especially the .copy section can be */
|
||||
/* huge if there are many or huge RAM areas to initialize. */
|
||||
/* For the HCS12X, which also copies the XGATE RAM located code via .copy */
|
||||
/* section, the startup code supports to allocate .copy in a banked flash */
|
||||
/* The placement of .copy in the prm file has to be adapted when adding or */
|
||||
/* removing the this macro. */
|
||||
/* Note: This macro is only supported for the HCS12X and when using ELF */
|
||||
/***************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define __EXTERN_C extern "C"
|
||||
#else
|
||||
#define __EXTERN_C
|
||||
#endif
|
||||
|
||||
/*lint -estring(961,"only preprocessor statements and comments before '#include'") , MISRA 19.1 ADV, non_bank.sgm and default.sgm each contain a conditionally compiled CODE_SEG pragma */
|
||||
|
||||
__EXTERN_C void main(void); /* prototype of main function */
|
||||
|
||||
#ifndef __ONLY_INIT_SP
|
||||
#pragma DATA_SEG __NEAR_SEG STARTUP_DATA /* _startupData can be accessed using 16 bit accesses. */
|
||||
/* This is needed because it contains the stack top, and without stack, far data cannot be accessed */
|
||||
struct _tagStartup _startupData; /* read-only: */
|
||||
/* _startupData is allocated in ROM and */
|
||||
/* initialized by the linker */
|
||||
#pragma DATA_SEG DEFAULT
|
||||
#endif /* __ONLY_INIT_SP */
|
||||
|
||||
#if defined(FAR_DATA) && (!defined(__HCS12X__) || defined(__BANKED_COPY_DOWN))
|
||||
/*lint -e451 non_bank.sgm contains a conditionally compiled CODE_SEG pragma */
|
||||
#include "non_bank.sgm"
|
||||
/*lint +e451 */
|
||||
|
||||
/* the init function must be in non banked memory if banked variables are used */
|
||||
/* because _SET_PAGE is called, which may change any page register. */
|
||||
|
||||
/*lint -esym(752,_SET_PAGE) , symbol '_SET_PAGE' is referenced in HLI */
|
||||
__EXTERN_C void _SET_PAGE(void); /* the inline assembler needs a prototype */
|
||||
/* this is a runtime routine with a special */
|
||||
/* calling convention, do not use it in c code! */
|
||||
#else
|
||||
/*lint -e451 default.sgm contains a conditionally compiled CODE_SEG pragma */
|
||||
#include "default.sgm"
|
||||
/*lint +e451 */
|
||||
#endif /* defined(FAR_DATA) && (!defined(__HCS12X__) || defined(__BANKED_COPY_DOWN)) */
|
||||
|
||||
|
||||
/* define value and bits for Windef Register */
|
||||
#ifdef HC812A4
|
||||
#define WINDEF (*(volatile unsigned char*) 0x37)
|
||||
#if defined( __BANKED__) || defined(__LARGE__) || defined(__PPAGE__)
|
||||
#define __ENABLE_PPAGE__ 0x40
|
||||
#else
|
||||
#define __ENABLE_PPAGE__ 0x0
|
||||
#endif
|
||||
#if defined(__DPAGE__)
|
||||
#define __ENABLE_DPAGE__ 0x80
|
||||
#else
|
||||
#define __ENABLE_DPAGE__ 0x0
|
||||
#endif
|
||||
#if defined(__EPAGE__)
|
||||
#define __ENABLE_EPAGE__ 0x20
|
||||
#else
|
||||
#define __ENABLE_EPAGE__ 0x0
|
||||
#endif
|
||||
#endif /* HC812A4 */
|
||||
|
||||
#ifdef _HCS12_SERIALMON
|
||||
/* for Monitor based software remap the RAM & EEPROM to adhere
|
||||
to EB386. Edit RAM and EEPROM sections in PRM file to match these. */
|
||||
#define ___INITRM (*(volatile unsigned char *) 0x0010)
|
||||
#define ___INITRG (*(volatile unsigned char *) 0x0011)
|
||||
#define ___INITEE (*(volatile unsigned char *) 0x0012)
|
||||
#endif
|
||||
|
||||
#if defined(_DO_FEED_COP_)
|
||||
#define __FEED_COP_IN_HLI() } asm movb #0x55, _COP_RST_ADR; asm movb #0xAA, _COP_RST_ADR; asm {
|
||||
#else
|
||||
#define __FEED_COP_IN_HLI() /* do nothing */
|
||||
#endif
|
||||
|
||||
#ifndef __ONLY_INIT_SP
|
||||
#if (!defined(FAR_DATA) || defined(__HCS12X__)) && (defined( __BANKED__) || defined(__LARGE__) || defined(__BANKED_COPY_DOWN))
|
||||
static void __far Init(void)
|
||||
#else
|
||||
static void Init(void)
|
||||
#endif
|
||||
{
|
||||
/* purpose: 1) zero out RAM-areas where data is allocated */
|
||||
/* 2) copy initialization data from ROM to RAM */
|
||||
/* 3) call global constructors in C++ */
|
||||
/* called from: _Startup, LibInits */
|
||||
asm {
|
||||
ZeroOut:
|
||||
#if defined(__HIWARE_OBJECT_FILE_FORMAT__) && defined(__LARGE__)
|
||||
LDX _startupData.pZeroOut:1 ; in the large memory model in the HIWARE format, pZeroOut is a 24 bit pointer
|
||||
#else
|
||||
LDX _startupData.pZeroOut ; *pZeroOut
|
||||
#endif
|
||||
LDY _startupData.nofZeroOuts ; nofZeroOuts
|
||||
BEQ CopyDown ; if nothing to zero out
|
||||
|
||||
NextZeroOut: PSHY ; save nofZeroOuts
|
||||
#if defined(FAR_DATA)
|
||||
LDAB 1,X+ ; load page of destination address
|
||||
LDY 2,X+ ; load offset of destination address
|
||||
#if defined(__HCS12X__)
|
||||
STAB __GPAGE_ADR__
|
||||
#else /* defined(__HCS12X__) */
|
||||
__PIC_JSR(_SET_PAGE) ; sets the page in the correct page register
|
||||
#endif /* defined(__HCS12X__) */
|
||||
#else /* FAR_DATA */
|
||||
LDY 2,X+ ; start address and advance *pZeroOut (X = X+4)
|
||||
#endif /* FAR_DATA */
|
||||
|
||||
#if defined(__HCS12X__) && defined(FAR_DATA)
|
||||
PSHX
|
||||
LDX 0,X ; byte count
|
||||
#if defined(__OPTIMIZE_FOR_SIZE__)
|
||||
CLRA
|
||||
NextWord: GSTAA 1,Y+ ; clear memory byte
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE X, NextWord ; dec byte count
|
||||
#else
|
||||
LDD #0
|
||||
LSRX
|
||||
BEQ LoopClrW1 ; do we copy more than 1 byte?
|
||||
NextWord: GSTD 2,Y+ ; clear memory word
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE X, NextWord ; dec word count
|
||||
LoopClrW1:
|
||||
BCC LastClr ; handle last byte
|
||||
GSTAA 1,Y+ ; handle last byte
|
||||
LastClr:
|
||||
#endif
|
||||
PULX
|
||||
LEAX 2,X
|
||||
#elif defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */
|
||||
LDD 2,X+ ; byte count
|
||||
NextWord: CLR 1,Y+ ; clear memory byte
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D, NextWord ; dec byte count
|
||||
#else /* __OPTIMIZE_FOR_TIME__ */
|
||||
LDD 2,X+ ; byte count
|
||||
LSRD ; /2 and save bit 0 in the carry
|
||||
BEQ LoopClrW1 ; do we copy more than 1 byte?
|
||||
PSHX
|
||||
LDX #0
|
||||
LoopClrW: STX 2,Y+ ; Word-Clear
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D, LoopClrW
|
||||
PULX
|
||||
LoopClrW1:
|
||||
BCC LastClr ; handle last byte
|
||||
CLR 1,Y+
|
||||
LastClr:
|
||||
#endif /* __OPTIMIZE_FOR_SIZE__/__OPTIMIZE_FOR_TIME__ */
|
||||
PULY ; restore nofZeroOuts
|
||||
DEY ; dec nofZeroOuts
|
||||
BNE NextZeroOut
|
||||
CopyDown:
|
||||
#if defined(__BANKED_COPY_DOWN)
|
||||
LDAA _startupData.toCopyDownBeg:0 ; get PAGE address of .copy section
|
||||
STAA __PPAGE_ADR__ ; set PPAGE address
|
||||
LDX _startupData.toCopyDownBeg:1 ; load address of copy down desc.
|
||||
#elif defined(__ELF_OBJECT_FILE_FORMAT__)
|
||||
LDX _startupData.toCopyDownBeg ; load address of copy down desc.
|
||||
#else
|
||||
LDX _startupData.toCopyDownBeg:2 ; load address of copy down desc.
|
||||
#endif
|
||||
NextBlock:
|
||||
LDD 2,X+ ; size of init-data -> D
|
||||
BEQ funcInits ; end of copy down desc.
|
||||
#ifdef FAR_DATA
|
||||
PSHD ; save counter
|
||||
LDAB 1,X+ ; load destination page
|
||||
LDY 2,X+ ; destination address
|
||||
#if defined(__HCS12X__)
|
||||
STAB __GPAGE_ADR__
|
||||
#else /* __HCS12X__ */
|
||||
__PIC_JSR(_SET_PAGE) ; sets the destinations page register
|
||||
#endif /* __HCS12X__ */
|
||||
PULD ; restore counter
|
||||
#else /* FAR_DATA */
|
||||
LDY 2,X+ ; load destination address
|
||||
#endif /* FAR_DATA */
|
||||
|
||||
#if defined(__HCS12X__) && defined(FAR_DATA)
|
||||
#if defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */
|
||||
Copy: PSHA
|
||||
LDAA 1,X+
|
||||
GSTAA 1,Y+ ; move a byte from ROM to the data area
|
||||
PULA
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D,Copy ; copy-byte loop
|
||||
#else
|
||||
LSRD ; /2 and save bit 0 in the carry
|
||||
BEQ Copy1 ; do we copy more than 1 byte?
|
||||
|
||||
Copy: PSHD
|
||||
LDD 2,X+
|
||||
GSTD 2,Y+ ; move a word from ROM to the data area
|
||||
PULD
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D,Copy ; copy-word loop
|
||||
Copy1:
|
||||
BCC NextBlock ; handle last byte?
|
||||
LDAA 1,X+
|
||||
GSTAA 1,Y+ ; move a byte from ROM to the data area
|
||||
#endif
|
||||
#elif defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */
|
||||
Copy: MOVB 1,X+,1,Y+ ; move a byte from ROM to the data area
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D,Copy ; copy-byte loop
|
||||
#else /* __OPTIMIZE_FOR_TIME__ */
|
||||
LSRD ; /2 and save bit 0 in the carry
|
||||
BEQ Copy1 ; do we copy more than 1 byte?
|
||||
Copy: MOVW 2,X+,2,Y+ ; move a word from ROM to the data area
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D,Copy ; copy-word loop
|
||||
Copy1:
|
||||
BCC NextBlock ; handle last byte?
|
||||
MOVB 1,X+,1,Y+ ; copy the last byte
|
||||
#endif /* __OPTIMIZE_FOR_SIZE__/__OPTIMIZE_FOR_TIME__ */
|
||||
BRA NextBlock
|
||||
funcInits: ; call of global construtors is only in c++ necessary
|
||||
#if defined(__cplusplus)
|
||||
#if defined(__ELF_OBJECT_FILE_FORMAT__)
|
||||
#if defined( __BANKED__) || defined(__LARGE__)
|
||||
LDY _startupData.nofInitBodies; load number of cpp.
|
||||
BEQ done ; if cppcount == 0, goto done
|
||||
LDX _startupData.initBodies ; load address of first module to initialize
|
||||
nextInit:
|
||||
LEAX 3,X ; increment to next init
|
||||
PSHX ; save address of next function to initialize
|
||||
PSHY ; save cpp counter
|
||||
CALL [-3,X] ; use double indirect call to load the page register also
|
||||
PULY ; restore cpp counter
|
||||
PULX ; restore actual address
|
||||
DEY ; decrement cpp counter
|
||||
BNE nextInit
|
||||
#else /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
|
||||
LDD _startupData.nofInitBodies; load number of cpp.
|
||||
BEQ done ; if cppcount == 0, goto done
|
||||
LDX _startupData.initBodies ; load address of first module to initialize
|
||||
nextInit:
|
||||
LDY 2,X+ ; load address of first module to initialize
|
||||
PSHD
|
||||
PSHX ; save actual address
|
||||
JSR 0,Y ; call initialization function
|
||||
PULX ; restore actual address
|
||||
PULD ; restore cpp counter
|
||||
DBNE D, nextInit
|
||||
#endif /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
#else /* __ELF_OBJECT_FILE_FORMAT__ */
|
||||
LDX _startupData.mInits ; load address of first module to initialize
|
||||
#if defined( __BANKED__) || defined(__LARGE__)
|
||||
nextInit: LDY 3,X+ ; load address of initialization function
|
||||
BEQ done ; stop when address == 0
|
||||
; in common environments the offset of a function is never 0, so this test could be avoided
|
||||
#ifdef __InitFunctionsMayHaveOffset0__
|
||||
BRCLR -1,X, done, 0xff ; stop when address == 0
|
||||
#endif /* __InitFunctionsMayHaveOffset0__ */
|
||||
PSHX ; save address of next function to initialize
|
||||
CALL [-3,X] ; use double indirect call to load the page register also
|
||||
#else /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
nextInit:
|
||||
LDY 2,X+ ; load address of first module to initialize
|
||||
BEQ done ; stop when address of function == 0
|
||||
PSHX ; save actual address
|
||||
JSR 0,Y ; call initialization function
|
||||
#endif /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
PULX ; restore actual address
|
||||
BRA nextInit
|
||||
#endif /* __ELF_OBJECT_FILE_FORMAT__ */
|
||||
done:
|
||||
#endif /* __cplusplus */
|
||||
}
|
||||
}
|
||||
#endif /* __ONLY_INIT_SP */
|
||||
|
||||
#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) && 0 /* the call to main does not support to return anymore */
|
||||
|
||||
#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__))
|
||||
static void __far Fini(void)
|
||||
#else
|
||||
static void Fini(void)
|
||||
#endif
|
||||
{
|
||||
/* purpose: 1) call global destructors in C++ */
|
||||
asm {
|
||||
#if defined( __BANKED__) || defined(__LARGE__)
|
||||
|
||||
LDY _startupData.nofFiniBodies; load number of cpp.
|
||||
BEQ done ; if cppcount == 0, goto done
|
||||
LDX _startupData.finiBodies ; load address of first module to finalize
|
||||
nextInit2:
|
||||
LEAX 3,X ; increment to next init
|
||||
PSHX ; save address of next function to finalize
|
||||
PSHY ; save cpp counter
|
||||
CALL [-3,X] ; use double indirect call to load the page register also
|
||||
PULY ; restore cpp counter
|
||||
PULX ; restore actual address
|
||||
DEY ; decrement cpp counter
|
||||
BNE nextInit2
|
||||
#else /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
|
||||
LDD _startupData.nofFiniBodies; load number of cpp.
|
||||
BEQ done ; if cppcount == 0, goto done
|
||||
LDX _startupData.finiBodies ; load address of first module to finalize
|
||||
nextInit2:
|
||||
LDY 2,X+ ; load address of first module to finalize
|
||||
PSHD
|
||||
PSHX ; save actual address
|
||||
JSR 0,Y ; call finalize function
|
||||
PULX ; restore actual address
|
||||
PULD ; restore cpp counter
|
||||
DBNE D, nextInit2
|
||||
#endif /* defined(__BANKED__) || defined(__LARGE__) */
|
||||
done:;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*lint -e451 non_bank.sgm contains a conditionally compiled CODE_SEG pragma */
|
||||
#include "non_bank.sgm"
|
||||
/*lint +e451 */
|
||||
|
||||
#pragma MESSAGE DISABLE C12053 /* Stack-pointer change not in debugging-information */
|
||||
#pragma NO_FRAME
|
||||
#pragma NO_ENTRY
|
||||
#if !defined(__SMALL__)
|
||||
#pragma NO_EXIT
|
||||
#endif
|
||||
|
||||
/* The function _Startup must be called in order to initialize global variables and to call main */
|
||||
/* You can adapt this function or call it from your startup code to implement a different startup */
|
||||
/* functionality. */
|
||||
|
||||
/* You should also setup the needed IO registers as WINDEF (HC12A4 only) or the COP registers to run */
|
||||
/* on hardware */
|
||||
|
||||
/* to set the reset vector several ways are possible : */
|
||||
/* 1. define the function with "interrupt 0" as done below in the first case */
|
||||
/* 2. add the following line to your prm file : VECTOR ADDRESS 0xfffe _Startup */
|
||||
/* of course, even more posibilities exists */
|
||||
/* the reset vector must be set so that the application has a defined entry point */
|
||||
|
||||
#if defined(__SET_RESET_VECTOR__)
|
||||
__EXTERN_C void __interrupt 0 _Startup(void) {
|
||||
#else
|
||||
__EXTERN_C void _Startup(void) {
|
||||
#endif
|
||||
/* purpose: 1) initialize the stack
|
||||
2) initialize the RAM, copy down init data etc (Init)
|
||||
3) call main;
|
||||
parameters: NONE
|
||||
called from: _PRESTART-code generated by the Linker
|
||||
or directly referenced by the reset vector */
|
||||
|
||||
/* initialize the stack pointer */
|
||||
/*lint -e{960} , MISRA 14.3 REQ, macro INIT_SP_FROM_STARTUP_DESC() expands to HLI code */
|
||||
/*lint -e{522} , MISRA 14.2 REQ, macro INIT_SP_FROM_STARTUP_DESC() expands to HLI code */
|
||||
INIT_SP_FROM_STARTUP_DESC(); /* HLI macro definition in hidef.h */
|
||||
#if defined(_HCS12_SERIALMON)
|
||||
/* for Monitor based software remap the RAM & EEPROM to adhere
|
||||
to EB386. Edit RAM and EEPROM sections in PRM file to match these. */
|
||||
___INITRG = 0x00; /* lock registers block to 0x0000 */
|
||||
___INITRM = 0x39; /* lock Ram to end at 0x3FFF */
|
||||
___INITEE = 0x09; /* lock EEPROM block to end at 0x0fff */
|
||||
#endif
|
||||
|
||||
/* Here user defined code could be inserted, the stack could be used */
|
||||
#if defined(_DO_DISABLE_COP_)
|
||||
_DISABLE_COP();
|
||||
#endif
|
||||
|
||||
/* Example : Set up WinDef Register to allow Paging */
|
||||
#ifdef HC812A4 /* HC12 A4 derivative needs WINDEF to configure which pages are available */
|
||||
#if (__ENABLE_EPAGE__ != 0 || __ENABLE_DPAGE__ != 0 || __ENABLE_PPAGE__ != 0)
|
||||
WINDEF= __ENABLE_EPAGE__ | __ENABLE_DPAGE__ | __ENABLE_PPAGE__;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(__MAP_RAM__) || defined(__MAP_FLASH__) || defined(__MAP_EXTERNAL__)) && !defined(__DO_SET_MMCTL1__)
|
||||
#define __DO_SET_MMCTL1__
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__DO_SET_MMCTL1__)
|
||||
/* Set the MMCTL1 byte. Please use for HCS12XE and change the bits according */
|
||||
/* to your configuration. */
|
||||
/* Note: MMCTL1 is write once therefore please adapt this initialization here. */
|
||||
/* This has to be done prior to the call to Init. */
|
||||
#define _MMCTL1_ADR (0x00000013)
|
||||
#define _MMCTL1_BIT_TGMRAMON (1<<7) /* EEE Tag RAM and FTM SCRATCH RAM visible in the memory map */
|
||||
#define _MMCTL1_BIT_EEEIFRON (1<<5) /* EEE IFR visible in the memory map */
|
||||
#define _MMCTL1_BIT_PGMIFRON (1<<4) /* Program IFR visible in the memory map */
|
||||
#define _MMCTL1_BIT_RAMHM (1<<3) /* RAM only in the higher half of the memory map */
|
||||
#define _MMCTL1_BIT_EROMON (1<<2) /* Enables emulated Flash or ROM memory in the memory map */
|
||||
#define _MMCTL1_BIT_ROMHM (1<<1) /* FLASH or ROM only in higher Half of Memory Map */
|
||||
#define _MMCTL1_BIT_ROMON (1<<0) /* Enable FLASH or ROM in the memory map */
|
||||
|
||||
#define _MMCTL1_SET(value) ((*(volatile unsigned char*)_MMCTL1_ADR)= (value))
|
||||
|
||||
#if defined(__MAP_FLASH__)
|
||||
_MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON);
|
||||
#elif defined(__MAP_EXTERNAL__)
|
||||
_MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON | _MMCTL1_BIT_ROMHM);
|
||||
#else /* RAM */
|
||||
_MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON | _MMCTL1_BIT_RAMHM | _MMCTL1_BIT_ROMHM);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __ONLY_INIT_SP
|
||||
/*lint -e{522} , MISRA 14.2 REQ, function Init() contains HLI only */
|
||||
Init(); /* zero out, copy down, call constructors */
|
||||
#endif
|
||||
|
||||
/* Here user defined code could be inserted, all global variables are initilized */
|
||||
#if defined(_DO_ENABLE_COP_)
|
||||
_ENABLE_COP(1);
|
||||
#endif
|
||||
|
||||
/* call main() */
|
||||
main();
|
||||
}
|
||||
|
||||
/*lint --e{766} , non_bank.sgm is not a regular header file, it contains a conditionally compiled CODE_SEG pragma */
|
||||
/*lint +estring(961,"only preprocessor statements and comments before '#include'") */
|
||||
/*lint +e451 */
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo/HCS12_DevKit_S12G128_CodeWarrior/Prog/header.h
|
||||
* \brief Generic header file.
|
||||
* \ingroup Prog_HCS12_DevKit_S12G128_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2018 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef HEADER_H
|
||||
#define HEADER_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Defines
|
||||
****************************************************************************************/
|
||||
/** \brief Configuration switch to enable programming and debugging with a BDM
|
||||
* interface.
|
||||
* \details To configure the program for downloading with the OpenBLT bootloader, set
|
||||
* this value to 0. This is typically done for release versions. If support
|
||||
* for programming and debugging with a BDM debugger interface is desired
|
||||
* during development, then set this value to 1.
|
||||
*/
|
||||
#define BDM_DEBUGGING_ENABLED (0)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include <hidef.h> /* common defines and macros */
|
||||
#include "../Boot/blt_conf.h" /* bootloader configuration */
|
||||
#include "boot.h" /* bootloader interface driver */
|
||||
#include "led.h" /* LED driver */
|
||||
#include "timer.h" /* Timer driver */
|
||||
#include "derivative.h" /* MCU registers */
|
||||
|
||||
|
||||
#endif /* HEADER_H */
|
||||
/*********************************** end of header.h ***********************************/
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
OPEN source 0 0 60 39
|
||||
Source < attributes MARKS off
|
||||
OPEN assembly 60 0 40 31
|
||||
Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C
|
||||
OPEN procedure 0 39 60 17
|
||||
Procedure < attributes VALUES on,TYPES off
|
||||
OPEN register 60 31 40 25
|
||||
Register < attributes FORMAT AUTO,COMPLEMENT None
|
||||
OPEN memory 60 56 40 22
|
||||
Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80
|
||||
OPEN data 0 56 60 22
|
||||
Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16
|
||||
OPEN data 0 78 60 22
|
||||
Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16
|
||||
OPEN command 60 78 40 22
|
||||
Command < attributes CACHESIZE 1000
|
||||
bckcolor 50331647
|
||||
font 'Courier New' 9 BLACK
|
||||
AUTOSIZE on
|
||||
ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory
|
||||
Binary file not shown.
|
|
@ -0,0 +1,80 @@
|
|||
[STARTUP]
|
||||
CPUTARGETTYPE=0
|
||||
USE_CYCLONEPRO_RELAYS=0
|
||||
PORT=21
|
||||
interface_selection=1
|
||||
SHOWDIALOG=0
|
||||
IO_DELAY_SET=1
|
||||
frequency_has_changed_old_io_delay_cnt=7
|
||||
CyclonePro_poweroffonexit=0
|
||||
CyclonePro_currentvoltage=255
|
||||
CyclonePro_PowerDownDelay=250
|
||||
CyclonePro_PowerUpDelay=250
|
||||
IO_DELAY_CNT=7
|
||||
PCI_DELAY=0
|
||||
RESET_DELAY=0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
[Environment Variables]
|
||||
GENPATH={Project}..\src;{Compiler}lib\hc12c\src;{Compiler}lib\hc12c\include;{Compiler}lib\hc12c\lib;{Compiler}lib\xgatec\src;{Compiler}lib\xgatec\include;{Compiler}lib\xgatec\lib
|
||||
LIBPATH={Compiler}lib\hc12c\include;{Compiler}lib\xgatec\include
|
||||
OBJPATH={Project}..\bin
|
||||
TEXTPATH={Project}..\bin
|
||||
ABSPATH={Project}..\bin
|
||||
|
||||
[HI-WAVE]
|
||||
Target=icd12
|
||||
Layout=C_layout.hwl
|
||||
LoadDialogOptions=AUTOERASEANDFLASH RUNANDSTOPAFTERLOAD="main"
|
||||
CPU=HC12
|
||||
AEFWarningDialog=FALSE
|
||||
MainFrame=2,3,-1,-1,-1,-1,234,234,1674,1001
|
||||
TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806
|
||||
|
||||
|
||||
|
||||
|
||||
[HC12MultilinkCyclonePro_GDI_SETTINGS]
|
||||
CMDFILE0=CMDFILE STARTUP ON ".\..\cmd\P&E_Multilink_USB_startup.cmd"
|
||||
CMDFILE1=CMDFILE RESET ON ".\..\cmd\P&E_Multilink_USB_reset.cmd"
|
||||
CMDFILE2=CMDFILE PRELOAD ON ".\..\cmd\P&E_Multilink_USB_preload.cmd"
|
||||
CMDFILE3=CMDFILE POSTLOAD ON ".\..\cmd\P&E_Multilink_USB_postload.cmd"
|
||||
CMDFILE4=CMDFILE VPPON ON ".\..\cmd\P&E_Multilink_USB_vppon.cmd"
|
||||
CMDFILE5=CMDFILE VPPOFF ON ".\..\cmd\P&E_Multilink_USB_vppoff.cmd"
|
||||
CMDFILE6=CMDFILE UNSECURE ON ".\..\cmd\P&E_Multilink_USB_erase_unsecure_hcs12p.cmd"
|
||||
MCUID=0x01C2
|
||||
CHIPSECURE=CHIPSECURE SETUP 0xFF0F 0x3 0x2
|
||||
DBG0=DBG GENERAL DISARM_ON PROTECT_OFF ANALYZE_ON STEPATRUN_ON
|
||||
DBG1=DBG PREDEFINED SELECT 0
|
||||
DBG2=DBG PREDEFINED DBGENGINE TRACE ENABLE RECORDAFTER PUREPC
|
||||
NV_PARAMETER_FILE=C:\Program Files (x86)\Freescale\CWS12v5.1\prog\FPP\mcu01C2.fpp
|
||||
NV_SAVE_WSP=0
|
||||
NV_AUTO_ID=1
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
[ICD12]
|
||||
COMSETTINGS=SETCOMM DRIVER NOPROTOCOL NOPERIODICAL
|
||||
SETCLKSW=0
|
||||
HOTPLUGGING=0
|
||||
DETECTRUNNING=0
|
||||
RESYNCONCOPRESET=0
|
||||
BDMAutoSpeed=0
|
||||
BDMClockSpeed=7
|
||||
HIGHIODELAYCONSTFORPLL=40
|
||||
|
||||
[PORT]
|
||||
IP=
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,97 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo/HCS12_DevKit_S12G128_CodeWarrior/Prog/led.c
|
||||
* \brief LED driver source file.
|
||||
* \ingroup Prog_HCS12_DevKit_S12G128_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2018 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Toggle interval time in milliseconds. */
|
||||
#define LED_TOGGLE_MS (500)
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the LED.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void LedInit(void)
|
||||
{
|
||||
/* disable pull device for PP6 */
|
||||
PERP_PERP6 = 0;
|
||||
/* configure PP6 as a digital output */
|
||||
DDRP_DDRP6 = 1;
|
||||
/* turn off the LED by default */
|
||||
PTP_PTP6 = 1;
|
||||
} /*** end of LedInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Toggles the LED at a fixed time interval.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void LedToggle(void)
|
||||
{
|
||||
static unsigned char led_toggle_state = 0;
|
||||
static unsigned long timer_counter_last = 0;
|
||||
unsigned long timer_counter_now;
|
||||
|
||||
/* check if toggle interval time passed */
|
||||
timer_counter_now = TimerGet();
|
||||
if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS)
|
||||
{
|
||||
/* not yet time to toggle */
|
||||
return;
|
||||
}
|
||||
|
||||
/* determine toggle action */
|
||||
if (led_toggle_state == 0)
|
||||
{
|
||||
led_toggle_state = 1;
|
||||
/* turn the LED on */
|
||||
PTP_PTP6 = 0;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
led_toggle_state = 0;
|
||||
/* turn the LED off */
|
||||
PTP_PTP6 = 1;
|
||||
}
|
||||
|
||||
/* store toggle time to determine next toggle interval */
|
||||
timer_counter_last = timer_counter_now;
|
||||
} /*** end of LedToggle ***/
|
||||
|
||||
|
||||
/*********************************** end of led.c **************************************/
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo/HCS12_DevKit_S12G128_CodeWarrior/Prog/led.h
|
||||
* \brief LED driver header file.
|
||||
* \ingroup Prog_HCS12_DevKit_S12G128_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2018 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef LED_H
|
||||
#define LED_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void LedInit(void);
|
||||
void LedToggle(void);
|
||||
|
||||
|
||||
#endif /* LED_H */
|
||||
/*********************************** end of led.h **************************************/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Note: This file is recreated by the project wizard whenever the MCU is
|
||||
* changed and should not be edited by hand
|
||||
*/
|
||||
|
||||
/* Include the derivative-specific header file */
|
||||
#include <mc9s12g128.h>
|
||||
|
||||
#pragma LINK_INFO DERIVATIVE "mc9s12g128"
|
||||
|
||||
|
|
@ -0,0 +1,287 @@
|
|||
/* Based on CPU DB MC9S12G128_100, version 3.00.001 (RegistersPrg V2.32) */
|
||||
/* DataSheet : MC9S12GRMV1 Rev. 0.29 April 20, 2010 */
|
||||
|
||||
#include <mc9s12g128.h>
|
||||
|
||||
/*lint -save -esym(765, *) */
|
||||
|
||||
|
||||
/* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */
|
||||
volatile PORTESTR _PORTE; /* Port E Data Register; 0x00000008 */
|
||||
volatile DDRESTR _DDRE; /* Port E Data Direction Register; 0x00000009 */
|
||||
volatile MODESTR _MODE; /* Mode Register; 0x0000000B */
|
||||
volatile PUCRSTR _PUCR; /* Pull-Up Control Register; 0x0000000C */
|
||||
volatile DIRECTSTR _DIRECT; /* Direct Page Register; 0x00000011 */
|
||||
volatile MMCCTL1STR _MMCCTL1; /* MMC Control Register; 0x00000013 */
|
||||
volatile PPAGESTR _PPAGE; /* Program Page Index Register; 0x00000015 */
|
||||
volatile ECLKCTLSTR _ECLKCTL; /* ECLK Control Register; 0x0000001C */
|
||||
volatile IRQCRSTR _IRQCR; /* Interrupt Control Register; 0x0000001E */
|
||||
volatile DBGC1STR _DBGC1; /* Debug Control Register 1; 0x00000020 */
|
||||
volatile DBGSRSTR _DBGSR; /* Debug Status Register; 0x00000021 */
|
||||
volatile DBGTCRSTR _DBGTCR; /* Debug Trace Control Register; 0x00000022 */
|
||||
volatile DBGC2STR _DBGC2; /* Debug Control Register 2; 0x00000023 */
|
||||
volatile DBGCNTSTR _DBGCNT; /* Debug Count Register; 0x00000026 */
|
||||
volatile DBGSCRXSTR _DBGSCRX; /* Debug State Control Register; 0x00000027 */
|
||||
volatile DBGXCTLSTR _DBGXCTL; /* Debug Comparator Control Register; 0x00000028 */
|
||||
volatile DBGXAHSTR _DBGXAH; /* Debug Comparator Address High Register; 0x00000029 */
|
||||
volatile DBGXAMSTR _DBGXAM; /* Debug Comparator Address Mid Register; 0x0000002A */
|
||||
volatile DBGXALSTR _DBGXAL; /* Debug Comparator Address Low Register; 0x0000002B */
|
||||
volatile DBGADHSTR _DBGADH; /* Debug Comparator Data High Register; 0x0000002C */
|
||||
volatile DBGADLSTR _DBGADL; /* Debug Comparator Data Low Register; 0x0000002D */
|
||||
volatile DBGADHMSTR _DBGADHM; /* Debug Comparator Data High Mask Register; 0x0000002E */
|
||||
volatile DBGADLMSTR _DBGADLM; /* Debug Comparator Data Low Mask Register; 0x0000002F */
|
||||
volatile CPMUSYNRSTR _CPMUSYNR; /* S12CPMU Synthesizer Register; 0x00000034 */
|
||||
volatile CPMUREFDIVSTR _CPMUREFDIV; /* S12CPMU Reference Divider Register; 0x00000035 */
|
||||
volatile CPMUPOSTDIVSTR _CPMUPOSTDIV; /* S12CPMU Post Divider Register; 0x00000036 */
|
||||
volatile CPMUFLGSTR _CPMUFLG; /* S12CPMU Flags Register; 0x00000037 */
|
||||
volatile CPMUINTSTR _CPMUINT; /* S12CPMU Interrupt Enable Register; 0x00000038 */
|
||||
volatile CPMUCLKSSTR _CPMUCLKS; /* S12CPMU Clock Select Register; 0x00000039 */
|
||||
volatile CPMUPLLSTR _CPMUPLL; /* S12CPMU PLL Control Register; 0x0000003A */
|
||||
volatile CPMURTISTR _CPMURTI; /* CPMU RTI Control Register; 0x0000003B */
|
||||
volatile CPMUCOPSTR _CPMUCOP; /* CPMU COP Control Register; 0x0000003C */
|
||||
volatile CPMUARMCOPSTR _CPMUARMCOP; /* CPMU COP Timer Arm/Reset Register; 0x0000003F */
|
||||
volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select; 0x00000040 */
|
||||
volatile CFORCSTR _CFORC; /* Timer Compare Force Register; 0x00000041 */
|
||||
volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register; 0x00000042 */
|
||||
volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register; 0x00000043 */
|
||||
volatile TSCR1STR _TSCR1; /* Timer System Control Register1; 0x00000046 */
|
||||
volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register; 0x00000047 */
|
||||
volatile TCTL1STR _TCTL1; /* Timer Control Register 1; 0x00000048 */
|
||||
volatile TCTL2STR _TCTL2; /* Timer Control Register 2; 0x00000049 */
|
||||
volatile TCTL3STR _TCTL3; /* Timer Control Register 3; 0x0000004A */
|
||||
volatile TCTL4STR _TCTL4; /* Timer Control Register 4; 0x0000004B */
|
||||
volatile TIESTR _TIE; /* Timer Interrupt Enable Register; 0x0000004C */
|
||||
volatile TSCR2STR _TSCR2; /* Timer System Control Register 2; 0x0000004D */
|
||||
volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1; 0x0000004E */
|
||||
volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2; 0x0000004F */
|
||||
volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register; 0x00000060 */
|
||||
volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register; 0x00000061 */
|
||||
volatile OCPDSTR _OCPD; /* Output Compare Pin Disconnect Register; 0x0000006C */
|
||||
volatile PTPSRSTR _PTPSR; /* Precision Timer Prescaler Select Register; 0x0000006E */
|
||||
volatile ATDSTAT0STR _ATDSTAT0; /* ATD Status Register 0; 0x00000076 */
|
||||
volatile PWMESTR _PWME; /* PWM Enable Register; 0x000000A0 */
|
||||
volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register; 0x000000A1 */
|
||||
volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register; 0x000000A2 */
|
||||
volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register; 0x000000A3 */
|
||||
volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register; 0x000000A4 */
|
||||
volatile PWMCTLSTR _PWMCTL; /* PWM Control Register; 0x000000A5 */
|
||||
volatile PWMCLKABSTR _PWMCLKAB; /* PWM Clock Select Register; 0x000000A6 */
|
||||
volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register; 0x000000A8 */
|
||||
volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register; 0x000000A9 */
|
||||
volatile SCI0ACR2STR _SCI0ACR2; /* SCI 0 Alternative Control Register 2; 0x000000CA */
|
||||
volatile SCI0CR2STR _SCI0CR2; /* SCI 0 Control Register 2; 0x000000CB */
|
||||
volatile SCI0SR1STR _SCI0SR1; /* SCI 0 Status Register 1; 0x000000CC */
|
||||
volatile SCI0SR2STR _SCI0SR2; /* SCI 0 Status Register 2; 0x000000CD */
|
||||
volatile SCI0DRHSTR _SCI0DRH; /* SCI 0 Data Register High; 0x000000CE */
|
||||
volatile SCI0DRLSTR _SCI0DRL; /* SCI 0 Data Register Low; 0x000000CF */
|
||||
volatile SCI1ACR2STR _SCI1ACR2; /* SCI 1 Alternative Control Register 2; 0x000000D2 */
|
||||
volatile SCI1CR2STR _SCI1CR2; /* SCI 1 Control Register 2; 0x000000D3 */
|
||||
volatile SCI1SR1STR _SCI1SR1; /* SCI 1 Status Register 1; 0x000000D4 */
|
||||
volatile SCI1SR2STR _SCI1SR2; /* SCI 1 Status Register 2; 0x000000D5 */
|
||||
volatile SCI1DRHSTR _SCI1DRH; /* SCI 1 Data Register High; 0x000000D6 */
|
||||
volatile SCI1DRLSTR _SCI1DRL; /* SCI 1 Data Register Low; 0x000000D7 */
|
||||
volatile SPI0CR1STR _SPI0CR1; /* SPI 0 Control Register 1; 0x000000D8 */
|
||||
volatile SPI0CR2STR _SPI0CR2; /* SPI 0 Control Register 2; 0x000000D9 */
|
||||
volatile SPI0BRSTR _SPI0BR; /* SPI 0 Baud Rate Register; 0x000000DA */
|
||||
volatile SPI0SRSTR _SPI0SR; /* SPI 0 Status Register; 0x000000DB */
|
||||
volatile SCI2ACR2STR _SCI2ACR2; /* SCI 2 Alternative Control Register 2; 0x000000EA */
|
||||
volatile SCI2CR2STR _SCI2CR2; /* SCI 2 Control Register 2; 0x000000EB */
|
||||
volatile SCI2SR1STR _SCI2SR1; /* SCI 2 Status Register 1; 0x000000EC */
|
||||
volatile SCI2SR2STR _SCI2SR2; /* SCI 2 Status Register 2; 0x000000ED */
|
||||
volatile SCI2DRHSTR _SCI2DRH; /* SCI 2 Data Register High; 0x000000EE */
|
||||
volatile SCI2DRLSTR _SCI2DRL; /* SCI 2 Data Register Low; 0x000000EF */
|
||||
volatile SPI1CR1STR _SPI1CR1; /* SPI 1 Control Register 1; 0x000000F0 */
|
||||
volatile SPI1CR2STR _SPI1CR2; /* SPI 1 Control Register 2; 0x000000F1 */
|
||||
volatile SPI1BRSTR _SPI1BR; /* SPI 1 Baud Rate Register; 0x000000F2 */
|
||||
volatile SPI1SRSTR _SPI1SR; /* SPI 1 Status Register; 0x000000F3 */
|
||||
volatile SPI2CR1STR _SPI2CR1; /* SPI 2 Control Register 1; 0x000000F8 */
|
||||
volatile SPI2CR2STR _SPI2CR2; /* SPI 2 Control Register 2; 0x000000F9 */
|
||||
volatile SPI2BRSTR _SPI2BR; /* SPI 2 Baud Rate Register; 0x000000FA */
|
||||
volatile SPI2SRSTR _SPI2SR; /* SPI 2 Status Register; 0x000000FB */
|
||||
volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register; 0x00000100 */
|
||||
volatile FSECSTR _FSEC; /* Flash Security Register; 0x00000101 */
|
||||
volatile FCCOBIXSTR _FCCOBIX; /* Flash CCOB Index Register; 0x00000102 */
|
||||
volatile FCNFGSTR _FCNFG; /* Flash Configuration Register; 0x00000104 */
|
||||
volatile FERCNFGSTR _FERCNFG; /* Flash Error Configuration Register; 0x00000105 */
|
||||
volatile FSTATSTR _FSTAT; /* Flash Status Register; 0x00000106 */
|
||||
volatile FERSTATSTR _FERSTAT; /* Flash Error Status Register; 0x00000107 */
|
||||
volatile FPROTSTR _FPROT; /* P-Flash Protection Register; 0x00000108 */
|
||||
volatile DFPROTSTR _DFPROT; /* D-Flash Protection Register; 0x00000109 */
|
||||
volatile FOPTSTR _FOPT; /* Flash Option Register; 0x00000110 */
|
||||
volatile IVBRSTR _IVBR; /* Interrupt Vector Base Register; 0x00000120 */
|
||||
volatile CANCTL0STR _CANCTL0; /* MSCAN Control 0 Register; 0x00000140 */
|
||||
volatile CANCTL1STR _CANCTL1; /* MSCAN Control 1 Register; 0x00000141 */
|
||||
volatile CANBTR0STR _CANBTR0; /* MSCAN Bus Timing Register 0; 0x00000142 */
|
||||
volatile CANBTR1STR _CANBTR1; /* MSCAN Bus Timing Register 1; 0x00000143 */
|
||||
volatile CANRFLGSTR _CANRFLG; /* MSCAN Receiver Flag Register; 0x00000144 */
|
||||
volatile CANRIERSTR _CANRIER; /* MSCAN Receiver Interrupt Enable Register; 0x00000145 */
|
||||
volatile CANTFLGSTR _CANTFLG; /* MSCAN Transmitter Flag Register; 0x00000146 */
|
||||
volatile CANTIERSTR _CANTIER; /* MSCAN Transmitter Interrupt Enable Register; 0x00000147 */
|
||||
volatile CANTARQSTR _CANTARQ; /* MSCAN Transmitter Message Abort Request; 0x00000148 */
|
||||
volatile CANTAAKSTR _CANTAAK; /* MSCAN Transmitter Message Abort Acknowledge; 0x00000149 */
|
||||
volatile CANTBSELSTR _CANTBSEL; /* MSCAN Transmit Buffer Selection; 0x0000014A */
|
||||
volatile CANIDACSTR _CANIDAC; /* MSCAN Identifier Acceptance Control Register; 0x0000014B */
|
||||
volatile CANMISCSTR _CANMISC; /* MSCAN Miscellaneous Register; 0x0000014D */
|
||||
volatile CANRXERRSTR _CANRXERR; /* MSCAN Receive Error Counter Register; 0x0000014E */
|
||||
volatile CANTXERRSTR _CANTXERR; /* MSCAN Transmit Error Counter Register; 0x0000014F */
|
||||
volatile CANIDAR0STR _CANIDAR0; /* MSCAN Identifier Acceptance Register 0; 0x00000150 */
|
||||
volatile CANIDAR1STR _CANIDAR1; /* MSCAN Identifier Acceptance Register 1; 0x00000151 */
|
||||
volatile CANIDAR2STR _CANIDAR2; /* MSCAN Identifier Acceptance Register 2; 0x00000152 */
|
||||
volatile CANIDAR3STR _CANIDAR3; /* MSCAN Identifier Acceptance Register 3; 0x00000153 */
|
||||
volatile CANIDMR0STR _CANIDMR0; /* MSCAN Identifier Mask Register 0; 0x00000154 */
|
||||
volatile CANIDMR1STR _CANIDMR1; /* MSCAN Identifier Mask Register 1; 0x00000155 */
|
||||
volatile CANIDMR2STR _CANIDMR2; /* MSCAN Identifier Mask Register 2; 0x00000156 */
|
||||
volatile CANIDMR3STR _CANIDMR3; /* MSCAN Identifier Mask Register 3; 0x00000157 */
|
||||
volatile CANIDAR4STR _CANIDAR4; /* MSCAN Identifier Acceptance Register 4; 0x00000158 */
|
||||
volatile CANIDAR5STR _CANIDAR5; /* MSCAN Identifier Acceptance Register 5; 0x00000159 */
|
||||
volatile CANIDAR6STR _CANIDAR6; /* MSCAN Identifier Acceptance Register 6; 0x0000015A */
|
||||
volatile CANIDAR7STR _CANIDAR7; /* MSCAN Identifier Acceptance Register 7; 0x0000015B */
|
||||
volatile CANIDMR4STR _CANIDMR4; /* MSCAN Identifier Mask Register 4; 0x0000015C */
|
||||
volatile CANIDMR5STR _CANIDMR5; /* MSCAN Identifier Mask Register 5; 0x0000015D */
|
||||
volatile CANIDMR6STR _CANIDMR6; /* MSCAN Identifier Mask Register 6; 0x0000015E */
|
||||
volatile CANIDMR7STR _CANIDMR7; /* MSCAN Identifier Mask Register 7; 0x0000015F */
|
||||
volatile CANRXIDR0STR _CANRXIDR0; /* MSCAN Receive Identifier Register 0; 0x00000160 */
|
||||
volatile CANRXIDR1STR _CANRXIDR1; /* MSCAN Receive Identifier Register 1; 0x00000161 */
|
||||
volatile CANRXIDR2STR _CANRXIDR2; /* MSCAN Receive Identifier Register 2; 0x00000162 */
|
||||
volatile CANRXIDR3STR _CANRXIDR3; /* MSCAN Receive Identifier Register 3; 0x00000163 */
|
||||
volatile CANRXDSR0STR _CANRXDSR0; /* MSCAN Receive Data Segment Register 0; 0x00000164 */
|
||||
volatile CANRXDSR1STR _CANRXDSR1; /* MSCAN Receive Data Segment Register 1; 0x00000165 */
|
||||
volatile CANRXDSR2STR _CANRXDSR2; /* MSCAN Receive Data Segment Register 2; 0x00000166 */
|
||||
volatile CANRXDSR3STR _CANRXDSR3; /* MSCAN Receive Data Segment Register 3; 0x00000167 */
|
||||
volatile CANRXDSR4STR _CANRXDSR4; /* MSCAN Receive Data Segment Register 4; 0x00000168 */
|
||||
volatile CANRXDSR5STR _CANRXDSR5; /* MSCAN Receive Data Segment Register 5; 0x00000169 */
|
||||
volatile CANRXDSR6STR _CANRXDSR6; /* MSCAN Receive Data Segment Register 6; 0x0000016A */
|
||||
volatile CANRXDSR7STR _CANRXDSR7; /* MSCAN Receive Data Segment Register 7; 0x0000016B */
|
||||
volatile CANRXDLRSTR _CANRXDLR; /* MSCAN Receive Data Length Register; 0x0000016C */
|
||||
volatile CANTXIDR0STR _CANTXIDR0; /* MSCAN Transmit Identifier Register 0; 0x00000170 */
|
||||
volatile CANTXIDR1STR _CANTXIDR1; /* MSCAN Transmit Identifier Register 1; 0x00000171 */
|
||||
volatile CANTXIDR2STR _CANTXIDR2; /* MSCAN Transmit Identifier Register 2; 0x00000172 */
|
||||
volatile CANTXIDR3STR _CANTXIDR3; /* MSCAN Transmit Identifier Register 3; 0x00000173 */
|
||||
volatile CANTXDSR0STR _CANTXDSR0; /* MSCAN Transmit Data Segment Register 0; 0x00000174 */
|
||||
volatile CANTXDSR1STR _CANTXDSR1; /* MSCAN Transmit Data Segment Register 1; 0x00000175 */
|
||||
volatile CANTXDSR2STR _CANTXDSR2; /* MSCAN Transmit Data Segment Register 2; 0x00000176 */
|
||||
volatile CANTXDSR3STR _CANTXDSR3; /* MSCAN Transmit Data Segment Register 3; 0x00000177 */
|
||||
volatile CANTXDSR4STR _CANTXDSR4; /* MSCAN Transmit Data Segment Register 4; 0x00000178 */
|
||||
volatile CANTXDSR5STR _CANTXDSR5; /* MSCAN Transmit Data Segment Register 5; 0x00000179 */
|
||||
volatile CANTXDSR6STR _CANTXDSR6; /* MSCAN Transmit Data Segment Register 6; 0x0000017A */
|
||||
volatile CANTXDSR7STR _CANTXDSR7; /* MSCAN Transmit Data Segment Register 7; 0x0000017B */
|
||||
volatile CANTXDLRSTR _CANTXDLR; /* MSCAN Transmit Data Length Register; 0x0000017C */
|
||||
volatile CANTXTBPRSTR _CANTXTBPR; /* MSCAN Transmit Buffer Priority; 0x0000017D */
|
||||
volatile PTTSTR _PTT; /* Port T Data Register; 0x00000240 */
|
||||
volatile PTITSTR _PTIT; /* Port T Input Register; 0x00000241 */
|
||||
volatile DDRTSTR _DDRT; /* Port T Data Direction Register; 0x00000242 */
|
||||
volatile PERTSTR _PERT; /* Port T Pull Device Enable Register; 0x00000244 */
|
||||
volatile PPSTSTR _PPST; /* Port T Polarity Select Register; 0x00000245 */
|
||||
volatile PTSSTR _PTS; /* Port S Data Register; 0x00000248 */
|
||||
volatile PTISSTR _PTIS; /* Port S Input Register; 0x00000249 */
|
||||
volatile DDRSSTR _DDRS; /* Port S Data Direction Register; 0x0000024A */
|
||||
volatile PERSSTR _PERS; /* Port S Pull Device Enable Register; 0x0000024C */
|
||||
volatile PPSSSTR _PPSS; /* Port S Polarity Select Register; 0x0000024D */
|
||||
volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register; 0x0000024E */
|
||||
volatile PRR0STR _PRR0; /* Pin Routing Register 0; 0x0000024F */
|
||||
volatile PTMSTR _PTM; /* Port M Data Register; 0x00000250 */
|
||||
volatile PTIMSTR _PTIM; /* Port M Input Register; 0x00000251 */
|
||||
volatile DDRMSTR _DDRM; /* Port M Data Direction Register; 0x00000252 */
|
||||
volatile PERMSTR _PERM; /* Port M Pull Device Enable Register; 0x00000254 */
|
||||
volatile PPSMSTR _PPSM; /* Port M Polarity Select Register; 0x00000255 */
|
||||
volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register; 0x00000256 */
|
||||
volatile PKGCRSTR _PKGCR; /* Package Code Register; 0x00000257 */
|
||||
volatile PTPSTR _PTP; /* Port P Data Register; 0x00000258 */
|
||||
volatile PTIPSTR _PTIP; /* Port P Input Register; 0x00000259 */
|
||||
volatile DDRPSTR _DDRP; /* Port P Data Direction Register; 0x0000025A */
|
||||
volatile PERPSTR _PERP; /* Port P Pull Device Enable Register; 0x0000025C */
|
||||
volatile PPSPSTR _PPSP; /* Port P Polarity Select Register; 0x0000025D */
|
||||
volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register; 0x0000025E */
|
||||
volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register; 0x0000025F */
|
||||
volatile PTJSTR _PTJ; /* Port J Data Register; 0x00000268 */
|
||||
volatile PTIJSTR _PTIJ; /* Port J Input Register; 0x00000269 */
|
||||
volatile DDRJSTR _DDRJ; /* Port J Data Direction Register; 0x0000026A */
|
||||
volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register; 0x0000026C */
|
||||
volatile PPSJSTR _PPSJ; /* Port J Polarity Select Register; 0x0000026D */
|
||||
volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register; 0x0000026E */
|
||||
volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register; 0x0000026F */
|
||||
volatile CPMULVCTLSTR _CPMULVCTL; /* Low Voltage Control Register; 0x000002F1 */
|
||||
volatile CPMUAPICTLSTR _CPMUAPICTL; /* Autonomous Periodical Interrupt Control Register; 0x000002F2 */
|
||||
volatile CPMUACLKTRSTR _CPMUACLKTR; /* Autonomous Clock Trimming Register; 0x000002F3 */
|
||||
volatile CPMUOSCSTR _CPMUOSC; /* S12CPMU Oscillator Register; 0x000002FA */
|
||||
volatile CPMUPROTSTR _CPMUPROT; /* S12CPMUV1 Protection Register; 0x000002FB */
|
||||
/* NVFPROT - macro for reading non volatile register Non Volatile P-Flash Protection Register; 0x0000FF0C */
|
||||
/* NVDFPROT - macro for reading non volatile register Non Volatile D-Flash Protection Register; 0x0000FF0D */
|
||||
/* NVFOPT - macro for reading non volatile register Non Volatile Flash Option Register; 0x0000FF0E */
|
||||
/* NVFSEC - macro for reading non volatile register Non Volatile Flash Security Register; 0x0000FF0F */
|
||||
|
||||
|
||||
/* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */
|
||||
volatile PORTABSTR _PORTAB; /* Port AB Data Register; 0x00000000 */
|
||||
volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register; 0x00000002 */
|
||||
volatile PORTCDSTR _PORTCD; /* Port CD Data Register; 0x00000004 */
|
||||
volatile DDRCDSTR _DDRCD; /* Port CD Data Direction Register; 0x00000006 */
|
||||
volatile PARTIDSTR _PARTID; /* Part ID Register; 0x0000001A */
|
||||
volatile DBGTBSTR _DBGTB; /* Debug Trace Buffer Register; 0x00000024 */
|
||||
volatile TCNTSTR _TCNT; /* Timer Count Register; 0x00000044 */
|
||||
volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0; 0x00000050 */
|
||||
volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1; 0x00000052 */
|
||||
volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2; 0x00000054 */
|
||||
volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3; 0x00000056 */
|
||||
volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4; 0x00000058 */
|
||||
volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5; 0x0000005A */
|
||||
volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6; 0x0000005C */
|
||||
volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7; 0x0000005E */
|
||||
volatile PACNTSTR _PACNT; /* Pulse Accumulators Count Register; 0x00000062 */
|
||||
volatile ATDCTL01STR _ATDCTL01; /* ATD Control Register 01; 0x00000070 */
|
||||
volatile ATDCTL23STR _ATDCTL23; /* ATD Control Register 23; 0x00000072 */
|
||||
volatile ATDCTL45STR _ATDCTL45; /* ATD Control Register 45; 0x00000074 */
|
||||
volatile ATDCMPESTR _ATDCMPE; /* ATD Compare Enable Register; 0x00000078 */
|
||||
volatile ATDSTAT2STR _ATDSTAT2; /* ATD Status Register 2; 0x0000007A */
|
||||
volatile ATDDIENSTR _ATDDIEN; /* ATD Input Enable Register; 0x0000007C */
|
||||
volatile ATDCMPHTSTR _ATDCMPHT; /* ATD Compare Higher Than Register; 0x0000007E */
|
||||
volatile ATDDR0STR _ATDDR0; /* ATD Conversion Result Register 0; 0x00000080 */
|
||||
volatile ATDDR1STR _ATDDR1; /* ATD Conversion Result Register 1; 0x00000082 */
|
||||
volatile ATDDR2STR _ATDDR2; /* ATD Conversion Result Register 2; 0x00000084 */
|
||||
volatile ATDDR3STR _ATDDR3; /* ATD Conversion Result Register 3; 0x00000086 */
|
||||
volatile ATDDR4STR _ATDDR4; /* ATD Conversion Result Register 4; 0x00000088 */
|
||||
volatile ATDDR5STR _ATDDR5; /* ATD Conversion Result Register 5; 0x0000008A */
|
||||
volatile ATDDR6STR _ATDDR6; /* ATD Conversion Result Register 6; 0x0000008C */
|
||||
volatile ATDDR7STR _ATDDR7; /* ATD Conversion Result Register 7; 0x0000008E */
|
||||
volatile ATDDR8STR _ATDDR8; /* ATD Conversion Result Register 8; 0x00000090 */
|
||||
volatile ATDDR9STR _ATDDR9; /* ATD Conversion Result Register 9; 0x00000092 */
|
||||
volatile ATDDR10STR _ATDDR10; /* ATD Conversion Result Register 10; 0x00000094 */
|
||||
volatile ATDDR11STR _ATDDR11; /* ATD Conversion Result Register 11; 0x00000096 */
|
||||
volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register; 0x000000AC */
|
||||
volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register; 0x000000AE */
|
||||
volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register; 0x000000B0 */
|
||||
volatile PWMCNT67STR _PWMCNT67; /* PWM Channel Counter 67 Register; 0x000000B2 */
|
||||
volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register; 0x000000B4 */
|
||||
volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register; 0x000000B6 */
|
||||
volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register; 0x000000B8 */
|
||||
volatile PWMPER67STR _PWMPER67; /* PWM Channel Period 67 Register; 0x000000BA */
|
||||
volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register; 0x000000BC */
|
||||
volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register; 0x000000BE */
|
||||
volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register; 0x000000C0 */
|
||||
volatile PWMDTY67STR _PWMDTY67; /* PWM Channel Duty 67 Register; 0x000000C2 */
|
||||
volatile SCI0BDSTR _SCI0BD; /* SCI 0 Baud Rate Register; 0x000000C8 */
|
||||
volatile SCI1BDSTR _SCI1BD; /* SCI 1 Baud Rate Register; 0x000000D0 */
|
||||
volatile SPI0DRSTR _SPI0DR; /* SPI 0 Data Register; 0x000000DC */
|
||||
volatile SCI2BDSTR _SCI2BD; /* SCI 2 Baud Rate Register; 0x000000E8 */
|
||||
volatile SPI1DRSTR _SPI1DR; /* SPI 1 Data Register; 0x000000F4 */
|
||||
volatile SPI2DRSTR _SPI2DR; /* SPI 2 Data Register; 0x000000FC */
|
||||
volatile FCCOBSTR _FCCOB; /* Flash Common Command Object Register; 0x0000010A */
|
||||
volatile CANRXTSRSTR _CANRXTSR; /* MSCAN Receive Time Stamp Register; 0x0000016E */
|
||||
volatile CANTXTSRSTR _CANTXTSR; /* MSCAN Transmit Time Stamp Register; 0x0000017E */
|
||||
volatile PT01ADSTR _PT01AD; /* Port AD Data Register; 0x00000270 */
|
||||
volatile PTI01ADSTR _PTI01AD; /* Port AD Input Register; 0x00000272 */
|
||||
volatile DDR01ADSTR _DDR01AD; /* Port AD Data Direction Register; 0x00000274 */
|
||||
volatile PER01ADSTR _PER01AD; /* Port AD Pull Up Enable Register; 0x00000278 */
|
||||
volatile PPS01ADSTR _PPS01AD; /* Port AD Polarity Select Register; 0x0000027A */
|
||||
volatile PIE01ADSTR _PIE01AD; /* Port AD Interrupt Enable Register; 0x0000027C */
|
||||
volatile PIF01ADSTR _PIF01AD; /* Port AD Interrupt Flag Register; 0x0000027E */
|
||||
volatile CPMUAPIRSTR _CPMUAPIR; /* Autonomous Periodical Interrupt Rate Register; 0x000002F4 */
|
||||
volatile CPMUIRCTRIMSTR _CPMUIRCTRIM; /* S12CPMU IRC1M Trim Registers; 0x000002F8 */
|
||||
/* BAKEY0 - macro for reading non volatile register Backdoor Comparison Key 0; 0x0000FF00 */
|
||||
/* BAKEY1 - macro for reading non volatile register Backdoor Comparison Key 1; 0x0000FF02 */
|
||||
/* BAKEY2 - macro for reading non volatile register Backdoor Comparison Key 2; 0x0000FF04 */
|
||||
/* BAKEY3 - macro for reading non volatile register Backdoor Comparison Key 3; 0x0000FF06 */
|
||||
|
||||
/*lint -restore */
|
||||
|
||||
/* EOF */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,215 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo/HCS12_DevKit_S12G128_CodeWarrior/Prog/main.c
|
||||
* \brief Demo program application source file.
|
||||
* \ingroup Prog_HCS12_DevKit_S12G128_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2018 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
static void Init(void);
|
||||
static void SystemClockInit(void);
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief This is the entry point for the bootloader application and is called
|
||||
** by the reset interrupt vector after the C-startup routines executed.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void main(void)
|
||||
{
|
||||
/* initialize the microcontroller */
|
||||
Init();
|
||||
/* initialize the bootloader interface */
|
||||
BootComInit();
|
||||
|
||||
/* start the infinite program loop */
|
||||
for (;;)
|
||||
{
|
||||
/* toggle LED with a fixed frequency */
|
||||
LedToggle();
|
||||
/* check for bootloader activation request */
|
||||
BootComCheckActivationRequest();
|
||||
}
|
||||
} /*** end of main ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the microcontroller.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void Init(void)
|
||||
{
|
||||
volatile unsigned long delayCnt;
|
||||
|
||||
/* ----- initialize the system clock ----- */
|
||||
SystemClockInit();
|
||||
|
||||
/* ----- configure the CAN Tx and Rx pins ----- */
|
||||
/* configure pullup device for the CAN pins */
|
||||
PPSM &= ~0x03;
|
||||
/* enable the pull device for the CAN pins */
|
||||
PERM |= 0x03;
|
||||
/* configure the CAN tx pin as a push pull output */
|
||||
WOMM |= 0x02;
|
||||
|
||||
/* ---- configure the SPI pins for the SBC with CAN transceiver ---- */
|
||||
/* configure a pullup device for SPI MISO, MOSI, CLK and a pulldown for CS */
|
||||
PPSJ &= ~0x7;
|
||||
PPSJ |= 0x10;
|
||||
/* enabled the pull device for the SPI pins */
|
||||
PERJ |= 0x0F;
|
||||
/* disable interrupt on the SPI CS pin */
|
||||
PIEJ &= ~0x10;
|
||||
/* configure the SPI CS pin as a digital output and deselect the chip */
|
||||
PTJ |= 0x10;
|
||||
DDRJ |= 0x10;
|
||||
|
||||
/* ---- initialize the SPI peripheral ---- */
|
||||
/* disable the SPI1 module and clearing flags in SPISR register */
|
||||
SPI1CR1 = 0x00;
|
||||
/* set configuration in control register 2
|
||||
* XFRW=1,MODFEN=1, BIDIROE=0, SPISWAI=0, SPC0=0
|
||||
*/
|
||||
SPI1CR2 = 0x50;
|
||||
/* configure the communication speed */
|
||||
SPI1BR = 0x42;
|
||||
/* set the configuration in control register 1
|
||||
* SPIE=0, SPE=1, SPTIE=0, MSTR=1, CPOL=0, CPHA=1, SSOE=1, LSBFE=0
|
||||
*/
|
||||
SPI1CR1 = 0x56;
|
||||
|
||||
/* ---- communicate with SBC via SPI to enable CAN communication ---- */
|
||||
/* delay a bit to make sure the SBC is ready to receive new data */
|
||||
delayCnt = 300;
|
||||
while(delayCnt-- > 0);
|
||||
/* read Vreg register H */
|
||||
SPI1DRH = 0xDF;
|
||||
SPI1DRL = 0x80;
|
||||
/* wait for the SPI transmit data register to be empty */
|
||||
while(SPI1SR_SPTEF == 0);
|
||||
|
||||
/* delay a bit to make sure the SBC is ready to receive new data */
|
||||
delayCnt = 300;
|
||||
while(delayCnt-- > 0);
|
||||
/* enter in "normal mode" */
|
||||
SPI1DRH = 0x5A;
|
||||
SPI1DRL = 0x00;
|
||||
/* wait for the SPI transmit data register to be empty */
|
||||
while(SPI1SR_SPTEF == 0);
|
||||
|
||||
/* delay a bit to make sure the SBC is ready to receive new data */
|
||||
delayCnt = 300;
|
||||
while(delayCnt-- > 0);
|
||||
/* enable 5V-CAN and Vaux */
|
||||
SPI1DRH = 0x5E;
|
||||
SPI1DRL = 0x90;
|
||||
/* wait for the SPI transmit data register to be empty */
|
||||
while(SPI1SR_SPTEF == 0);
|
||||
|
||||
/* delay a bit to make sure the SBC is ready to receive new data */
|
||||
delayCnt = 300;
|
||||
while(delayCnt-- > 0);
|
||||
/* set CAN in Tx-Rx mode, fast slew rate */
|
||||
SPI1DRH = 0x60;
|
||||
SPI1DRL = 0xC0;
|
||||
/* wait for the SPI transmit data register to be empty */
|
||||
while(SPI1SR_SPTEF == 0);
|
||||
|
||||
/* ---- init the led driver ---- */
|
||||
LedInit();
|
||||
|
||||
/* ---- init the timer driver ---- */
|
||||
TimerInit();
|
||||
|
||||
/* ---- enable interrupts ---- */
|
||||
EnableInterrupts;
|
||||
} /*** end of Init ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the clock configuration of the microcontroller.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void SystemClockInit(void)
|
||||
{
|
||||
/* system clock initialization in PEE mode. the external 8 MHz crystal oscillator is
|
||||
* used to drive the PLL such that the system clock (Fpll) is 24 MHz, with and Fvco
|
||||
* of 48 MHz and the bus clock is Fpll/2 = 12 MHz.
|
||||
*/
|
||||
/* disable the protection of the clock configuration registers */
|
||||
CPMUPROT = 0x26;
|
||||
/* configure the oscillator to be disabled in stop mode */
|
||||
CPMUCLKS_PSTP = 0;
|
||||
/* enable the PLL to allow write to divider registers */
|
||||
CPMUCLKS_PLLSEL = 1;
|
||||
/* configure Fref to be 4 MHz. REFDIV = 0, REFCLK = 2 - 6 MHz.
|
||||
* Fref = Fosc / (REFDIV + 1)
|
||||
*/
|
||||
CPMUREFDIV = 0x41;
|
||||
/* configure Fvco to be 48 MHz. SYNDIV = 11, VCOFRQ = 48 - 50 MHz.
|
||||
* Fvco = Fref * (SYNDIV + 1)
|
||||
*/
|
||||
CPMUSYNR = 0x4B;
|
||||
/* select Fpll (locked) to be 24 MHz. POSTDIV = 1.
|
||||
* Fpll = Fvco / (POSTDIV + 1)
|
||||
*/
|
||||
CPMUPOSTDIV = 0x01;
|
||||
/* set Fpll as the source of the system clocks */
|
||||
CPMUCLKS_PLLSEL = 1;
|
||||
/* wait for hardware handshake, which verifies a correct configuration of CPMUCLKS */
|
||||
while(CPMUCLKS_PLLSEL == 0)
|
||||
{
|
||||
;
|
||||
}
|
||||
/* enabled the external oscillator, since it is used to drive the PLL */
|
||||
CPMUOSC_OSCE = 1;
|
||||
/* wait for the oscillation to stabilize */
|
||||
while(CPMUFLG_UPOSC == 0)
|
||||
{
|
||||
;
|
||||
}
|
||||
/* configure the PLL frequency modulation */
|
||||
CPMUPLL = 0x00U;
|
||||
/* wait for the PLL to lock */
|
||||
while(CPMUFLG_LOCK == 0)
|
||||
{
|
||||
;
|
||||
}
|
||||
/* enable the protection of the clock configuration registers */
|
||||
CPMUPROT = 0x00;
|
||||
} /*** end of SystemClockInit ***/
|
||||
|
||||
|
||||
/*********************************** end of main.c *************************************/
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/**
|
||||
\defgroup Prog_HCS12_DevKit_S12G128_CodeWarrior User Program
|
||||
\ingroup HCS12_DevKit_S12G128_CodeWarrior
|
||||
\brief User Program.
|
||||
\details The intention of the demo user program is two-fold. (1) To test the
|
||||
bootloader, you need some sort of firmware to see if you can perform a
|
||||
firmware update with the bootloader. This program can be used for this
|
||||
purpose. (2) To make firmware programmable by the bootloader, a few
|
||||
adjustments to the firmware are required. The demo user program serves as an
|
||||
example for how these adjustments can be implemented. Additional details on
|
||||
this subject can be found in the port specifics documentation, which is
|
||||
available at:
|
||||
https://www.feaser.com/openblt/doku.php?id=manual:ports:hcs12.
|
||||
*/
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo/HCS12_DevKit_S12G128_CodeWarrior/Prog/timer.c
|
||||
* \brief Timer driver source file.
|
||||
* \ingroup Prog_HCS12_DevKit_S12G128_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2018 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Number of free running timer counts in 1 millisecond. */
|
||||
#define TIMER_COUNTS_PER_MS (24000)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Local data declarations
|
||||
****************************************************************************************/
|
||||
/** \brief Local variable for storing the number of milliseconds that have elapsed since
|
||||
* startup.
|
||||
*/
|
||||
static unsigned long millisecond_counter;
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the timer.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void TimerInit(void)
|
||||
{
|
||||
/* reset the timer configuration. note that this also sets the default prescaler
|
||||
* to 1, so the free running counter runs at the same speed as the system clock.
|
||||
*/
|
||||
TimerDeinit();
|
||||
|
||||
/* configure timer channel 0 as a 1 millisecond software timer */
|
||||
TIOS_IOS0 = 1;
|
||||
/* make sure timer 0 interrupt flag is cleared */
|
||||
TFLG1 = TFLG1_C0F_MASK;
|
||||
/* generate output compare event in 1 milliseconds from now */
|
||||
TC0 = TCNT + TIMER_COUNTS_PER_MS;
|
||||
/* enable the interrupt for timer channel 0 */
|
||||
TIE_C0I = 1;
|
||||
/* enable the timer subsystem */
|
||||
TSCR1_TEN = 1;
|
||||
/* reset the millisecond counter */
|
||||
TimerSet(0);
|
||||
} /*** end of TimerInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Stops and disables the timer.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void TimerDeinit(void)
|
||||
{
|
||||
/* bring the timer subsystem back into its reset state */
|
||||
TIE = 0;
|
||||
TSCR1 = 0;
|
||||
TSCR2 = 0;
|
||||
TIOS = 0;
|
||||
TTOV = 0;
|
||||
TCTL1 = 0;
|
||||
TCTL2 = 0;
|
||||
TCTL3 = 0;
|
||||
TCTL4 = 0;
|
||||
} /*** end of TimerDeinit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Sets the initial counter value of the millisecond timer.
|
||||
** \param timer_value initialize value of the millisecond timer.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void TimerSet(unsigned long timer_value)
|
||||
{
|
||||
/* set the millisecond counter */
|
||||
millisecond_counter = timer_value;
|
||||
} /*** end of TimerSet ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Obtains the counter value of the millisecond timer.
|
||||
** \return Current value of the millisecond timer.
|
||||
**
|
||||
****************************************************************************************/
|
||||
unsigned long TimerGet(void)
|
||||
{
|
||||
/* read and return the millisecond counter value */
|
||||
return millisecond_counter;
|
||||
} /*** end of TimerGet ***/
|
||||
|
||||
|
||||
#pragma CODE_SEG __NEAR_SEG NON_BANKED
|
||||
/************************************************************************************//**
|
||||
** \brief Interrupt service routine of the timer.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
__interrupt void TimerISRHandler(void)
|
||||
{
|
||||
/* make sure timer 0 interrupt flag is cleared */
|
||||
TFLG1 = TFLG1_C0F_MASK;
|
||||
/* generate output compare event in 1 milliseconds from now */
|
||||
TC0 += TIMER_COUNTS_PER_MS;
|
||||
/* increment the millisecond counter */
|
||||
millisecond_counter++;
|
||||
} /*** end of TimerISRHandler ***/
|
||||
#pragma CODE_SEG DEFAULT
|
||||
|
||||
|
||||
/*********************************** end of timer.c ************************************/
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo/HCS12_DevKit_S12G128_CodeWarrior/Prog/timer.h
|
||||
* \brief Timer driver header file.
|
||||
* \ingroup Prog_HCS12_DevKit_S12G128_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2018 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef TIMER_H
|
||||
#define TIMER_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void TimerInit(void);
|
||||
void TimerDeinit(void);
|
||||
void TimerSet(unsigned long timer_value);
|
||||
unsigned long TimerGet(void);
|
||||
#pragma CODE_SEG __NEAR_SEG NON_BANKED
|
||||
__interrupt void TimerISRHandler(void);
|
||||
#pragma CODE_SEG DEFAULT
|
||||
|
||||
#endif /* TIMER_H */
|
||||
/*********************************** end of timer.h ************************************/
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo/HCS12_DevKit_S12G128_CodeWarrior/Prog/vectors.c
|
||||
* \brief Demo program interrupt vectors source file.
|
||||
* \ingroup Prog_HCS12_DevKit_S12G128_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2018 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* External functions
|
||||
****************************************************************************************/
|
||||
extern void near _Startup(void);
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Type definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Type for vector table entries. */
|
||||
typedef void (*near tIsrFunc)(void);
|
||||
|
||||
|
||||
#pragma CODE_SEG __NEAR_SEG NON_BANKED
|
||||
/****************************************************************************************
|
||||
** NAME: UnusedISR
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Catch-all for unused interrrupt service routines.
|
||||
**
|
||||
****************************************************************************************/
|
||||
__interrupt void UnusedISR(void)
|
||||
{
|
||||
/* unexpected interrupt occured, so halt the system */
|
||||
for (;;)
|
||||
{
|
||||
;
|
||||
}
|
||||
} /*** end of UnusedISR ***/
|
||||
#pragma CODE_SEG DEFAULT
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* I N T E R R U P T V E C T O R T A B L E
|
||||
****************************************************************************************/
|
||||
/** \brief Interrupt vector table.
|
||||
* \details Normally, these are at 0xff80-0xffff, but the bootloader occupies 0xe800 -
|
||||
* 0xffff. The bootloader expects the vector table to be at the end of user
|
||||
* program flash, which is 0xe780 - 0xe7ff. 2 more bytes are reserved for the
|
||||
* checksum that is programmed and verified by the bootloader, so the start
|
||||
* address ends up being 0xe77e. Note that this needs to be updated when the
|
||||
* size of the bootloader changes, as defined in the flashLayout[] table in
|
||||
* flash.c of the bootloader.
|
||||
*/
|
||||
#if (BDM_DEBUGGING_ENABLED == 1)
|
||||
/* for programming and debugging with a BDM device, the vector table should be at
|
||||
* its default location.
|
||||
*/
|
||||
const tIsrFunc _vectab[] @0xff80 =
|
||||
#else
|
||||
const tIsrFunc _vectab[] @0xe77e =
|
||||
#endif
|
||||
{
|
||||
#if (BDM_DEBUGGING_ENABLED != 1)
|
||||
/* for programming and debugging with a BDM device, the checksum should not be
|
||||
* programmed because it would be in a reserved flash memory space.
|
||||
*/
|
||||
(tIsrFunc)0xaa55, /* Reserved for OpenBLT checksum */
|
||||
#endif
|
||||
(tIsrFunc)UnusedISR, /* Spurious interrupt */
|
||||
(tIsrFunc)UnusedISR, /* Port AD interrupt */
|
||||
(tIsrFunc)UnusedISR, /* ADC compare interrupt */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFF86 */
|
||||
(tIsrFunc)UnusedISR, /* Autonomous periodical int. */
|
||||
(tIsrFunc)UnusedISR, /* Low voltage interrupt */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFF8C */
|
||||
(tIsrFunc)UnusedISR, /* PortP interrupt */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFF90 */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFF92 */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFF94 */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFF96 */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFF98 */
|
||||
(tIsrFunc)UnusedISR, /* Reseved 0xFF9A */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFF9C */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFF9E */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFFA0 */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFFA2 */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFFA4 */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFFA6 */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFFA8 */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFFAA */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFFAC */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFFAE */
|
||||
(tIsrFunc)UnusedISR, /* CAN transmit */
|
||||
(tIsrFunc)UnusedISR, /* CAN receive */
|
||||
(tIsrFunc)UnusedISR, /* CAN errors */
|
||||
(tIsrFunc)UnusedISR, /* CAN wakeup */
|
||||
(tIsrFunc)UnusedISR, /* Flash command */
|
||||
(tIsrFunc)UnusedISR, /* Flash error */
|
||||
(tIsrFunc)UnusedISR, /* SPI2 */
|
||||
(tIsrFunc)UnusedISR, /* SPI1 */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFFC0 */
|
||||
(tIsrFunc)UnusedISR, /* SCI2 */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFFC4 */
|
||||
(tIsrFunc)UnusedISR, /* PLL lock */
|
||||
(tIsrFunc)UnusedISR, /* Oscillator status interrupt */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFFCA */
|
||||
(tIsrFunc)UnusedISR, /* ACMP */
|
||||
(tIsrFunc)UnusedISR, /* PortJ interrupt */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFFD0 */
|
||||
(tIsrFunc)UnusedISR, /* ADC */
|
||||
(tIsrFunc)UnusedISR, /* SCI1 */
|
||||
(tIsrFunc)UnusedISR, /* SCI0 */
|
||||
(tIsrFunc)UnusedISR, /* SPI0 */
|
||||
(tIsrFunc)UnusedISR, /* TIM pulse acc input edge */
|
||||
(tIsrFunc)UnusedISR, /* TIM pulse acc A overflow */
|
||||
(tIsrFunc)UnusedISR, /* TIM timer overflow */
|
||||
(tIsrFunc)UnusedISR, /* TIM timer channel 7 */
|
||||
(tIsrFunc)UnusedISR, /* TIM timer channel 6 */
|
||||
(tIsrFunc)UnusedISR, /* TIM timer channel 5 */
|
||||
(tIsrFunc)UnusedISR, /* TIM timer channel 4 */
|
||||
(tIsrFunc)UnusedISR, /* TIM timer channel 3 */
|
||||
(tIsrFunc)UnusedISR, /* TIM timer channel 2 */
|
||||
(tIsrFunc)UnusedISR, /* TIM timer channel 1 */
|
||||
(tIsrFunc)TimerISRHandler, /* TIM timer channel 0 */
|
||||
(tIsrFunc)UnusedISR, /* RTI time-out interrupt */
|
||||
(tIsrFunc)UnusedISR, /* IRQ */
|
||||
(tIsrFunc)UnusedISR, /* XIRQ */
|
||||
(tIsrFunc)UnusedISR, /* SWI */
|
||||
(tIsrFunc)UnusedISR, /* Unimplemented trap interrupt */
|
||||
(tIsrFunc)UnusedISR, /* COP watchdog reset */
|
||||
(tIsrFunc)UnusedISR, /* Clock monitor reset */
|
||||
(tIsrFunc)_Startup /* Reset */
|
||||
};
|
||||
|
||||
|
||||
/************************************ end of vectors.c *********************************/
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/**
|
||||
\defgroup HCS12_DevKit_S12G128_CodeWarrior Demo for NXP DevKit-S12G128/CodeWarrior
|
||||
\ingroup Demos
|
||||
\brief Preconfigured programs for the NXP DevKit-S12G128 and the CodeWarrior IDE.
|
||||
\details For detailed getting started instructions, refer to:
|
||||
https://www.feaser.com/openblt/doku.php?id=manual:demos:devkit_s12g128_codewarrior.
|
||||
*/
|
||||
|
||||
|
||||
Loading…
Reference in New Issue