mirror of https://github.com/rusefi/openblt.git
Added Freescale HCS12 port including a Dragon12plus demo.
git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@60 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
Frank Voorburg
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[sci]
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port=3
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port=5
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baudrate=8
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[xcp]
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seedkey=
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||||
S9030000FC
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,168 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Boot\blt_conf.h
|
||||
* \brief Bootloader configuration header file.
|
||||
* \ingroup Boot_HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef BLT_CONF_H
|
||||
#define BLT_CONF_H
|
||||
|
||||
/****************************************************************************************
|
||||
* C P U D R I V E R C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* To properly initialize the baudrate clocks of the communication interface, typically
|
||||
* the speed of the crystal oscillator and/or the speed at which the system runs is
|
||||
* needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
|
||||
* BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
|
||||
* not dependent on the targets architecture, the byte ordering needs to be known.
|
||||
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects little endian mode and 0 selects
|
||||
* big endian mode.
|
||||
*
|
||||
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
|
||||
* called the moment the user program is about to be started. This could be used to
|
||||
* de-initialize application specific parts, for example to stop blinking an LED, etc.
|
||||
*/
|
||||
/** \brief Frequency of the external crystal oscillator. */
|
||||
#define BOOT_CPU_XTAL_SPEED_KHZ (8000)
|
||||
/** \brief Desired system speed. */
|
||||
#define BOOT_CPU_SYSTEM_SPEED_KHZ (24000)
|
||||
/** \brief Motorola or Intel style byte ordering. */
|
||||
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (1)
|
||||
/** \brief Enable/disable hook function call right before user program start. */
|
||||
#define BOOT_CPU_USER_PROGRAM_START_HOOK (0)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE
|
||||
* configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed
|
||||
* in bits/second. The maximum amount of data bytes in a message for data transmission
|
||||
* and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA,
|
||||
* respectively. It is common for a microcontroller to have more than 1 UART interface
|
||||
* on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface.
|
||||
*
|
||||
*/
|
||||
/** \brief Enable/disable UART transport layer. */
|
||||
#define BOOT_COM_UART_ENABLE (1)
|
||||
/** \brief Configure the desired communication speed. */
|
||||
#define BOOT_COM_UART_BAUDRATE (57600)
|
||||
/** \brief Configure number of bytes in the target->host data packet. */
|
||||
#define BOOT_COM_UART_TX_MAX_DATA (64)
|
||||
/** \brief Configure number of bytes in the host->target data packet. */
|
||||
#define BOOT_COM_UART_RX_MAX_DATA (64)
|
||||
/** \brief Select the desired UART peripheral as a zero based index. */
|
||||
#define BOOT_COM_UART_CHANNEL_INDEX (0)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* F I L E S Y S T E M I N T E R F A C E C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* The file system interface is selected by setting the BOOT_FILE_SYS_ENABLE configurable
|
||||
* to 1. This enables support for firmware updates from a file stored on a locally
|
||||
* attached file system such as an SD-card. Note that this interface can be enabled
|
||||
* together with one of the remote communication interfaces such as UART, CAN or USB.
|
||||
*
|
||||
* Set BOOT_FILE_LOGGING_ENABLE to 1 if you would like log messages to be created during
|
||||
* a firmware update. The hook function FileFirmwareUpdateLogHook() will be called each
|
||||
* time a new string formatted log entry is available. This could be used during testing
|
||||
* by outputting the string on UART or to create a log file on the file system itself.
|
||||
*
|
||||
* Set BOOT_FILE_ERROR_HOOK_ENABLE to 1 if you would like to be informed in case an error
|
||||
* occurs during the firmware update. This could for example be used to turn on an error
|
||||
* LED to inform the user that something went wrong. Inspecting the log messages provides
|
||||
* additional information on the error cause.
|
||||
*
|
||||
* Set BOOT_FILE_STARTED_HOOK_ENABLE to 1 if you would like to be informed when a new
|
||||
* firmware update is started by the bootloader.
|
||||
*
|
||||
* Set BOOT_FILE_COMPLETED_HOOK_ENABLE to 1 if you would like to be informed when a
|
||||
* firmware update is completed by the bootloader.
|
||||
*/
|
||||
/** \brief Enable/disable support for firmware updates from a locally attached storage.*/
|
||||
#define BOOT_FILE_SYS_ENABLE (0)
|
||||
/** \brief Enable/disable logging messages during firmware updates. */
|
||||
#define BOOT_FILE_LOGGING_ENABLE (0)
|
||||
/** \brief Enable/disable a hook function that is called upon detection of an error. */
|
||||
#define BOOT_FILE_ERROR_HOOK_ENABLE (0)
|
||||
/** \brief Enable/disable a hook function that is called at the start of the update. */
|
||||
#define BOOT_FILE_STARTED_HOOK_ENABLE (0)
|
||||
/** \brief Enable/disable a hook function that is called at the end of the update. */
|
||||
#define BOOT_FILE_COMPLETED_HOOK_ENABLE (0)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* B A C K D O O R E N T R Y C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* It is possible to implement an application specific method to force the bootloader to
|
||||
* stay active after a reset. Such a backdoor entry into the bootloader is desired in
|
||||
* situations where the user program does not run properly and therefore cannot
|
||||
* reactivate the bootloader. By enabling these hook functions, the application can
|
||||
* implement the backdoor, which overrides the default backdoor entry that is programmed
|
||||
* into the bootloader. When desired for security purposes, these hook functions can
|
||||
* also be implemented in a way that disables the backdoor entry altogether.
|
||||
*/
|
||||
/** \brief Enable/disable the backdoor override hook functions. */
|
||||
#define BOOT_BACKDOOR_HOOKS_ENABLE (0)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* The NVM driver typically supports erase and program operations of the internal memory
|
||||
* present on the microcontroller. Through these hook functions the NVM driver can be
|
||||
* extended to support additional memory types such as external flash memory and serial
|
||||
* eeproms. The size of the internal memory in kilobytes is specified with configurable
|
||||
* BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can
|
||||
* be overridden with a application specific method by enabling configuration switch
|
||||
* BOOT_NVM_CHECKSUM_HOOKS_ENABLE.
|
||||
*/
|
||||
/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */
|
||||
#define BOOT_NVM_HOOKS_ENABLE (0)
|
||||
/** \brief Configure the size of the default memory device (typically flash EEPROM). */
|
||||
#define BOOT_NVM_SIZE_KB (256)
|
||||
/** \brief Enable/disable hooks functions to override the user program checksum handling. */
|
||||
#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* W A T C H D O G D R I V E R C O N F I G U R A T I O N
|
||||
****************************************************************************************/
|
||||
/* The COP driver cannot be configured internally in the bootloader, because its use
|
||||
* and configuration is application specific. The bootloader does need to service the
|
||||
* watchdog in case it is used. When the application requires the use of a watchdog,
|
||||
* set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
|
||||
* hook functions.
|
||||
*/
|
||||
/** \brief Enable/disable the hook functions for controlling the watchdog. */
|
||||
#define BOOT_COP_HOOKS_ENABLE (0)
|
||||
|
||||
|
||||
#endif /* BLT_CONF_H */
|
||||
/*********************************** end of blt_conf.h *********************************/
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
/**
|
||||
\defgroup Boot_HCS12_Evbplus_Dragon12p_CodeWarrior Bootloader
|
||||
\brief Bootloader.
|
||||
\ingroup HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
*/
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
// ver 1.1 (7/7/04)
|
||||
// HCS12X Core erasing + unsecuring command file:
|
||||
// These commands mass erase the chip then program the security byte to 0xFE (unsecured state).
|
||||
|
||||
// Evaluate the clock divider to set in ECLKDIV/FCLKDIV registers:
|
||||
|
||||
DEFINEVALUEDLG "Information required to unsecure the device" "CLKDIV" 0x49 "To unsecure the device, the command script needs \nthe correct value for ECLKDIV/FCLKDIV onchip\nregisters.\nIf the bus frequency is less than 10 MHz, the value\nto store in ECLKDIV/FCLKDIV is equal to:\n \"bus frequency (kHz) / 175\"\n\nIf the bus frequency is higher than 10 MHz, the value\nto store in ECLKDIV/FCLKDIV is equal to:\n \" bus frequency (kHz) / 1400 + 64\"\n(+64 (0x40) is to set PRDIV8 flag)\n\nDatasheet proposed values:\n\nbus frequency\t\tE/FCLKDIV value (decimal)\n\n 16 \tMHz\t\t73\n 8 \tMHz\t\t39\n 4 \tMHz\t\t19\n 2 \tMHz\t\t9\n 1 \tMHz\t\t4\n"
|
||||
|
||||
// An average programming clock of 175 kHz is chosen.
|
||||
|
||||
// If the oscillator frequency is less than 10 MHz, the value to store
|
||||
// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 175 ".
|
||||
|
||||
// If the oscillator frequency is higher than 10 MHz, the value to store
|
||||
// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 1400 + 0x40 (to set PRDIV8 flag)".
|
||||
|
||||
// Datasheet proposed values:
|
||||
//
|
||||
// oscillator frequency ECLKDIV/FCLKDIV value (hexadecimal)
|
||||
//
|
||||
// 16 MHz $49
|
||||
// 8 MHz $27
|
||||
// 4 MHz $13
|
||||
// 2 MHz $9
|
||||
// 1 MHz $4
|
||||
|
||||
|
||||
FLASH RELEASE // do not interact with regular flash programming monitor
|
||||
|
||||
//mass erase flash
|
||||
reset
|
||||
wb 0x03c 0x00 //disable cop
|
||||
wait 20
|
||||
wb 0x100 CLKDIV // set FCLKDIV clock divider
|
||||
wb 0x104 0xFF // FPROT all protection disabled
|
||||
wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register
|
||||
wb 0x102 0x00 // clear the WRALL bit in FTSTMOD
|
||||
wb 0x105 0x02
|
||||
wb 0x102 0x10 // set the WRALL bit in FTSTMOD to affect all blocks
|
||||
ww 0x108 0xFFFE
|
||||
ww 0x10A 0xFFFF
|
||||
wb 0x106 0x41 // write MASS ERASE command in FCMD register
|
||||
wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command
|
||||
wait 20 // wait for command to complete
|
||||
|
||||
//mass erase eeprom
|
||||
wb 0x110 CLKDIV // set ECLKDV clock divider
|
||||
wb 0x114 0xFF // EPROT all protection disabled
|
||||
wb 0x115 0x30 // clear PVIOL and ACCERR in ESTAT register
|
||||
wb 0x112 0x00 // clear the WRALL bit in FTSTMOD
|
||||
wb 0x115 0x02
|
||||
ww 0x118 0x0C00 // write to EADDR eeprom address register
|
||||
ww 0x11A 0x0000 // write to EDATA eeprom data register
|
||||
wb 0x116 0x41 // write MASS ERASE command in ECMD register
|
||||
wb 0x115 0x80 // clear CBEIF in ESTAT register to execute the command
|
||||
wait 20 // wait for command to complete
|
||||
|
||||
//reprogram Security byte to Unsecure state
|
||||
reset
|
||||
wb 0x03c 0x00 //disable cop
|
||||
wait 20
|
||||
wb 0x102 0x00 // clear the WRALL bit in FTSTMOD
|
||||
wb 0x105 0x02
|
||||
wb 0x100 CLKDIV // set FCLKDIV clock divider
|
||||
wb 0x100 CLKDIV // set FCLKDIV clock divider
|
||||
wb 0x104 0xFF // FPROT all protection disabled
|
||||
wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register
|
||||
wb 0x102 0x00 // clear the WRALL bit in FTSTMOD
|
||||
wb 0x105 0x02
|
||||
ww 0xFF0E 0xFFFE // write security byte to "Unsecured" state
|
||||
wb 0x106 0x20 // write MEMORY PROGRAM command in FCMD register
|
||||
wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command
|
||||
wait 20 // wait for command to complete
|
||||
|
||||
reset
|
||||
|
||||
undef CLKDIV // undefine variable
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
// After load the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// Before load the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// After reset the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// At startup the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// After programming the flash, the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// Before programming the flash, the commands written below will be executed
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
/* logical s-record file */
|
||||
OPENFILE "%ABS_FILE%.s19"
|
||||
format=motorola
|
||||
busWidth=1
|
||||
origin=0
|
||||
len=0x1000000
|
||||
destination=0
|
||||
SRECORD=Sx
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
CLOSE
|
||||
|
||||
|
||||
/* physical s-record file */
|
||||
OPENFILE "%ABS_FILE%.phy"
|
||||
format = motorola
|
||||
busWidth = 1
|
||||
len = 0x4000
|
||||
|
||||
/* logical non banked flash at $4000 and $C000 to physical */
|
||||
origin = 0x004000
|
||||
destination = 0x0F8000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x00C000
|
||||
destination = 0x0FC000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
/* physical FTS512K flash window to physical
|
||||
origin = 0x008000
|
||||
destination = 0x080000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
*/
|
||||
|
||||
/* physical FTS256K parts flash window to physical
|
||||
origin = 0x008000
|
||||
destination = 0x0C0000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
*/
|
||||
|
||||
/* physical FTS128K parts flash window to physical
|
||||
origin = 0x008000
|
||||
destination = 0x0E0000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
*/
|
||||
|
||||
/* physical FTS64K parts flash window to physical
|
||||
origin = 0x008000
|
||||
destination = 0x0F0000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
*/
|
||||
|
||||
/* physical FTS32K parts flash window to physical
|
||||
origin = 0x008000
|
||||
destination = 0x0F8000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
*/
|
||||
|
||||
/* logical 512 kB banked flash to physical */
|
||||
origin = 0x208000
|
||||
destination = 0x080000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x218000
|
||||
destination = 0x084000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x228000
|
||||
destination = 0x088000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x238000
|
||||
destination = 0x08C000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x248000
|
||||
destination = 0x090000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x258000
|
||||
destination = 0x094000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x268000
|
||||
destination = 0x098000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x278000
|
||||
destination = 0x09C000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x288000
|
||||
destination = 0x0A0000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x298000
|
||||
destination = 0x0A4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x2A8000
|
||||
destination = 0x0A8000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x2B8000
|
||||
destination = 0x0AC000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x2C8000
|
||||
destination = 0x0B0000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x2D8000
|
||||
destination = 0x0B4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x2E8000
|
||||
destination = 0x0B8000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x2F8000
|
||||
destination = 0x0BC000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x308000
|
||||
destination = 0x0C0000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x318000
|
||||
destination = 0x0C4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x328000
|
||||
destination = 0x0C8000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x338000
|
||||
destination = 0x0CC000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x348000
|
||||
destination = 0x0D0000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x358000
|
||||
destination = 0x0D4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x368000
|
||||
destination = 0x0D8000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x378000
|
||||
destination = 0x0DC000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x388000
|
||||
destination = 0x0E0000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x398000
|
||||
destination = 0x0E4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x3A8000
|
||||
destination = 0x0E8000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x3B8000
|
||||
destination = 0x0EC000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x3C8000
|
||||
destination = 0x0F0000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x3D8000
|
||||
destination = 0x0F4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x3E8000
|
||||
destination = 0x0F8000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x3F8000
|
||||
destination = 0x0FC000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
CLOSE
|
||||
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Boot\hooks.c
|
||||
* \brief Bootloader callback source file.
|
||||
* \ingroup Boot_HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* B A C K D O O R E N T R Y H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the backdoor entry option.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void BackDoorInitHook(void)
|
||||
{
|
||||
} /*** end of BackDoorInitHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Checks if a backdoor entry is requested.
|
||||
** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool BackDoorEntryHook(void)
|
||||
{
|
||||
/* default implementation always activates the bootloader after a reset */
|
||||
return BLT_TRUE;
|
||||
} /*** end of BackDoorEntryHook ***/
|
||||
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* C P U D R I V E R H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called when the bootloader is about to exit and
|
||||
** hand over control to the user program. This is the last moment that
|
||||
** some final checking can be performed and if necessary prevent the
|
||||
** bootloader from activiting the user program.
|
||||
** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
|
||||
** keep the bootloader active.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool CpuUserProgramStartHook(void)
|
||||
{
|
||||
/* okay to start the user program */
|
||||
return BLT_TRUE;
|
||||
} /*** end of CpuUserProgramStartHook ***/
|
||||
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the start of the internal NVM driver
|
||||
** initialization routine.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void NvmInitHook(void)
|
||||
{
|
||||
} /*** end of NvmInitHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the start of the NVM driver write
|
||||
** routine. It allows additional memory to be operated on. If the address
|
||||
** is not within the range of the additional memory, then
|
||||
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
|
||||
** been written yet.
|
||||
** \param addr Start address.
|
||||
** \param len Length in bytes.
|
||||
** \param data Pointer to the data buffer.
|
||||
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
|
||||
** not within the supported memory range, or BLT_NVM_ERROR is the write
|
||||
** operation failed.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
|
||||
{
|
||||
return BLT_NVM_NOT_IN_RANGE;
|
||||
} /*** end of NvmWriteHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the start of the NVM driver erase
|
||||
** routine. It allows additional memory to be operated on. If the address
|
||||
** is not within the range of the additional memory, then
|
||||
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory
|
||||
** hasn't been erased yet.
|
||||
** \param addr Start address.
|
||||
** \param len Length in bytes.
|
||||
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
|
||||
** not within the supported memory range, or BLT_NVM_ERROR is the erase
|
||||
** operation failed.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len)
|
||||
{
|
||||
return BLT_NVM_NOT_IN_RANGE;
|
||||
} /*** end of NvmEraseHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the end of the NVM programming session.
|
||||
** \return BLT_TRUE is successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmDoneHook(void)
|
||||
{
|
||||
return BLT_TRUE;
|
||||
} /*** end of NvmDoneHook ***/
|
||||
#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Verifies the checksum, which indicates that a valid user program is
|
||||
** present and can be started.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmVerifyChecksumHook(void)
|
||||
{
|
||||
return BLT_TRUE;
|
||||
} /*** end of NvmVerifyChecksum ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Writes a checksum of the user program to non-volatile memory. This is
|
||||
** performed once the entire user program has been programmed. Through
|
||||
** the checksum, the bootloader can check if a valid user programming is
|
||||
** present and can be started.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmWriteChecksumHook(void)
|
||||
{
|
||||
return BLT_TRUE;
|
||||
}
|
||||
#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* W A T C H D O G D R I V E R H O O K F U N C T I O N S
|
||||
****************************************************************************************/
|
||||
|
||||
#if (BOOT_COP_HOOKS_ENABLE > 0)
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the end of the internal COP driver
|
||||
** initialization routine. It can be used to configure and enable the
|
||||
** watchdog.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void CopInitHook(void)
|
||||
{
|
||||
} /*** end of CopInitHook ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Callback that gets called at the end of the internal COP driver
|
||||
** service routine. This gets called upon initialization and during
|
||||
** potential long lasting loops and routine. It can be used to service
|
||||
** the watchdog to prevent a watchdog reset.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void CopServiceHook(void)
|
||||
{
|
||||
} /*** end of CopServiceHook ***/
|
||||
#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
|
||||
|
||||
|
||||
|
||||
/*********************************** end of hooks.c ************************************/
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
OPEN source 0 0 60 39
|
||||
Source < attributes MARKS off
|
||||
OPEN assembly 60 0 40 31
|
||||
Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C
|
||||
OPEN procedure 0 39 60 17
|
||||
Procedure < attributes VALUES on,TYPES off
|
||||
OPEN register 60 31 40 25
|
||||
Register < attributes FORMAT AUTO,COMPLEMENT None
|
||||
OPEN memory 60 56 40 22
|
||||
Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80
|
||||
OPEN data 0 56 60 22
|
||||
Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16
|
||||
OPEN data 0 78 60 22
|
||||
Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16
|
||||
OPEN command 60 78 40 22
|
||||
Command < attributes CACHESIZE 1000
|
||||
bckcolor 50331647
|
||||
font 'Courier New' 9 BLACK
|
||||
AUTOSIZE on
|
||||
ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory
|
||||
Binary file not shown.
|
|
@ -0,0 +1,95 @@
|
|||
[STARTUP]
|
||||
CPUTARGETTYPE=0
|
||||
USE_CYCLONEPRO_RELAYS=0
|
||||
PORT=21
|
||||
interface_selection=1
|
||||
SHOWDIALOG=0
|
||||
IO_DELAY_SET=1
|
||||
frequency_has_changed_old_io_delay_cnt=29
|
||||
CyclonePro_poweroffonexit=0
|
||||
CyclonePro_currentvoltage=255
|
||||
CyclonePro_PowerDownDelay=250
|
||||
CyclonePro_PowerUpDelay=250
|
||||
IO_DELAY_CNT=29
|
||||
PCI_DELAY=0
|
||||
RESET_DELAY=0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
[Environment Variables]
|
||||
GENPATH={Project}..\src;{Compiler}lib\hc12c\src;{Compiler}lib\hc12c\include;{Compiler}lib\hc12c\lib;{Compiler}lib\xgatec\src;{Compiler}lib\xgatec\include;{Compiler}lib\xgatec\lib
|
||||
LIBPATH={Compiler}lib\hc12c\include;{Compiler}lib\xgatec\include
|
||||
OBJPATH={Project}..\bin
|
||||
TEXTPATH={Project}..\bin
|
||||
ABSPATH={Project}..\bin
|
||||
|
||||
[HI-WAVE]
|
||||
Target=icd12
|
||||
Layout=C_layout.hwl
|
||||
LoadDialogOptions=AUTOERASEANDFLASH RUNANDSTOPAFTERLOAD="main"
|
||||
CPU=HC12
|
||||
MainFrame=2,3,-1,-31,-1,-1,200,200,1640,967
|
||||
TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806
|
||||
AEFWarningDialog=FALSE
|
||||
|
||||
|
||||
|
||||
|
||||
[HC12MultilinkCyclonePro_GDI_SETTINGS]
|
||||
CMDFILE0=CMDFILE STARTUP ON ".\..\cmd\P&E_Multilink_USB_startup.cmd"
|
||||
CMDFILE1=CMDFILE RESET ON ".\..\cmd\P&E_Multilink_USB_reset.cmd"
|
||||
CMDFILE2=CMDFILE PRELOAD ON ".\..\cmd\P&E_Multilink_USB_preload.cmd"
|
||||
CMDFILE3=CMDFILE POSTLOAD ON ".\..\cmd\P&E_Multilink_USB_postload.cmd"
|
||||
CMDFILE4=CMDFILE VPPON ON ".\..\cmd\P&E_Multilink_USB_vppon.cmd"
|
||||
CMDFILE5=CMDFILE VPPOFF ON ".\..\cmd\P&E_Multilink_USB_vppoff.cmd"
|
||||
CMDFILE6=CMDFILE UNSECURE ON ".\..\cmd\P&E_Multilink_USB_erase_unsecure_hcs12.cmd"
|
||||
MCUID=0x03D9
|
||||
NV_PARAMETER_FILE=C:\Program Files (x86)\Freescale\CWS12v5.1\prog\FPP\mcu03D9.fpp
|
||||
NV_SAVE_WSP=0
|
||||
NV_AUTO_ID=1
|
||||
CHIPSECURE=CHIPSECURE SETUP 0xFF0F 0x3 0x2
|
||||
HWBPD_MCUID03D9_HWBPM0=HWBPM MODE AUTOMATIC BPM22BITS 0x28 SKIP_OFF
|
||||
HWBPD_MCUID03D9_BKPT_REMAP0=HWBPM REMAP_22BITS RANGE 0x4000 0x7FFF 0x3E
|
||||
HWBPD_MCUID03D9_BKPT_REMAP1=HWBPM REMAP_22BITS RANGE 0xC000 0xFFFF 0x3F
|
||||
HWBPD_MCUID03D9_HWBPM1=HWBPM SET16BITS 0x0 0x0 0x0 0x0
|
||||
HWBPD_MCUID03D9_HWBPM2=HWBPM SET22BITS 0x0 0x0 0x0 0x0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
[ICD12]
|
||||
COMSETTINGS=SETCOMM DRIVER NOPROTOCOL NOPERIODICAL
|
||||
SETCLKSW=0
|
||||
HOTPLUGGING=0
|
||||
DETECTRUNNING=0
|
||||
RESYNCONCOPRESET=0
|
||||
BDMAutoSpeed=0
|
||||
BDMClockSpeed=29
|
||||
HIGHIODELAYCONSTFORPLL=40
|
||||
|
||||
[PORT]
|
||||
IP=
|
||||
|
||||
|
||||
[Recent Applications File List]
|
||||
File0=C:\Work\software\OpenBLT\Target\Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Boot\bin\openblt_evbplus_dragon12p.abs
|
||||
File1=C:\Work\software\OpenBLT\Target\Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\bin\demoprog_evbplus_dragon12p.abs
|
||||
File2=
|
||||
File3=
|
||||
LoadFlags0=NORUNAFTERLOAD
|
||||
LoadFlags1=AUTOERASEANDFLASH RUNANDSTOPAFTERLOAD="main"
|
||||
LoadFlags2=
|
||||
LoadFlags3=
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Note: This file is recreated by the project wizard whenever the MCU is
|
||||
* changed and should not be edited by hand
|
||||
*/
|
||||
|
||||
/* Include the derivative-specific header file */
|
||||
#include <mc9s12dg256.h>
|
||||
|
||||
#pragma LINK_INFO DERIVATIVE "mc9s12dg256"
|
||||
|
||||
|
|
@ -0,0 +1,366 @@
|
|||
/* Based on CPU DB MC9S12DG256_112, version 2.87.346 (RegistersPrg V2.28) */
|
||||
/* DataSheet : 9S12DT256DGV3/D V03.04 */
|
||||
|
||||
#include <mc9s12dg256.h>
|
||||
|
||||
/*lint -save -esym(765, *) */
|
||||
|
||||
|
||||
/* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */
|
||||
volatile PORTESTR _PORTE; /* Port E Register; 0x00000008 */
|
||||
volatile DDRESTR _DDRE; /* Port E Data Direction Register; 0x00000009 */
|
||||
volatile PEARSTR _PEAR; /* Port E Assignment Register; 0x0000000A */
|
||||
volatile MODESTR _MODE; /* Mode Register; 0x0000000B */
|
||||
volatile PUCRSTR _PUCR; /* Pull-Up Control Register; 0x0000000C */
|
||||
volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines; 0x0000000D */
|
||||
volatile EBICTLSTR _EBICTL; /* External Bus Interface Control; 0x0000000E */
|
||||
volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register; 0x00000010 */
|
||||
volatile INITRGSTR _INITRG; /* Initialization of Internal Registers Position Register; 0x00000011 */
|
||||
volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register; 0x00000012 */
|
||||
volatile MISCSTR _MISC; /* Miscellaneous System Control Register; 0x00000013 */
|
||||
volatile ITCRSTR _ITCR; /* Interrupt Test Control Register; 0x00000015 */
|
||||
volatile ITESTSTR _ITEST; /* Interrupt Test Register; 0x00000016 */
|
||||
volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero; 0x0000001C */
|
||||
volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One; 0x0000001D */
|
||||
volatile INTCRSTR _INTCR; /* Interrupt Control Register; 0x0000001E */
|
||||
volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt; 0x0000001F */
|
||||
volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0; 0x00000028 */
|
||||
volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1; 0x00000029 */
|
||||
volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register; 0x0000002A */
|
||||
volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register; 0x0000002B */
|
||||
volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register; 0x0000002C */
|
||||
volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register; 0x0000002D */
|
||||
volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register; 0x0000002E */
|
||||
volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register; 0x0000002F */
|
||||
volatile PPAGESTR _PPAGE; /* Page Index Register; 0x00000030 */
|
||||
volatile PORTKSTR _PORTK; /* Port K Data Register; 0x00000032 */
|
||||
volatile DDRKSTR _DDRK; /* Port K Data Direction Register; 0x00000033 */
|
||||
volatile SYNRSTR _SYNR; /* CRG Synthesizer Register; 0x00000034 */
|
||||
volatile REFDVSTR _REFDV; /* CRG Reference Divider Register; 0x00000035 */
|
||||
volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register; 0x00000037 */
|
||||
volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register; 0x00000038 */
|
||||
volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register; 0x00000039 */
|
||||
volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register; 0x0000003A */
|
||||
volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register; 0x0000003B */
|
||||
volatile COPCTLSTR _COPCTL; /* CRG COP Control Register; 0x0000003C */
|
||||
volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register; 0x0000003F */
|
||||
volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select; 0x00000040 */
|
||||
volatile CFORCSTR _CFORC; /* Timer Compare Force Register; 0x00000041 */
|
||||
volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register; 0x00000042 */
|
||||
volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register; 0x00000043 */
|
||||
volatile TSCR1STR _TSCR1; /* Timer System Control Register1; 0x00000046 */
|
||||
volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register; 0x00000047 */
|
||||
volatile TCTL1STR _TCTL1; /* Timer Control Register 1; 0x00000048 */
|
||||
volatile TCTL2STR _TCTL2; /* Timer Control Register 2; 0x00000049 */
|
||||
volatile TCTL3STR _TCTL3; /* Timer Control Register 3; 0x0000004A */
|
||||
volatile TCTL4STR _TCTL4; /* Timer Control Register 4; 0x0000004B */
|
||||
volatile TIESTR _TIE; /* Timer Interrupt Enable Register; 0x0000004C */
|
||||
volatile TSCR2STR _TSCR2; /* Timer System Control Register 2; 0x0000004D */
|
||||
volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1; 0x0000004E */
|
||||
volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2; 0x0000004F */
|
||||
volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register; 0x00000060 */
|
||||
volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register; 0x00000061 */
|
||||
volatile MCCTLSTR _MCCTL; /* Modulus Down Counter underflow; 0x00000066 */
|
||||
volatile MCFLGSTR _MCFLG; /* 16-Bit Modulus Down Counter Flag Register; 0x00000067 */
|
||||
volatile ICPARSTR _ICPAR; /* Input Control Pulse Accumulator Register; 0x00000068 */
|
||||
volatile DLYCTSTR _DLYCT; /* Delay Counter Control Register; 0x00000069 */
|
||||
volatile ICOVWSTR _ICOVW; /* Input Control Overwrite Register; 0x0000006A */
|
||||
volatile ICSYSSTR _ICSYS; /* Input Control System Control Register; 0x0000006B */
|
||||
volatile PBCTLSTR _PBCTL; /* 16-Bit Pulse Accumulator B Control Register; 0x00000070 */
|
||||
volatile PBFLGSTR _PBFLG; /* Pulse Accumulator B Flag Register; 0x00000071 */
|
||||
volatile ATD0STAT0STR _ATD0STAT0; /* ATD 0 Status Register 0; 0x00000086 */
|
||||
volatile ATD0TEST1STR _ATD0TEST1; /* ATD0 Test Register; 0x00000089 */
|
||||
volatile ATD0STAT1STR _ATD0STAT1; /* ATD 0 Status Register 1; 0x0000008B */
|
||||
volatile ATD0DIENSTR _ATD0DIEN; /* ATD 0 Input Enable Register; 0x0000008D */
|
||||
volatile PORTAD0STR _PORTAD0; /* Port AD0 Register; 0x0000008F */
|
||||
volatile PWMESTR _PWME; /* PWM Enable Register; 0x000000A0 */
|
||||
volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register; 0x000000A1 */
|
||||
volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register; 0x000000A2 */
|
||||
volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register; 0x000000A3 */
|
||||
volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register; 0x000000A4 */
|
||||
volatile PWMCTLSTR _PWMCTL; /* PWM Control Register; 0x000000A5 */
|
||||
volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register; 0x000000A8 */
|
||||
volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register; 0x000000A9 */
|
||||
volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register; 0x000000C4 */
|
||||
volatile SCI0CR1STR _SCI0CR1; /* SCI 0 Control Register 1; 0x000000CA */
|
||||
volatile SCI0CR2STR _SCI0CR2; /* SCI 0 Control Register 2; 0x000000CB */
|
||||
volatile SCI0SR1STR _SCI0SR1; /* SCI 0 Status Register 1; 0x000000CC */
|
||||
volatile SCI0SR2STR _SCI0SR2; /* SCI 0 Status Register 2; 0x000000CD */
|
||||
volatile SCI0DRHSTR _SCI0DRH; /* SCI 0 Data Register High; 0x000000CE */
|
||||
volatile SCI0DRLSTR _SCI0DRL; /* SCI 0 Data Register Low; 0x000000CF */
|
||||
volatile SCI1CR1STR _SCI1CR1; /* SCI 1 Control Register 1; 0x000000D2 */
|
||||
volatile SCI1CR2STR _SCI1CR2; /* SCI 1 Control Register 2; 0x000000D3 */
|
||||
volatile SCI1SR1STR _SCI1SR1; /* SCI 1 Status Register 1; 0x000000D4 */
|
||||
volatile SCI1SR2STR _SCI1SR2; /* SCI 1 Status Register 2; 0x000000D5 */
|
||||
volatile SCI1DRHSTR _SCI1DRH; /* SCI 1 Data Register High; 0x000000D6 */
|
||||
volatile SCI1DRLSTR _SCI1DRL; /* SCI 1 Data Register Low; 0x000000D7 */
|
||||
volatile SPI0CR1STR _SPI0CR1; /* SPI 0 Control Register; 0x000000D8 */
|
||||
volatile SPI0CR2STR _SPI0CR2; /* SPI 0 Control Register 2; 0x000000D9 */
|
||||
volatile SPI0BRSTR _SPI0BR; /* SPI 0 Baud Rate Register; 0x000000DA */
|
||||
volatile SPI0SRSTR _SPI0SR; /* SPI 0 Status Register; 0x000000DB */
|
||||
volatile SPI0DRSTR _SPI0DR; /* SPI 0 Data Register; 0x000000DD */
|
||||
volatile IBADSTR _IBAD; /* IIC Address Register; 0x000000E0 */
|
||||
volatile IBFDSTR _IBFD; /* IIC Frequency Divider Register; 0x000000E1 */
|
||||
volatile IBCRSTR _IBCR; /* IIC Control Register; 0x000000E2 */
|
||||
volatile IBSRSTR _IBSR; /* IIC Status Register; 0x000000E3 */
|
||||
volatile IBDRSTR _IBDR; /* IIC Data I/O Register; 0x000000E4 */
|
||||
volatile SPI1CR1STR _SPI1CR1; /* SPI 1 Control Register; 0x000000F0 */
|
||||
volatile SPI1CR2STR _SPI1CR2; /* SPI 1 Control Register 2; 0x000000F1 */
|
||||
volatile SPI1BRSTR _SPI1BR; /* SPI 1 Baud Rate Register; 0x000000F2 */
|
||||
volatile SPI1SRSTR _SPI1SR; /* SPI 1 Status Register; 0x000000F3 */
|
||||
volatile SPI1DRSTR _SPI1DR; /* SPI 1 Data Register; 0x000000F5 */
|
||||
volatile SPI2CR1STR _SPI2CR1; /* SPI 2 Control Register; 0x000000F8 */
|
||||
volatile SPI2CR2STR _SPI2CR2; /* SPI 2 Control Register 2; 0x000000F9 */
|
||||
volatile SPI2BRSTR _SPI2BR; /* SPI 2 Baud Rate Register; 0x000000FA */
|
||||
volatile SPI2SRSTR _SPI2SR; /* SPI 2 Status Register; 0x000000FB */
|
||||
volatile SPI2DRSTR _SPI2DR; /* SPI 2 Data Register; 0x000000FD */
|
||||
volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register; 0x00000100 */
|
||||
volatile FSECSTR _FSEC; /* Flash Security Register; 0x00000101 */
|
||||
volatile FCNFGSTR _FCNFG; /* Flash Configuration Register; 0x00000103 */
|
||||
volatile FPROTSTR _FPROT; /* Flash Protection Register; 0x00000104 */
|
||||
volatile FSTATSTR _FSTAT; /* Flash Status Register; 0x00000105 */
|
||||
volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register; 0x00000106 */
|
||||
volatile ECLKDIVSTR _ECLKDIV; /* EEPROM Clock Divider Register; 0x00000110 */
|
||||
volatile ECNFGSTR _ECNFG; /* EEPROM Configuration Register; 0x00000113 */
|
||||
volatile EPROTSTR _EPROT; /* EEPROM Protection Register; 0x00000114 */
|
||||
volatile ESTATSTR _ESTAT; /* EEPROM Status Register; 0x00000115 */
|
||||
volatile ECMDSTR _ECMD; /* EEPROM Command Buffer and Register; 0x00000116 */
|
||||
volatile ATD1STAT0STR _ATD1STAT0; /* ATD 1 Status Register 0; 0x00000126 */
|
||||
volatile ATD1TEST1STR _ATD1TEST1; /* ATD1 Test Register; 0x00000129 */
|
||||
volatile ATD1STAT1STR _ATD1STAT1; /* ATD 1 Status Register 1; 0x0000012B */
|
||||
volatile ATD1DIENSTR _ATD1DIEN; /* ATD 1 Input Enable Register; 0x0000012D */
|
||||
volatile PORTAD1STR _PORTAD1; /* Port AD1 Register; 0x0000012F */
|
||||
volatile CAN0CTL0STR _CAN0CTL0; /* MSCAN 0 Control 0 Register; 0x00000140 */
|
||||
volatile CAN0CTL1STR _CAN0CTL1; /* MSCAN 0 Control 1 Register; 0x00000141 */
|
||||
volatile CAN0BTR0STR _CAN0BTR0; /* MSCAN 0 Bus Timing Register 0; 0x00000142 */
|
||||
volatile CAN0BTR1STR _CAN0BTR1; /* MSCAN 0 Bus Timing Register 1; 0x00000143 */
|
||||
volatile CAN0RFLGSTR _CAN0RFLG; /* MSCAN 0 Receiver Flag Register; 0x00000144 */
|
||||
volatile CAN0RIERSTR _CAN0RIER; /* MSCAN 0 Receiver Interrupt Enable Register; 0x00000145 */
|
||||
volatile CAN0TFLGSTR _CAN0TFLG; /* MSCAN 0 Transmitter Flag Register; 0x00000146 */
|
||||
volatile CAN0TIERSTR _CAN0TIER; /* MSCAN 0 Transmitter Interrupt Enable Register; 0x00000147 */
|
||||
volatile CAN0TARQSTR _CAN0TARQ; /* MSCAN 0 Transmitter Message Abort Request; 0x00000148 */
|
||||
volatile CAN0TAAKSTR _CAN0TAAK; /* MSCAN 0 Transmitter Message Abort Control; 0x00000149 */
|
||||
volatile CAN0TBSELSTR _CAN0TBSEL; /* MSCAN 0 Transmit Buffer Selection; 0x0000014A */
|
||||
volatile CAN0IDACSTR _CAN0IDAC; /* MSCAN 0 Identifier Acceptance Control Register; 0x0000014B */
|
||||
volatile CAN0RXERRSTR _CAN0RXERR; /* MSCAN 0 Receive Error Counter Register; 0x0000014E */
|
||||
volatile CAN0TXERRSTR _CAN0TXERR; /* MSCAN 0 Transmit Error Counter Register; 0x0000014F */
|
||||
volatile CAN0IDAR0STR _CAN0IDAR0; /* MSCAN 0 Identifier Acceptance Register 0; 0x00000150 */
|
||||
volatile CAN0IDAR1STR _CAN0IDAR1; /* MSCAN 0 Identifier Acceptance Register 1; 0x00000151 */
|
||||
volatile CAN0IDAR2STR _CAN0IDAR2; /* MSCAN 0 Identifier Acceptance Register 2; 0x00000152 */
|
||||
volatile CAN0IDAR3STR _CAN0IDAR3; /* MSCAN 0 Identifier Acceptance Register 3; 0x00000153 */
|
||||
volatile CAN0IDMR0STR _CAN0IDMR0; /* MSCAN 0 Identifier Mask Register 0; 0x00000154 */
|
||||
volatile CAN0IDMR1STR _CAN0IDMR1; /* MSCAN 0 Identifier Mask Register 1; 0x00000155 */
|
||||
volatile CAN0IDMR2STR _CAN0IDMR2; /* MSCAN 0 Identifier Mask Register 2; 0x00000156 */
|
||||
volatile CAN0IDMR3STR _CAN0IDMR3; /* MSCAN 0 Identifier Mask Register 3; 0x00000157 */
|
||||
volatile CAN0IDAR4STR _CAN0IDAR4; /* MSCAN 0 Identifier Acceptance Register 4; 0x00000158 */
|
||||
volatile CAN0IDAR5STR _CAN0IDAR5; /* MSCAN 0 Identifier Acceptance Register 5; 0x00000159 */
|
||||
volatile CAN0IDAR6STR _CAN0IDAR6; /* MSCAN 0 Identifier Acceptance Register 6; 0x0000015A */
|
||||
volatile CAN0IDAR7STR _CAN0IDAR7; /* MSCAN 0 Identifier Acceptance Register 7; 0x0000015B */
|
||||
volatile CAN0IDMR4STR _CAN0IDMR4; /* MSCAN 0 Identifier Mask Register 4; 0x0000015C */
|
||||
volatile CAN0IDMR5STR _CAN0IDMR5; /* MSCAN 0 Identifier Mask Register 5; 0x0000015D */
|
||||
volatile CAN0IDMR6STR _CAN0IDMR6; /* MSCAN 0 Identifier Mask Register 6; 0x0000015E */
|
||||
volatile CAN0IDMR7STR _CAN0IDMR7; /* MSCAN 0 Identifier Mask Register 7; 0x0000015F */
|
||||
volatile CAN0RXIDR0STR _CAN0RXIDR0; /* MSCAN 0 Receive Identifier Register 0; 0x00000160 */
|
||||
volatile CAN0RXIDR1STR _CAN0RXIDR1; /* MSCAN 0 Receive Identifier Register 1; 0x00000161 */
|
||||
volatile CAN0RXIDR2STR _CAN0RXIDR2; /* MSCAN 0 Receive Identifier Register 2; 0x00000162 */
|
||||
volatile CAN0RXIDR3STR _CAN0RXIDR3; /* MSCAN 0 Receive Identifier Register 3; 0x00000163 */
|
||||
volatile CAN0RXDSR0STR _CAN0RXDSR0; /* MSCAN 0 Receive Data Segment Register 0; 0x00000164 */
|
||||
volatile CAN0RXDSR1STR _CAN0RXDSR1; /* MSCAN 0 Receive Data Segment Register 1; 0x00000165 */
|
||||
volatile CAN0RXDSR2STR _CAN0RXDSR2; /* MSCAN 0 Receive Data Segment Register 2; 0x00000166 */
|
||||
volatile CAN0RXDSR3STR _CAN0RXDSR3; /* MSCAN 0 Receive Data Segment Register 3; 0x00000167 */
|
||||
volatile CAN0RXDSR4STR _CAN0RXDSR4; /* MSCAN 0 Receive Data Segment Register 4; 0x00000168 */
|
||||
volatile CAN0RXDSR5STR _CAN0RXDSR5; /* MSCAN 0 Receive Data Segment Register 5; 0x00000169 */
|
||||
volatile CAN0RXDSR6STR _CAN0RXDSR6; /* MSCAN 0 Receive Data Segment Register 6; 0x0000016A */
|
||||
volatile CAN0RXDSR7STR _CAN0RXDSR7; /* MSCAN 0 Receive Data Segment Register 7; 0x0000016B */
|
||||
volatile CAN0RXDLRSTR _CAN0RXDLR; /* MSCAN 0 Receive Data Length Register; 0x0000016C */
|
||||
volatile CAN0TXIDR0STR _CAN0TXIDR0; /* MSCAN 0 Transmit Identifier Register 0; 0x00000170 */
|
||||
volatile CAN0TXIDR1STR _CAN0TXIDR1; /* MSCAN 0 Transmit Identifier Register 1; 0x00000171 */
|
||||
volatile CAN0TXIDR2STR _CAN0TXIDR2; /* MSCAN 0 Transmit Identifier Register 2; 0x00000172 */
|
||||
volatile CAN0TXIDR3STR _CAN0TXIDR3; /* MSCAN 0 Transmit Identifier Register 3; 0x00000173 */
|
||||
volatile CAN0TXDSR0STR _CAN0TXDSR0; /* MSCAN 0 Transmit Data Segment Register 0; 0x00000174 */
|
||||
volatile CAN0TXDSR1STR _CAN0TXDSR1; /* MSCAN 0 Transmit Data Segment Register 1; 0x00000175 */
|
||||
volatile CAN0TXDSR2STR _CAN0TXDSR2; /* MSCAN 0 Transmit Data Segment Register 2; 0x00000176 */
|
||||
volatile CAN0TXDSR3STR _CAN0TXDSR3; /* MSCAN 0 Transmit Data Segment Register 3; 0x00000177 */
|
||||
volatile CAN0TXDSR4STR _CAN0TXDSR4; /* MSCAN 0 Transmit Data Segment Register 4; 0x00000178 */
|
||||
volatile CAN0TXDSR5STR _CAN0TXDSR5; /* MSCAN 0 Transmit Data Segment Register 5; 0x00000179 */
|
||||
volatile CAN0TXDSR6STR _CAN0TXDSR6; /* MSCAN 0 Transmit Data Segment Register 6; 0x0000017A */
|
||||
volatile CAN0TXDSR7STR _CAN0TXDSR7; /* MSCAN 0 Transmit Data Segment Register 7; 0x0000017B */
|
||||
volatile CAN0TXDLRSTR _CAN0TXDLR; /* MSCAN 0 Transmit Data Length Register; 0x0000017C */
|
||||
volatile CAN0TXTBPRSTR _CAN0TXTBPR; /* MSCAN 0 Transmit Buffer Priority; 0x0000017D */
|
||||
volatile PTTSTR _PTT; /* Port T I/O Register; 0x00000240 */
|
||||
volatile PTITSTR _PTIT; /* Port T Input Register; 0x00000241 */
|
||||
volatile DDRTSTR _DDRT; /* Port T Data Direction Register; 0x00000242 */
|
||||
volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register; 0x00000243 */
|
||||
volatile PERTSTR _PERT; /* Port T Pull Device Enable Register; 0x00000244 */
|
||||
volatile PPSTSTR _PPST; /* Port T Polarity Select Register; 0x00000245 */
|
||||
volatile PTSSTR _PTS; /* Port S I/O Register; 0x00000248 */
|
||||
volatile PTISSTR _PTIS; /* Port S Input Register; 0x00000249 */
|
||||
volatile DDRSSTR _DDRS; /* Port S Data Direction Register; 0x0000024A */
|
||||
volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register; 0x0000024B */
|
||||
volatile PERSSTR _PERS; /* Port S Pull Device Enable Register; 0x0000024C */
|
||||
volatile PPSSSTR _PPSS; /* Port S Polarity Select Register; 0x0000024D */
|
||||
volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register; 0x0000024E */
|
||||
volatile PTMSTR _PTM; /* Port M I/O Register; 0x00000250 */
|
||||
volatile PTIMSTR _PTIM; /* Port M Input Register; 0x00000251 */
|
||||
volatile DDRMSTR _DDRM; /* Port M Data Direction Register; 0x00000252 */
|
||||
volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register; 0x00000253 */
|
||||
volatile PERMSTR _PERM; /* Port M Pull Device Enable Register; 0x00000254 */
|
||||
volatile PPSMSTR _PPSM; /* Port M Polarity Select Register; 0x00000255 */
|
||||
volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register; 0x00000256 */
|
||||
volatile MODRRSTR _MODRR; /* Module Routing Register; 0x00000257 */
|
||||
volatile PTPSTR _PTP; /* Port P I/O Register; 0x00000258 */
|
||||
volatile PTIPSTR _PTIP; /* Port P Input Register; 0x00000259 */
|
||||
volatile DDRPSTR _DDRP; /* Port P Data Direction Register; 0x0000025A */
|
||||
volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register; 0x0000025B */
|
||||
volatile PERPSTR _PERP; /* Port P Pull Device Enable Register; 0x0000025C */
|
||||
volatile PPSPSTR _PPSP; /* Port P Polarity Select Register; 0x0000025D */
|
||||
volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register; 0x0000025E */
|
||||
volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register; 0x0000025F */
|
||||
volatile PTHSTR _PTH; /* Port H I/O Register; 0x00000260 */
|
||||
volatile PTIHSTR _PTIH; /* Port H Input Register; 0x00000261 */
|
||||
volatile DDRHSTR _DDRH; /* Port H Data Direction Register; 0x00000262 */
|
||||
volatile RDRHSTR _RDRH; /* Port H Reduced Drive Register; 0x00000263 */
|
||||
volatile PERHSTR _PERH; /* Port H Pull Device Enable Register; 0x00000264 */
|
||||
volatile PPSHSTR _PPSH; /* Port H Polarity Select Register; 0x00000265 */
|
||||
volatile PIEHSTR _PIEH; /* Port H Interrupt Enable Register; 0x00000266 */
|
||||
volatile PIFHSTR _PIFH; /* Port H Interrupt Flag Register; 0x00000267 */
|
||||
volatile PTJSTR _PTJ; /* Port J I/O Register; 0x00000268 */
|
||||
volatile PTIJSTR _PTIJ; /* Port J Input Register; 0x00000269 */
|
||||
volatile DDRJSTR _DDRJ; /* Port J Data Direction Register; 0x0000026A */
|
||||
volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register; 0x0000026B */
|
||||
volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register; 0x0000026C */
|
||||
volatile PPSJSTR _PPSJ; /* Port J Polarity Select Register; 0x0000026D */
|
||||
volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register; 0x0000026E */
|
||||
volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register; 0x0000026F */
|
||||
volatile CAN4CTL0STR _CAN4CTL0; /* MSCAN4 Control 0 Register; 0x00000280 */
|
||||
volatile CAN4CTL1STR _CAN4CTL1; /* MSCAN4 Control 1 Register; 0x00000281 */
|
||||
volatile CAN4BTR0STR _CAN4BTR0; /* MSCAN4 Bus Timing Register 0; 0x00000282 */
|
||||
volatile CAN4BTR1STR _CAN4BTR1; /* MSCAN4 Bus Timing Register 1; 0x00000283 */
|
||||
volatile CAN4RFLGSTR _CAN4RFLG; /* MSCAN4 Receiver Flag Register; 0x00000284 */
|
||||
volatile CAN4RIERSTR _CAN4RIER; /* MSCAN4 Receiver Interrupt Enable Register; 0x00000285 */
|
||||
volatile CAN4TFLGSTR _CAN4TFLG; /* MSCAN4 Transmitter Flag Register; 0x00000286 */
|
||||
volatile CAN4TIERSTR _CAN4TIER; /* MSCAN4 Transmitter Interrupt Enable Register; 0x00000287 */
|
||||
volatile CAN4TARQSTR _CAN4TARQ; /* MSCAN 4 Transmitter Message Abort Request; 0x00000288 */
|
||||
volatile CAN4TAAKSTR _CAN4TAAK; /* MSCAN4 Transmitter Message Abort Control; 0x00000289 */
|
||||
volatile CAN4TBSELSTR _CAN4TBSEL; /* MSCAN4 Transmit Buffer Selection; 0x0000028A */
|
||||
volatile CAN4IDACSTR _CAN4IDAC; /* MSCAN4 Identifier Acceptance Control Register; 0x0000028B */
|
||||
volatile CAN4RXERRSTR _CAN4RXERR; /* MSCAN4 Receive Error Counter Register; 0x0000028E */
|
||||
volatile CAN4TXERRSTR _CAN4TXERR; /* MSCAN4 Transmit Error Counter Register; 0x0000028F */
|
||||
volatile CAN4IDAR0STR _CAN4IDAR0; /* MSCAN4 Identifier Acceptance Register 0; 0x00000290 */
|
||||
volatile CAN4IDAR1STR _CAN4IDAR1; /* MSCAN4 Identifier Acceptance Register 1; 0x00000291 */
|
||||
volatile CAN4IDAR2STR _CAN4IDAR2; /* MSCAN4 Identifier Acceptance Register 2; 0x00000292 */
|
||||
volatile CAN4IDAR3STR _CAN4IDAR3; /* MSCAN4 Identifier Acceptance Register 3; 0x00000293 */
|
||||
volatile CAN4IDMR0STR _CAN4IDMR0; /* MSCAN4 Identifier Mask Register 0; 0x00000294 */
|
||||
volatile CAN4IDMR1STR _CAN4IDMR1; /* MSCAN4 Identifier Mask Register 1; 0x00000295 */
|
||||
volatile CAN4IDMR2STR _CAN4IDMR2; /* MSCAN4 Identifier Mask Register 2; 0x00000296 */
|
||||
volatile CAN4IDMR3STR _CAN4IDMR3; /* MSCAN4 Identifier Mask Register 3; 0x00000297 */
|
||||
volatile CAN4IDAR4STR _CAN4IDAR4; /* MSCAN4 Identifier Acceptance Register 4; 0x00000298 */
|
||||
volatile CAN4IDAR5STR _CAN4IDAR5; /* MSCAN4 Identifier Acceptance Register 5; 0x00000299 */
|
||||
volatile CAN4IDAR6STR _CAN4IDAR6; /* MSCAN4 Identifier Acceptance Register 6; 0x0000029A */
|
||||
volatile CAN4IDAR7STR _CAN4IDAR7; /* MSCAN4 Identifier Acceptance Register 7; 0x0000029B */
|
||||
volatile CAN4IDMR4STR _CAN4IDMR4; /* MSCAN4 Identifier Mask Register 4; 0x0000029C */
|
||||
volatile CAN4IDMR5STR _CAN4IDMR5; /* MSCAN4 Identifier Mask Register 5; 0x0000029D */
|
||||
volatile CAN4IDMR6STR _CAN4IDMR6; /* MSCAN4 Identifier Mask Register 6; 0x0000029E */
|
||||
volatile CAN4IDMR7STR _CAN4IDMR7; /* MSCAN4 Identifier Mask Register 7; 0x0000029F */
|
||||
volatile CAN4RXIDR0STR _CAN4RXIDR0; /* MSCAN4 Receive Identifier Register 0; 0x000002A0 */
|
||||
volatile CAN4RXIDR1STR _CAN4RXIDR1; /* MSCAN4 Receive Identifier Register 1; 0x000002A1 */
|
||||
volatile CAN4RXIDR2STR _CAN4RXIDR2; /* MSCAN4 Receive Identifier Register 2; 0x000002A2 */
|
||||
volatile CAN4RXIDR3STR _CAN4RXIDR3; /* MSCAN4 Receive Identifier Register 3; 0x000002A3 */
|
||||
volatile CAN4RXDSR0STR _CAN4RXDSR0; /* MSCAN4 Receive Data Segment Register 0; 0x000002A4 */
|
||||
volatile CAN4RXDSR1STR _CAN4RXDSR1; /* MSCAN4 Receive Data Segment Register 1; 0x000002A5 */
|
||||
volatile CAN4RXDSR2STR _CAN4RXDSR2; /* MSCAN4 Receive Data Segment Register 2; 0x000002A6 */
|
||||
volatile CAN4RXDSR3STR _CAN4RXDSR3; /* MSCAN4 Receive Data Segment Register 3; 0x000002A7 */
|
||||
volatile CAN4RXDSR4STR _CAN4RXDSR4; /* MSCAN4 Receive Data Segment Register 4; 0x000002A8 */
|
||||
volatile CAN4RXDSR5STR _CAN4RXDSR5; /* MSCAN4 Receive Data Segment Register 5; 0x000002A9 */
|
||||
volatile CAN4RXDSR6STR _CAN4RXDSR6; /* MSCAN4 Receive Data Segment Register 6; 0x000002AA */
|
||||
volatile CAN4RXDSR7STR _CAN4RXDSR7; /* MSCAN4 Receive Data Segment Register 7; 0x000002AB */
|
||||
volatile CAN4RXDLRSTR _CAN4RXDLR; /* MSCAN4 Receive Data Length Register; 0x000002AC */
|
||||
volatile CAN4TXIDR0STR _CAN4TXIDR0; /* MSCAN4 Transmit Identifier Register 0; 0x000002B0 */
|
||||
volatile CAN4TXIDR1STR _CAN4TXIDR1; /* MSCAN4 Transmit Identifier Register 1; 0x000002B1 */
|
||||
volatile CAN4TXIDR2STR _CAN4TXIDR2; /* MSCAN4 Transmit Identifier Register 2; 0x000002B2 */
|
||||
volatile CAN4TXIDR3STR _CAN4TXIDR3; /* MSCAN4 Transmit Identifier Register 3; 0x000002B3 */
|
||||
volatile CAN4TXDSR0STR _CAN4TXDSR0; /* MSCAN4 Transmit Data Segment Register 0; 0x000002B4 */
|
||||
volatile CAN4TXDSR1STR _CAN4TXDSR1; /* MSCAN4 Transmit Data Segment Register 1; 0x000002B5 */
|
||||
volatile CAN4TXDSR2STR _CAN4TXDSR2; /* MSCAN4 Transmit Data Segment Register 2; 0x000002B6 */
|
||||
volatile CAN4TXDSR3STR _CAN4TXDSR3; /* MSCAN4 Transmit Data Segment Register 3; 0x000002B7 */
|
||||
volatile CAN4TXDSR4STR _CAN4TXDSR4; /* MSCAN4 Transmit Data Segment Register 4; 0x000002B8 */
|
||||
volatile CAN4TXDSR5STR _CAN4TXDSR5; /* MSCAN4 Transmit Data Segment Register 5; 0x000002B9 */
|
||||
volatile CAN4TXDSR6STR _CAN4TXDSR6; /* MSCAN4 Transmit Data Segment Register 6; 0x000002BA */
|
||||
volatile CAN4TXDSR7STR _CAN4TXDSR7; /* MSCAN4 Transmit Data Segment Register 7; 0x000002BB */
|
||||
volatile CAN4TXDLRSTR _CAN4TXDLR; /* MSCAN4 Transmit Data Length Register; 0x000002BC */
|
||||
volatile CAN4TXTBPRSTR _CAN4TXTBPR; /* MSCAN4 Transmit Transmit Buffer Priority; 0x000002BD */
|
||||
/* NVFPROT3 - macro for reading non volatile register Non volatile Block 3 Flash Protection Register; 0x0000FF0A */
|
||||
/* NVFPROT2 - macro for reading non volatile register Non volatile Block 2 Flash Protection Register; 0x0000FF0B */
|
||||
/* NVFPROT1 - macro for reading non volatile register Non volatile Block 1 Flash Protection Register; 0x0000FF0C */
|
||||
/* NVFPROT0 - macro for reading non volatile register Non volatile Block 0 Flash Protection Register; 0x0000FF0D */
|
||||
/* NVFSEC - macro for reading non volatile register Non volatile Flash Security Register; 0x0000FF0F */
|
||||
|
||||
|
||||
/* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */
|
||||
volatile PORTABSTR _PORTAB; /* Port AB Register; 0x00000000 */
|
||||
volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register; 0x00000002 */
|
||||
volatile PARTIDSTR _PARTID; /* Part ID Register; 0x0000001A */
|
||||
volatile TCNTSTR _TCNT; /* Timer Count Register; 0x00000044 */
|
||||
volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0; 0x00000050 */
|
||||
volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1; 0x00000052 */
|
||||
volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2; 0x00000054 */
|
||||
volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3; 0x00000056 */
|
||||
volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4; 0x00000058 */
|
||||
volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5; 0x0000005A */
|
||||
volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6; 0x0000005C */
|
||||
volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7; 0x0000005E */
|
||||
volatile PACN32STR _PACN32; /* Pulse Accumulators Count 32 Register; 0x00000062 */
|
||||
volatile PACN10STR _PACN10; /* Pulse Accumulators Count 10 Register; 0x00000064 */
|
||||
volatile PA32HSTR _PA32H; /* 8-Bit Pulse Accumulators Holding 32 Register; 0x00000072 */
|
||||
volatile PA10HSTR _PA10H; /* 8-Bit Pulse Accumulators Holding 10 Register; 0x00000074 */
|
||||
volatile MCCNTSTR _MCCNT; /* Modulus Down-Counter Count Register; 0x00000076 */
|
||||
volatile TC0HSTR _TC0H; /* Timer Input Capture Holding Registers 0; 0x00000078 */
|
||||
volatile TC1HSTR _TC1H; /* Timer Input Capture Holding Registers 1; 0x0000007A */
|
||||
volatile TC2HSTR _TC2H; /* Timer Input Capture Holding Registers 2; 0x0000007C */
|
||||
volatile TC3HSTR _TC3H; /* Timer Input Capture Holding Registers 3; 0x0000007E */
|
||||
volatile ATD0CTL23STR _ATD0CTL23; /* ATD 0 Control Register 23; 0x00000082 */
|
||||
volatile ATD0CTL45STR _ATD0CTL45; /* ATD 0 Control Register 45; 0x00000084 */
|
||||
volatile ATD0DR0STR _ATD0DR0; /* ATD 0 Conversion Result Register 0; 0x00000090 */
|
||||
volatile ATD0DR1STR _ATD0DR1; /* ATD 0 Conversion Result Register 1; 0x00000092 */
|
||||
volatile ATD0DR2STR _ATD0DR2; /* ATD 0 Conversion Result Register 2; 0x00000094 */
|
||||
volatile ATD0DR3STR _ATD0DR3; /* ATD 0 Conversion Result Register 3; 0x00000096 */
|
||||
volatile ATD0DR4STR _ATD0DR4; /* ATD 0 Conversion Result Register 4; 0x00000098 */
|
||||
volatile ATD0DR5STR _ATD0DR5; /* ATD 0 Conversion Result Register 5; 0x0000009A */
|
||||
volatile ATD0DR6STR _ATD0DR6; /* ATD 0 Conversion Result Register 6; 0x0000009C */
|
||||
volatile ATD0DR7STR _ATD0DR7; /* ATD 0 Conversion Result Register 7; 0x0000009E */
|
||||
volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register; 0x000000AC */
|
||||
volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register; 0x000000AE */
|
||||
volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register; 0x000000B0 */
|
||||
volatile PWMCNT67STR _PWMCNT67; /* PWM Channel Counter 67 Register; 0x000000B2 */
|
||||
volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register; 0x000000B4 */
|
||||
volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register; 0x000000B6 */
|
||||
volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register; 0x000000B8 */
|
||||
volatile PWMPER67STR _PWMPER67; /* PWM Channel Period 67 Register; 0x000000BA */
|
||||
volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register; 0x000000BC */
|
||||
volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register; 0x000000BE */
|
||||
volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register; 0x000000C0 */
|
||||
volatile PWMDTY67STR _PWMDTY67; /* PWM Channel Duty 67 Register; 0x000000C2 */
|
||||
volatile SCI0BDSTR _SCI0BD; /* SCI 0 Baud Rate Register; 0x000000C8 */
|
||||
volatile SCI1BDSTR _SCI1BD; /* SCI 1 Baud Rate Register; 0x000000D0 */
|
||||
volatile ATD1CTL23STR _ATD1CTL23; /* ATD 1 Control Register 23; 0x00000122 */
|
||||
volatile ATD1CTL45STR _ATD1CTL45; /* ATD 1 Control Register 45; 0x00000124 */
|
||||
volatile ATD1DR0STR _ATD1DR0; /* ATD 1 Conversion Result Register 0; 0x00000130 */
|
||||
volatile ATD1DR1STR _ATD1DR1; /* ATD 1 Conversion Result Register 1; 0x00000132 */
|
||||
volatile ATD1DR2STR _ATD1DR2; /* ATD 1 Conversion Result Register 2; 0x00000134 */
|
||||
volatile ATD1DR3STR _ATD1DR3; /* ATD 1 Conversion Result Register 3; 0x00000136 */
|
||||
volatile ATD1DR4STR _ATD1DR4; /* ATD 1 Conversion Result Register 4; 0x00000138 */
|
||||
volatile ATD1DR5STR _ATD1DR5; /* ATD 1 Conversion Result Register 5; 0x0000013A */
|
||||
volatile ATD1DR6STR _ATD1DR6; /* ATD 1 Conversion Result Register 6; 0x0000013C */
|
||||
volatile ATD1DR7STR _ATD1DR7; /* ATD 1 Conversion Result Register 7; 0x0000013E */
|
||||
volatile CAN0RXTSRSTR _CAN0RXTSR; /* MSCAN 0 Receive Time Stamp Register; 0x0000016E */
|
||||
volatile CAN0TXTSRSTR _CAN0TXTSR; /* MSCAN 0 Transmit Time Stamp Register; 0x0000017E */
|
||||
volatile CAN4RXTSRSTR _CAN4RXTSR; /* MSCAN 4 Receive Time Stamp Register; 0x000002AE */
|
||||
volatile CAN4TXTSRSTR _CAN4TXTSR; /* MSCAN 4 Transmit Time Stamp Register; 0x000002BE */
|
||||
/* BAKEY0 - macro for reading non volatile register Backdoor Access Key 0; 0x0000FF00 */
|
||||
/* BAKEY1 - macro for reading non volatile register Backdoor Access Key 1; 0x0000FF02 */
|
||||
/* BAKEY2 - macro for reading non volatile register Backdoor Access Key 2; 0x0000FF04 */
|
||||
/* BAKEY3 - macro for reading non volatile register Backdoor Access Key 3; 0x0000FF06 */
|
||||
|
||||
/*lint -restore */
|
||||
|
||||
/* EOF */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,136 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Boot\main.c
|
||||
* \brief Bootloader application source file.
|
||||
* \ingroup Boot_HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
#include "derivative.h" /* MCU registers */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
static void Init(void);
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief This is the entry point for the bootloader application and is called
|
||||
** by the reset interrupt vector after the C-startup routines executed.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void main(void)
|
||||
{
|
||||
/* ##Vg TODO basic bootloader works, including the timed backdoor. next steps:
|
||||
* - bootloader activation from user program
|
||||
* - support for CAN
|
||||
*/
|
||||
|
||||
/* initialize the microcontroller */
|
||||
Init();
|
||||
|
||||
/* initialize the bootloader */
|
||||
BootInit();
|
||||
|
||||
/* start the infinite program loop */
|
||||
while (1)
|
||||
{
|
||||
/* run the bootloader task */
|
||||
BootTask();
|
||||
}
|
||||
} /*** end of main ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the microcontroller.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void Init(void)
|
||||
{
|
||||
blt_int8u synrCnt;
|
||||
blt_int8u refdvCnt;
|
||||
blt_int32u systemSpeed;
|
||||
blt_bool found = BLT_FALSE;
|
||||
|
||||
/* disable the global interrupts. the bootloader does not use interrupts and this
|
||||
* automatically prevents a jump back into the user program in case it was not
|
||||
* properly uninitialized.
|
||||
*/
|
||||
asm("sei");
|
||||
/* initialize the system clock to BOOT_CPU_SYSTEM_SPEED_KHZ by configuring the PLL
|
||||
* subsystem. first default to oscillator clock source.
|
||||
*/
|
||||
CLKSEL &= ~0x80;
|
||||
/* search for the synthesizer and reference divider values. the equation to use is:
|
||||
* PLLCLK = EXTCLK * ( (synrCnt + 1) / (refdvCnt + 1) ), with synrCnt can be from
|
||||
* 0..63 and refdvCnt can be from 0..15
|
||||
*/
|
||||
for (refdvCnt = 0; refdvCnt <= 15; refdvCnt++)
|
||||
{
|
||||
for (synrCnt = 0; synrCnt <= 63; synrCnt++)
|
||||
{
|
||||
/* calculate the system speed with these SYNR and REFDV settings */
|
||||
systemSpeed = ((blt_int32u)BOOT_CPU_XTAL_SPEED_KHZ * (synrCnt+1)) / (refdvCnt+1);
|
||||
/* was a match found? */
|
||||
if (systemSpeed == BOOT_CPU_SYSTEM_SPEED_KHZ)
|
||||
{
|
||||
/* flag success */
|
||||
found = BLT_TRUE;
|
||||
/* break loop */
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (found == BLT_TRUE)
|
||||
{
|
||||
/* break this loop as well if a match was already found */
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* flag error if no match was found */
|
||||
ASSERT_RT(found == BLT_TRUE);
|
||||
/* set the synthesizer and reference divider values */
|
||||
SYNR = synrCnt;
|
||||
REFDV = refdvCnt;
|
||||
/* wait for PLL to lock */
|
||||
while((CRGFLG & 0x08) == 0)
|
||||
{
|
||||
;
|
||||
}
|
||||
/* select PLL as clock source */
|
||||
CLKSEL |= 0x80;
|
||||
} /*** end of Init ***/
|
||||
|
||||
|
||||
/*********************************** end of main.c *************************************/
|
||||
Binary file not shown.
|
|
@ -0,0 +1,21 @@
|
|||
S0730000433A5C576F726B5C736F6674776172655C4F70656E424C545C5461726765745C44656D6F5C48435331325F457662706C75735F447261676F6E3132705F436F646557617272696F725C50726F675C62696E5C64656D6F70726F675F657662706C75735F647261676F6E3132702E616273F8
|
||||
S2240FC000FEC033FDC031270E35ED31EC3169700434FB310326F2FEC035EC31270BED3118B8
|
||||
S2240FC0200A30700434F920F13DCF110007D206C1120001C037C1AC1100004C3B16C147CC4A
|
||||
S2240FC040FEF06C8015F300003A3D7900CB7900CA7900C87900C9C61A873B5AC85BC94CCB6A
|
||||
S2240FC060043A3DF611002612CC110116C0A7042135C6017B11007911423DF6114287C3004E
|
||||
S2240FC0800187C3110116C0A704211B721142F61142F111012610791100F6110204A107F6F6
|
||||
S2240FC0A01103260207953D3B4FCC2009D6CFEE806B00C60121C7303D10EF3D1C026A021D5B
|
||||
S2240FC0C00268024C03014D01013D1B9C16C16A6C826E80B31146B7C5F21145B21144CD018D
|
||||
S2240FC0E0F435B746C7873BB754B76516C18E251FF61143260AC6017B11434C0101200679B0
|
||||
S2240FC10011434D0101EC827C1146EC807C11441B843D16C12016C04A16C0CA16C06320F806
|
||||
S2240FC12016C0BB16C12906C0B816C1474C4001C6015B4EDC44C35DC05C504C4C014C46806A
|
||||
S2240FC140C787B74506C16379004C79004679004D79004079004779004879004979004A79D5
|
||||
S2240FC160004B3D7C114A7E11483DFC114AFE11483DC6015B4EDC50C35DC05C50FC114AFED0
|
||||
S2240FC180114816C1A77C114A7E11480B20FEAC84270E34B7C5E285A284B7C510FB30200262
|
||||
S2120FC1A0AE82311B84054004A401083D00004A
|
||||
S2240FE77EAA55C18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CE5
|
||||
S2240FE79EC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18C77
|
||||
S2240FE7BEC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18CC18C57
|
||||
S2240FE7DEC18CC18CC18CC18CC18CC18CC18CC18CC171C18CC18CC18CC18CC18CC18CC18C52
|
||||
S2060FE7FEC0291C
|
||||
S9030000FC
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,169 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\boot.c
|
||||
* \brief Demo program bootloader interface source file.
|
||||
* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Bootloader activation function.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void BootActivate(void)
|
||||
{
|
||||
void (*near pEntryFromProgFnc)(void);
|
||||
|
||||
/* stop the timer from generating interrupts */
|
||||
TimeDeinit();
|
||||
/* set pointer to the address of function reset_connected_handler in the bootloader. */
|
||||
pEntryFromProgFnc = (void(*)(void))(0xfef0);
|
||||
/* call EntryFromProg to activate the bootloader. */
|
||||
pEntryFromProgFnc();
|
||||
} /*** end of BootActivate ***/
|
||||
|
||||
|
||||
#if (BOOT_COM_UART_ENABLE > 0)
|
||||
/****************************************************************************************
|
||||
* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
static unsigned char UartReceiveByte(unsigned char *data);
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the UART communication interface.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void BootComInit(void)
|
||||
{
|
||||
unsigned short baudrate_sbr0_12;
|
||||
|
||||
/* reset the SCI subsystem's configuration, which automatically configures it for
|
||||
* 8,n,1 communication mode.
|
||||
*/
|
||||
SCI0CR2 = 0;
|
||||
SCI0CR1 = 0;
|
||||
SCI0BDH = 0;
|
||||
SCI0BDL = 0;
|
||||
/* configure the baudrate from BOOT_COM_UART_BAUDRATE */
|
||||
baudrate_sbr0_12 = (BOOT_CPU_SYSTEM_SPEED_KHZ * 1000ul) / 16 / BOOT_COM_UART_BAUDRATE;
|
||||
baudrate_sbr0_12 &= SCI0BD_SBR_MASK;
|
||||
/* write first MSB then LSB for the baudrate to latch */
|
||||
SCI0BDH = (unsigned char)(baudrate_sbr0_12 >> 8);
|
||||
SCI0BDL = (unsigned char)baudrate_sbr0_12;
|
||||
/* enable the receiver */
|
||||
SCI0CR2 |= (SCI0CR2_RE_MASK);
|
||||
} /*** end of BootComInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Receives the CONNECT request from the host, which indicates that the
|
||||
** bootloader should be activated and, if so, activates it.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void BootComCheckActivationRequest(void)
|
||||
{
|
||||
static unsigned char xcpCtoReqPacket[BOOT_COM_UART_RX_MAX_DATA+1];
|
||||
static unsigned char xcpCtoRxLength;
|
||||
static unsigned char xcpCtoRxInProgress = 0;
|
||||
|
||||
/* start of cto packet received? */
|
||||
if (xcpCtoRxInProgress == 0)
|
||||
{
|
||||
/* store the message length when received */
|
||||
if (UartReceiveByte(&xcpCtoReqPacket[0]) == 1)
|
||||
{
|
||||
/* indicate that a cto packet is being received */
|
||||
xcpCtoRxInProgress = 1;
|
||||
|
||||
/* reset packet data count */
|
||||
xcpCtoRxLength = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* store the next packet byte */
|
||||
if (UartReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1)
|
||||
{
|
||||
/* increment the packet data count */
|
||||
xcpCtoRxLength++;
|
||||
|
||||
/* check to see if the entire packet was received */
|
||||
if (xcpCtoRxLength == xcpCtoReqPacket[0])
|
||||
{
|
||||
/* done with cto packet reception */
|
||||
xcpCtoRxInProgress = 0;
|
||||
|
||||
/* check if this was an XCP CONNECT command */
|
||||
if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00))
|
||||
{
|
||||
/* connection request received so start the bootloader */
|
||||
BootActivate();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
} /*** end of BootComCheckActivationRequest ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Receives a communication interface byte if one is present.
|
||||
** \param data Pointer to byte where the data is to be stored.
|
||||
** \return 1 if a byte was received, 0 otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static unsigned char UartReceiveByte(unsigned char *data)
|
||||
{
|
||||
/* check if a new byte was received by means of the RDRF-bit */
|
||||
if((SCI0SR1 & SCI0SR1_RDRF_MASK) != 0)
|
||||
{
|
||||
/* store the received byte */
|
||||
data[0] = SCI0DRL;
|
||||
/* inform caller of the newly received byte */
|
||||
return 1;
|
||||
}
|
||||
/* inform caller that no new data was received */
|
||||
return 0;
|
||||
} /*** end of UartReceiveByte ***/
|
||||
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
||||
|
||||
|
||||
/*********************************** end of boot.c *************************************/
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\boot.h
|
||||
* \brief Demo program bootloader interface header file.
|
||||
* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef BOOT_H
|
||||
#define BOOT_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void BootComInit(void);
|
||||
void BootComCheckActivationRequest(void);
|
||||
|
||||
|
||||
#endif /* BOOT_H */
|
||||
/*********************************** end of boot.h *************************************/
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
// ver 1.1 (7/7/04)
|
||||
// HCS12X Core erasing + unsecuring command file:
|
||||
// These commands mass erase the chip then program the security byte to 0xFE (unsecured state).
|
||||
|
||||
// Evaluate the clock divider to set in ECLKDIV/FCLKDIV registers:
|
||||
|
||||
DEFINEVALUEDLG "Information required to unsecure the device" "CLKDIV" 0x49 "To unsecure the device, the command script needs \nthe correct value for ECLKDIV/FCLKDIV onchip\nregisters.\nIf the bus frequency is less than 10 MHz, the value\nto store in ECLKDIV/FCLKDIV is equal to:\n \"bus frequency (kHz) / 175\"\n\nIf the bus frequency is higher than 10 MHz, the value\nto store in ECLKDIV/FCLKDIV is equal to:\n \" bus frequency (kHz) / 1400 + 64\"\n(+64 (0x40) is to set PRDIV8 flag)\n\nDatasheet proposed values:\n\nbus frequency\t\tE/FCLKDIV value (decimal)\n\n 16 \tMHz\t\t73\n 8 \tMHz\t\t39\n 4 \tMHz\t\t19\n 2 \tMHz\t\t9\n 1 \tMHz\t\t4\n"
|
||||
|
||||
// An average programming clock of 175 kHz is chosen.
|
||||
|
||||
// If the oscillator frequency is less than 10 MHz, the value to store
|
||||
// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 175 ".
|
||||
|
||||
// If the oscillator frequency is higher than 10 MHz, the value to store
|
||||
// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 1400 + 0x40 (to set PRDIV8 flag)".
|
||||
|
||||
// Datasheet proposed values:
|
||||
//
|
||||
// oscillator frequency ECLKDIV/FCLKDIV value (hexadecimal)
|
||||
//
|
||||
// 16 MHz $49
|
||||
// 8 MHz $27
|
||||
// 4 MHz $13
|
||||
// 2 MHz $9
|
||||
// 1 MHz $4
|
||||
|
||||
|
||||
FLASH RELEASE // do not interact with regular flash programming monitor
|
||||
|
||||
//mass erase flash
|
||||
reset
|
||||
wb 0x03c 0x00 //disable cop
|
||||
wait 20
|
||||
wb 0x100 CLKDIV // set FCLKDIV clock divider
|
||||
wb 0x104 0xFF // FPROT all protection disabled
|
||||
wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register
|
||||
wb 0x102 0x00 // clear the WRALL bit in FTSTMOD
|
||||
wb 0x105 0x02
|
||||
wb 0x102 0x10 // set the WRALL bit in FTSTMOD to affect all blocks
|
||||
ww 0x108 0xFFFE
|
||||
ww 0x10A 0xFFFF
|
||||
wb 0x106 0x41 // write MASS ERASE command in FCMD register
|
||||
wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command
|
||||
wait 20 // wait for command to complete
|
||||
|
||||
//mass erase eeprom
|
||||
wb 0x110 CLKDIV // set ECLKDV clock divider
|
||||
wb 0x114 0xFF // EPROT all protection disabled
|
||||
wb 0x115 0x30 // clear PVIOL and ACCERR in ESTAT register
|
||||
wb 0x112 0x00 // clear the WRALL bit in FTSTMOD
|
||||
wb 0x115 0x02
|
||||
ww 0x118 0x0C00 // write to EADDR eeprom address register
|
||||
ww 0x11A 0x0000 // write to EDATA eeprom data register
|
||||
wb 0x116 0x41 // write MASS ERASE command in ECMD register
|
||||
wb 0x115 0x80 // clear CBEIF in ESTAT register to execute the command
|
||||
wait 20 // wait for command to complete
|
||||
|
||||
//reprogram Security byte to Unsecure state
|
||||
reset
|
||||
wb 0x03c 0x00 //disable cop
|
||||
wait 20
|
||||
wb 0x102 0x00 // clear the WRALL bit in FTSTMOD
|
||||
wb 0x105 0x02
|
||||
wb 0x100 CLKDIV // set FCLKDIV clock divider
|
||||
wb 0x100 CLKDIV // set FCLKDIV clock divider
|
||||
wb 0x104 0xFF // FPROT all protection disabled
|
||||
wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register
|
||||
wb 0x102 0x00 // clear the WRALL bit in FTSTMOD
|
||||
wb 0x105 0x02
|
||||
ww 0xFF0E 0xFFFE // write security byte to "Unsecured" state
|
||||
wb 0x106 0x20 // write MEMORY PROGRAM command in FCMD register
|
||||
wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command
|
||||
wait 20 // wait for command to complete
|
||||
|
||||
reset
|
||||
|
||||
undef CLKDIV // undefine variable
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
// After load the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// Before load the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// After reset the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// At startup the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// After programming the flash, the commands written below will be executed
|
||||
|
|
@ -0,0 +1 @@
|
|||
// Before programming the flash, the commands written below will be executed
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
/* s-record file with linear addresses for MicroBoot/OpenBLT */
|
||||
OPENFILE "%ABS_FILE%.sx"
|
||||
format = motorola
|
||||
busWidth = 1
|
||||
len = 0x4000
|
||||
|
||||
/* logical non banked flash at $4000 and $C000 to physical */
|
||||
origin = 0x004000
|
||||
destination = 0x0F8000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
origin = 0x00C000
|
||||
destination = 0x0FC000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
/* 512 kB banked flash addresses to linear */
|
||||
origin = 0x208000
|
||||
destination = 0x080000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x218000
|
||||
destination = 0x084000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x228000
|
||||
destination = 0x088000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x238000
|
||||
destination = 0x08C000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x248000
|
||||
destination = 0x090000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x258000
|
||||
destination = 0x094000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x268000
|
||||
destination = 0x098000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x278000
|
||||
destination = 0x09C000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x288000
|
||||
destination = 0x0A0000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x298000
|
||||
destination = 0x0A4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x2A8000
|
||||
destination = 0x0A8000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x2B8000
|
||||
destination = 0x0AC000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x2C8000
|
||||
destination = 0x0B0000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x2D8000
|
||||
destination = 0x0B4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x2E8000
|
||||
destination = 0x0B8000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x2F8000
|
||||
destination = 0x0BC000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x308000
|
||||
destination = 0x0C0000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x318000
|
||||
destination = 0x0C4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x328000
|
||||
destination = 0x0C8000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x338000
|
||||
destination = 0x0CC000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x348000
|
||||
destination = 0x0D0000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x358000
|
||||
destination = 0x0D4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x368000
|
||||
destination = 0x0D8000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x378000
|
||||
destination = 0x0DC000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x388000
|
||||
destination = 0x0E0000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x398000
|
||||
destination = 0x0E4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x3A8000
|
||||
destination = 0x0E8000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x3B8000
|
||||
destination = 0x0EC000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x3C8000
|
||||
destination = 0x0F0000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x3D8000
|
||||
destination = 0x0F4000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x3E8000
|
||||
destination = 0x0F8000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
origin = 0x3F8000
|
||||
destination = 0x0FC000
|
||||
SENDBYTE 1 "%ABS_FILE%"
|
||||
|
||||
CLOSE
|
||||
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\header.h
|
||||
* \brief Generic header file.
|
||||
* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef HEADER_H
|
||||
#define HEADER_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "../Boot/blt_conf.h" /* bootloader configuration */
|
||||
#include "boot.h" /* bootloader interface driver */
|
||||
#include "irq.h" /* IRQ driver */
|
||||
#include "led.h" /* LED driver */
|
||||
#include "time.h" /* Timer driver */
|
||||
#include "derivative.h" /* MCU registers */
|
||||
|
||||
|
||||
|
||||
#endif /* HEADER_H */
|
||||
/*********************************** end of header.h ***********************************/
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
OPEN source 0 0 60 39
|
||||
Source < attributes MARKS off
|
||||
OPEN assembly 60 0 40 31
|
||||
Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C
|
||||
OPEN procedure 0 39 60 17
|
||||
Procedure < attributes VALUES on,TYPES off
|
||||
OPEN register 60 31 40 25
|
||||
Register < attributes FORMAT AUTO,COMPLEMENT None
|
||||
OPEN memory 60 56 40 22
|
||||
Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80
|
||||
OPEN data 0 56 60 22
|
||||
Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16
|
||||
OPEN data 0 78 60 22
|
||||
Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16
|
||||
OPEN command 60 78 40 22
|
||||
Command < attributes CACHESIZE 1000
|
||||
bckcolor 50331647
|
||||
font 'Courier New' 9 BLACK
|
||||
AUTOSIZE on
|
||||
ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory
|
||||
Binary file not shown.
|
|
@ -0,0 +1,84 @@
|
|||
[STARTUP]
|
||||
CPUTARGETTYPE=0
|
||||
USE_CYCLONEPRO_RELAYS=0
|
||||
PORT=21
|
||||
interface_selection=1
|
||||
SHOWDIALOG=0
|
||||
IO_DELAY_SET=1
|
||||
frequency_has_changed_old_io_delay_cnt=29
|
||||
CyclonePro_poweroffonexit=0
|
||||
CyclonePro_currentvoltage=255
|
||||
CyclonePro_PowerDownDelay=250
|
||||
CyclonePro_PowerUpDelay=250
|
||||
IO_DELAY_CNT=29
|
||||
PCI_DELAY=0
|
||||
RESET_DELAY=0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
[Environment Variables]
|
||||
GENPATH={Project}..\src;{Compiler}lib\hc12c\src;{Compiler}lib\hc12c\include;{Compiler}lib\hc12c\lib;{Compiler}lib\xgatec\src;{Compiler}lib\xgatec\include;{Compiler}lib\xgatec\lib
|
||||
LIBPATH={Compiler}lib\hc12c\include;{Compiler}lib\xgatec\include
|
||||
OBJPATH={Project}..\bin
|
||||
TEXTPATH={Project}..\bin
|
||||
ABSPATH={Project}..\bin
|
||||
|
||||
[HI-WAVE]
|
||||
Target=icd12
|
||||
Layout=C_layout.hwl
|
||||
LoadDialogOptions=AUTOERASEANDFLASH RUNANDSTOPAFTERLOAD="main"
|
||||
CPU=HC12
|
||||
MainFrame=2,3,-1,-1,-1,-1,200,200,1640,967
|
||||
TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806
|
||||
AEFWarningDialog=FALSE
|
||||
|
||||
|
||||
|
||||
|
||||
[HC12MultilinkCyclonePro_GDI_SETTINGS]
|
||||
CMDFILE0=CMDFILE STARTUP ON ".\..\cmd\P&E_Multilink_USB_startup.cmd"
|
||||
CMDFILE1=CMDFILE RESET ON ".\..\cmd\P&E_Multilink_USB_reset.cmd"
|
||||
CMDFILE2=CMDFILE PRELOAD ON ".\..\cmd\P&E_Multilink_USB_preload.cmd"
|
||||
CMDFILE3=CMDFILE POSTLOAD ON ".\..\cmd\P&E_Multilink_USB_postload.cmd"
|
||||
CMDFILE4=CMDFILE VPPON ON ".\..\cmd\P&E_Multilink_USB_vppon.cmd"
|
||||
CMDFILE5=CMDFILE VPPOFF ON ".\..\cmd\P&E_Multilink_USB_vppoff.cmd"
|
||||
CMDFILE6=CMDFILE UNSECURE ON ".\..\cmd\P&E_Multilink_USB_erase_unsecure_hcs12.cmd"
|
||||
MCUID=0x03D9
|
||||
NV_PARAMETER_FILE=C:\Program Files (x86)\Freescale\CWS12v5.1\prog\FPP\mcu03D9.fpp
|
||||
NV_SAVE_WSP=0
|
||||
NV_AUTO_ID=1
|
||||
CHIPSECURE=CHIPSECURE SETUP 0xFF0F 0x3 0x2
|
||||
HWBPD_MCUID03D9_HWBPM0=HWBPM MODE AUTOMATIC BPM22BITS 0x28 SKIP_OFF
|
||||
HWBPD_MCUID03D9_BKPT_REMAP0=HWBPM REMAP_22BITS RANGE 0x4000 0x7FFF 0x3E
|
||||
HWBPD_MCUID03D9_BKPT_REMAP1=HWBPM REMAP_22BITS RANGE 0xC000 0xFFFF 0x3F
|
||||
HWBPD_MCUID03D9_HWBPM1=HWBPM SET16BITS 0x0 0x0 0x0 0x0
|
||||
HWBPD_MCUID03D9_HWBPM2=HWBPM SET22BITS 0x0 0x0 0x0 0x0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
[ICD12]
|
||||
COMSETTINGS=SETCOMM DRIVER NOPROTOCOL NOPERIODICAL
|
||||
SETCLKSW=0
|
||||
HOTPLUGGING=0
|
||||
DETECTRUNNING=0
|
||||
RESYNCONCOPRESET=0
|
||||
BDMAutoSpeed=0
|
||||
BDMClockSpeed=29
|
||||
HIGHIODELAYCONSTFORPLL=40
|
||||
|
||||
[PORT]
|
||||
IP=
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,106 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\irq.c
|
||||
* \brief IRQ driver source file.
|
||||
* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Local data definitions
|
||||
****************************************************************************************/
|
||||
/** \brief IRQ nesting counter . */
|
||||
static volatile unsigned long irqNesting=0;
|
||||
/** \brief Copy of CCR register. */
|
||||
static volatile unsigned char irqCCRregSave;
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Enables the generation IRQ interrupts. Typically called once during
|
||||
** software startup after completion of the initialization.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void IrqInterruptEnable(void)
|
||||
{
|
||||
/* enable the global interrupts */
|
||||
asm("cli");
|
||||
} /*** end of IrqInterruptEnable ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Disables the generation IRQ interrupts and stores information on
|
||||
** whether or not the interrupts were already disabled before explicitly
|
||||
** disabling them with this function. Normally used as a pair together
|
||||
** with IrqInterruptRestore during a critical section.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void IrqInterruptDisable(void)
|
||||
{
|
||||
if (irqNesting == 0)
|
||||
{
|
||||
asm
|
||||
{
|
||||
tpa
|
||||
sei
|
||||
staa irqCCRregSave
|
||||
}
|
||||
}
|
||||
irqNesting++;
|
||||
} /*** end of IrqInterruptDisable ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Restore the generation IRQ interrupts to the setting it had prior to
|
||||
** calling IrqInterruptDisable. Normally used as a pair together with
|
||||
** IrqInterruptDisable during a critical section.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void IrqInterruptRestore(void)
|
||||
{
|
||||
irqNesting--;
|
||||
if (irqNesting == 0)
|
||||
{
|
||||
asm
|
||||
{
|
||||
ldaa irqCCRregSave
|
||||
tap
|
||||
}
|
||||
}
|
||||
} /*** end of IrqInterruptRestore ***/
|
||||
|
||||
|
||||
/*********************************** end of irq.c **************************************/
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\irq.h
|
||||
* \brief IRQ driver header file.
|
||||
* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef IRQ_H
|
||||
#define IRQ_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void IrqInterruptEnable(void);
|
||||
void IrqInterruptDisable(void);
|
||||
void IrqInterruptRestore(void);
|
||||
|
||||
|
||||
#endif /* IRQ_H */
|
||||
/*********************************** end of irq.h **************************************/
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\led.c
|
||||
* \brief LED driver source file.
|
||||
* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Toggle interval time in milliseconds. */
|
||||
#define LED_TOGGLE_MS (500)
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the LED. The board doesn't have a dedicted LED so an
|
||||
** indicator on the LCD is used instead.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void LedInit(void)
|
||||
{
|
||||
/* enable LEDs connected to PORTB */
|
||||
DDRJ_DDRJ1 = 1;
|
||||
PTJ_PTJ1 = 0;
|
||||
/* configure PB0 as a digital output */
|
||||
DDRB_BIT0 = 1;
|
||||
/* turn off the LED by default */
|
||||
PORTB_BIT0 = 0;
|
||||
} /*** end of LedInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Toggles the LED at a fixed time interval.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void LedToggle(void)
|
||||
{
|
||||
static unsigned char led_toggle_state = 0;
|
||||
static unsigned long timer_counter_last = 0;
|
||||
unsigned long timer_counter_now;
|
||||
|
||||
/* check if toggle interval time passed */
|
||||
timer_counter_now = TimeGet();
|
||||
if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS)
|
||||
{
|
||||
/* not yet time to toggle */
|
||||
return;
|
||||
}
|
||||
|
||||
/* determine toggle action */
|
||||
if (led_toggle_state == 0)
|
||||
{
|
||||
led_toggle_state = 1;
|
||||
/* turn the LED on */
|
||||
PORTB_BIT0 = 1;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
led_toggle_state = 0;
|
||||
/* turn the LED off */
|
||||
PORTB_BIT0 = 0;
|
||||
}
|
||||
|
||||
/* store toggle time to determine next toggle interval */
|
||||
timer_counter_last = timer_counter_now;
|
||||
} /*** end of LedToggle ***/
|
||||
|
||||
|
||||
/*********************************** end of led.c **************************************/
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\led.h
|
||||
* \brief LED driver header file.
|
||||
* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef LED_H
|
||||
#define LED_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void LedInit(void);
|
||||
void LedToggle(void);
|
||||
|
||||
|
||||
#endif /* LED_H */
|
||||
/*********************************** end of led.h **************************************/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Note: This file is recreated by the project wizard whenever the MCU is
|
||||
* changed and should not be edited by hand
|
||||
*/
|
||||
|
||||
/* Include the derivative-specific header file */
|
||||
#include <mc9s12dg256.h>
|
||||
|
||||
#pragma LINK_INFO DERIVATIVE "mc9s12dg256"
|
||||
|
||||
|
|
@ -0,0 +1,366 @@
|
|||
/* Based on CPU DB MC9S12DG256_112, version 2.87.346 (RegistersPrg V2.28) */
|
||||
/* DataSheet : 9S12DT256DGV3/D V03.04 */
|
||||
|
||||
#include <mc9s12dg256.h>
|
||||
|
||||
/*lint -save -esym(765, *) */
|
||||
|
||||
|
||||
/* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */
|
||||
volatile PORTESTR _PORTE; /* Port E Register; 0x00000008 */
|
||||
volatile DDRESTR _DDRE; /* Port E Data Direction Register; 0x00000009 */
|
||||
volatile PEARSTR _PEAR; /* Port E Assignment Register; 0x0000000A */
|
||||
volatile MODESTR _MODE; /* Mode Register; 0x0000000B */
|
||||
volatile PUCRSTR _PUCR; /* Pull-Up Control Register; 0x0000000C */
|
||||
volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines; 0x0000000D */
|
||||
volatile EBICTLSTR _EBICTL; /* External Bus Interface Control; 0x0000000E */
|
||||
volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register; 0x00000010 */
|
||||
volatile INITRGSTR _INITRG; /* Initialization of Internal Registers Position Register; 0x00000011 */
|
||||
volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register; 0x00000012 */
|
||||
volatile MISCSTR _MISC; /* Miscellaneous System Control Register; 0x00000013 */
|
||||
volatile ITCRSTR _ITCR; /* Interrupt Test Control Register; 0x00000015 */
|
||||
volatile ITESTSTR _ITEST; /* Interrupt Test Register; 0x00000016 */
|
||||
volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero; 0x0000001C */
|
||||
volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One; 0x0000001D */
|
||||
volatile INTCRSTR _INTCR; /* Interrupt Control Register; 0x0000001E */
|
||||
volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt; 0x0000001F */
|
||||
volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0; 0x00000028 */
|
||||
volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1; 0x00000029 */
|
||||
volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register; 0x0000002A */
|
||||
volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register; 0x0000002B */
|
||||
volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register; 0x0000002C */
|
||||
volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register; 0x0000002D */
|
||||
volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register; 0x0000002E */
|
||||
volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register; 0x0000002F */
|
||||
volatile PPAGESTR _PPAGE; /* Page Index Register; 0x00000030 */
|
||||
volatile PORTKSTR _PORTK; /* Port K Data Register; 0x00000032 */
|
||||
volatile DDRKSTR _DDRK; /* Port K Data Direction Register; 0x00000033 */
|
||||
volatile SYNRSTR _SYNR; /* CRG Synthesizer Register; 0x00000034 */
|
||||
volatile REFDVSTR _REFDV; /* CRG Reference Divider Register; 0x00000035 */
|
||||
volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register; 0x00000037 */
|
||||
volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register; 0x00000038 */
|
||||
volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register; 0x00000039 */
|
||||
volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register; 0x0000003A */
|
||||
volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register; 0x0000003B */
|
||||
volatile COPCTLSTR _COPCTL; /* CRG COP Control Register; 0x0000003C */
|
||||
volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register; 0x0000003F */
|
||||
volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select; 0x00000040 */
|
||||
volatile CFORCSTR _CFORC; /* Timer Compare Force Register; 0x00000041 */
|
||||
volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register; 0x00000042 */
|
||||
volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register; 0x00000043 */
|
||||
volatile TSCR1STR _TSCR1; /* Timer System Control Register1; 0x00000046 */
|
||||
volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register; 0x00000047 */
|
||||
volatile TCTL1STR _TCTL1; /* Timer Control Register 1; 0x00000048 */
|
||||
volatile TCTL2STR _TCTL2; /* Timer Control Register 2; 0x00000049 */
|
||||
volatile TCTL3STR _TCTL3; /* Timer Control Register 3; 0x0000004A */
|
||||
volatile TCTL4STR _TCTL4; /* Timer Control Register 4; 0x0000004B */
|
||||
volatile TIESTR _TIE; /* Timer Interrupt Enable Register; 0x0000004C */
|
||||
volatile TSCR2STR _TSCR2; /* Timer System Control Register 2; 0x0000004D */
|
||||
volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1; 0x0000004E */
|
||||
volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2; 0x0000004F */
|
||||
volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register; 0x00000060 */
|
||||
volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register; 0x00000061 */
|
||||
volatile MCCTLSTR _MCCTL; /* Modulus Down Counter underflow; 0x00000066 */
|
||||
volatile MCFLGSTR _MCFLG; /* 16-Bit Modulus Down Counter Flag Register; 0x00000067 */
|
||||
volatile ICPARSTR _ICPAR; /* Input Control Pulse Accumulator Register; 0x00000068 */
|
||||
volatile DLYCTSTR _DLYCT; /* Delay Counter Control Register; 0x00000069 */
|
||||
volatile ICOVWSTR _ICOVW; /* Input Control Overwrite Register; 0x0000006A */
|
||||
volatile ICSYSSTR _ICSYS; /* Input Control System Control Register; 0x0000006B */
|
||||
volatile PBCTLSTR _PBCTL; /* 16-Bit Pulse Accumulator B Control Register; 0x00000070 */
|
||||
volatile PBFLGSTR _PBFLG; /* Pulse Accumulator B Flag Register; 0x00000071 */
|
||||
volatile ATD0STAT0STR _ATD0STAT0; /* ATD 0 Status Register 0; 0x00000086 */
|
||||
volatile ATD0TEST1STR _ATD0TEST1; /* ATD0 Test Register; 0x00000089 */
|
||||
volatile ATD0STAT1STR _ATD0STAT1; /* ATD 0 Status Register 1; 0x0000008B */
|
||||
volatile ATD0DIENSTR _ATD0DIEN; /* ATD 0 Input Enable Register; 0x0000008D */
|
||||
volatile PORTAD0STR _PORTAD0; /* Port AD0 Register; 0x0000008F */
|
||||
volatile PWMESTR _PWME; /* PWM Enable Register; 0x000000A0 */
|
||||
volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register; 0x000000A1 */
|
||||
volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register; 0x000000A2 */
|
||||
volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register; 0x000000A3 */
|
||||
volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register; 0x000000A4 */
|
||||
volatile PWMCTLSTR _PWMCTL; /* PWM Control Register; 0x000000A5 */
|
||||
volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register; 0x000000A8 */
|
||||
volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register; 0x000000A9 */
|
||||
volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register; 0x000000C4 */
|
||||
volatile SCI0CR1STR _SCI0CR1; /* SCI 0 Control Register 1; 0x000000CA */
|
||||
volatile SCI0CR2STR _SCI0CR2; /* SCI 0 Control Register 2; 0x000000CB */
|
||||
volatile SCI0SR1STR _SCI0SR1; /* SCI 0 Status Register 1; 0x000000CC */
|
||||
volatile SCI0SR2STR _SCI0SR2; /* SCI 0 Status Register 2; 0x000000CD */
|
||||
volatile SCI0DRHSTR _SCI0DRH; /* SCI 0 Data Register High; 0x000000CE */
|
||||
volatile SCI0DRLSTR _SCI0DRL; /* SCI 0 Data Register Low; 0x000000CF */
|
||||
volatile SCI1CR1STR _SCI1CR1; /* SCI 1 Control Register 1; 0x000000D2 */
|
||||
volatile SCI1CR2STR _SCI1CR2; /* SCI 1 Control Register 2; 0x000000D3 */
|
||||
volatile SCI1SR1STR _SCI1SR1; /* SCI 1 Status Register 1; 0x000000D4 */
|
||||
volatile SCI1SR2STR _SCI1SR2; /* SCI 1 Status Register 2; 0x000000D5 */
|
||||
volatile SCI1DRHSTR _SCI1DRH; /* SCI 1 Data Register High; 0x000000D6 */
|
||||
volatile SCI1DRLSTR _SCI1DRL; /* SCI 1 Data Register Low; 0x000000D7 */
|
||||
volatile SPI0CR1STR _SPI0CR1; /* SPI 0 Control Register; 0x000000D8 */
|
||||
volatile SPI0CR2STR _SPI0CR2; /* SPI 0 Control Register 2; 0x000000D9 */
|
||||
volatile SPI0BRSTR _SPI0BR; /* SPI 0 Baud Rate Register; 0x000000DA */
|
||||
volatile SPI0SRSTR _SPI0SR; /* SPI 0 Status Register; 0x000000DB */
|
||||
volatile SPI0DRSTR _SPI0DR; /* SPI 0 Data Register; 0x000000DD */
|
||||
volatile IBADSTR _IBAD; /* IIC Address Register; 0x000000E0 */
|
||||
volatile IBFDSTR _IBFD; /* IIC Frequency Divider Register; 0x000000E1 */
|
||||
volatile IBCRSTR _IBCR; /* IIC Control Register; 0x000000E2 */
|
||||
volatile IBSRSTR _IBSR; /* IIC Status Register; 0x000000E3 */
|
||||
volatile IBDRSTR _IBDR; /* IIC Data I/O Register; 0x000000E4 */
|
||||
volatile SPI1CR1STR _SPI1CR1; /* SPI 1 Control Register; 0x000000F0 */
|
||||
volatile SPI1CR2STR _SPI1CR2; /* SPI 1 Control Register 2; 0x000000F1 */
|
||||
volatile SPI1BRSTR _SPI1BR; /* SPI 1 Baud Rate Register; 0x000000F2 */
|
||||
volatile SPI1SRSTR _SPI1SR; /* SPI 1 Status Register; 0x000000F3 */
|
||||
volatile SPI1DRSTR _SPI1DR; /* SPI 1 Data Register; 0x000000F5 */
|
||||
volatile SPI2CR1STR _SPI2CR1; /* SPI 2 Control Register; 0x000000F8 */
|
||||
volatile SPI2CR2STR _SPI2CR2; /* SPI 2 Control Register 2; 0x000000F9 */
|
||||
volatile SPI2BRSTR _SPI2BR; /* SPI 2 Baud Rate Register; 0x000000FA */
|
||||
volatile SPI2SRSTR _SPI2SR; /* SPI 2 Status Register; 0x000000FB */
|
||||
volatile SPI2DRSTR _SPI2DR; /* SPI 2 Data Register; 0x000000FD */
|
||||
volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register; 0x00000100 */
|
||||
volatile FSECSTR _FSEC; /* Flash Security Register; 0x00000101 */
|
||||
volatile FCNFGSTR _FCNFG; /* Flash Configuration Register; 0x00000103 */
|
||||
volatile FPROTSTR _FPROT; /* Flash Protection Register; 0x00000104 */
|
||||
volatile FSTATSTR _FSTAT; /* Flash Status Register; 0x00000105 */
|
||||
volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register; 0x00000106 */
|
||||
volatile ECLKDIVSTR _ECLKDIV; /* EEPROM Clock Divider Register; 0x00000110 */
|
||||
volatile ECNFGSTR _ECNFG; /* EEPROM Configuration Register; 0x00000113 */
|
||||
volatile EPROTSTR _EPROT; /* EEPROM Protection Register; 0x00000114 */
|
||||
volatile ESTATSTR _ESTAT; /* EEPROM Status Register; 0x00000115 */
|
||||
volatile ECMDSTR _ECMD; /* EEPROM Command Buffer and Register; 0x00000116 */
|
||||
volatile ATD1STAT0STR _ATD1STAT0; /* ATD 1 Status Register 0; 0x00000126 */
|
||||
volatile ATD1TEST1STR _ATD1TEST1; /* ATD1 Test Register; 0x00000129 */
|
||||
volatile ATD1STAT1STR _ATD1STAT1; /* ATD 1 Status Register 1; 0x0000012B */
|
||||
volatile ATD1DIENSTR _ATD1DIEN; /* ATD 1 Input Enable Register; 0x0000012D */
|
||||
volatile PORTAD1STR _PORTAD1; /* Port AD1 Register; 0x0000012F */
|
||||
volatile CAN0CTL0STR _CAN0CTL0; /* MSCAN 0 Control 0 Register; 0x00000140 */
|
||||
volatile CAN0CTL1STR _CAN0CTL1; /* MSCAN 0 Control 1 Register; 0x00000141 */
|
||||
volatile CAN0BTR0STR _CAN0BTR0; /* MSCAN 0 Bus Timing Register 0; 0x00000142 */
|
||||
volatile CAN0BTR1STR _CAN0BTR1; /* MSCAN 0 Bus Timing Register 1; 0x00000143 */
|
||||
volatile CAN0RFLGSTR _CAN0RFLG; /* MSCAN 0 Receiver Flag Register; 0x00000144 */
|
||||
volatile CAN0RIERSTR _CAN0RIER; /* MSCAN 0 Receiver Interrupt Enable Register; 0x00000145 */
|
||||
volatile CAN0TFLGSTR _CAN0TFLG; /* MSCAN 0 Transmitter Flag Register; 0x00000146 */
|
||||
volatile CAN0TIERSTR _CAN0TIER; /* MSCAN 0 Transmitter Interrupt Enable Register; 0x00000147 */
|
||||
volatile CAN0TARQSTR _CAN0TARQ; /* MSCAN 0 Transmitter Message Abort Request; 0x00000148 */
|
||||
volatile CAN0TAAKSTR _CAN0TAAK; /* MSCAN 0 Transmitter Message Abort Control; 0x00000149 */
|
||||
volatile CAN0TBSELSTR _CAN0TBSEL; /* MSCAN 0 Transmit Buffer Selection; 0x0000014A */
|
||||
volatile CAN0IDACSTR _CAN0IDAC; /* MSCAN 0 Identifier Acceptance Control Register; 0x0000014B */
|
||||
volatile CAN0RXERRSTR _CAN0RXERR; /* MSCAN 0 Receive Error Counter Register; 0x0000014E */
|
||||
volatile CAN0TXERRSTR _CAN0TXERR; /* MSCAN 0 Transmit Error Counter Register; 0x0000014F */
|
||||
volatile CAN0IDAR0STR _CAN0IDAR0; /* MSCAN 0 Identifier Acceptance Register 0; 0x00000150 */
|
||||
volatile CAN0IDAR1STR _CAN0IDAR1; /* MSCAN 0 Identifier Acceptance Register 1; 0x00000151 */
|
||||
volatile CAN0IDAR2STR _CAN0IDAR2; /* MSCAN 0 Identifier Acceptance Register 2; 0x00000152 */
|
||||
volatile CAN0IDAR3STR _CAN0IDAR3; /* MSCAN 0 Identifier Acceptance Register 3; 0x00000153 */
|
||||
volatile CAN0IDMR0STR _CAN0IDMR0; /* MSCAN 0 Identifier Mask Register 0; 0x00000154 */
|
||||
volatile CAN0IDMR1STR _CAN0IDMR1; /* MSCAN 0 Identifier Mask Register 1; 0x00000155 */
|
||||
volatile CAN0IDMR2STR _CAN0IDMR2; /* MSCAN 0 Identifier Mask Register 2; 0x00000156 */
|
||||
volatile CAN0IDMR3STR _CAN0IDMR3; /* MSCAN 0 Identifier Mask Register 3; 0x00000157 */
|
||||
volatile CAN0IDAR4STR _CAN0IDAR4; /* MSCAN 0 Identifier Acceptance Register 4; 0x00000158 */
|
||||
volatile CAN0IDAR5STR _CAN0IDAR5; /* MSCAN 0 Identifier Acceptance Register 5; 0x00000159 */
|
||||
volatile CAN0IDAR6STR _CAN0IDAR6; /* MSCAN 0 Identifier Acceptance Register 6; 0x0000015A */
|
||||
volatile CAN0IDAR7STR _CAN0IDAR7; /* MSCAN 0 Identifier Acceptance Register 7; 0x0000015B */
|
||||
volatile CAN0IDMR4STR _CAN0IDMR4; /* MSCAN 0 Identifier Mask Register 4; 0x0000015C */
|
||||
volatile CAN0IDMR5STR _CAN0IDMR5; /* MSCAN 0 Identifier Mask Register 5; 0x0000015D */
|
||||
volatile CAN0IDMR6STR _CAN0IDMR6; /* MSCAN 0 Identifier Mask Register 6; 0x0000015E */
|
||||
volatile CAN0IDMR7STR _CAN0IDMR7; /* MSCAN 0 Identifier Mask Register 7; 0x0000015F */
|
||||
volatile CAN0RXIDR0STR _CAN0RXIDR0; /* MSCAN 0 Receive Identifier Register 0; 0x00000160 */
|
||||
volatile CAN0RXIDR1STR _CAN0RXIDR1; /* MSCAN 0 Receive Identifier Register 1; 0x00000161 */
|
||||
volatile CAN0RXIDR2STR _CAN0RXIDR2; /* MSCAN 0 Receive Identifier Register 2; 0x00000162 */
|
||||
volatile CAN0RXIDR3STR _CAN0RXIDR3; /* MSCAN 0 Receive Identifier Register 3; 0x00000163 */
|
||||
volatile CAN0RXDSR0STR _CAN0RXDSR0; /* MSCAN 0 Receive Data Segment Register 0; 0x00000164 */
|
||||
volatile CAN0RXDSR1STR _CAN0RXDSR1; /* MSCAN 0 Receive Data Segment Register 1; 0x00000165 */
|
||||
volatile CAN0RXDSR2STR _CAN0RXDSR2; /* MSCAN 0 Receive Data Segment Register 2; 0x00000166 */
|
||||
volatile CAN0RXDSR3STR _CAN0RXDSR3; /* MSCAN 0 Receive Data Segment Register 3; 0x00000167 */
|
||||
volatile CAN0RXDSR4STR _CAN0RXDSR4; /* MSCAN 0 Receive Data Segment Register 4; 0x00000168 */
|
||||
volatile CAN0RXDSR5STR _CAN0RXDSR5; /* MSCAN 0 Receive Data Segment Register 5; 0x00000169 */
|
||||
volatile CAN0RXDSR6STR _CAN0RXDSR6; /* MSCAN 0 Receive Data Segment Register 6; 0x0000016A */
|
||||
volatile CAN0RXDSR7STR _CAN0RXDSR7; /* MSCAN 0 Receive Data Segment Register 7; 0x0000016B */
|
||||
volatile CAN0RXDLRSTR _CAN0RXDLR; /* MSCAN 0 Receive Data Length Register; 0x0000016C */
|
||||
volatile CAN0TXIDR0STR _CAN0TXIDR0; /* MSCAN 0 Transmit Identifier Register 0; 0x00000170 */
|
||||
volatile CAN0TXIDR1STR _CAN0TXIDR1; /* MSCAN 0 Transmit Identifier Register 1; 0x00000171 */
|
||||
volatile CAN0TXIDR2STR _CAN0TXIDR2; /* MSCAN 0 Transmit Identifier Register 2; 0x00000172 */
|
||||
volatile CAN0TXIDR3STR _CAN0TXIDR3; /* MSCAN 0 Transmit Identifier Register 3; 0x00000173 */
|
||||
volatile CAN0TXDSR0STR _CAN0TXDSR0; /* MSCAN 0 Transmit Data Segment Register 0; 0x00000174 */
|
||||
volatile CAN0TXDSR1STR _CAN0TXDSR1; /* MSCAN 0 Transmit Data Segment Register 1; 0x00000175 */
|
||||
volatile CAN0TXDSR2STR _CAN0TXDSR2; /* MSCAN 0 Transmit Data Segment Register 2; 0x00000176 */
|
||||
volatile CAN0TXDSR3STR _CAN0TXDSR3; /* MSCAN 0 Transmit Data Segment Register 3; 0x00000177 */
|
||||
volatile CAN0TXDSR4STR _CAN0TXDSR4; /* MSCAN 0 Transmit Data Segment Register 4; 0x00000178 */
|
||||
volatile CAN0TXDSR5STR _CAN0TXDSR5; /* MSCAN 0 Transmit Data Segment Register 5; 0x00000179 */
|
||||
volatile CAN0TXDSR6STR _CAN0TXDSR6; /* MSCAN 0 Transmit Data Segment Register 6; 0x0000017A */
|
||||
volatile CAN0TXDSR7STR _CAN0TXDSR7; /* MSCAN 0 Transmit Data Segment Register 7; 0x0000017B */
|
||||
volatile CAN0TXDLRSTR _CAN0TXDLR; /* MSCAN 0 Transmit Data Length Register; 0x0000017C */
|
||||
volatile CAN0TXTBPRSTR _CAN0TXTBPR; /* MSCAN 0 Transmit Buffer Priority; 0x0000017D */
|
||||
volatile PTTSTR _PTT; /* Port T I/O Register; 0x00000240 */
|
||||
volatile PTITSTR _PTIT; /* Port T Input Register; 0x00000241 */
|
||||
volatile DDRTSTR _DDRT; /* Port T Data Direction Register; 0x00000242 */
|
||||
volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register; 0x00000243 */
|
||||
volatile PERTSTR _PERT; /* Port T Pull Device Enable Register; 0x00000244 */
|
||||
volatile PPSTSTR _PPST; /* Port T Polarity Select Register; 0x00000245 */
|
||||
volatile PTSSTR _PTS; /* Port S I/O Register; 0x00000248 */
|
||||
volatile PTISSTR _PTIS; /* Port S Input Register; 0x00000249 */
|
||||
volatile DDRSSTR _DDRS; /* Port S Data Direction Register; 0x0000024A */
|
||||
volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register; 0x0000024B */
|
||||
volatile PERSSTR _PERS; /* Port S Pull Device Enable Register; 0x0000024C */
|
||||
volatile PPSSSTR _PPSS; /* Port S Polarity Select Register; 0x0000024D */
|
||||
volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register; 0x0000024E */
|
||||
volatile PTMSTR _PTM; /* Port M I/O Register; 0x00000250 */
|
||||
volatile PTIMSTR _PTIM; /* Port M Input Register; 0x00000251 */
|
||||
volatile DDRMSTR _DDRM; /* Port M Data Direction Register; 0x00000252 */
|
||||
volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register; 0x00000253 */
|
||||
volatile PERMSTR _PERM; /* Port M Pull Device Enable Register; 0x00000254 */
|
||||
volatile PPSMSTR _PPSM; /* Port M Polarity Select Register; 0x00000255 */
|
||||
volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register; 0x00000256 */
|
||||
volatile MODRRSTR _MODRR; /* Module Routing Register; 0x00000257 */
|
||||
volatile PTPSTR _PTP; /* Port P I/O Register; 0x00000258 */
|
||||
volatile PTIPSTR _PTIP; /* Port P Input Register; 0x00000259 */
|
||||
volatile DDRPSTR _DDRP; /* Port P Data Direction Register; 0x0000025A */
|
||||
volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register; 0x0000025B */
|
||||
volatile PERPSTR _PERP; /* Port P Pull Device Enable Register; 0x0000025C */
|
||||
volatile PPSPSTR _PPSP; /* Port P Polarity Select Register; 0x0000025D */
|
||||
volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register; 0x0000025E */
|
||||
volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register; 0x0000025F */
|
||||
volatile PTHSTR _PTH; /* Port H I/O Register; 0x00000260 */
|
||||
volatile PTIHSTR _PTIH; /* Port H Input Register; 0x00000261 */
|
||||
volatile DDRHSTR _DDRH; /* Port H Data Direction Register; 0x00000262 */
|
||||
volatile RDRHSTR _RDRH; /* Port H Reduced Drive Register; 0x00000263 */
|
||||
volatile PERHSTR _PERH; /* Port H Pull Device Enable Register; 0x00000264 */
|
||||
volatile PPSHSTR _PPSH; /* Port H Polarity Select Register; 0x00000265 */
|
||||
volatile PIEHSTR _PIEH; /* Port H Interrupt Enable Register; 0x00000266 */
|
||||
volatile PIFHSTR _PIFH; /* Port H Interrupt Flag Register; 0x00000267 */
|
||||
volatile PTJSTR _PTJ; /* Port J I/O Register; 0x00000268 */
|
||||
volatile PTIJSTR _PTIJ; /* Port J Input Register; 0x00000269 */
|
||||
volatile DDRJSTR _DDRJ; /* Port J Data Direction Register; 0x0000026A */
|
||||
volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register; 0x0000026B */
|
||||
volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register; 0x0000026C */
|
||||
volatile PPSJSTR _PPSJ; /* Port J Polarity Select Register; 0x0000026D */
|
||||
volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register; 0x0000026E */
|
||||
volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register; 0x0000026F */
|
||||
volatile CAN4CTL0STR _CAN4CTL0; /* MSCAN4 Control 0 Register; 0x00000280 */
|
||||
volatile CAN4CTL1STR _CAN4CTL1; /* MSCAN4 Control 1 Register; 0x00000281 */
|
||||
volatile CAN4BTR0STR _CAN4BTR0; /* MSCAN4 Bus Timing Register 0; 0x00000282 */
|
||||
volatile CAN4BTR1STR _CAN4BTR1; /* MSCAN4 Bus Timing Register 1; 0x00000283 */
|
||||
volatile CAN4RFLGSTR _CAN4RFLG; /* MSCAN4 Receiver Flag Register; 0x00000284 */
|
||||
volatile CAN4RIERSTR _CAN4RIER; /* MSCAN4 Receiver Interrupt Enable Register; 0x00000285 */
|
||||
volatile CAN4TFLGSTR _CAN4TFLG; /* MSCAN4 Transmitter Flag Register; 0x00000286 */
|
||||
volatile CAN4TIERSTR _CAN4TIER; /* MSCAN4 Transmitter Interrupt Enable Register; 0x00000287 */
|
||||
volatile CAN4TARQSTR _CAN4TARQ; /* MSCAN 4 Transmitter Message Abort Request; 0x00000288 */
|
||||
volatile CAN4TAAKSTR _CAN4TAAK; /* MSCAN4 Transmitter Message Abort Control; 0x00000289 */
|
||||
volatile CAN4TBSELSTR _CAN4TBSEL; /* MSCAN4 Transmit Buffer Selection; 0x0000028A */
|
||||
volatile CAN4IDACSTR _CAN4IDAC; /* MSCAN4 Identifier Acceptance Control Register; 0x0000028B */
|
||||
volatile CAN4RXERRSTR _CAN4RXERR; /* MSCAN4 Receive Error Counter Register; 0x0000028E */
|
||||
volatile CAN4TXERRSTR _CAN4TXERR; /* MSCAN4 Transmit Error Counter Register; 0x0000028F */
|
||||
volatile CAN4IDAR0STR _CAN4IDAR0; /* MSCAN4 Identifier Acceptance Register 0; 0x00000290 */
|
||||
volatile CAN4IDAR1STR _CAN4IDAR1; /* MSCAN4 Identifier Acceptance Register 1; 0x00000291 */
|
||||
volatile CAN4IDAR2STR _CAN4IDAR2; /* MSCAN4 Identifier Acceptance Register 2; 0x00000292 */
|
||||
volatile CAN4IDAR3STR _CAN4IDAR3; /* MSCAN4 Identifier Acceptance Register 3; 0x00000293 */
|
||||
volatile CAN4IDMR0STR _CAN4IDMR0; /* MSCAN4 Identifier Mask Register 0; 0x00000294 */
|
||||
volatile CAN4IDMR1STR _CAN4IDMR1; /* MSCAN4 Identifier Mask Register 1; 0x00000295 */
|
||||
volatile CAN4IDMR2STR _CAN4IDMR2; /* MSCAN4 Identifier Mask Register 2; 0x00000296 */
|
||||
volatile CAN4IDMR3STR _CAN4IDMR3; /* MSCAN4 Identifier Mask Register 3; 0x00000297 */
|
||||
volatile CAN4IDAR4STR _CAN4IDAR4; /* MSCAN4 Identifier Acceptance Register 4; 0x00000298 */
|
||||
volatile CAN4IDAR5STR _CAN4IDAR5; /* MSCAN4 Identifier Acceptance Register 5; 0x00000299 */
|
||||
volatile CAN4IDAR6STR _CAN4IDAR6; /* MSCAN4 Identifier Acceptance Register 6; 0x0000029A */
|
||||
volatile CAN4IDAR7STR _CAN4IDAR7; /* MSCAN4 Identifier Acceptance Register 7; 0x0000029B */
|
||||
volatile CAN4IDMR4STR _CAN4IDMR4; /* MSCAN4 Identifier Mask Register 4; 0x0000029C */
|
||||
volatile CAN4IDMR5STR _CAN4IDMR5; /* MSCAN4 Identifier Mask Register 5; 0x0000029D */
|
||||
volatile CAN4IDMR6STR _CAN4IDMR6; /* MSCAN4 Identifier Mask Register 6; 0x0000029E */
|
||||
volatile CAN4IDMR7STR _CAN4IDMR7; /* MSCAN4 Identifier Mask Register 7; 0x0000029F */
|
||||
volatile CAN4RXIDR0STR _CAN4RXIDR0; /* MSCAN4 Receive Identifier Register 0; 0x000002A0 */
|
||||
volatile CAN4RXIDR1STR _CAN4RXIDR1; /* MSCAN4 Receive Identifier Register 1; 0x000002A1 */
|
||||
volatile CAN4RXIDR2STR _CAN4RXIDR2; /* MSCAN4 Receive Identifier Register 2; 0x000002A2 */
|
||||
volatile CAN4RXIDR3STR _CAN4RXIDR3; /* MSCAN4 Receive Identifier Register 3; 0x000002A3 */
|
||||
volatile CAN4RXDSR0STR _CAN4RXDSR0; /* MSCAN4 Receive Data Segment Register 0; 0x000002A4 */
|
||||
volatile CAN4RXDSR1STR _CAN4RXDSR1; /* MSCAN4 Receive Data Segment Register 1; 0x000002A5 */
|
||||
volatile CAN4RXDSR2STR _CAN4RXDSR2; /* MSCAN4 Receive Data Segment Register 2; 0x000002A6 */
|
||||
volatile CAN4RXDSR3STR _CAN4RXDSR3; /* MSCAN4 Receive Data Segment Register 3; 0x000002A7 */
|
||||
volatile CAN4RXDSR4STR _CAN4RXDSR4; /* MSCAN4 Receive Data Segment Register 4; 0x000002A8 */
|
||||
volatile CAN4RXDSR5STR _CAN4RXDSR5; /* MSCAN4 Receive Data Segment Register 5; 0x000002A9 */
|
||||
volatile CAN4RXDSR6STR _CAN4RXDSR6; /* MSCAN4 Receive Data Segment Register 6; 0x000002AA */
|
||||
volatile CAN4RXDSR7STR _CAN4RXDSR7; /* MSCAN4 Receive Data Segment Register 7; 0x000002AB */
|
||||
volatile CAN4RXDLRSTR _CAN4RXDLR; /* MSCAN4 Receive Data Length Register; 0x000002AC */
|
||||
volatile CAN4TXIDR0STR _CAN4TXIDR0; /* MSCAN4 Transmit Identifier Register 0; 0x000002B0 */
|
||||
volatile CAN4TXIDR1STR _CAN4TXIDR1; /* MSCAN4 Transmit Identifier Register 1; 0x000002B1 */
|
||||
volatile CAN4TXIDR2STR _CAN4TXIDR2; /* MSCAN4 Transmit Identifier Register 2; 0x000002B2 */
|
||||
volatile CAN4TXIDR3STR _CAN4TXIDR3; /* MSCAN4 Transmit Identifier Register 3; 0x000002B3 */
|
||||
volatile CAN4TXDSR0STR _CAN4TXDSR0; /* MSCAN4 Transmit Data Segment Register 0; 0x000002B4 */
|
||||
volatile CAN4TXDSR1STR _CAN4TXDSR1; /* MSCAN4 Transmit Data Segment Register 1; 0x000002B5 */
|
||||
volatile CAN4TXDSR2STR _CAN4TXDSR2; /* MSCAN4 Transmit Data Segment Register 2; 0x000002B6 */
|
||||
volatile CAN4TXDSR3STR _CAN4TXDSR3; /* MSCAN4 Transmit Data Segment Register 3; 0x000002B7 */
|
||||
volatile CAN4TXDSR4STR _CAN4TXDSR4; /* MSCAN4 Transmit Data Segment Register 4; 0x000002B8 */
|
||||
volatile CAN4TXDSR5STR _CAN4TXDSR5; /* MSCAN4 Transmit Data Segment Register 5; 0x000002B9 */
|
||||
volatile CAN4TXDSR6STR _CAN4TXDSR6; /* MSCAN4 Transmit Data Segment Register 6; 0x000002BA */
|
||||
volatile CAN4TXDSR7STR _CAN4TXDSR7; /* MSCAN4 Transmit Data Segment Register 7; 0x000002BB */
|
||||
volatile CAN4TXDLRSTR _CAN4TXDLR; /* MSCAN4 Transmit Data Length Register; 0x000002BC */
|
||||
volatile CAN4TXTBPRSTR _CAN4TXTBPR; /* MSCAN4 Transmit Transmit Buffer Priority; 0x000002BD */
|
||||
/* NVFPROT3 - macro for reading non volatile register Non volatile Block 3 Flash Protection Register; 0x0000FF0A */
|
||||
/* NVFPROT2 - macro for reading non volatile register Non volatile Block 2 Flash Protection Register; 0x0000FF0B */
|
||||
/* NVFPROT1 - macro for reading non volatile register Non volatile Block 1 Flash Protection Register; 0x0000FF0C */
|
||||
/* NVFPROT0 - macro for reading non volatile register Non volatile Block 0 Flash Protection Register; 0x0000FF0D */
|
||||
/* NVFSEC - macro for reading non volatile register Non volatile Flash Security Register; 0x0000FF0F */
|
||||
|
||||
|
||||
/* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */
|
||||
volatile PORTABSTR _PORTAB; /* Port AB Register; 0x00000000 */
|
||||
volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register; 0x00000002 */
|
||||
volatile PARTIDSTR _PARTID; /* Part ID Register; 0x0000001A */
|
||||
volatile TCNTSTR _TCNT; /* Timer Count Register; 0x00000044 */
|
||||
volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0; 0x00000050 */
|
||||
volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1; 0x00000052 */
|
||||
volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2; 0x00000054 */
|
||||
volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3; 0x00000056 */
|
||||
volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4; 0x00000058 */
|
||||
volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5; 0x0000005A */
|
||||
volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6; 0x0000005C */
|
||||
volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7; 0x0000005E */
|
||||
volatile PACN32STR _PACN32; /* Pulse Accumulators Count 32 Register; 0x00000062 */
|
||||
volatile PACN10STR _PACN10; /* Pulse Accumulators Count 10 Register; 0x00000064 */
|
||||
volatile PA32HSTR _PA32H; /* 8-Bit Pulse Accumulators Holding 32 Register; 0x00000072 */
|
||||
volatile PA10HSTR _PA10H; /* 8-Bit Pulse Accumulators Holding 10 Register; 0x00000074 */
|
||||
volatile MCCNTSTR _MCCNT; /* Modulus Down-Counter Count Register; 0x00000076 */
|
||||
volatile TC0HSTR _TC0H; /* Timer Input Capture Holding Registers 0; 0x00000078 */
|
||||
volatile TC1HSTR _TC1H; /* Timer Input Capture Holding Registers 1; 0x0000007A */
|
||||
volatile TC2HSTR _TC2H; /* Timer Input Capture Holding Registers 2; 0x0000007C */
|
||||
volatile TC3HSTR _TC3H; /* Timer Input Capture Holding Registers 3; 0x0000007E */
|
||||
volatile ATD0CTL23STR _ATD0CTL23; /* ATD 0 Control Register 23; 0x00000082 */
|
||||
volatile ATD0CTL45STR _ATD0CTL45; /* ATD 0 Control Register 45; 0x00000084 */
|
||||
volatile ATD0DR0STR _ATD0DR0; /* ATD 0 Conversion Result Register 0; 0x00000090 */
|
||||
volatile ATD0DR1STR _ATD0DR1; /* ATD 0 Conversion Result Register 1; 0x00000092 */
|
||||
volatile ATD0DR2STR _ATD0DR2; /* ATD 0 Conversion Result Register 2; 0x00000094 */
|
||||
volatile ATD0DR3STR _ATD0DR3; /* ATD 0 Conversion Result Register 3; 0x00000096 */
|
||||
volatile ATD0DR4STR _ATD0DR4; /* ATD 0 Conversion Result Register 4; 0x00000098 */
|
||||
volatile ATD0DR5STR _ATD0DR5; /* ATD 0 Conversion Result Register 5; 0x0000009A */
|
||||
volatile ATD0DR6STR _ATD0DR6; /* ATD 0 Conversion Result Register 6; 0x0000009C */
|
||||
volatile ATD0DR7STR _ATD0DR7; /* ATD 0 Conversion Result Register 7; 0x0000009E */
|
||||
volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register; 0x000000AC */
|
||||
volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register; 0x000000AE */
|
||||
volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register; 0x000000B0 */
|
||||
volatile PWMCNT67STR _PWMCNT67; /* PWM Channel Counter 67 Register; 0x000000B2 */
|
||||
volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register; 0x000000B4 */
|
||||
volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register; 0x000000B6 */
|
||||
volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register; 0x000000B8 */
|
||||
volatile PWMPER67STR _PWMPER67; /* PWM Channel Period 67 Register; 0x000000BA */
|
||||
volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register; 0x000000BC */
|
||||
volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register; 0x000000BE */
|
||||
volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register; 0x000000C0 */
|
||||
volatile PWMDTY67STR _PWMDTY67; /* PWM Channel Duty 67 Register; 0x000000C2 */
|
||||
volatile SCI0BDSTR _SCI0BD; /* SCI 0 Baud Rate Register; 0x000000C8 */
|
||||
volatile SCI1BDSTR _SCI1BD; /* SCI 1 Baud Rate Register; 0x000000D0 */
|
||||
volatile ATD1CTL23STR _ATD1CTL23; /* ATD 1 Control Register 23; 0x00000122 */
|
||||
volatile ATD1CTL45STR _ATD1CTL45; /* ATD 1 Control Register 45; 0x00000124 */
|
||||
volatile ATD1DR0STR _ATD1DR0; /* ATD 1 Conversion Result Register 0; 0x00000130 */
|
||||
volatile ATD1DR1STR _ATD1DR1; /* ATD 1 Conversion Result Register 1; 0x00000132 */
|
||||
volatile ATD1DR2STR _ATD1DR2; /* ATD 1 Conversion Result Register 2; 0x00000134 */
|
||||
volatile ATD1DR3STR _ATD1DR3; /* ATD 1 Conversion Result Register 3; 0x00000136 */
|
||||
volatile ATD1DR4STR _ATD1DR4; /* ATD 1 Conversion Result Register 4; 0x00000138 */
|
||||
volatile ATD1DR5STR _ATD1DR5; /* ATD 1 Conversion Result Register 5; 0x0000013A */
|
||||
volatile ATD1DR6STR _ATD1DR6; /* ATD 1 Conversion Result Register 6; 0x0000013C */
|
||||
volatile ATD1DR7STR _ATD1DR7; /* ATD 1 Conversion Result Register 7; 0x0000013E */
|
||||
volatile CAN0RXTSRSTR _CAN0RXTSR; /* MSCAN 0 Receive Time Stamp Register; 0x0000016E */
|
||||
volatile CAN0TXTSRSTR _CAN0TXTSR; /* MSCAN 0 Transmit Time Stamp Register; 0x0000017E */
|
||||
volatile CAN4RXTSRSTR _CAN4RXTSR; /* MSCAN 4 Receive Time Stamp Register; 0x000002AE */
|
||||
volatile CAN4TXTSRSTR _CAN4TXTSR; /* MSCAN 4 Transmit Time Stamp Register; 0x000002BE */
|
||||
/* BAKEY0 - macro for reading non volatile register Backdoor Access Key 0; 0x0000FF00 */
|
||||
/* BAKEY1 - macro for reading non volatile register Backdoor Access Key 1; 0x0000FF02 */
|
||||
/* BAKEY2 - macro for reading non volatile register Backdoor Access Key 2; 0x0000FF04 */
|
||||
/* BAKEY3 - macro for reading non volatile register Backdoor Access Key 3; 0x0000FF06 */
|
||||
|
||||
/*lint -restore */
|
||||
|
||||
/* EOF */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,86 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\main.c
|
||||
* \brief Demo program application source file.
|
||||
* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
static void Init(void);
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief This is the entry point for the bootloader application and is called
|
||||
** by the reset interrupt vector after the C-startup routines executed.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void main(void)
|
||||
{
|
||||
/* initialize the microcontroller */
|
||||
Init();
|
||||
/* initialize the bootloader interface */
|
||||
BootComInit();
|
||||
|
||||
/* start the infinite program loop */
|
||||
while (1)
|
||||
{
|
||||
/* toggle LED with a fixed frequency */
|
||||
LedToggle();
|
||||
/* check for bootloader activation request */
|
||||
BootComCheckActivationRequest();
|
||||
}
|
||||
} /*** end of main ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the microcontroller.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void Init(void)
|
||||
{
|
||||
/* init the led driver */
|
||||
LedInit();
|
||||
/* init the timer driver */
|
||||
TimeInit();
|
||||
/* enable IRQ's, because they were initially disabled by the bootloader */
|
||||
IrqInterruptEnable();
|
||||
} /*** end of Init ***/
|
||||
|
||||
|
||||
/*********************************** end of main.c *************************************/
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/* This is a linker parameter file for the MC9S12DG256B */
|
||||
NAMES END /* CodeWarrior will pass all the needed files to the linker by command line. But here you may add your own files too. */
|
||||
|
||||
SEGMENTS /* Here all RAM/ROM areas of the device are listed. Used in PLACEMENT below. */
|
||||
|
||||
/* Register space */
|
||||
/* IO_SEG = PAGED 0x0000 TO 0x03FF; intentionally not defined */
|
||||
|
||||
/* EPROM */
|
||||
EEPROM = READ_ONLY 0x0400 TO 0x0FEF;
|
||||
|
||||
/* RAM */
|
||||
RAM = READ_WRITE 0x1000 TO 0x3FFF;
|
||||
|
||||
/* non-paged FLASHs */
|
||||
ROM_4000 = READ_ONLY 0x4000 TO 0x7FFF;
|
||||
ROM_C000 = READ_ONLY 0xC000 TO 0xE7FF; /* last part reserved for OpenBLT */
|
||||
|
||||
/* paged FLASH: 0x8000 TO 0xBFFF; addressed through PPAGE */
|
||||
PAGE_30 = READ_ONLY 0x308000 TO 0x30BFFF;
|
||||
PAGE_31 = READ_ONLY 0x318000 TO 0x31BFFF;
|
||||
PAGE_32 = READ_ONLY 0x328000 TO 0x32BFFF;
|
||||
PAGE_33 = READ_ONLY 0x338000 TO 0x33BFFF;
|
||||
PAGE_34 = READ_ONLY 0x348000 TO 0x34BFFF;
|
||||
PAGE_35 = READ_ONLY 0x358000 TO 0x35BFFF;
|
||||
PAGE_36 = READ_ONLY 0x368000 TO 0x36BFFF;
|
||||
PAGE_37 = READ_ONLY 0x378000 TO 0x37BFFF;
|
||||
PAGE_38 = READ_ONLY 0x388000 TO 0x38BFFF;
|
||||
PAGE_39 = READ_ONLY 0x398000 TO 0x39BFFF;
|
||||
PAGE_3A = READ_ONLY 0x3A8000 TO 0x3ABFFF;
|
||||
PAGE_3B = READ_ONLY 0x3B8000 TO 0x3BBFFF;
|
||||
PAGE_3C = READ_ONLY 0x3C8000 TO 0x3CBFFF;
|
||||
PAGE_3D = READ_ONLY 0x3D8000 TO 0x3DBFFF;
|
||||
/* PAGE_3E = READ_ONLY 0x3E8000 TO 0x3EBFFF; not used: equivalent to ROM_4000 */
|
||||
/* PAGE_3F = READ_ONLY 0x3F8000 TO 0x3FBEFF; not used: equivalent to ROM_C000 */
|
||||
END
|
||||
|
||||
PLACEMENT /* here all predefined and user segments are placed into the SEGMENTS defined above. */
|
||||
_PRESTART, /* Used in HIWARE format: jump to _Startup at the code start */
|
||||
STARTUP, /* startup data structures */
|
||||
ROM_VAR, /* constant variables */
|
||||
STRINGS, /* string literals */
|
||||
VIRTUAL_TABLE_SEGMENT, /* C++ virtual table segment */
|
||||
DEFAULT_ROM, NON_BANKED, /* runtime routines which must not be banked */
|
||||
COPY /* copy down information: how to initialize variables */
|
||||
/* in case you want to use ROM_4000 here as well, make sure
|
||||
that all files (incl. library files) are compiled with the
|
||||
option: -OnB=b */
|
||||
INTO ROM_C000/*, ROM_4000*/;
|
||||
|
||||
OTHER_ROM INTO PAGE_30, PAGE_31, PAGE_32, PAGE_33, PAGE_34, PAGE_35, PAGE_36, PAGE_37,
|
||||
PAGE_38, PAGE_39, PAGE_3A, PAGE_3B, PAGE_3C, PAGE_3D ;
|
||||
|
||||
SSTACK, /* allocate stack first to avoid overwriting variables on overflow */
|
||||
DEFAULT_RAM INTO RAM;
|
||||
|
||||
END
|
||||
|
||||
ENTRIES /* keep the following unreferenced variables */
|
||||
_vectab
|
||||
END
|
||||
|
||||
STACKSIZE 0x100
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
/**
|
||||
\defgroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior User Program
|
||||
\brief User Program.
|
||||
\ingroup HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
*/
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,475 @@
|
|||
/*****************************************************
|
||||
start12.c - standard startup code
|
||||
The startup code may be optimized to special user requests
|
||||
----------------------------------------------------
|
||||
Copyright (c) Metrowerks, Basel, Switzerland
|
||||
All rights reserved
|
||||
|
||||
Note: ROM libraries are not implemented in this startup code
|
||||
Note: C++ destructors of global objects are NOT yet supported in the HIWARE Object File Format.
|
||||
To use this feature, please build your application with the ELF object file format.
|
||||
*****************************************************/
|
||||
/* these macros remove some unused fields in the startup descriptor */
|
||||
#define __NO_FLAGS_OFFSET /* we do not need the flags field in the startup data descriptor */
|
||||
#define __NO_MAIN_OFFSET /* we do not need the main field in the startup data descriptor */
|
||||
#define __NO_STACKOFFSET_OFFSET /* we do not need the stackOffset field in the startup data descriptor */
|
||||
|
||||
/*#define __BANKED_COPY_DOWN : allow to allocate .copy in flash area */
|
||||
#if defined(__BANKED_COPY_DOWN) && (!defined(__HCS12X__) || !defined(__ELF_OBJECT_FILE_FORMAT__))
|
||||
#error /* the __BANKED_COPY_DOWN switch is only supported for the HCS12X with ELF */
|
||||
/* (and not for the HC12, HCS12 or for the HIWARE object file format) */
|
||||
#endif
|
||||
|
||||
#include "hidef.h"
|
||||
#include "start12.h"
|
||||
|
||||
/***************************************************************************/
|
||||
/* Macros to control how the startup code handles the COP: */
|
||||
/* #define _DO_FEED_COP_ : do feed the COP */
|
||||
/* #define _DO_ENABLE_COP_: do enable the COP */
|
||||
/* #define _DO_DISABLE_COP_: disable the COP */
|
||||
/* Without defining any of these, the startup code does NOT handle the COP */
|
||||
/***************************************************************************/
|
||||
/* __ONLY_INIT_SP define: */
|
||||
/* This define selects an shorter version of the startup code */
|
||||
/* which only loads the stack pointer and directly afterwards calls */
|
||||
/* main. This version does however NOT initialized global variables */
|
||||
/* (So this version is not ANSI compliant!) */
|
||||
/***************************************************************************/
|
||||
/* __FAR_DATA define: */
|
||||
/* By default, the startup code only supports to initialize the default */
|
||||
/* kind of memory. If some memory is allocated far in the small or banked */
|
||||
/* memory model, then the startup code only supports to initialize this */
|
||||
/* memory blocks if __FAR_DATA is defined. If __FAR_DATA is not defined, */
|
||||
/* then the linker will issue a message like */
|
||||
/* "L1128: Cutting value _Range beg data member from 0xF01000 to 0x1000" */
|
||||
/* and this startup code writes to the cutted address */
|
||||
/***************************************************************************/
|
||||
/* __BANKED_COPY_DOWN define: */
|
||||
/* by default, the startup code assumes that the startup data structure */
|
||||
/* _startupData, the zero out areas and the .copy section are all */
|
||||
/* allocated in NON_BANKED memory. Especially the .copy section can be */
|
||||
/* huge if there are many or huge RAM areas to initialize. */
|
||||
/* For the HCS12X, which also copies the XGATE RAM located code via .copy */
|
||||
/* section, the startup code supports to allocate .copy in a banked flash */
|
||||
/* The placement of .copy in the prm file has to be adapted when adding or */
|
||||
/* removing the this macro. */
|
||||
/* Note: This macro is only supported for the HCS12X and when using ELF */
|
||||
/***************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define __EXTERN_C extern "C"
|
||||
#else
|
||||
#define __EXTERN_C
|
||||
#endif
|
||||
|
||||
/*lint -estring(961,"only preprocessor statements and comments before '#include'") , MISRA 19.1 ADV, non_bank.sgm and default.sgm each contain a conditionally compiled CODE_SEG pragma */
|
||||
|
||||
__EXTERN_C void main(void); /* prototype of main function */
|
||||
|
||||
#ifndef __ONLY_INIT_SP
|
||||
#pragma DATA_SEG __NEAR_SEG STARTUP_DATA /* _startupData can be accessed using 16 bit accesses. */
|
||||
/* This is needed because it contains the stack top, and without stack, far data cannot be accessed */
|
||||
struct _tagStartup _startupData; /* read-only: */
|
||||
/* _startupData is allocated in ROM and */
|
||||
/* initialized by the linker */
|
||||
#pragma DATA_SEG DEFAULT
|
||||
#endif /* __ONLY_INIT_SP */
|
||||
|
||||
#if defined(FAR_DATA) && (!defined(__HCS12X__) || defined(__BANKED_COPY_DOWN))
|
||||
/*lint -e451 non_bank.sgm contains a conditionally compiled CODE_SEG pragma */
|
||||
#include "non_bank.sgm"
|
||||
/*lint +e451 */
|
||||
|
||||
/* the init function must be in non banked memory if banked variables are used */
|
||||
/* because _SET_PAGE is called, which may change any page register. */
|
||||
|
||||
/*lint -esym(752,_SET_PAGE) , symbol '_SET_PAGE' is referenced in HLI */
|
||||
__EXTERN_C void _SET_PAGE(void); /* the inline assembler needs a prototype */
|
||||
/* this is a runtime routine with a special */
|
||||
/* calling convention, do not use it in c code! */
|
||||
#else
|
||||
/*lint -e451 default.sgm contains a conditionally compiled CODE_SEG pragma */
|
||||
#include "default.sgm"
|
||||
/*lint +e451 */
|
||||
#endif /* defined(FAR_DATA) && (!defined(__HCS12X__) || defined(__BANKED_COPY_DOWN)) */
|
||||
|
||||
|
||||
/* define value and bits for Windef Register */
|
||||
#ifdef HC812A4
|
||||
#define WINDEF (*(volatile unsigned char*) 0x37)
|
||||
#if defined( __BANKED__) || defined(__LARGE__) || defined(__PPAGE__)
|
||||
#define __ENABLE_PPAGE__ 0x40
|
||||
#else
|
||||
#define __ENABLE_PPAGE__ 0x0
|
||||
#endif
|
||||
#if defined(__DPAGE__)
|
||||
#define __ENABLE_DPAGE__ 0x80
|
||||
#else
|
||||
#define __ENABLE_DPAGE__ 0x0
|
||||
#endif
|
||||
#if defined(__EPAGE__)
|
||||
#define __ENABLE_EPAGE__ 0x20
|
||||
#else
|
||||
#define __ENABLE_EPAGE__ 0x0
|
||||
#endif
|
||||
#endif /* HC812A4 */
|
||||
|
||||
#define ___INITRM (*(volatile unsigned char *) 0x0010)
|
||||
#define ___INITRG (*(volatile unsigned char *) 0x0011)
|
||||
#define ___INITEE (*(volatile unsigned char *) 0x0012)
|
||||
|
||||
#if defined(_DO_FEED_COP_)
|
||||
#define __FEED_COP_IN_HLI() } asm movb #0x55, _COP_RST_ADR; asm movb #0xAA, _COP_RST_ADR; asm {
|
||||
#else
|
||||
#define __FEED_COP_IN_HLI() /* do nothing */
|
||||
#endif
|
||||
|
||||
#ifndef __ONLY_INIT_SP
|
||||
#if (!defined(FAR_DATA) || defined(__HCS12X__)) && (defined( __BANKED__) || defined(__LARGE__) || defined(__BANKED_COPY_DOWN))
|
||||
static void __far Init(void)
|
||||
#else
|
||||
static void Init(void)
|
||||
#endif
|
||||
{
|
||||
/* purpose: 1) zero out RAM-areas where data is allocated */
|
||||
/* 2) copy initialization data from ROM to RAM */
|
||||
/* 3) call global constructors in C++ */
|
||||
/* called from: _Startup, LibInits */
|
||||
asm {
|
||||
ZeroOut:
|
||||
#if defined(__HIWARE_OBJECT_FILE_FORMAT__) && defined(__LARGE__)
|
||||
LDX _startupData.pZeroOut:1 ; in the large memory model in the HIWARE format, pZeroOut is a 24 bit pointer
|
||||
#else
|
||||
LDX _startupData.pZeroOut ; *pZeroOut
|
||||
#endif
|
||||
LDY _startupData.nofZeroOuts ; nofZeroOuts
|
||||
BEQ CopyDown ; if nothing to zero out
|
||||
|
||||
NextZeroOut: PSHY ; save nofZeroOuts
|
||||
#if defined(FAR_DATA)
|
||||
LDAB 1,X+ ; load page of destination address
|
||||
LDY 2,X+ ; load offset of destination address
|
||||
#if defined(__HCS12X__)
|
||||
STAB __GPAGE_ADR__
|
||||
#else /* defined(__HCS12X__) */
|
||||
__PIC_JSR(_SET_PAGE) ; sets the page in the correct page register
|
||||
#endif /* defined(__HCS12X__) */
|
||||
#else /* FAR_DATA */
|
||||
LDY 2,X+ ; start address and advance *pZeroOut (X = X+4)
|
||||
#endif /* FAR_DATA */
|
||||
|
||||
#if defined(__HCS12X__) && defined(FAR_DATA)
|
||||
PSHX
|
||||
LDX 0,X ; byte count
|
||||
#if defined(__OPTIMIZE_FOR_SIZE__)
|
||||
CLRA
|
||||
NextWord: GSTAA 1,Y+ ; clear memory byte
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE X, NextWord ; dec byte count
|
||||
#else
|
||||
LDD #0
|
||||
LSRX
|
||||
BEQ LoopClrW1 ; do we copy more than 1 byte?
|
||||
NextWord: GSTD 2,Y+ ; clear memory word
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE X, NextWord ; dec word count
|
||||
LoopClrW1:
|
||||
BCC LastClr ; handle last byte
|
||||
GSTAA 1,Y+ ; handle last byte
|
||||
LastClr:
|
||||
#endif
|
||||
PULX
|
||||
LEAX 2,X
|
||||
#elif defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */
|
||||
LDD 2,X+ ; byte count
|
||||
NextWord: CLR 1,Y+ ; clear memory byte
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D, NextWord ; dec byte count
|
||||
#else /* __OPTIMIZE_FOR_TIME__ */
|
||||
LDD 2,X+ ; byte count
|
||||
LSRD ; /2 and save bit 0 in the carry
|
||||
BEQ LoopClrW1 ; do we copy more than 1 byte?
|
||||
PSHX
|
||||
LDX #0
|
||||
LoopClrW: STX 2,Y+ ; Word-Clear
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D, LoopClrW
|
||||
PULX
|
||||
LoopClrW1:
|
||||
BCC LastClr ; handle last byte
|
||||
CLR 1,Y+
|
||||
LastClr:
|
||||
#endif /* __OPTIMIZE_FOR_SIZE__/__OPTIMIZE_FOR_TIME__ */
|
||||
PULY ; restore nofZeroOuts
|
||||
DEY ; dec nofZeroOuts
|
||||
BNE NextZeroOut
|
||||
CopyDown:
|
||||
#if defined(__BANKED_COPY_DOWN)
|
||||
LDAA _startupData.toCopyDownBeg:0 ; get PAGE address of .copy section
|
||||
STAA __PPAGE_ADR__ ; set PPAGE address
|
||||
LDX _startupData.toCopyDownBeg:1 ; load address of copy down desc.
|
||||
#elif defined(__ELF_OBJECT_FILE_FORMAT__)
|
||||
LDX _startupData.toCopyDownBeg ; load address of copy down desc.
|
||||
#else
|
||||
LDX _startupData.toCopyDownBeg:2 ; load address of copy down desc.
|
||||
#endif
|
||||
NextBlock:
|
||||
LDD 2,X+ ; size of init-data -> D
|
||||
BEQ funcInits ; end of copy down desc.
|
||||
#ifdef FAR_DATA
|
||||
PSHD ; save counter
|
||||
LDAB 1,X+ ; load destination page
|
||||
LDY 2,X+ ; destination address
|
||||
#if defined(__HCS12X__)
|
||||
STAB __GPAGE_ADR__
|
||||
#else /* __HCS12X__ */
|
||||
__PIC_JSR(_SET_PAGE) ; sets the destinations page register
|
||||
#endif /* __HCS12X__ */
|
||||
PULD ; restore counter
|
||||
#else /* FAR_DATA */
|
||||
LDY 2,X+ ; load destination address
|
||||
#endif /* FAR_DATA */
|
||||
|
||||
#if defined(__HCS12X__) && defined(FAR_DATA)
|
||||
#if defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */
|
||||
Copy: PSHA
|
||||
LDAA 1,X+
|
||||
GSTAA 1,Y+ ; move a byte from ROM to the data area
|
||||
PULA
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D,Copy ; copy-byte loop
|
||||
#else
|
||||
LSRD ; /2 and save bit 0 in the carry
|
||||
BEQ Copy1 ; do we copy more than 1 byte?
|
||||
|
||||
Copy: PSHD
|
||||
LDD 2,X+
|
||||
GSTD 2,Y+ ; move a word from ROM to the data area
|
||||
PULD
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D,Copy ; copy-word loop
|
||||
Copy1:
|
||||
BCC NextBlock ; handle last byte?
|
||||
LDAA 1,X+
|
||||
GSTAA 1,Y+ ; move a byte from ROM to the data area
|
||||
#endif
|
||||
#elif defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */
|
||||
Copy: MOVB 1,X+,1,Y+ ; move a byte from ROM to the data area
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D,Copy ; copy-byte loop
|
||||
#else /* __OPTIMIZE_FOR_TIME__ */
|
||||
LSRD ; /2 and save bit 0 in the carry
|
||||
BEQ Copy1 ; do we copy more than 1 byte?
|
||||
Copy: MOVW 2,X+,2,Y+ ; move a word from ROM to the data area
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D,Copy ; copy-word loop
|
||||
Copy1:
|
||||
BCC NextBlock ; handle last byte?
|
||||
MOVB 1,X+,1,Y+ ; copy the last byte
|
||||
#endif /* __OPTIMIZE_FOR_SIZE__/__OPTIMIZE_FOR_TIME__ */
|
||||
BRA NextBlock
|
||||
funcInits: ; call of global construtors is only in c++ necessary
|
||||
#if defined(__cplusplus)
|
||||
#if defined(__ELF_OBJECT_FILE_FORMAT__)
|
||||
#if defined( __BANKED__) || defined(__LARGE__)
|
||||
LDY _startupData.nofInitBodies; load number of cpp.
|
||||
BEQ done ; if cppcount == 0, goto done
|
||||
LDX _startupData.initBodies ; load address of first module to initialize
|
||||
nextInit:
|
||||
LEAX 3,X ; increment to next init
|
||||
PSHX ; save address of next function to initialize
|
||||
PSHY ; save cpp counter
|
||||
CALL [-3,X] ; use double indirect call to load the page register also
|
||||
PULY ; restore cpp counter
|
||||
PULX ; restore actual address
|
||||
DEY ; decrement cpp counter
|
||||
BNE nextInit
|
||||
#else /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
|
||||
LDD _startupData.nofInitBodies; load number of cpp.
|
||||
BEQ done ; if cppcount == 0, goto done
|
||||
LDX _startupData.initBodies ; load address of first module to initialize
|
||||
nextInit:
|
||||
LDY 2,X+ ; load address of first module to initialize
|
||||
PSHD
|
||||
PSHX ; save actual address
|
||||
JSR 0,Y ; call initialization function
|
||||
PULX ; restore actual address
|
||||
PULD ; restore cpp counter
|
||||
DBNE D, nextInit
|
||||
#endif /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
#else /* __ELF_OBJECT_FILE_FORMAT__ */
|
||||
LDX _startupData.mInits ; load address of first module to initialize
|
||||
#if defined( __BANKED__) || defined(__LARGE__)
|
||||
nextInit: LDY 3,X+ ; load address of initialization function
|
||||
BEQ done ; stop when address == 0
|
||||
; in common environments the offset of a function is never 0, so this test could be avoided
|
||||
#ifdef __InitFunctionsMayHaveOffset0__
|
||||
BRCLR -1,X, done, 0xff ; stop when address == 0
|
||||
#endif /* __InitFunctionsMayHaveOffset0__ */
|
||||
PSHX ; save address of next function to initialize
|
||||
CALL [-3,X] ; use double indirect call to load the page register also
|
||||
#else /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
nextInit:
|
||||
LDY 2,X+ ; load address of first module to initialize
|
||||
BEQ done ; stop when address of function == 0
|
||||
PSHX ; save actual address
|
||||
JSR 0,Y ; call initialization function
|
||||
#endif /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
PULX ; restore actual address
|
||||
BRA nextInit
|
||||
#endif /* __ELF_OBJECT_FILE_FORMAT__ */
|
||||
done:
|
||||
#endif /* __cplusplus */
|
||||
}
|
||||
}
|
||||
#endif /* __ONLY_INIT_SP */
|
||||
|
||||
#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) && 0 /* the call to main does not support to return anymore */
|
||||
|
||||
#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__))
|
||||
static void __far Fini(void)
|
||||
#else
|
||||
static void Fini(void)
|
||||
#endif
|
||||
{
|
||||
/* purpose: 1) call global destructors in C++ */
|
||||
asm {
|
||||
#if defined( __BANKED__) || defined(__LARGE__)
|
||||
|
||||
LDY _startupData.nofFiniBodies; load number of cpp.
|
||||
BEQ done ; if cppcount == 0, goto done
|
||||
LDX _startupData.finiBodies ; load address of first module to finalize
|
||||
nextInit2:
|
||||
LEAX 3,X ; increment to next init
|
||||
PSHX ; save address of next function to finalize
|
||||
PSHY ; save cpp counter
|
||||
CALL [-3,X] ; use double indirect call to load the page register also
|
||||
PULY ; restore cpp counter
|
||||
PULX ; restore actual address
|
||||
DEY ; decrement cpp counter
|
||||
BNE nextInit2
|
||||
#else /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
|
||||
LDD _startupData.nofFiniBodies; load number of cpp.
|
||||
BEQ done ; if cppcount == 0, goto done
|
||||
LDX _startupData.finiBodies ; load address of first module to finalize
|
||||
nextInit2:
|
||||
LDY 2,X+ ; load address of first module to finalize
|
||||
PSHD
|
||||
PSHX ; save actual address
|
||||
JSR 0,Y ; call finalize function
|
||||
PULX ; restore actual address
|
||||
PULD ; restore cpp counter
|
||||
DBNE D, nextInit2
|
||||
#endif /* defined(__BANKED__) || defined(__LARGE__) */
|
||||
done:;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*lint -e451 non_bank.sgm contains a conditionally compiled CODE_SEG pragma */
|
||||
#include "non_bank.sgm"
|
||||
/*lint +e451 */
|
||||
|
||||
#pragma MESSAGE DISABLE C12053 /* Stack-pointer change not in debugging-information */
|
||||
#pragma NO_FRAME
|
||||
#pragma NO_ENTRY
|
||||
#if !defined(__SMALL__)
|
||||
#pragma NO_EXIT
|
||||
#endif
|
||||
|
||||
/* The function _Startup must be called in order to initialize global variables and to call main */
|
||||
/* You can adapt this function or call it from your startup code to implement a different startup */
|
||||
/* functionality. */
|
||||
|
||||
/* You should also setup the needed IO registers as WINDEF (HC12A4 only) or the COP registers to run */
|
||||
/* on hardware */
|
||||
|
||||
/* to set the reset vector several ways are possible : */
|
||||
/* 1. define the function with "interrupt 0" as done below in the first case */
|
||||
/* 2. add the following line to your prm file : VECTOR ADDRESS 0xfffe _Startup */
|
||||
/* of course, even more posibilities exists */
|
||||
/* the reset vector must be set so that the application has a defined entry point */
|
||||
|
||||
#if defined(__SET_RESET_VECTOR__)
|
||||
__EXTERN_C void __interrupt 0 _Startup(void) {
|
||||
#else
|
||||
__EXTERN_C void _Startup(void) {
|
||||
#endif
|
||||
/* purpose: 1) initialize the stack
|
||||
2) initialize the RAM, copy down init data etc (Init)
|
||||
3) call main;
|
||||
parameters: NONE
|
||||
called from: _PRESTART-code generated by the Linker
|
||||
or directly referenced by the reset vector */
|
||||
|
||||
/* initialize the stack pointer */
|
||||
/*lint -e{960} , MISRA 14.3 REQ, macro INIT_SP_FROM_STARTUP_DESC() expands to HLI code */
|
||||
/*lint -e{522} , MISRA 14.2 REQ, macro INIT_SP_FROM_STARTUP_DESC() expands to HLI code */
|
||||
INIT_SP_FROM_STARTUP_DESC(); /* HLI macro definition in hidef.h */
|
||||
|
||||
___INITRG = 0x00; /* lock registers block to 0x0000 */
|
||||
___INITRM = 0x39; /* lock Ram to end at 0x3FFF */
|
||||
___INITEE = 0x09; /* lock EEPROM block to end at 0x0fff */
|
||||
|
||||
/* Here user defined code could be inserted, the stack could be used */
|
||||
#if defined(_DO_DISABLE_COP_)
|
||||
_DISABLE_COP();
|
||||
#endif
|
||||
|
||||
/* Example : Set up WinDef Register to allow Paging */
|
||||
#ifdef HC812A4 /* HC12 A4 derivative needs WINDEF to configure which pages are available */
|
||||
#if (__ENABLE_EPAGE__ != 0 || __ENABLE_DPAGE__ != 0 || __ENABLE_PPAGE__ != 0)
|
||||
WINDEF= __ENABLE_EPAGE__ | __ENABLE_DPAGE__ | __ENABLE_PPAGE__;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(__MAP_RAM__) || defined(__MAP_FLASH__) || defined(__MAP_EXTERNAL__)) && !defined(__DO_SET_MMCTL1__)
|
||||
#define __DO_SET_MMCTL1__
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__DO_SET_MMCTL1__)
|
||||
/* Set the MMCTL1 byte. Please use for HCS12XE and change the bits according */
|
||||
/* to your configuration. */
|
||||
/* Note: MMCTL1 is write once therefore please adapt this initialization here. */
|
||||
/* This has to be done prior to the call to Init. */
|
||||
#define _MMCTL1_ADR (0x00000013)
|
||||
#define _MMCTL1_BIT_TGMRAMON (1<<7) /* EEE Tag RAM and FTM SCRATCH RAM visible in the memory map */
|
||||
#define _MMCTL1_BIT_EEEIFRON (1<<5) /* EEE IFR visible in the memory map */
|
||||
#define _MMCTL1_BIT_PGMIFRON (1<<4) /* Program IFR visible in the memory map */
|
||||
#define _MMCTL1_BIT_RAMHM (1<<3) /* RAM only in the higher half of the memory map */
|
||||
#define _MMCTL1_BIT_EROMON (1<<2) /* Enables emulated Flash or ROM memory in the memory map */
|
||||
#define _MMCTL1_BIT_ROMHM (1<<1) /* FLASH or ROM only in higher Half of Memory Map */
|
||||
#define _MMCTL1_BIT_ROMON (1<<0) /* Enable FLASH or ROM in the memory map */
|
||||
|
||||
#define _MMCTL1_SET(value) ((*(volatile unsigned char*)_MMCTL1_ADR)= (value))
|
||||
|
||||
#if defined(__MAP_FLASH__)
|
||||
_MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON);
|
||||
#elif defined(__MAP_EXTERNAL__)
|
||||
_MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON | _MMCTL1_BIT_ROMHM);
|
||||
#else /* RAM */
|
||||
_MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON | _MMCTL1_BIT_RAMHM | _MMCTL1_BIT_ROMHM);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __ONLY_INIT_SP
|
||||
/*lint -e{522} , MISRA 14.2 REQ, function Init() contains HLI only */
|
||||
Init(); /* zero out, copy down, call constructors */
|
||||
#endif
|
||||
|
||||
/* Here user defined code could be inserted, all global variables are initilized */
|
||||
#if defined(_DO_ENABLE_COP_)
|
||||
_ENABLE_COP(1);
|
||||
#endif
|
||||
|
||||
/* call main() */
|
||||
main();
|
||||
}
|
||||
|
||||
/*lint --e{766} , non_bank.sgm is not a regular header file, it contains a conditionally compiled CODE_SEG pragma */
|
||||
/*lint +estring(961,"only preprocessor statements and comments before '#include'") */
|
||||
/*lint +e451 */
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\timer.c
|
||||
* \brief Timer driver source file.
|
||||
* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Number of free running timer counts in 1 millisecond. */
|
||||
#define TIMER_COUNTS_PER_MS (BOOT_CPU_SYSTEM_SPEED_KHZ)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Local data declarations
|
||||
****************************************************************************************/
|
||||
/** \brief Local variable for storing the number of milliseconds that have elapsed since
|
||||
* startup.
|
||||
*/
|
||||
static unsigned long millisecond_counter;
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the timer.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void TimeInit(void)
|
||||
{
|
||||
/* reset the timer configuration. note that this also sets the default prescaler
|
||||
* to 1, so the free running counter runs at the same speed as the system clock.
|
||||
*/
|
||||
TimeDeinit();
|
||||
|
||||
/* configure timer channel 0 as a 1 millisecond software timer */
|
||||
TIOS_IOS0 = 1;
|
||||
/* make sure timer 0 interrupt flag is cleared */
|
||||
TFLG1 = TFLG1_C0F_MASK;
|
||||
/* generate output compare event in 1 milliseconds from now */
|
||||
TC0 = TCNT + TIMER_COUNTS_PER_MS;
|
||||
/* enable the interrupt for timer channel 0 */
|
||||
TIE_C0I = 1;
|
||||
/* enable the timer subsystem */
|
||||
TSCR1_TEN = 1;
|
||||
/* reset the millisecond counter */
|
||||
TimeSet(0);
|
||||
} /*** end of TimeInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Stops and disables the timer.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void TimeDeinit(void)
|
||||
{
|
||||
/* bring the timer subsystem back into its reset state */
|
||||
TIE = 0;
|
||||
TSCR1 = 0;
|
||||
TSCR2 = 0;
|
||||
TIOS = 0;
|
||||
TTOV = 0;
|
||||
TCTL1 = 0;
|
||||
TCTL2 = 0;
|
||||
TCTL3 = 0;
|
||||
TCTL4 = 0;
|
||||
} /*** end of TimeDeinit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Sets the initial counter value of the millisecond timer.
|
||||
** \param timer_value initialize value of the millisecond timer.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void TimeSet(unsigned long timer_value)
|
||||
{
|
||||
/* set the millisecond counter */
|
||||
millisecond_counter = timer_value;
|
||||
} /*** end of TimeSet ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Obtains the counter value of the millisecond timer.
|
||||
** \return Current value of the millisecond timer.
|
||||
**
|
||||
****************************************************************************************/
|
||||
unsigned long TimeGet(void)
|
||||
{
|
||||
/* read and return the millisecond counter value */
|
||||
return millisecond_counter;
|
||||
} /*** end of TimeGet ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Interrupt service routine of the timer.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
__interrupt void TimeISRHandler(void)
|
||||
{
|
||||
/* make sure timer 0 interrupt flag is cleared */
|
||||
TFLG1 = TFLG1_C0F_MASK;
|
||||
/* generate output compare event in 1 milliseconds from now */
|
||||
TC0 += TIMER_COUNTS_PER_MS;
|
||||
/* increment the millisecond counter */
|
||||
millisecond_counter++;
|
||||
} /*** end of TimeISRHandler ***/
|
||||
|
||||
|
||||
/*********************************** end of time.c *************************************/
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\timer.h
|
||||
* \brief Timer driver header file.
|
||||
* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef TIME_H
|
||||
#define TIME_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void TimeInit(void);
|
||||
void TimeDeinit(void);
|
||||
void TimeSet(unsigned long timer_value);
|
||||
unsigned long TimeGet(void);
|
||||
void TimeISRHandler(void);
|
||||
|
||||
#endif /* TIME_H */
|
||||
/*********************************** end of time.h *************************************/
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
/************************************************************************************//**
|
||||
* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\vectors.c
|
||||
* \brief Demo program interrupt vectors source file.
|
||||
* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "header.h" /* generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* External functions
|
||||
****************************************************************************************/
|
||||
extern void near _Startup(void);
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Type definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Type for vector table entries. */
|
||||
typedef void (*near tIsrFunc)(void);
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
** NAME: UnusedISR
|
||||
** PARAMETER: none
|
||||
** RETURN VALUE: none
|
||||
** DESCRIPTION: Catch-all for unused interrrupt service routines.
|
||||
**
|
||||
****************************************************************************************/
|
||||
__interrupt void UnusedISR(void)
|
||||
{
|
||||
/* unexpected interrupt occured, so halt the system */
|
||||
while (1) { ; }
|
||||
} /*** end of UnusedISR ***/
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* I N T E R R U P T V E C T O R T A B L E
|
||||
****************************************************************************************/
|
||||
/** \brief Interrupt vector table.
|
||||
* \details Normally, these are at 0xff80-0xffff, but the bootloader occupies 0xe800 -
|
||||
* 0xffff. The bootloader expects the vector table to be at the end of user
|
||||
* program flash, which is 0xe780 - 0xe7ff. 2 more bytes are reserved for the
|
||||
* checksum that is programmed and verified by the bootloader, so the start
|
||||
* address ends up being 0xe77e. Note that this needs to be updated when the
|
||||
* size of the bootloader changes, as defined in the flashLayout[] table in
|
||||
* flash.c of the bootloader.
|
||||
*/
|
||||
const tIsrFunc _vectab[] @0xe77e =
|
||||
{
|
||||
(tIsrFunc)0xaa55, /* Reserved for OpenBLT checksum */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFF80 */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFF82 */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFF84 */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFF86 */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFF88 */
|
||||
(tIsrFunc)UnusedISR, /* Reserved 0xFF8A */
|
||||
(tIsrFunc)UnusedISR, /* PWM Emergency Shutdown 0xFF8C */
|
||||
(tIsrFunc)UnusedISR, /* PortP Interrupt 0xFF8E */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN4 Transmit 0xFF90 */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN4 Receive 0xFF92 */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN4 Errors 0xFF94 */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN4 WakeUp 0xFF96 */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN3 Transmit 0xFF98 */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN3 Receive 0xFF9A */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN3 Errors 0xFF9C */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN3 WakeUp 0xFF9E */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN2 Transmit 0xFFA0 */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN2 Receive 0xFFA2 */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN2 Errors 0xFFA4 */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN2 WakeUp 0xFFA6 */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN1 Transmit 0xFFA8 */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN1 Receive 0xFFAA */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN1 Errors 0xFFAC */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN1 WakeUp 0xFFAE */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN0 Transmit 0xFFB0 */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN0 Receive 0xFFB2 */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN0 Errors 0xFFB4 */
|
||||
(tIsrFunc)UnusedISR, /* MSCAN0 WakeUp 0xFFB6 */
|
||||
(tIsrFunc)UnusedISR, /* Flash 0xFFB8 */
|
||||
(tIsrFunc)UnusedISR, /* Eeprom WakeUp 0xFFBA */
|
||||
(tIsrFunc)UnusedISR, /* SPI2 0xFFBC */
|
||||
(tIsrFunc)UnusedISR, /* SPI1 0xFFBE */
|
||||
(tIsrFunc)UnusedISR, /* IIC Bus 0xFFC0 */
|
||||
(tIsrFunc)UnusedISR, /* DLC 0xFFC2 */
|
||||
(tIsrFunc)UnusedISR, /* SCME 0xFFC4 */
|
||||
(tIsrFunc)UnusedISR, /* CRG Lock 0xFFC6 */
|
||||
(tIsrFunc)UnusedISR, /* Pulse AccB Overflow 0xFFC8 */
|
||||
(tIsrFunc)UnusedISR, /* Mod Down Cnt Underflow 0xFFCA */
|
||||
(tIsrFunc)UnusedISR, /* PortH Interrupt 0xFFCC */
|
||||
(tIsrFunc)UnusedISR, /* PortJ Interrupt 0xFFCE */
|
||||
(tIsrFunc)UnusedISR, /* ATD1 0xFFD0 */
|
||||
(tIsrFunc)UnusedISR, /* ATD0 0xFFD2 */
|
||||
(tIsrFunc)UnusedISR, /* SCI1 0xFFD4 */
|
||||
(tIsrFunc)UnusedISR, /* SCI0 0xFFD6 */
|
||||
(tIsrFunc)UnusedISR, /* SPI0 0xFFD8 */
|
||||
(tIsrFunc)UnusedISR, /* Pulse AccA Input Edge 0xFFDA */
|
||||
(tIsrFunc)UnusedISR, /* Pulse AccA Overflow 0xFFDC */
|
||||
(tIsrFunc)UnusedISR, /* Timer Overflow 0xFFDE */
|
||||
(tIsrFunc)UnusedISR, /* Timer 7 0xFFE0 */
|
||||
(tIsrFunc)UnusedISR, /* Timer 6 0xFFE2 */
|
||||
(tIsrFunc)UnusedISR, /* Timer 5 0xFFE4 */
|
||||
(tIsrFunc)UnusedISR, /* Timer 4 0xFFE6 */
|
||||
(tIsrFunc)UnusedISR, /* Timer 3 0xFFE8 */
|
||||
(tIsrFunc)UnusedISR, /* Timer 2 0xFFEA */
|
||||
(tIsrFunc)UnusedISR, /* Timer 1 0xFFEC */
|
||||
(tIsrFunc)TimeISRHandler, /* Timer 0 0xFFEE */
|
||||
(tIsrFunc)UnusedISR, /* RTI 0xFFF0 */
|
||||
(tIsrFunc)UnusedISR, /* IRQ 0xFFF2 */
|
||||
(tIsrFunc)UnusedISR, /* XIRQ 0xFFF4 */
|
||||
(tIsrFunc)UnusedISR, /* SWI 0xFFF6 */
|
||||
(tIsrFunc)UnusedISR, /* Unimpl Instr Trap 0xFFF8 */
|
||||
(tIsrFunc)UnusedISR, /* COP Failure Reset 0xFFFA */
|
||||
(tIsrFunc)UnusedISR, /* COP Clk Mon Fail 0xFFFC */
|
||||
(tIsrFunc)_Startup /* Reset(N/A) 0xFFFE */
|
||||
};
|
||||
#pragma CODE_SEG DEFAULT
|
||||
/************************************ end of vectors.c *********************************/
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/**
|
||||
\defgroup HCS12_Evbplus_Dragon12p_CodeWarrior Demo for Dragon12-plus/CodeWarrior
|
||||
\brief Preconfigured programs for the EVBplus Dragon12-plus and the CodeWarrior IDE.
|
||||
\details Refer to http://feaser.com/openblt/doku.php?id=manual:demos
|
||||
for detailed getting started instructions.
|
||||
*/
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
NAMES END /* CodeWarrior will pass all the needed files to the linker by command line. But here you may add your own files too. */
|
||||
|
||||
SEGMENTS /* Here all RAM/ROM areas of the device are listed. Used in PLACEMENT below. */
|
||||
/* RAM */
|
||||
RAM = READ_WRITE 0x3800 TO 0x3FFF;
|
||||
/* non-paged FLASHs */
|
||||
ROM_C000 = READ_ONLY 0xe800 TO 0xFEEF;
|
||||
/* for fixed address reset_connected_handler OpenBLT function */
|
||||
ENTRY_SEG = READ_ONLY 0xFEF0 TO 0xFEFF;
|
||||
END
|
||||
|
||||
PLACEMENT /* here all predefined and user segments are placed into the SEGMENTS defined above. */
|
||||
_PRESTART, /* Used in HIWARE format: jump to _Startup at the code start */
|
||||
STARTUP, /* startup data structures */
|
||||
ROM_VAR, /* constant variables */
|
||||
STRINGS, /* string literals */
|
||||
VIRTUAL_TABLE_SEGMENT, /* C++ virtual table segment */
|
||||
DEFAULT_ROM, NON_BANKED, /* runtime routines which must not be banked */
|
||||
COPY /* copy down information: how to initialize variables */
|
||||
/* in case you want to use ROM_4000 here as well, make sure
|
||||
that all files (incl. library files) are compiled with the
|
||||
option: -OnB=b */
|
||||
INTO ROM_C000;
|
||||
ENTRY INTO ENTRY_SEG;
|
||||
|
||||
SSTACK, /* allocate stack first to avoid overwriting variables on overflow */
|
||||
DEFAULT_RAM INTO RAM;
|
||||
END
|
||||
|
||||
ENTRIES /* keep the following unreferenced variables/functios */
|
||||
_vectab
|
||||
reset_connected_handler
|
||||
END
|
||||
|
||||
STACKSIZE 0x100
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,485 @@
|
|||
/*****************************************************
|
||||
start12.c - standard startup code
|
||||
The startup code may be optimized to special user requests
|
||||
----------------------------------------------------
|
||||
Copyright (c) Metrowerks, Basel, Switzerland
|
||||
All rights reserved
|
||||
|
||||
Note: ROM libraries are not implemented in this startup code
|
||||
Note: C++ destructors of global objects are NOT yet supported in the HIWARE Object File Format.
|
||||
To use this feature, please build your application with the ELF object file format.
|
||||
*****************************************************/
|
||||
/* these macros remove some unused fields in the startup descriptor */
|
||||
#define __NO_FLAGS_OFFSET /* we do not need the flags field in the startup data descriptor */
|
||||
#define __NO_MAIN_OFFSET /* we do not need the main field in the startup data descriptor */
|
||||
#define __NO_STACKOFFSET_OFFSET /* we do not need the stackOffset field in the startup data descriptor */
|
||||
|
||||
/*#define __BANKED_COPY_DOWN : allow to allocate .copy in flash area */
|
||||
#if defined(__BANKED_COPY_DOWN) && (!defined(__HCS12X__) || !defined(__ELF_OBJECT_FILE_FORMAT__))
|
||||
#error /* the __BANKED_COPY_DOWN switch is only supported for the HCS12X with ELF */
|
||||
/* (and not for the HC12, HCS12 or for the HIWARE object file format) */
|
||||
#endif
|
||||
|
||||
#include "hidef.h"
|
||||
#include "start12.h"
|
||||
|
||||
/***************************************************************************/
|
||||
/* Macros to control how the startup code handles the COP: */
|
||||
/* #define _DO_FEED_COP_ : do feed the COP */
|
||||
/* #define _DO_ENABLE_COP_: do enable the COP */
|
||||
/* #define _DO_DISABLE_COP_: disable the COP */
|
||||
/* Without defining any of these, the startup code does NOT handle the COP */
|
||||
/***************************************************************************/
|
||||
/* __ONLY_INIT_SP define: */
|
||||
/* This define selects an shorter version of the startup code */
|
||||
/* which only loads the stack pointer and directly afterwards calls */
|
||||
/* main. This version does however NOT initialized global variables */
|
||||
/* (So this version is not ANSI compliant!) */
|
||||
/***************************************************************************/
|
||||
/* __FAR_DATA define: */
|
||||
/* By default, the startup code only supports to initialize the default */
|
||||
/* kind of memory. If some memory is allocated far in the small or banked */
|
||||
/* memory model, then the startup code only supports to initialize this */
|
||||
/* memory blocks if __FAR_DATA is defined. If __FAR_DATA is not defined, */
|
||||
/* then the linker will issue a message like */
|
||||
/* "L1128: Cutting value _Range beg data member from 0xF01000 to 0x1000" */
|
||||
/* and this startup code writes to the cutted address */
|
||||
/***************************************************************************/
|
||||
/* __BANKED_COPY_DOWN define: */
|
||||
/* by default, the startup code assumes that the startup data structure */
|
||||
/* _startupData, the zero out areas and the .copy section are all */
|
||||
/* allocated in NON_BANKED memory. Especially the .copy section can be */
|
||||
/* huge if there are many or huge RAM areas to initialize. */
|
||||
/* For the HCS12X, which also copies the XGATE RAM located code via .copy */
|
||||
/* section, the startup code supports to allocate .copy in a banked flash */
|
||||
/* The placement of .copy in the prm file has to be adapted when adding or */
|
||||
/* removing the this macro. */
|
||||
/* Note: This macro is only supported for the HCS12X and when using ELF */
|
||||
/***************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define __EXTERN_C extern "C"
|
||||
#else
|
||||
#define __EXTERN_C
|
||||
#endif
|
||||
|
||||
/*lint -estring(961,"only preprocessor statements and comments before '#include'") , MISRA 19.1 ADV, non_bank.sgm and default.sgm each contain a conditionally compiled CODE_SEG pragma */
|
||||
|
||||
__EXTERN_C void main(void); /* prototype of main function */
|
||||
|
||||
#ifndef __ONLY_INIT_SP
|
||||
#pragma DATA_SEG __NEAR_SEG STARTUP_DATA /* _startupData can be accessed using 16 bit accesses. */
|
||||
/* This is needed because it contains the stack top, and without stack, far data cannot be accessed */
|
||||
struct _tagStartup _startupData; /* read-only: */
|
||||
/* _startupData is allocated in ROM and */
|
||||
/* initialized by the linker */
|
||||
#pragma DATA_SEG DEFAULT
|
||||
#endif /* __ONLY_INIT_SP */
|
||||
|
||||
#if defined(FAR_DATA) && (!defined(__HCS12X__) || defined(__BANKED_COPY_DOWN))
|
||||
/*lint -e451 non_bank.sgm contains a conditionally compiled CODE_SEG pragma */
|
||||
#include "non_bank.sgm"
|
||||
/*lint +e451 */
|
||||
|
||||
/* the init function must be in non banked memory if banked variables are used */
|
||||
/* because _SET_PAGE is called, which may change any page register. */
|
||||
|
||||
/*lint -esym(752,_SET_PAGE) , symbol '_SET_PAGE' is referenced in HLI */
|
||||
__EXTERN_C void _SET_PAGE(void); /* the inline assembler needs a prototype */
|
||||
/* this is a runtime routine with a special */
|
||||
/* calling convention, do not use it in c code! */
|
||||
#else
|
||||
/*lint -e451 default.sgm contains a conditionally compiled CODE_SEG pragma */
|
||||
#include "default.sgm"
|
||||
/*lint +e451 */
|
||||
#endif /* defined(FAR_DATA) && (!defined(__HCS12X__) || defined(__BANKED_COPY_DOWN)) */
|
||||
|
||||
|
||||
/* define value and bits for Windef Register */
|
||||
#ifdef HC812A4
|
||||
#define WINDEF (*(volatile unsigned char*) 0x37)
|
||||
#if defined( __BANKED__) || defined(__LARGE__) || defined(__PPAGE__)
|
||||
#define __ENABLE_PPAGE__ 0x40
|
||||
#else
|
||||
#define __ENABLE_PPAGE__ 0x0
|
||||
#endif
|
||||
#if defined(__DPAGE__)
|
||||
#define __ENABLE_DPAGE__ 0x80
|
||||
#else
|
||||
#define __ENABLE_DPAGE__ 0x0
|
||||
#endif
|
||||
#if defined(__EPAGE__)
|
||||
#define __ENABLE_EPAGE__ 0x20
|
||||
#else
|
||||
#define __ENABLE_EPAGE__ 0x0
|
||||
#endif
|
||||
#endif /* HC812A4 */
|
||||
|
||||
#define ___INITRM (*(volatile unsigned char *) 0x0010)
|
||||
#define ___INITRG (*(volatile unsigned char *) 0x0011)
|
||||
#define ___INITEE (*(volatile unsigned char *) 0x0012)
|
||||
|
||||
#if defined(_DO_FEED_COP_)
|
||||
#define __FEED_COP_IN_HLI() } asm movb #0x55, _COP_RST_ADR; asm movb #0xAA, _COP_RST_ADR; asm {
|
||||
#else
|
||||
#define __FEED_COP_IN_HLI() /* do nothing */
|
||||
#endif
|
||||
|
||||
#ifndef __ONLY_INIT_SP
|
||||
#if (!defined(FAR_DATA) || defined(__HCS12X__)) && (defined( __BANKED__) || defined(__LARGE__) || defined(__BANKED_COPY_DOWN))
|
||||
static void __far Init(void)
|
||||
#else
|
||||
static void Init(void)
|
||||
#endif
|
||||
{
|
||||
/* purpose: 1) zero out RAM-areas where data is allocated */
|
||||
/* 2) copy initialization data from ROM to RAM */
|
||||
/* 3) call global constructors in C++ */
|
||||
/* called from: _Startup, LibInits */
|
||||
asm {
|
||||
ZeroOut:
|
||||
#if defined(__HIWARE_OBJECT_FILE_FORMAT__) && defined(__LARGE__)
|
||||
LDX _startupData.pZeroOut:1 ; in the large memory model in the HIWARE format, pZeroOut is a 24 bit pointer
|
||||
#else
|
||||
LDX _startupData.pZeroOut ; *pZeroOut
|
||||
#endif
|
||||
LDY _startupData.nofZeroOuts ; nofZeroOuts
|
||||
BEQ CopyDown ; if nothing to zero out
|
||||
|
||||
NextZeroOut: PSHY ; save nofZeroOuts
|
||||
#if defined(FAR_DATA)
|
||||
LDAB 1,X+ ; load page of destination address
|
||||
LDY 2,X+ ; load offset of destination address
|
||||
#if defined(__HCS12X__)
|
||||
STAB __GPAGE_ADR__
|
||||
#else /* defined(__HCS12X__) */
|
||||
__PIC_JSR(_SET_PAGE) ; sets the page in the correct page register
|
||||
#endif /* defined(__HCS12X__) */
|
||||
#else /* FAR_DATA */
|
||||
LDY 2,X+ ; start address and advance *pZeroOut (X = X+4)
|
||||
#endif /* FAR_DATA */
|
||||
|
||||
#if defined(__HCS12X__) && defined(FAR_DATA)
|
||||
PSHX
|
||||
LDX 0,X ; byte count
|
||||
#if defined(__OPTIMIZE_FOR_SIZE__)
|
||||
CLRA
|
||||
NextWord: GSTAA 1,Y+ ; clear memory byte
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE X, NextWord ; dec byte count
|
||||
#else
|
||||
LDD #0
|
||||
LSRX
|
||||
BEQ LoopClrW1 ; do we copy more than 1 byte?
|
||||
NextWord: GSTD 2,Y+ ; clear memory word
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE X, NextWord ; dec word count
|
||||
LoopClrW1:
|
||||
BCC LastClr ; handle last byte
|
||||
GSTAA 1,Y+ ; handle last byte
|
||||
LastClr:
|
||||
#endif
|
||||
PULX
|
||||
LEAX 2,X
|
||||
#elif defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */
|
||||
LDD 2,X+ ; byte count
|
||||
NextWord: CLR 1,Y+ ; clear memory byte
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D, NextWord ; dec byte count
|
||||
#else /* __OPTIMIZE_FOR_TIME__ */
|
||||
LDD 2,X+ ; byte count
|
||||
LSRD ; /2 and save bit 0 in the carry
|
||||
BEQ LoopClrW1 ; do we copy more than 1 byte?
|
||||
PSHX
|
||||
LDX #0
|
||||
LoopClrW: STX 2,Y+ ; Word-Clear
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D, LoopClrW
|
||||
PULX
|
||||
LoopClrW1:
|
||||
BCC LastClr ; handle last byte
|
||||
CLR 1,Y+
|
||||
LastClr:
|
||||
#endif /* __OPTIMIZE_FOR_SIZE__/__OPTIMIZE_FOR_TIME__ */
|
||||
PULY ; restore nofZeroOuts
|
||||
DEY ; dec nofZeroOuts
|
||||
BNE NextZeroOut
|
||||
CopyDown:
|
||||
#if defined(__BANKED_COPY_DOWN)
|
||||
LDAA _startupData.toCopyDownBeg:0 ; get PAGE address of .copy section
|
||||
STAA __PPAGE_ADR__ ; set PPAGE address
|
||||
LDX _startupData.toCopyDownBeg:1 ; load address of copy down desc.
|
||||
#elif defined(__ELF_OBJECT_FILE_FORMAT__)
|
||||
LDX _startupData.toCopyDownBeg ; load address of copy down desc.
|
||||
#else
|
||||
LDX _startupData.toCopyDownBeg:2 ; load address of copy down desc.
|
||||
#endif
|
||||
NextBlock:
|
||||
LDD 2,X+ ; size of init-data -> D
|
||||
BEQ funcInits ; end of copy down desc.
|
||||
#ifdef FAR_DATA
|
||||
PSHD ; save counter
|
||||
LDAB 1,X+ ; load destination page
|
||||
LDY 2,X+ ; destination address
|
||||
#if defined(__HCS12X__)
|
||||
STAB __GPAGE_ADR__
|
||||
#else /* __HCS12X__ */
|
||||
__PIC_JSR(_SET_PAGE) ; sets the destinations page register
|
||||
#endif /* __HCS12X__ */
|
||||
PULD ; restore counter
|
||||
#else /* FAR_DATA */
|
||||
LDY 2,X+ ; load destination address
|
||||
#endif /* FAR_DATA */
|
||||
|
||||
#if defined(__HCS12X__) && defined(FAR_DATA)
|
||||
#if defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */
|
||||
Copy: PSHA
|
||||
LDAA 1,X+
|
||||
GSTAA 1,Y+ ; move a byte from ROM to the data area
|
||||
PULA
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D,Copy ; copy-byte loop
|
||||
#else
|
||||
LSRD ; /2 and save bit 0 in the carry
|
||||
BEQ Copy1 ; do we copy more than 1 byte?
|
||||
|
||||
Copy: PSHD
|
||||
LDD 2,X+
|
||||
GSTD 2,Y+ ; move a word from ROM to the data area
|
||||
PULD
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D,Copy ; copy-word loop
|
||||
Copy1:
|
||||
BCC NextBlock ; handle last byte?
|
||||
LDAA 1,X+
|
||||
GSTAA 1,Y+ ; move a byte from ROM to the data area
|
||||
#endif
|
||||
#elif defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */
|
||||
Copy: MOVB 1,X+,1,Y+ ; move a byte from ROM to the data area
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D,Copy ; copy-byte loop
|
||||
#else /* __OPTIMIZE_FOR_TIME__ */
|
||||
LSRD ; /2 and save bit 0 in the carry
|
||||
BEQ Copy1 ; do we copy more than 1 byte?
|
||||
Copy: MOVW 2,X+,2,Y+ ; move a word from ROM to the data area
|
||||
__FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */
|
||||
DBNE D,Copy ; copy-word loop
|
||||
Copy1:
|
||||
BCC NextBlock ; handle last byte?
|
||||
MOVB 1,X+,1,Y+ ; copy the last byte
|
||||
#endif /* __OPTIMIZE_FOR_SIZE__/__OPTIMIZE_FOR_TIME__ */
|
||||
BRA NextBlock
|
||||
funcInits: ; call of global construtors is only in c++ necessary
|
||||
#if defined(__cplusplus)
|
||||
#if defined(__ELF_OBJECT_FILE_FORMAT__)
|
||||
#if defined( __BANKED__) || defined(__LARGE__)
|
||||
LDY _startupData.nofInitBodies; load number of cpp.
|
||||
BEQ done ; if cppcount == 0, goto done
|
||||
LDX _startupData.initBodies ; load address of first module to initialize
|
||||
nextInit:
|
||||
LEAX 3,X ; increment to next init
|
||||
PSHX ; save address of next function to initialize
|
||||
PSHY ; save cpp counter
|
||||
CALL [-3,X] ; use double indirect call to load the page register also
|
||||
PULY ; restore cpp counter
|
||||
PULX ; restore actual address
|
||||
DEY ; decrement cpp counter
|
||||
BNE nextInit
|
||||
#else /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
|
||||
LDD _startupData.nofInitBodies; load number of cpp.
|
||||
BEQ done ; if cppcount == 0, goto done
|
||||
LDX _startupData.initBodies ; load address of first module to initialize
|
||||
nextInit:
|
||||
LDY 2,X+ ; load address of first module to initialize
|
||||
PSHD
|
||||
PSHX ; save actual address
|
||||
JSR 0,Y ; call initialization function
|
||||
PULX ; restore actual address
|
||||
PULD ; restore cpp counter
|
||||
DBNE D, nextInit
|
||||
#endif /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
#else /* __ELF_OBJECT_FILE_FORMAT__ */
|
||||
LDX _startupData.mInits ; load address of first module to initialize
|
||||
#if defined( __BANKED__) || defined(__LARGE__)
|
||||
nextInit: LDY 3,X+ ; load address of initialization function
|
||||
BEQ done ; stop when address == 0
|
||||
; in common environments the offset of a function is never 0, so this test could be avoided
|
||||
#ifdef __InitFunctionsMayHaveOffset0__
|
||||
BRCLR -1,X, done, 0xff ; stop when address == 0
|
||||
#endif /* __InitFunctionsMayHaveOffset0__ */
|
||||
PSHX ; save address of next function to initialize
|
||||
CALL [-3,X] ; use double indirect call to load the page register also
|
||||
#else /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
nextInit:
|
||||
LDY 2,X+ ; load address of first module to initialize
|
||||
BEQ done ; stop when address of function == 0
|
||||
PSHX ; save actual address
|
||||
JSR 0,Y ; call initialization function
|
||||
#endif /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
PULX ; restore actual address
|
||||
BRA nextInit
|
||||
#endif /* __ELF_OBJECT_FILE_FORMAT__ */
|
||||
done:
|
||||
#endif /* __cplusplus */
|
||||
}
|
||||
}
|
||||
#endif /* __ONLY_INIT_SP */
|
||||
|
||||
#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) && 0 /* the call to main does not support to return anymore */
|
||||
|
||||
#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__))
|
||||
static void __far Fini(void)
|
||||
#else
|
||||
static void Fini(void)
|
||||
#endif
|
||||
{
|
||||
/* purpose: 1) call global destructors in C++ */
|
||||
asm {
|
||||
#if defined( __BANKED__) || defined(__LARGE__)
|
||||
|
||||
LDY _startupData.nofFiniBodies; load number of cpp.
|
||||
BEQ done ; if cppcount == 0, goto done
|
||||
LDX _startupData.finiBodies ; load address of first module to finalize
|
||||
nextInit2:
|
||||
LEAX 3,X ; increment to next init
|
||||
PSHX ; save address of next function to finalize
|
||||
PSHY ; save cpp counter
|
||||
CALL [-3,X] ; use double indirect call to load the page register also
|
||||
PULY ; restore cpp counter
|
||||
PULX ; restore actual address
|
||||
DEY ; decrement cpp counter
|
||||
BNE nextInit2
|
||||
#else /* defined( __BANKED__) || defined(__LARGE__) */
|
||||
|
||||
LDD _startupData.nofFiniBodies; load number of cpp.
|
||||
BEQ done ; if cppcount == 0, goto done
|
||||
LDX _startupData.finiBodies ; load address of first module to finalize
|
||||
nextInit2:
|
||||
LDY 2,X+ ; load address of first module to finalize
|
||||
PSHD
|
||||
PSHX ; save actual address
|
||||
JSR 0,Y ; call finalize function
|
||||
PULX ; restore actual address
|
||||
PULD ; restore cpp counter
|
||||
DBNE D, nextInit2
|
||||
#endif /* defined(__BANKED__) || defined(__LARGE__) */
|
||||
done:;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*lint -e451 non_bank.sgm contains a conditionally compiled CODE_SEG pragma */
|
||||
#include "non_bank.sgm"
|
||||
/*lint +e451 */
|
||||
|
||||
#pragma MESSAGE DISABLE C12053 /* Stack-pointer change not in debugging-information */
|
||||
#pragma NO_FRAME
|
||||
#pragma NO_ENTRY
|
||||
#if !defined(__SMALL__)
|
||||
#pragma NO_EXIT
|
||||
#endif
|
||||
|
||||
/* The function _Startup must be called in order to initialize global variables and to call main */
|
||||
/* You can adapt this function or call it from your startup code to implement a different startup */
|
||||
/* functionality. */
|
||||
|
||||
/* You should also setup the needed IO registers as WINDEF (HC12A4 only) or the COP registers to run */
|
||||
/* on hardware */
|
||||
|
||||
/* to set the reset vector several ways are possible : */
|
||||
/* 1. define the function with "interrupt 0" as done below in the first case */
|
||||
/* 2. add the following line to your prm file : VECTOR ADDRESS 0xfffe _Startup */
|
||||
/* of course, even more posibilities exists */
|
||||
/* the reset vector must be set so that the application has a defined entry point */
|
||||
|
||||
#if defined(__SET_RESET_VECTOR__)
|
||||
__EXTERN_C void __interrupt 0 _Startup(void) {
|
||||
#else
|
||||
__EXTERN_C void _Startup(void) {
|
||||
#endif
|
||||
/* purpose: 1) initialize the stack
|
||||
2) initialize the RAM, copy down init data etc (Init)
|
||||
3) call main;
|
||||
parameters: NONE
|
||||
called from: _PRESTART-code generated by the Linker
|
||||
or directly referenced by the reset vector */
|
||||
|
||||
/* initialize the stack pointer */
|
||||
/*lint -e{960} , MISRA 14.3 REQ, macro INIT_SP_FROM_STARTUP_DESC() expands to HLI code */
|
||||
/*lint -e{522} , MISRA 14.2 REQ, macro INIT_SP_FROM_STARTUP_DESC() expands to HLI code */
|
||||
/* With OpenBLT this function is not directly called at reset, but called by a custom
|
||||
* reset handler. For this to work, the stackpointer must be initialized before this
|
||||
* function is called, otherwise the RTS instruction won't know where to go.
|
||||
*/
|
||||
/*INIT_SP_FROM_STARTUP_DESC();*/ /* HLI macro definition in hidef.h */
|
||||
|
||||
___INITRG = 0x00; /* lock registers block to 0x0000 */
|
||||
___INITRM = 0x39; /* lock Ram to end at 0x3FFF */
|
||||
___INITEE = 0x09; /* lock EEPROM block to end at 0x0fff */
|
||||
|
||||
/* Here user defined code could be inserted, the stack could be used */
|
||||
#if defined(_DO_DISABLE_COP_)
|
||||
_DISABLE_COP();
|
||||
#endif
|
||||
|
||||
/* Example : Set up WinDef Register to allow Paging */
|
||||
#ifdef HC812A4 /* HC12 A4 derivative needs WINDEF to configure which pages are available */
|
||||
#if (__ENABLE_EPAGE__ != 0 || __ENABLE_DPAGE__ != 0 || __ENABLE_PPAGE__ != 0)
|
||||
WINDEF= __ENABLE_EPAGE__ | __ENABLE_DPAGE__ | __ENABLE_PPAGE__;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(__MAP_RAM__) || defined(__MAP_FLASH__) || defined(__MAP_EXTERNAL__)) && !defined(__DO_SET_MMCTL1__)
|
||||
#define __DO_SET_MMCTL1__
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__DO_SET_MMCTL1__)
|
||||
/* Set the MMCTL1 byte. Please use for HCS12XE and change the bits according */
|
||||
/* to your configuration. */
|
||||
/* Note: MMCTL1 is write once therefore please adapt this initialization here. */
|
||||
/* This has to be done prior to the call to Init. */
|
||||
#define _MMCTL1_ADR (0x00000013)
|
||||
#define _MMCTL1_BIT_TGMRAMON (1<<7) /* EEE Tag RAM and FTM SCRATCH RAM visible in the memory map */
|
||||
#define _MMCTL1_BIT_EEEIFRON (1<<5) /* EEE IFR visible in the memory map */
|
||||
#define _MMCTL1_BIT_PGMIFRON (1<<4) /* Program IFR visible in the memory map */
|
||||
#define _MMCTL1_BIT_RAMHM (1<<3) /* RAM only in the higher half of the memory map */
|
||||
#define _MMCTL1_BIT_EROMON (1<<2) /* Enables emulated Flash or ROM memory in the memory map */
|
||||
#define _MMCTL1_BIT_ROMHM (1<<1) /* FLASH or ROM only in higher Half of Memory Map */
|
||||
#define _MMCTL1_BIT_ROMON (1<<0) /* Enable FLASH or ROM in the memory map */
|
||||
|
||||
#define _MMCTL1_SET(value) ((*(volatile unsigned char*)_MMCTL1_ADR)= (value))
|
||||
|
||||
#if defined(__MAP_FLASH__)
|
||||
_MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON);
|
||||
#elif defined(__MAP_EXTERNAL__)
|
||||
_MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON | _MMCTL1_BIT_ROMHM);
|
||||
#else /* RAM */
|
||||
_MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON | _MMCTL1_BIT_RAMHM | _MMCTL1_BIT_ROMHM);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __ONLY_INIT_SP
|
||||
/*lint -e{522} , MISRA 14.2 REQ, function Init() contains HLI only */
|
||||
Init(); /* zero out, copy down, call constructors */
|
||||
#endif
|
||||
|
||||
/* Here user defined code could be inserted, all global variables are initilized */
|
||||
#if defined(_DO_ENABLE_COP_)
|
||||
_ENABLE_COP(1);
|
||||
#endif
|
||||
|
||||
/* OpenBLT modifcation: do not call main. instead do this in the reset handler found in
|
||||
* vectors.c
|
||||
*/
|
||||
main();
|
||||
/* main(); */
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/*lint --e{766} , non_bank.sgm is not a regular header file, it contains a conditionally compiled CODE_SEG pragma */
|
||||
/*lint +estring(961,"only preprocessor statements and comments before '#include'") */
|
||||
/*lint +e451 */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,144 @@
|
|||
/************************************************************************************//**
|
||||
* \file Source\HCS12\cpu.c
|
||||
* \brief Bootloader cpu module source file.
|
||||
* \ingroup Target_HCS12
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Start address of the user program. This is the address of the reset vector
|
||||
* in the user program's vector table.
|
||||
* \attention This value must be updated if the memory reserved for the bootloader
|
||||
* changes.
|
||||
*/
|
||||
#define CPU_USER_PROGRAM_STARTADDR_PTR (0xE7FE)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Hook functions
|
||||
****************************************************************************************/
|
||||
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
|
||||
extern blt_bool CpuUserProgramStartHook(void);
|
||||
#endif
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* External functions
|
||||
****************************************************************************************/
|
||||
extern void reset_handler(void); /* implemented in C startup */
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Starts the user program, if one is present. In this case this function
|
||||
** does not return.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void CpuStartUserProgram(void)
|
||||
{
|
||||
void (*pProgResetHandler)(void);
|
||||
|
||||
/* check if a user program is present by verifying the checksum */
|
||||
if (NvmVerifyChecksum() == BLT_FALSE)
|
||||
{
|
||||
/* not a valid user program so it cannot be started */
|
||||
return;
|
||||
}
|
||||
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
|
||||
/* invoke callback */
|
||||
if (CpuUserProgramStartHook() == BLT_FALSE)
|
||||
{
|
||||
/* callback requests the user program to not be started */
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
#if (BOOT_COM_ENABLE > 0)
|
||||
/* release the communication interface */
|
||||
ComFree();
|
||||
#endif
|
||||
/* reset the timer */
|
||||
TimerReset();
|
||||
/* set the address where the bootloader needs to jump to. this is the address of
|
||||
* the last entry in the user program's vector table. this address points to the
|
||||
* user program's reset handler.
|
||||
*/
|
||||
pProgResetHandler = (void(*)(void))(*((blt_int16u*)CPU_USER_PROGRAM_STARTADDR_PTR));
|
||||
/* start the user program by activating its reset interrupt service routine */
|
||||
pProgResetHandler();
|
||||
} /*** end of CpuStartUserProgram ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Copies data from the source to the destination address.
|
||||
** \param dest Destination address for the data.
|
||||
** \param src Source address of the data.
|
||||
** \param len length of the data in bytes.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void CpuMemCopy(blt_addr dest, blt_addr src, blt_int16u len)
|
||||
{
|
||||
blt_int8u *from, *to;
|
||||
|
||||
/* set casted pointers */
|
||||
from = (blt_int8u *)src;
|
||||
to = (blt_int8u *)dest;
|
||||
|
||||
/* copy all bytes from source address to destination address */
|
||||
while(len-- > 0)
|
||||
{
|
||||
/* store byte value from source to destination */
|
||||
*to++ = *from++;
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
}
|
||||
} /*** end of CpuMemCopy ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Perform a soft reset of the microcontroller by starting from the reset ISR.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void CpuReset(void)
|
||||
{
|
||||
/* perform a software reset by calling the reset ISR routine */
|
||||
reset_handler();
|
||||
} /*** end of CpuReset ***/
|
||||
|
||||
|
||||
/*********************************** end of cpu.c **************************************/
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/************************************************************************************//**
|
||||
* \file Source\HCS12\cpu.h
|
||||
* \brief Bootloader cpu module header file.
|
||||
* \ingroup Target_HCS12
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef CPU_H
|
||||
#define CPU_H
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void CpuStartUserProgram(void);
|
||||
void CpuMemCopy(blt_addr dest, blt_addr src, blt_int16u len);
|
||||
void CpuReset(void);
|
||||
|
||||
|
||||
#endif /* CPU_H */
|
||||
/*********************************** end of cpu.h **************************************/
|
||||
|
|
@ -0,0 +1,975 @@
|
|||
/************************************************************************************//**
|
||||
* \file Source\HCS12\flash.c
|
||||
* \brief Bootloader flash driver source file.
|
||||
* \ingroup Target_HCS12
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Value for an invalid flash sector. */
|
||||
#define FLASH_INVALID_SECTOR_IDX (0xff)
|
||||
/** \brief Value for an invalid flash address. */
|
||||
#define FLASH_INVALID_ADDRESS (0xffffffff)
|
||||
/** \brief Standard size of a flash block for writing. */
|
||||
#define FLASH_WRITE_BLOCK_SIZE (512)
|
||||
/** \brief Total numbers of sectors in array flashLayout[]. */
|
||||
#define FLASH_TOTAL_SECTORS (sizeof(flashLayout)/sizeof(flashLayout[0]))
|
||||
#define FLASH_LAST_SECTOR_IDX (FLASH_TOTAL_SECTORS-1)
|
||||
#define FLASH_ERASE_BLOCK_SIZE (512)
|
||||
/** \brief Offset into the user program's vector table where the checksum is located. */
|
||||
#define FLASH_VECTOR_TABLE_CS_OFFSET (0x82)
|
||||
/** \brief Total size of the vector table, excluding the bootloader specific checksum. */
|
||||
#define FLASH_VECTOR_TABLE_SIZE (0x80)
|
||||
/** \brief Start address of the bootloader programmable flash. */
|
||||
#define FLASH_START_ADDRESS (flashLayout[0].sector_start)
|
||||
/** \brief End address of the bootloader programmable flash. */
|
||||
#define FLASH_END_ADDRESS (flashLayout[FLASH_LAST_SECTOR_IDX].sector_start + \
|
||||
flashLayout[FLASH_LAST_SECTOR_IDX].sector_size - 1)
|
||||
/** \brief Size of a flash page on the HCS12. */
|
||||
#define FLASH_PAGE_SIZE (0x4000) /* flash page size in bytes */
|
||||
/** \brief Physical start address of the HCS12 page window. */
|
||||
#define FLASH_PAGE_OFFSET (0x8000) /* physical start addr. of pages */
|
||||
/** \brief PPAGE register to select a specific flash page. */
|
||||
#define FLASH_PPAGE_REG (*(volatile blt_int8u *)(0x0030))
|
||||
/** \brief Base address of the flash related control registers. */
|
||||
#define FLASH_REGS_BASE_ADDRESS (0x0100)
|
||||
/** \brief Macro for accessing the flash related control registers. */
|
||||
#define FLASH ((volatile tFlashRegs *)FLASH_REGS_BASE_ADDRESS)
|
||||
/** \brief Program word flash command. */
|
||||
#define FLASH_PROGRAM_WORD_CMD (0x20)
|
||||
/** \brief Erase sector flash command. */
|
||||
#define FLASH_ERASE_SECTOR_CMD (0x40)
|
||||
#if (BOOT_NVM_SIZE_KB > 256)
|
||||
/** \brief Number of flash pages in a block. */
|
||||
#define FLASH_PAGES_PER_BLOCK (8)
|
||||
#else
|
||||
/** \brief Number of flash pages in a block. */
|
||||
#define FLASH_PAGES_PER_BLOCK (4)
|
||||
#endif
|
||||
/** \brief Bitmask for selecting a block with flash pages. */
|
||||
#define FLASH_BLOCK_SEL_MASK (0x03)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Register definitions
|
||||
****************************************************************************************/
|
||||
/** \brief FCLKDIV - enable prescaler by 8 bit. */
|
||||
#define PRDIV8_BIT (0x40)
|
||||
/** \brief FSTAT - flash access error bit. */
|
||||
#define ACCERR_BIT (0x10)
|
||||
/** \brief FSTAT - protection violation bit. */
|
||||
#define PVIOL_BIT (0x20)
|
||||
/** \brief FSTAT - command buffer empty flag bit. */
|
||||
#define CBEIF_BIT (0x80)
|
||||
/** \brief FCNFG - command buf. empty irq enable bit. */
|
||||
#define CBEIE_BIT (0x80)
|
||||
/** \brief FCNFG - command complete irg enable bit. */
|
||||
#define CCIE_BIT (0x40)
|
||||
/** \brief FCNFG - enable security key writing bit. */
|
||||
#define KEYACC_BIT (0x20)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Type definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Structure type for the flash sectors in the flash layout table. */
|
||||
typedef struct
|
||||
{
|
||||
blt_addr sector_start; /**< sector start address */
|
||||
blt_int32u sector_size; /**< sector size in bytes */
|
||||
} tFlashSector;
|
||||
|
||||
/** \brief Structure type for grouping flash block information.
|
||||
* \details Programming is done per block of max FLASH_WRITE_BLOCK_SIZE. for this a
|
||||
* flash block manager is implemented in this driver. this flash block manager
|
||||
* depends on this flash block info structure. It holds the base address of
|
||||
* the flash block and the data that should be programmed into the flash
|
||||
* block. The .base_addr must be a multiple of FLASH_WRITE_BLOCK_SIZE.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
blt_addr base_addr;
|
||||
blt_int8u data[FLASH_WRITE_BLOCK_SIZE];
|
||||
} tFlashBlockInfo;
|
||||
|
||||
/** \brief Structure type for the flash control registers. */
|
||||
typedef volatile struct
|
||||
{
|
||||
volatile blt_int8u fclkdiv; /**< flash clock devider register */
|
||||
volatile blt_int8u fsec; /**< flash security register */
|
||||
volatile blt_int8u ftstmod; /**< flash test mode register */
|
||||
volatile blt_int8u fcnfg; /**< flash configuration register */
|
||||
volatile blt_int8u fprot; /**< flash protection register */
|
||||
volatile blt_int8u fstat; /**< flash status register */
|
||||
volatile blt_int8u fcmd; /**< flash command register */
|
||||
} tFlashRegs;
|
||||
|
||||
/** \brief Pointer type to flash command execution function. */
|
||||
typedef void (*pFlashExeCmdFct) (void);
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
static blt_bool FlashInitBlock(tFlashBlockInfo *block, blt_addr address);
|
||||
static tFlashBlockInfo *FlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr);
|
||||
static blt_bool FlashAddToBlock(tFlashBlockInfo *block, blt_addr address,
|
||||
blt_int8u *data, blt_int32u len);
|
||||
static blt_bool FlashWriteBlock(tFlashBlockInfo *block);
|
||||
static blt_int8u FlashGetLinearAddrByte(blt_addr addr);
|
||||
static blt_int8u FlashGetPhysPage(blt_addr addr);
|
||||
static blt_int16u FlashGetPhysAddr(blt_addr addr);
|
||||
static void FlashExecuteCommand(void);
|
||||
static blt_bool FlashOperate(blt_int8u cmd, blt_addr addr, blt_int16u data);
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Local constant declarations
|
||||
****************************************************************************************/
|
||||
/** \brief Array wit the layout of the flash memory.
|
||||
* \details Also controls what part of the flash memory is reserved for the bootloader.
|
||||
* If the bootloader size changes, the reserved sectors for the bootloader
|
||||
* might need adjustment to make sure the bootloader doesn't get overwritten.
|
||||
* This layout uses linear addresses only. For example, the first address on
|
||||
* page 0x3F is: 0x3F * 0x4000 (page size) = 0xFC000. Note that page 0x3F is
|
||||
* where the bootloader also resides and it has been entered as 8 chunks of 2kb.
|
||||
* This allows flexibility for reserving more/less space for the bootloader in
|
||||
* case its size changes in the future.
|
||||
*/
|
||||
static const tFlashSector flashLayout[] =
|
||||
{
|
||||
#if (BOOT_NVM_SIZE_KB > 512)
|
||||
#error "BOOT_NVM_SIZE_KB > 512 is currently not supported."
|
||||
#endif
|
||||
#if (BOOT_NVM_SIZE_KB >= 512)
|
||||
{ 0x80000, 0x4000 }, /* flash page 0x20 - 16kb */
|
||||
{ 0x84000, 0x4000 }, /* flash page 0x21 - 16kb */
|
||||
{ 0x88000, 0x4000 }, /* flash page 0x22 - 16kb */
|
||||
{ 0x8C000, 0x4000 }, /* flash page 0x23 - 16kb */
|
||||
{ 0x90000, 0x4000 }, /* flash page 0x24 - 16kb */
|
||||
{ 0x94000, 0x4000 }, /* flash page 0x25 - 16kb */
|
||||
{ 0x98000, 0x4000 }, /* flash page 0x26 - 16kb */
|
||||
{ 0x9C000, 0x4000 }, /* flash page 0x27 - 16kb */
|
||||
{ 0xA0000, 0x4000 }, /* flash page 0x28 - 16kb */
|
||||
{ 0xA4000, 0x4000 }, /* flash page 0x29 - 16kb */
|
||||
{ 0xA8000, 0x4000 }, /* flash page 0x2A - 16kb */
|
||||
{ 0xAC000, 0x4000 }, /* flash page 0x2B - 16kb */
|
||||
{ 0xB0000, 0x4000 }, /* flash page 0x2C - 16kb */
|
||||
{ 0xB4000, 0x4000 }, /* flash page 0x2D - 16kb */
|
||||
{ 0xB8000, 0x4000 }, /* flash page 0x2E - 16kb */
|
||||
{ 0xBC000, 0x4000 }, /* flash page 0x2F - 16kb */
|
||||
#endif
|
||||
#if (BOOT_NVM_SIZE_KB >= 256)
|
||||
{ 0xC0000, 0x4000 }, /* flash page 0x30 - 16kb */
|
||||
{ 0xC4000, 0x4000 }, /* flash page 0x31 - 16kb */
|
||||
{ 0xC8000, 0x4000 }, /* flash page 0x32 - 16kb */
|
||||
{ 0xCC000, 0x4000 }, /* flash page 0x33 - 16kb */
|
||||
{ 0xD0000, 0x4000 }, /* flash page 0x34 - 16kb */
|
||||
{ 0xD4000, 0x4000 }, /* flash page 0x35 - 16kb */
|
||||
{ 0xD8000, 0x4000 }, /* flash page 0x36 - 16kb */
|
||||
{ 0xDC000, 0x4000 }, /* flash page 0x37 - 16kb */
|
||||
#endif
|
||||
#if (BOOT_NVM_SIZE_KB >= 128)
|
||||
{ 0xE0000, 0x4000 }, /* flash page 0x38 - 16kb */
|
||||
{ 0xE4000, 0x4000 }, /* flash page 0x39 - 16kb */
|
||||
#endif
|
||||
#if (BOOT_NVM_SIZE_KB >= 96)
|
||||
{ 0xE8000, 0x4000 }, /* flash page 0x3A - 16kb */
|
||||
{ 0xEC000, 0x4000 }, /* flash page 0x3B - 16kb */
|
||||
#endif
|
||||
#if (BOOT_NVM_SIZE_KB >= 64)
|
||||
{ 0xF0000, 0x4000 }, /* flash page 0x3C - 16kb */
|
||||
{ 0xF4000, 0x4000 }, /* flash page 0x3D - 16kb */
|
||||
#endif
|
||||
{ 0xF8000, 0x4000 }, /* flash page 0x3E - 16kb */
|
||||
{ 0xFC000, 0x0800 }, /* flash page 0x3F - 2kb */
|
||||
{ 0xFC800, 0x0800 }, /* flash page 0x3F - 2kb */
|
||||
{ 0xFD000, 0x0800 }, /* flash page 0x3F - 2kb */
|
||||
{ 0xFD800, 0x0800 }, /* flash page 0x3F - 2kb */
|
||||
{ 0xFE000, 0x0800 }, /* flash page 0x3F - 2kb */
|
||||
/* { 0xFE800, 0x0800 }, flash page 0x3F - reserved for bootloader */
|
||||
/* { 0xFF000, 0x0800 }, flash page 0x3F - reserved for bootloader */
|
||||
/* { 0xFF800, 0x0800 }, flash page 0x3F - reserved for bootloader */
|
||||
};
|
||||
|
||||
/** \brief Array with executable code for performing flash operations.
|
||||
* \details This array contains the machine code to perform the actual command on the
|
||||
* flash device, such as program or erase. the code is compiler and location
|
||||
* independent. This allows us to copy it to a ram buffer and execute the code
|
||||
* from ram. This way the flash driver can be located in flash memory without
|
||||
* running into problems when erasing/programming the same flash block that
|
||||
* contains the flash driver. the source code for the machine code is as
|
||||
* follows:
|
||||
* // launch the command
|
||||
* FLASH->fstat = CBEIF_BIT;
|
||||
* // wait at least 4 cycles (per AN2720)
|
||||
* asm("nop");
|
||||
* asm("nop");
|
||||
* asm("nop");
|
||||
* asm("nop");
|
||||
* // wait for command to complete
|
||||
* while ((FLASH->fstat & CCIF_BIT) != CCIF_BIT);
|
||||
*/
|
||||
static const blt_int8u flashExecCmd[] =
|
||||
{
|
||||
/* asm("psha"); backup A */
|
||||
0x36,
|
||||
/* asm("pshx"); backup X */
|
||||
0x34,
|
||||
/* asm("ldx #0x100"); load flash register base in X */
|
||||
0xce, 0x01, 0x00,
|
||||
/* asm("leax 5,x"); point X to FSTAT register */
|
||||
0x1a, 0x05,
|
||||
/* asm("ldaa #0x80"); load CBEIF mask in A */
|
||||
0x86, 0x80,
|
||||
/* asm("staa 0,x"); set CBEIF bit in FSTAT to launch the command */
|
||||
0x6a, 0x00,
|
||||
/* asm("nop"); [4 times] wait at least 4 cycles */
|
||||
0xa7,0xa7, 0xa7, 0xa7,
|
||||
/* asm("brclr 0,x,#0x40,*"); wait for command completion: CCIF in FSTAT equals 1 */
|
||||
0x0f, 0x00, 0x40, 0xfc,
|
||||
/* asm("pulx"); restore X */
|
||||
0x30,
|
||||
/* asm("pula"); restore A */
|
||||
0x32,
|
||||
/* asm("rts"); return */
|
||||
0x3d
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Local data declarations
|
||||
****************************************************************************************/
|
||||
/** \brief Local variable with information about the flash block that is currently
|
||||
* being operated on.
|
||||
* \details The smallest amount of flash that can be programmed is
|
||||
* FLASH_WRITE_BLOCK_SIZE. A flash block manager is implemented in this driver
|
||||
* and stores info in this variable. Whenever new data should be flashed, it
|
||||
* is first added to a RAM buffer, which is part of this variable. Whenever
|
||||
* the RAM buffer, which has the size of a flash block, is full or data needs
|
||||
* to be written to a different block, the contents of the RAM buffer are
|
||||
* programmed to flash. The flash block manager requires some software
|
||||
* overhead, yet results is faster flash programming because data is first
|
||||
* harvested, ideally until there is enough to program an entire flash block,
|
||||
* before the flash device is actually operated on.
|
||||
*/
|
||||
static tFlashBlockInfo blockInfo;
|
||||
|
||||
/** \brief Local variable with information about the flash boot block.
|
||||
* \details The first block of the user program holds the vector table, which on the
|
||||
* STM32 is also the where the checksum is written to. Is it likely that
|
||||
* the vector table is first flashed and then, at the end of the programming
|
||||
* sequence, the checksum. This means that this flash block need to be written
|
||||
* to twice. Normally this is not a problem with flash memory, as long as you
|
||||
* write the same values to those bytes that are not supposed to be changed
|
||||
* and the locations where you do write to are still in the erased 0xFF state.
|
||||
* Unfortunately, writing twice to flash this way, does not work reliably on
|
||||
* all micros. This is why we need to have an extra block, the bootblock,
|
||||
* placed under the management of the block manager. This way is it possible
|
||||
* to implement functionality so that the bootblock is only written to once
|
||||
* at the end of the programming sequence.
|
||||
*/
|
||||
static tFlashBlockInfo bootBlockInfo;
|
||||
|
||||
/** \brief RAM buffer where the executable flash operation code is copied to. */
|
||||
static blt_int8u flashExecCmdRam[(sizeof(flashExecCmd)/sizeof(flashExecCmd[0]))];
|
||||
|
||||
/** \brief Maximum number of supported blocks, which is determined dynamically to have
|
||||
* code that is independent of the used HCS12 derivative.
|
||||
*/
|
||||
static blt_int8u flashMaxNrBlocks;
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the flash driver.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void FlashInit(void)
|
||||
{
|
||||
blt_bool result = BLT_FALSE;
|
||||
blt_int8u cnt;
|
||||
blt_int8u prescaler = 1;
|
||||
blt_int16u clockFreq;
|
||||
|
||||
/* flash EEPROM programming requires a minimal system speed of 1 MHz */
|
||||
ASSERT_CT(BOOT_CPU_SYSTEM_SPEED_KHZ >= 1000);
|
||||
|
||||
/* init the flash block info structs by setting the address to an invalid address */
|
||||
blockInfo.base_addr = FLASH_INVALID_ADDRESS;
|
||||
bootBlockInfo.base_addr = FLASH_INVALID_ADDRESS;
|
||||
|
||||
/* determine how many flash blocks this device supports by first trying to set all
|
||||
* all block selection bits. on devices where a specific block is not supported,
|
||||
* the bit is reserved and will read back 0 afterwards
|
||||
*/
|
||||
FLASH->fcnfg |= FLASH_BLOCK_SEL_MASK;
|
||||
/* read back which ones got set */
|
||||
flashMaxNrBlocks = (FLASH->fcnfg & FLASH_BLOCK_SEL_MASK) + 1;
|
||||
/* set back to default reset value */
|
||||
FLASH->fcnfg &= ~(CBEIE_BIT | CCIE_BIT | KEYACC_BIT | FLASH_BLOCK_SEL_MASK);
|
||||
|
||||
/* enable extra prescale factor of 8 when the external crystal is > 12.8 MHz */
|
||||
if (BOOT_CPU_XTAL_SPEED_KHZ > 12800)
|
||||
{
|
||||
prescaler = 8;
|
||||
}
|
||||
|
||||
/* FDIV[5..0] can only be between 0 and 63 so do a linear search to find the correct
|
||||
* setting.
|
||||
*/
|
||||
for (cnt = 0; cnt <= 63; cnt++)
|
||||
{
|
||||
/* calculate current clock: FCLK = Fexternal_clock / (1 + FDIV[5..0]) */
|
||||
clockFreq = BOOT_CPU_XTAL_SPEED_KHZ / (prescaler * (1 + cnt));
|
||||
|
||||
/* is this a valid setting? */
|
||||
if ( (clockFreq > 150) && (clockFreq < 200) )
|
||||
{
|
||||
/* configure the setting while taking into account the prescaler */
|
||||
if (prescaler == 8)
|
||||
{
|
||||
FLASH->fclkdiv = (PRDIV8_BIT | cnt);
|
||||
}
|
||||
else
|
||||
{
|
||||
FLASH->fclkdiv = cnt;
|
||||
}
|
||||
|
||||
/* all done */
|
||||
result = BLT_TRUE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* make sure that a valid clock divider was found */
|
||||
ASSERT_RT(result == BLT_TRUE);
|
||||
} /*** end of FlashInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Writes the data to flash through a flash block manager. Note that this
|
||||
** function also checks that no data is programmed outside the flash
|
||||
** memory region, so the bootloader can never be overwritten.
|
||||
** \param addr Start address.
|
||||
** \param len Length in bytes.
|
||||
** \param data Pointer to the data buffer.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data)
|
||||
{
|
||||
blt_addr base_addr;
|
||||
blt_addr last_block_base_addr;
|
||||
|
||||
/* make sure the addresses are within the flash device */
|
||||
if ( (addr < FLASH_START_ADDRESS) || ((addr+len-1) > FLASH_END_ADDRESS) )
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
|
||||
/* determine the start address of the last block in flash */
|
||||
last_block_base_addr = flashLayout[FLASH_LAST_SECTOR_IDX].sector_start + \
|
||||
flashLayout[FLASH_LAST_SECTOR_IDX].sector_size - \
|
||||
FLASH_ERASE_BLOCK_SIZE;
|
||||
|
||||
/* if this is the bootblock, then let the boot block manager handle it */
|
||||
base_addr = (addr/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE;
|
||||
if (base_addr == last_block_base_addr)
|
||||
{
|
||||
/* let the boot block manager handle it */
|
||||
return FlashAddToBlock(&bootBlockInfo, addr, data, len);
|
||||
}
|
||||
/* let the block manager handle it */
|
||||
return FlashAddToBlock(&blockInfo, addr, data, len);
|
||||
} /*** end of FlashWrite ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Erases the flash memory. Note that this function also checks that no
|
||||
** data is erased outside the flash memory region, so the bootloader can
|
||||
** never be erased.
|
||||
** \param addr Start address.
|
||||
** \param len Length in bytes.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool FlashErase(blt_addr addr, blt_int32u len)
|
||||
{
|
||||
blt_addr erase_base_addr;
|
||||
blt_int16u nr_of_erase_blocks;
|
||||
blt_int32u total_erase_len;
|
||||
blt_int16u block_cnt;
|
||||
|
||||
/* determine the base address for the erase operation, by aligning to
|
||||
* FLASH_ERASE_BLOCK_SIZE.
|
||||
*/
|
||||
erase_base_addr = (addr/FLASH_ERASE_BLOCK_SIZE)*FLASH_ERASE_BLOCK_SIZE;
|
||||
|
||||
/* make sure the addresses are within the flash device */
|
||||
if ( (erase_base_addr < FLASH_START_ADDRESS) || ((addr+len-1) > FLASH_END_ADDRESS) )
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
|
||||
/* determine number of bytes to erase from base address */
|
||||
total_erase_len = len + (addr - erase_base_addr);
|
||||
|
||||
/* determine the number of blocks to erase */
|
||||
nr_of_erase_blocks = (blt_int16u) (total_erase_len / FLASH_ERASE_BLOCK_SIZE);
|
||||
if ((total_erase_len % FLASH_ERASE_BLOCK_SIZE) > 0)
|
||||
{
|
||||
nr_of_erase_blocks++;
|
||||
}
|
||||
|
||||
/* erase all blocks one by one */
|
||||
for (block_cnt=0; block_cnt<nr_of_erase_blocks; block_cnt++)
|
||||
{
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
|
||||
/* erase the block */
|
||||
if (FlashOperate(FLASH_ERASE_SECTOR_CMD, erase_base_addr, 0x55aa) == BLT_FALSE)
|
||||
{
|
||||
/* error occurred */
|
||||
return BLT_FALSE;
|
||||
}
|
||||
/* point to the next block's base address */
|
||||
erase_base_addr += FLASH_ERASE_BLOCK_SIZE;
|
||||
}
|
||||
|
||||
/* erase successful */
|
||||
return BLT_TRUE;
|
||||
} /*** end of FlashErase ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Writes a checksum of the user program to non-volatile memory. This is
|
||||
** performed once the entire user program has been programmed. Through
|
||||
** the checksum, the bootloader can check if the programming session
|
||||
** was completed, which indicates that a valid user programming is
|
||||
** present and can be started.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool FlashWriteChecksum(void)
|
||||
{
|
||||
blt_int16u signature_checksum = 0;
|
||||
blt_int8u byte_counter;
|
||||
blt_int16u vectab_offset;
|
||||
blt_addr checksum_address;
|
||||
|
||||
/* for the HCS12 target we defined the checksum as the 16-bit Two's complement value
|
||||
* of the sum of all the 64 interrupt vector addresses, so basically a checksum over
|
||||
* the contents of the entire user program interrupt vector table.
|
||||
*
|
||||
* the bootloader writes this 16-bit checksum value right after the vector table
|
||||
* of the user program. note that this means one extra dummy entry must be added
|
||||
* at the end of the user program's vector table to reserve storage space for the
|
||||
* checksum.
|
||||
*/
|
||||
|
||||
/* first check that the bootblock contains valid data. if not, this means the
|
||||
* bootblock is not part of the reprogramming this time and therefore no
|
||||
* new checksum needs to be written
|
||||
*/
|
||||
if (bootBlockInfo.base_addr == FLASH_INVALID_ADDRESS)
|
||||
{
|
||||
return BLT_TRUE;
|
||||
}
|
||||
|
||||
/* the bootblock contains the data for the last sector in flashLayout. the
|
||||
* user program vector table and the checkum will be located at the end
|
||||
* of this block. first determine the offset in the bootblock data to
|
||||
* reach the start of the vector table.
|
||||
*/
|
||||
vectab_offset = FLASH_WRITE_BLOCK_SIZE - FLASH_VECTOR_TABLE_SIZE;
|
||||
|
||||
/* compute the checksum. note that the user program's vectors are not yet written
|
||||
* to flash but are present in the bootblock data structure at this point.
|
||||
*/
|
||||
for (byte_counter=0; byte_counter<FLASH_VECTOR_TABLE_SIZE; byte_counter++)
|
||||
{
|
||||
|
||||
signature_checksum += bootBlockInfo.data[vectab_offset + byte_counter];
|
||||
}
|
||||
signature_checksum = ~signature_checksum; /* one's complement */
|
||||
signature_checksum += 1; /* two's complement */
|
||||
|
||||
/* write the checksum */
|
||||
checksum_address = flashLayout[FLASH_LAST_SECTOR_IDX].sector_start + \
|
||||
flashLayout[FLASH_LAST_SECTOR_IDX].sector_size - \
|
||||
FLASH_VECTOR_TABLE_CS_OFFSET;
|
||||
return FlashWrite(checksum_address, sizeof(signature_checksum),
|
||||
(blt_int8u*)&signature_checksum);
|
||||
} /*** end of FlashWriteChecksum ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Verifies the checksum, which indicates that a valid user program is
|
||||
** present and can be started.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool FlashVerifyChecksum(void)
|
||||
{
|
||||
blt_int16u signature_checksum = 0;
|
||||
blt_int8u byte_counter;
|
||||
blt_addr checksum_addr_lin;
|
||||
blt_addr vector_table_addr_lin;
|
||||
|
||||
/* get linear address of the checksum */
|
||||
checksum_addr_lin = (flashLayout[FLASH_LAST_SECTOR_IDX].sector_start + \
|
||||
flashLayout[FLASH_LAST_SECTOR_IDX].sector_size - \
|
||||
FLASH_VECTOR_TABLE_CS_OFFSET);
|
||||
/* get linear address of the vector table start */
|
||||
vector_table_addr_lin = (flashLayout[FLASH_LAST_SECTOR_IDX].sector_start + \
|
||||
flashLayout[FLASH_LAST_SECTOR_IDX].sector_size - \
|
||||
FLASH_VECTOR_TABLE_SIZE);
|
||||
/* compute the checksum based on how it was written by FlashWriteChecksum() */
|
||||
for (byte_counter=0; byte_counter<FLASH_VECTOR_TABLE_SIZE; byte_counter++)
|
||||
{
|
||||
signature_checksum += FlashGetLinearAddrByte(vector_table_addr_lin + byte_counter);
|
||||
}
|
||||
/* add the 16-bit checksum value */
|
||||
signature_checksum += (((blt_int16u)FlashGetLinearAddrByte(checksum_addr_lin) << 8) +
|
||||
FlashGetLinearAddrByte(checksum_addr_lin + 1));
|
||||
/* sum should add up to an unsigned 16-bit value of 0 */
|
||||
if (signature_checksum == 0)
|
||||
{
|
||||
/* checksum okay */
|
||||
return BLT_TRUE;
|
||||
}
|
||||
/* checksum incorrect */
|
||||
return BLT_FALSE;
|
||||
} /*** end of FlashVerifyChecksum ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Finalizes the flash driver operations. There could still be data in
|
||||
** the currently active block that needs to be flashed.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool FlashDone(void)
|
||||
{
|
||||
blt_int8u cnt;
|
||||
|
||||
/* check if there is still data waiting to be programmed in the boot block */
|
||||
if (bootBlockInfo.base_addr != FLASH_INVALID_ADDRESS)
|
||||
{
|
||||
if (FlashWriteBlock(&bootBlockInfo) == BLT_FALSE)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
/* check if there is still data waiting to be programmed */
|
||||
if (blockInfo.base_addr != FLASH_INVALID_ADDRESS)
|
||||
{
|
||||
if (FlashWriteBlock(&blockInfo) == BLT_FALSE)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
/* flash operations complete, so clear the RAM buffer with operation execution code */
|
||||
for (cnt=0; cnt<(sizeof(flashExecCmd)/sizeof(flashExecCmd[0])); cnt++)
|
||||
{
|
||||
// ##Vg TODO enable again.. flashExecCmdRam[cnt] = 0;
|
||||
}
|
||||
|
||||
/* still here so all is okay */
|
||||
return BLT_TRUE;
|
||||
} /*** end of FlashDone ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Copies data currently in flash to the block->data and sets the
|
||||
** base address.
|
||||
** \param block Pointer to flash block info structure to operate on.
|
||||
** \param address Base address of the block data.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_bool FlashInitBlock(tFlashBlockInfo *block, blt_addr address)
|
||||
{
|
||||
blt_int8u oldPage;
|
||||
|
||||
/* check address alignment */
|
||||
if ((address % FLASH_WRITE_BLOCK_SIZE) != 0)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
/* make sure that we are initializing a new block and not the same one */
|
||||
if (block->base_addr == address)
|
||||
{
|
||||
/* block already initialized, so nothing to do */
|
||||
return BLT_TRUE;
|
||||
}
|
||||
/* set the base address */
|
||||
block->base_addr = address;
|
||||
/* backup originally selected page */
|
||||
oldPage = FLASH_PPAGE_REG;
|
||||
/* select correct page */
|
||||
FLASH_PPAGE_REG = FlashGetPhysPage(address);
|
||||
/* copy the current data from flash */
|
||||
CpuMemCopy((blt_addr)block->data, (blt_addr)FlashGetPhysAddr(address), FLASH_WRITE_BLOCK_SIZE);
|
||||
/* restore originally selected page */
|
||||
FLASH_PPAGE_REG = oldPage;
|
||||
|
||||
return BLT_TRUE;
|
||||
} /*** end of FlashInitBlock ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Switches blocks by programming the current one and initializing the
|
||||
** next.
|
||||
** \param block Pointer to flash block info structure to operate on.
|
||||
** \param base_addr Base address of the next block.
|
||||
** \return The pointer of the block info struct that is no being used, or a NULL
|
||||
** pointer in case of error.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static tFlashBlockInfo *FlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr)
|
||||
{
|
||||
/* check if a switch needs to be made away from the boot block. in this case the boot
|
||||
* block shouldn't be written yet, because this is done at the end of the programming
|
||||
* session by FlashDone(), this is right after the checksum was written.
|
||||
*/
|
||||
if (block == &bootBlockInfo)
|
||||
{
|
||||
/* switch from the boot block to the generic block info structure */
|
||||
block = &blockInfo;
|
||||
}
|
||||
/* check if a switch back into the bootblock is needed. in this case the generic block
|
||||
* doesn't need to be written here yet.
|
||||
*/
|
||||
else if (base_addr == flashLayout[FLASH_LAST_SECTOR_IDX].sector_start)
|
||||
{
|
||||
/* switch from the generic block to the boot block info structure */
|
||||
block = &bootBlockInfo;
|
||||
base_addr = flashLayout[FLASH_LAST_SECTOR_IDX].sector_start;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* need to switch to a new block, so program the current one and init the next */
|
||||
if (FlashWriteBlock(block) == BLT_FALSE)
|
||||
{
|
||||
return BLT_NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/* initialize tne new block when necessary */
|
||||
if (FlashInitBlock(block, base_addr) == BLT_FALSE)
|
||||
{
|
||||
return BLT_NULL;
|
||||
}
|
||||
|
||||
/* still here to all is okay */
|
||||
return block;
|
||||
} /*** end of FlashSwitchBlock ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Programming is done per block. This function adds data to the block
|
||||
** that is currently collecting data to be written to flash. If the
|
||||
** address is outside of the current block, the current block is written
|
||||
** to flash an a new block is initialized.
|
||||
** \param block Pointer to flash block info structure to operate on.
|
||||
** \param address Flash destination address.
|
||||
** \param data Pointer to the byte array with data.
|
||||
** \param len Number of bytes to add to the block.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_bool FlashAddToBlock(tFlashBlockInfo *block, blt_addr address,
|
||||
blt_int8u *data, blt_int32u len)
|
||||
{
|
||||
blt_addr current_base_addr;
|
||||
blt_int8u *dst;
|
||||
blt_int8u *src;
|
||||
|
||||
/* determine the current base address */
|
||||
current_base_addr = (address/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE;
|
||||
|
||||
/* make sure the blockInfo is not uninitialized */
|
||||
if (block->base_addr == FLASH_INVALID_ADDRESS)
|
||||
{
|
||||
/* initialize the blockInfo struct for the current block */
|
||||
if (FlashInitBlock(block, current_base_addr) == BLT_FALSE)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
/* check if the new data fits in the current block */
|
||||
if (block->base_addr != current_base_addr)
|
||||
{
|
||||
/* need to switch to a new block, so program the current one and init the next */
|
||||
block = FlashSwitchBlock(block, current_base_addr);
|
||||
if (block == BLT_NULL)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
/* add the data to the current block, but check for block overflow */
|
||||
dst = &(block->data[address - block->base_addr]);
|
||||
src = data;
|
||||
do
|
||||
{
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
/* buffer overflow? */
|
||||
if ((blt_addr)(dst-&(block->data[0])) >= FLASH_WRITE_BLOCK_SIZE)
|
||||
{
|
||||
/* need to switch to a new block, so program the current one and init the next */
|
||||
block = FlashSwitchBlock(block, current_base_addr+FLASH_WRITE_BLOCK_SIZE);
|
||||
if (block == BLT_NULL)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
/* reset destination pointer */
|
||||
dst = &(block->data[0]);
|
||||
}
|
||||
/* write the data to the buffer */
|
||||
*dst = *src;
|
||||
/* update pointers */
|
||||
dst++;
|
||||
src++;
|
||||
/* decrement byte counter */
|
||||
len--;
|
||||
}
|
||||
while (len > 0);
|
||||
/* still here so all is good */
|
||||
return BLT_TRUE;
|
||||
} /*** end of FlashAddToBlock ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Programs FLASH_WRITE_BLOCK_SIZE bytes to flash from the block->data
|
||||
** array.
|
||||
** \param block Pointer to flash block info structure to operate on.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_bool FlashWriteBlock(tFlashBlockInfo *block)
|
||||
{
|
||||
blt_bool result = BLT_TRUE;
|
||||
blt_addr prog_addr;
|
||||
blt_int16u prog_data;
|
||||
blt_int16u word_cnt;
|
||||
|
||||
|
||||
/* make sure the blockInfo is not uninitialized */
|
||||
if (block->base_addr == FLASH_INVALID_ADDRESS)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
/* program all words in the block one by one */
|
||||
for (word_cnt=0; word_cnt<(FLASH_WRITE_BLOCK_SIZE/sizeof(blt_int16u)); word_cnt++)
|
||||
{
|
||||
prog_addr = block->base_addr + (word_cnt * sizeof(blt_int16u));
|
||||
prog_data = *(volatile blt_int16u*)(&block->data[word_cnt * sizeof(blt_int16u)]);
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
/* program the word to flash */
|
||||
if (FlashOperate(FLASH_PROGRAM_WORD_CMD, prog_addr, prog_data) == BLT_FALSE)
|
||||
{
|
||||
/* error occurred */
|
||||
result = BLT_FALSE;
|
||||
break;
|
||||
}
|
||||
/* verify that the written data is actually there */
|
||||
if (FlashGetLinearAddrByte(prog_addr) != (blt_int8u)(prog_data >> 8))
|
||||
{
|
||||
/* msb not correctly written */
|
||||
result = BLT_FALSE;
|
||||
break;
|
||||
}
|
||||
if (FlashGetLinearAddrByte(prog_addr+1) != (blt_int8u)(prog_data))
|
||||
{
|
||||
/* lsb not correctly written */
|
||||
result = BLT_FALSE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* still here so all is okay */
|
||||
return result;
|
||||
} /*** end of FlashWriteBlock ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Reads the byte value from the linear address.
|
||||
** \param addr Linear address.
|
||||
** \return The byte value located at the linear address.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_int8u FlashGetLinearAddrByte(blt_addr addr)
|
||||
{
|
||||
blt_int8u oldPage;
|
||||
blt_int8u result;
|
||||
|
||||
/* backup originally selected page */
|
||||
oldPage = FLASH_PPAGE_REG;
|
||||
|
||||
/* select correct page */
|
||||
FLASH_PPAGE_REG = FlashGetPhysPage(addr);
|
||||
|
||||
/* read the byte value from the page address */
|
||||
result = *((blt_int8u*)FlashGetPhysAddr(addr));
|
||||
|
||||
/* restore originally selected page */
|
||||
FLASH_PPAGE_REG = oldPage;
|
||||
|
||||
/* return the read byte value */
|
||||
return result;
|
||||
} /*** end of FlashGetLinearAddrByte ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Extracts the physical flash page number from a linear address.
|
||||
** \param addr Linear address.
|
||||
** \return The page number.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_int8u FlashGetPhysPage(blt_addr addr)
|
||||
{
|
||||
return (blt_int8u)(addr / FLASH_PAGE_SIZE);
|
||||
} /*** end of FlashGetPhysPage ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Extracts the physical address on the flash page number from a
|
||||
** linear address.
|
||||
** \param addr Linear address.
|
||||
** \return The physical address.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_int16u FlashGetPhysAddr(blt_addr addr)
|
||||
{
|
||||
return (blt_int16u)(((blt_int16u)addr % FLASH_PAGE_SIZE) + FLASH_PAGE_OFFSET);
|
||||
} /*** end of FlashGetPhysAddr ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Executes the command. The actual code for the command execution is
|
||||
** stored as location independant machine code in array flashExecCmd[].
|
||||
** The contents of this array are temporarily copied to RAM. This way the
|
||||
** function can be executed from RAM avoiding problem when try to perform
|
||||
** a flash operation on the same flash block that this driver is located.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static void FlashExecuteCommand(void)
|
||||
{
|
||||
/* pointer to command execution function */
|
||||
pFlashExeCmdFct pExecCommandFct;
|
||||
blt_int8u cnt;
|
||||
|
||||
/* copy code for command execution to ram buffer */
|
||||
for (cnt=0; cnt<(sizeof(flashExecCmd)/sizeof(flashExecCmd[0])); cnt++)
|
||||
{
|
||||
flashExecCmdRam[cnt] = flashExecCmd[cnt];
|
||||
}
|
||||
|
||||
/* init the function pointer */
|
||||
pExecCommandFct = (pFlashExeCmdFct) ((void *)flashExecCmdRam);
|
||||
/* call the command execution function */
|
||||
pExecCommandFct();
|
||||
} /*** end of FlashExecuteCommand ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Prepares the flash command and executes it.
|
||||
** \param cmd Command to be launched.
|
||||
** \param addr Physical address for operation.
|
||||
** \param data Data to write to addr for operation.
|
||||
** \return BLT_TRUE if operation was successful, otherwise BLT_FALSE.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_bool FlashOperate(blt_int8u cmd, blt_addr addr, blt_int16u data)
|
||||
{
|
||||
blt_bool result;
|
||||
blt_int8u oldPage;
|
||||
blt_int8u selPage;
|
||||
|
||||
/* set default result to error */
|
||||
result = BLT_FALSE;
|
||||
/* backup originally selected page */
|
||||
oldPage = FLASH_PPAGE_REG;
|
||||
/* calculate page number */
|
||||
selPage = FlashGetPhysPage(addr);
|
||||
/* select correct page */
|
||||
FLASH_PPAGE_REG = selPage;
|
||||
|
||||
/* there are always a fixed number of pages per block. to get the block index number
|
||||
* we simply divide by this number of pages per block. to one tricky thing is that
|
||||
* the block number goes from high to low with increasing page numbers so we need to
|
||||
* invert it. After the inversion we apply a bitmask to obtain the block selection bits
|
||||
*/
|
||||
FLASH->fcnfg &= ~FLASH_BLOCK_SEL_MASK;
|
||||
FLASH->fcnfg |= (~(selPage / FLASH_PAGES_PER_BLOCK)) & FLASH_BLOCK_SEL_MASK;
|
||||
|
||||
/* clear error flags */
|
||||
FLASH->fstat = (ACCERR_BIT | PVIOL_BIT);
|
||||
/* command buffer empty? */
|
||||
if ((FLASH->fstat & CBEIF_BIT) == CBEIF_BIT)
|
||||
{
|
||||
/* write data value to the physical address to operate on */
|
||||
*((blt_int16u*)FlashGetPhysAddr(addr)) = data;
|
||||
/* write the command */
|
||||
FLASH->fcmd = cmd;
|
||||
/* launch the actual command */
|
||||
FlashExecuteCommand();
|
||||
/* check error flags */
|
||||
if ((FLASH->fstat & (ACCERR_BIT | PVIOL_BIT)) == 0)
|
||||
{
|
||||
/* operation was successful */
|
||||
result = BLT_TRUE;
|
||||
}
|
||||
}
|
||||
|
||||
/* restore originally selected page */
|
||||
FLASH_PPAGE_REG = oldPage;
|
||||
|
||||
return result;
|
||||
} /*** end of FlashOperate ***/
|
||||
|
||||
|
||||
/*********************************** end of flash.c ************************************/
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/************************************************************************************//**
|
||||
* \file Source\HCS12\flash.c
|
||||
* \brief Bootloader flash driver source file.
|
||||
* \ingroup Target_HCS12
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef FLASH_H
|
||||
#define FLASH_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void FlashInit(void);
|
||||
blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data);
|
||||
blt_bool FlashErase(blt_addr addr, blt_int32u len);
|
||||
blt_bool FlashWriteChecksum(void);
|
||||
blt_bool FlashVerifyChecksum(void);
|
||||
blt_bool FlashDone(void);
|
||||
|
||||
|
||||
#endif /* FLASH_H */
|
||||
/*********************************** end of flash.h ************************************/
|
||||
|
|
@ -0,0 +1,216 @@
|
|||
/************************************************************************************//**
|
||||
* \file Source\HCS12\nvm.c
|
||||
* \brief Bootloader non-volatile memory driver source file.
|
||||
* \ingroup Target_HCS12
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Hook functions
|
||||
****************************************************************************************/
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
extern void NvmInitHook(void);
|
||||
extern blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data);
|
||||
extern blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len);
|
||||
extern blt_bool NvmDoneHook(void);
|
||||
#endif
|
||||
|
||||
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
|
||||
extern blt_bool NvmWriteChecksumHook(void);
|
||||
extern blt_bool NvmVerifyChecksumHook(void);
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the NVM driver.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void NvmInit(void)
|
||||
{
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
/* give the application a chance to initialize a driver for operating on NVM
|
||||
* that is not by default supported by this driver.
|
||||
*/
|
||||
NvmInitHook();
|
||||
#endif
|
||||
|
||||
/* init the internal driver */
|
||||
FlashInit();
|
||||
} /*** end of NvmInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Programs the non-volatile memory.
|
||||
** \param addr Start address.
|
||||
** \param len Length in bytes.
|
||||
** \param data Pointer to the data buffer.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmWrite(blt_addr addr, blt_int32u len, blt_int8u *data)
|
||||
{
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
blt_int8u result = BLT_NVM_NOT_IN_RANGE;
|
||||
#endif
|
||||
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
/* give the application a chance to operate on memory that is not by default supported
|
||||
* by this driver.
|
||||
*/
|
||||
result = NvmWriteHook(addr, len, data);
|
||||
|
||||
/* process the return code */
|
||||
if (result == BLT_NVM_OKAY)
|
||||
{
|
||||
/* data was within range of the additionally supported memory and succesfully
|
||||
* programmed, so we are all done.
|
||||
*/
|
||||
return BLT_TRUE;
|
||||
}
|
||||
else if (result == BLT_NVM_ERROR)
|
||||
{
|
||||
/* data was within range of the additionally supported memory and attempted to be
|
||||
* programmed, but an error occurred, so we can't continue.
|
||||
*/
|
||||
return BLT_FALSE;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* still here so the internal driver should try and perform the program operation */
|
||||
return FlashWrite(addr, len, data);
|
||||
} /*** end of NvmWrite ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Erases the non-volatile memory.
|
||||
** \param addr Start address.
|
||||
** \param len Length in bytes.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmErase(blt_addr addr, blt_int32u len)
|
||||
{
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
blt_int8u result = BLT_NVM_NOT_IN_RANGE;
|
||||
#endif
|
||||
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
/* give the application a chance to operate on memory that is not by default supported
|
||||
* by this driver.
|
||||
*/
|
||||
result = NvmEraseHook(addr, len);
|
||||
|
||||
/* process the return code */
|
||||
if (result == BLT_NVM_OKAY)
|
||||
{
|
||||
/* address was within range of the additionally supported memory and succesfully
|
||||
* erased, so we are all done.
|
||||
*/
|
||||
return BLT_TRUE;
|
||||
}
|
||||
else if (result == BLT_NVM_ERROR)
|
||||
{
|
||||
/* address was within range of the additionally supported memory and attempted to be
|
||||
* erased, but an error occurred, so we can't continue.
|
||||
*/
|
||||
return BLT_FALSE;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* still here so the internal driver should try and perform the erase operation */
|
||||
return FlashErase(addr, len);
|
||||
} /*** end of NvmErase ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Verifies the checksum, which indicates that a valid user program is
|
||||
** present and can be started.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmVerifyChecksum(void)
|
||||
{
|
||||
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
|
||||
/* check checksum using the application specific method. */
|
||||
return NvmVerifyChecksumHook();
|
||||
#else
|
||||
/* check checksum using the interally supported method. */
|
||||
return FlashVerifyChecksum();
|
||||
#endif
|
||||
} /*** end of NvmVerifyChecksum ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Once all erase and programming operations are completed, this
|
||||
** function is called, so at the end of the programming session and
|
||||
** right before a software reset is performed. It is used to calculate
|
||||
** a checksum and program this into flash. This checksum is later used
|
||||
** to determine if a valid user program is present in flash.
|
||||
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool NvmDone(void)
|
||||
{
|
||||
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||
/* give the application's NVM driver a chance to finish up */
|
||||
if (NvmDoneHook() == BLT_FALSE)
|
||||
{
|
||||
/* error so no need to continue */
|
||||
return BLT_FALSE;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
|
||||
/* compute and write checksum, using the application specific method. */
|
||||
if (NvmWriteChecksumHook() == BLT_FALSE)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
#else
|
||||
/* compute and write checksum, which is programmed by the internal driver. */
|
||||
if (FlashWriteChecksum() == BLT_FALSE)
|
||||
{
|
||||
return BLT_FALSE;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* finish up internal driver operations */
|
||||
return FlashDone();
|
||||
} /*** end of NvmDone ***/
|
||||
|
||||
|
||||
/*********************************** end of nvm.c **************************************/
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/************************************************************************************//**
|
||||
* \file Source\HCS12\nvm.h
|
||||
* \brief Bootloader non-volatile memory driver header file.
|
||||
* \ingroup Target_HCS12
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef NVM_H
|
||||
#define NVM_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "flash.h" /* LPC2xxx flash driver */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void NvmInit(void);
|
||||
blt_bool NvmWrite(blt_addr addr, blt_int32u len, blt_int8u *data);
|
||||
blt_bool NvmErase(blt_addr addr, blt_int32u len);
|
||||
blt_bool NvmVerifyChecksum(void);
|
||||
blt_bool NvmDone(void);
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
/* return codes for hook function NvmWrite/Erase */
|
||||
/** \brief Return code for success. */
|
||||
#define BLT_NVM_ERROR (0x00)
|
||||
/** \brief Return code for error. */
|
||||
#define BLT_NVM_OKAY (0x01)
|
||||
/** \brief Return code for not in range. */
|
||||
#define BLT_NVM_NOT_IN_RANGE (0x02)
|
||||
|
||||
|
||||
#endif /* NVM_H */
|
||||
/*********************************** end of nvm.h **************************************/
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/**
|
||||
\defgroup Target_HCS12 Target HCS12
|
||||
\brief Target dependent code for the Freescale HCS12 microcontroller family.
|
||||
\details This module implements the bootloader's target dependent part for the
|
||||
Freescale HCS12 microcontroller family.
|
||||
*/
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,178 @@
|
|||
/************************************************************************************//**
|
||||
* \file Source\HCS12\timer.c
|
||||
* \brief Bootloader timer driver source file.
|
||||
* \ingroup Target_HCS12
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Type definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Structure type with the layout of the timer related control registers. */
|
||||
typedef struct
|
||||
{
|
||||
volatile blt_int8u tios; /**< input capture/output compare select */
|
||||
volatile blt_int8u cforc; /**< compare force register */
|
||||
volatile blt_int8u oc7m; /**< output compare 7 mask register */
|
||||
volatile blt_int8u oc7d; /**< output compare 7 data register */
|
||||
volatile blt_int16u tcnt; /**< timer counter register */
|
||||
volatile blt_int8u tscr1; /**< system control register 1 */
|
||||
volatile blt_int8u ttov; /**< toggle overflow register */
|
||||
volatile blt_int8u tctl1; /**< timer control register 1 */
|
||||
volatile blt_int8u tctl2; /**< timer control register 2 */
|
||||
volatile blt_int8u tctl3; /**< timer control register 3 */
|
||||
volatile blt_int8u tctl4; /**< timer control register 4 */
|
||||
volatile blt_int8u tie; /**< interrupt enable register */
|
||||
volatile blt_int8u tscr2; /**< system control register 2 */
|
||||
volatile blt_int8u tflg1; /**< timer interrupt flag 1 */
|
||||
volatile blt_int8u tflg2; /**< timer interrupt flag 2 */
|
||||
volatile blt_int16u tc[8]; /**< input capture/output compare register n */
|
||||
} tTimerRegs; /**< timer related registers */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Base address for the timer related control registers. */
|
||||
#define TIMER_REGS_BASE_ADDRESS (0x0040)
|
||||
/** \brief Macro for accessing the flash related control registers. */
|
||||
#define TIMER ((volatile tTimerRegs *)TIMER_REGS_BASE_ADDRESS)
|
||||
/** \brief Number of free running counter ticks in one millisecond. */
|
||||
#define TIMER_COUNTS_PER_MS (BOOT_CPU_SYSTEM_SPEED_KHZ)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Local data declarations
|
||||
****************************************************************************************/
|
||||
/** \brief Local variable for storing the number of milliseconds that have elapsed since
|
||||
* startup.
|
||||
*/
|
||||
static blt_int32u millisecond_counter;
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Register definitions
|
||||
****************************************************************************************/
|
||||
/** \brief TSCR1 - timer enable bit. */
|
||||
#define TEN_BIT (0x80)
|
||||
/** \brief TIOS - channel 0 ic/oc configuration bit. */
|
||||
#define IOS0_BIT (0x01)
|
||||
/** \brief TFLG1 - channel 0 ic/oc event flag bit. */
|
||||
#define C0F_BIT (0x01)
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the polling based millisecond timer driver.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void TimerInit(void)
|
||||
{
|
||||
/* reset the timer configuration. note that this also sets the default prescaler
|
||||
* to 1, so the free running counter runs at the same speed as the system
|
||||
* (BOOT_CPU_SYSTEM_SPEED_KHZ).
|
||||
*/
|
||||
TimerReset();
|
||||
/* configure timer channel 0 as a 1 millisecond software timer */
|
||||
TIMER->tios |= IOS0_BIT;
|
||||
/* make sure timer 0 interrupt flag is cleared */
|
||||
TIMER->tflg1 = C0F_BIT;
|
||||
/* generate output compare event in 1 milliseconds from now */
|
||||
TIMER->tc[0] = TIMER->tcnt + TIMER_COUNTS_PER_MS;
|
||||
/* enable the timer subsystem */
|
||||
TIMER->tscr1 |= TEN_BIT;
|
||||
/* reset the millisecond counter value */
|
||||
millisecond_counter = 0;
|
||||
} /*** end of TimerInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Reset the timer by placing the timer back into it's default reset
|
||||
** configuration.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void TimerReset(void)
|
||||
{
|
||||
/* bring the timer subsystem back into its reset state */
|
||||
TIMER->tie = 0;
|
||||
TIMER->tscr1 = 0;
|
||||
TIMER->tscr2 = 0;
|
||||
TIMER->tios = 0;
|
||||
TIMER->ttov = 0;
|
||||
TIMER->tctl1 = 0;
|
||||
TIMER->tctl2 = 0;
|
||||
TIMER->tctl3 = 0;
|
||||
TIMER->tctl4 = 0;
|
||||
} /* end of TimerReset */
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Updates the millisecond timer.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void TimerUpdate(void)
|
||||
{
|
||||
/* check if the millisecond event occurred */
|
||||
if ((TIMER->tflg1 & C0F_BIT) == C0F_BIT)
|
||||
{
|
||||
/* make sure timer 0 interrupt flag is cleared */
|
||||
TIMER->tflg1 = C0F_BIT;
|
||||
/* generate output compare event in 1 milliseconds from now */
|
||||
TIMER->tc[0] += TIMER_COUNTS_PER_MS;
|
||||
/* increment the millisecond counter */
|
||||
millisecond_counter++;
|
||||
}
|
||||
} /*** end of TimerUpdate ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Obtains the counter value of the millisecond timer.
|
||||
** \return Current value of the millisecond timer.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_int32u TimerGet(void)
|
||||
{
|
||||
/* updating timer here allows this function to be called in a loop with timeout
|
||||
* detection.
|
||||
*/
|
||||
TimerUpdate();
|
||||
/* read and return the amount of milliseconds that passed since initialization */
|
||||
return millisecond_counter;
|
||||
} /*** end of TimerGet ***/
|
||||
|
||||
|
||||
/*********************************** end of timer.c ************************************/
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/************************************************************************************//**
|
||||
* \file Source\HCS12\timer.h
|
||||
* \brief Bootloader timer driver header file.
|
||||
* \ingroup Target_HCS12
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef TIMER_H
|
||||
#define TIMER_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void TimerInit(void);
|
||||
void TimerUpdate(void);
|
||||
blt_int32u TimerGet(void);
|
||||
void TimerReset(void);
|
||||
|
||||
|
||||
#endif /* TIMER_H */
|
||||
/*********************************** end of timer.h ************************************/
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/************************************************************************************//**
|
||||
* \file Source\HCS12\types.h
|
||||
* \brief Bootloader types header file.
|
||||
* \ingroup Target_HCS12
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef TYPES_H
|
||||
#define TYPES_H
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Boolean true value. */
|
||||
#define BLT_TRUE (1)
|
||||
/** \brief Boolean false value. */
|
||||
#define BLT_FALSE (0)
|
||||
/** \brief NULL pointer value. */
|
||||
#define BLT_NULL ((void *)0)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Type definitions
|
||||
****************************************************************************************/
|
||||
typedef unsigned char blt_bool; /**< boolean type */
|
||||
typedef char blt_char; /**< character type */
|
||||
typedef unsigned long blt_addr; /**< memory address type */
|
||||
typedef unsigned char blt_int8u; /**< 8-bit unsigned integer */
|
||||
typedef signed char blt_int8s; /**< 8-bit signed integer */
|
||||
typedef unsigned short blt_int16u; /**< 16-bit unsigned integer */
|
||||
typedef signed short blt_int16s; /**< 16-bit signed integer */
|
||||
typedef unsigned long blt_int32u; /**< 32-bit unsigned integer */
|
||||
typedef signed long blt_int32s; /**< 32-bit signed integer */
|
||||
|
||||
|
||||
#endif /* TYPES_H */
|
||||
/*********************************** end of types.h ************************************/
|
||||
|
|
@ -0,0 +1,252 @@
|
|||
/************************************************************************************//**
|
||||
* \file Source\HCS12\uart.c
|
||||
* \brief Bootloader UART communication interface source file.
|
||||
* \ingroup Target_HCS12
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Include files
|
||||
****************************************************************************************/
|
||||
#include "boot.h" /* bootloader generic header */
|
||||
|
||||
|
||||
#if (BOOT_COM_UART_ENABLE > 0)
|
||||
/****************************************************************************************
|
||||
* Type definitions
|
||||
****************************************************************************************/
|
||||
/** \brief Structure type with the layout of the UART related controler registers. */
|
||||
typedef volatile struct
|
||||
{
|
||||
volatile blt_int8u scibdh; /**< baudrate control register [SBR 12..8] */
|
||||
volatile blt_int8u scibdl; /**< baudrate control register [SBR 8..0] */
|
||||
volatile blt_int8u scicr1; /**< control register 1 */
|
||||
volatile blt_int8u scicr2; /**< control register 2 */
|
||||
volatile blt_int8u scisr1; /**< status regsiter 1 */
|
||||
volatile blt_int8u scisr2; /**< status register 2 */
|
||||
volatile blt_int8u scidrh; /**< data register high (for ninth bit) */
|
||||
volatile blt_int8u scidrl; /**< data regsiter low */
|
||||
} tUartRegs; /**< sci related registers */
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Macro definitions
|
||||
****************************************************************************************/
|
||||
#if (BOOT_COM_UART_CHANNEL_INDEX == 0)
|
||||
/** \brief Set UART base address to SCI0. */
|
||||
#define UART_REGS_BASE_ADDRESS (0x00c8)
|
||||
#elif (BOOT_COM_UART_CHANNEL_INDEX == 1)
|
||||
/** \brief Set UART base address to SCI1. */
|
||||
#define UART_REGS_BASE_ADDRESS (0x00d0)
|
||||
#endif
|
||||
/** \brief Macro for accessing the UART related control registers. */
|
||||
#define UART ((volatile tUartRegs *)UART_REGS_BASE_ADDRESS)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Register definitions
|
||||
****************************************************************************************/
|
||||
/** \brief SCICR2 - transmitter enable bit. */
|
||||
#define TE_BIT (0x08)
|
||||
/** \brief SCICR2 - receiver enable bit. */
|
||||
#define RE_BIT (0x04)
|
||||
/** \brief SCISR1 - receiver data register full bit. */
|
||||
#define RDRF_BIT (0x20)
|
||||
/** \brief SCISR1 - transmit data register empty bit. */
|
||||
#define TDRE_BIT (0x80)
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
static blt_bool UartReceiveByte(blt_int8u *data);
|
||||
static blt_bool UartTransmitByte(blt_int8u data);
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Initializes the UART communication interface.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void UartInit(void)
|
||||
{
|
||||
blt_int16u baudrate_sbr0_12;
|
||||
|
||||
/* the current implementation supports SCI0 and SCI1. throw an assertion error in
|
||||
* case a different UART channel is configured.
|
||||
*/
|
||||
ASSERT_CT((BOOT_COM_UART_CHANNEL_INDEX == 0) || (BOOT_COM_UART_CHANNEL_INDEX == 1));
|
||||
/* reset the SCI subsystem's configuration, which automatically configures it for
|
||||
* 8,n,1 communication mode.
|
||||
*/
|
||||
UART->scicr2 = 0;
|
||||
UART->scicr1 = 0;
|
||||
UART->scibdh = 0;
|
||||
UART->scibdl = 0;
|
||||
/* configure the baudrate from BOOT_COM_UART_BAUDRATE */
|
||||
baudrate_sbr0_12 = (BOOT_CPU_SYSTEM_SPEED_KHZ * 1000ul) / 16 / BOOT_COM_UART_BAUDRATE;
|
||||
/* baudrate register value cannot be more than 13 bits */
|
||||
ASSERT_RT((baudrate_sbr0_12 & 0xe000) == 0);
|
||||
/* write first MSB then LSB for the baudrate to latch */
|
||||
UART->scibdh = (blt_int8u)(baudrate_sbr0_12 >> 8);
|
||||
UART->scibdl = (blt_int8u)baudrate_sbr0_12;
|
||||
/* enable the transmitted and receiver */
|
||||
UART->scicr2 |= (TE_BIT | RE_BIT);
|
||||
} /*** end of UartInit ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Transmits a packet formatted for the communication interface.
|
||||
** \param data Pointer to byte array with data that it to be transmitted.
|
||||
** \param len Number of bytes that are to be transmitted.
|
||||
** \return none.
|
||||
**
|
||||
****************************************************************************************/
|
||||
void UartTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||
{
|
||||
blt_int16u data_index;
|
||||
|
||||
/* verify validity of the len-paramenter */
|
||||
ASSERT_RT(len <= BOOT_COM_TX_MAX_DATA);
|
||||
|
||||
/* first transmit the length of the packet */
|
||||
ASSERT_RT(UartTransmitByte(len) == BLT_TRUE);
|
||||
|
||||
/* transmit all the packet bytes one-by-one */
|
||||
for (data_index = 0; data_index < len; data_index++)
|
||||
{
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
/* write byte */
|
||||
ASSERT_RT(UartTransmitByte(data[data_index]) == BLT_TRUE);
|
||||
}
|
||||
} /*** end of UartTransmitPacket ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Receives a communication interface packet if one is present.
|
||||
** \param data Pointer to byte array where the data is to be stored.
|
||||
** \return BLT_TRUE if a packet was received, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
blt_bool UartReceivePacket(blt_int8u *data)
|
||||
{
|
||||
static blt_int8u xcpCtoReqPacket[XCP_CTO_PACKET_LEN+1]; /* one extra for length */
|
||||
static blt_int8u xcpCtoRxLength;
|
||||
static blt_bool xcpCtoRxInProgress = BLT_FALSE;
|
||||
|
||||
/* start of cto packet received? */
|
||||
if (xcpCtoRxInProgress == BLT_FALSE)
|
||||
{
|
||||
/* store the message length when received */
|
||||
if (UartReceiveByte(&xcpCtoReqPacket[0]) == BLT_TRUE)
|
||||
{
|
||||
/* indicate that a cto packet is being received */
|
||||
xcpCtoRxInProgress = BLT_TRUE;
|
||||
|
||||
/* reset packet data count */
|
||||
xcpCtoRxLength = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* store the next packet byte */
|
||||
if (UartReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == BLT_TRUE)
|
||||
{
|
||||
/* increment the packet data count */
|
||||
xcpCtoRxLength++;
|
||||
|
||||
/* check to see if the entire packet was received */
|
||||
if (xcpCtoRxLength == xcpCtoReqPacket[0])
|
||||
{
|
||||
/* copy the packet data */
|
||||
CpuMemCopy((blt_int32u)data, (blt_int32u)&xcpCtoReqPacket[1], xcpCtoRxLength);
|
||||
/* done with cto packet reception */
|
||||
xcpCtoRxInProgress = BLT_FALSE;
|
||||
|
||||
/* packet reception complete */
|
||||
return BLT_TRUE;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* packet reception not yet complete */
|
||||
return BLT_FALSE;
|
||||
} /*** end of UartReceivePacket ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Receives a communication interface byte if one is present.
|
||||
** \param data Pointer to byte where the data is to be stored.
|
||||
** \return BLT_TRUE if a byte was received, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_bool UartReceiveByte(blt_int8u *data)
|
||||
{
|
||||
/* check if a new byte was received by means of the RDRF-bit */
|
||||
if((UART->scisr1 & RDRF_BIT) != 0)
|
||||
{
|
||||
/* store the received byte */
|
||||
data[0] = UART->scidrl;
|
||||
/* inform caller of the newly received byte */
|
||||
return BLT_TRUE;
|
||||
}
|
||||
/* inform caller that no new data was received */
|
||||
return BLT_FALSE;
|
||||
} /*** end of UartReceiveByte ***/
|
||||
|
||||
|
||||
/************************************************************************************//**
|
||||
** \brief Transmits a communication interface byte.
|
||||
** \param data Value of byte that is to be transmitted.
|
||||
** \return BLT_TRUE if the byte was transmitted, BLT_FALSE otherwise.
|
||||
**
|
||||
****************************************************************************************/
|
||||
static blt_bool UartTransmitByte(blt_int8u data)
|
||||
{
|
||||
/* check if tx holding register can accept new data */
|
||||
if ((UART->scisr1 & TDRE_BIT) == 0)
|
||||
{
|
||||
/* UART not ready. should not happen */
|
||||
return BLT_FALSE;
|
||||
}
|
||||
/* write byte to transmit holding register */
|
||||
UART->scidrl = data;
|
||||
/* wait for tx holding register to be empty */
|
||||
while((UART->scisr1 & TDRE_BIT) == 0)
|
||||
{
|
||||
/* keep the watchdog happy */
|
||||
CopService();
|
||||
}
|
||||
/* byte transmitted */
|
||||
return BLT_TRUE;
|
||||
} /*** end of UartTransmitByte ***/
|
||||
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
||||
|
||||
|
||||
/*********************************** end of uart.c *************************************/
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/************************************************************************************//**
|
||||
* \file Source\HCS12\uart.h
|
||||
* \brief Bootloader UART communication interface header file.
|
||||
* \ingroup Target_HCS12
|
||||
* \internal
|
||||
*----------------------------------------------------------------------------------------
|
||||
* C O P Y R I G H T
|
||||
*----------------------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
||||
*
|
||||
*----------------------------------------------------------------------------------------
|
||||
* L I C E N S E
|
||||
*----------------------------------------------------------------------------------------
|
||||
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||
* version.
|
||||
*
|
||||
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with OpenBLT.
|
||||
* If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* A special exception to the GPL is included to allow you to distribute a combined work
|
||||
* that includes OpenBLT without being obliged to provide the source code for any
|
||||
* proprietary components. The exception text is included at the bottom of the license
|
||||
* file <license.html>.
|
||||
*
|
||||
* \endinternal
|
||||
****************************************************************************************/
|
||||
#ifndef UART_H
|
||||
#define UART_H
|
||||
|
||||
#if (BOOT_COM_UART_ENABLE > 0)
|
||||
/****************************************************************************************
|
||||
* Function prototypes
|
||||
****************************************************************************************/
|
||||
void UartInit(void);
|
||||
void UartTransmitPacket(blt_int8u *data, blt_int8u len);
|
||||
blt_bool UartReceivePacket(blt_int8u *data);
|
||||
#endif /* BOOT_COM_UART_ENABLE > 0 */
|
||||
|
||||
|
||||
#endif /* UART_H */
|
||||
/*********************************** end of uart.h *************************************/
|
||||
Loading…
Reference in New Issue