From ba2ce9232b3fea3d35296888644d77daf3c5004a Mon Sep 17 00:00:00 2001 From: Frank Voorburg Date: Tue, 24 Sep 2013 13:54:15 +0000 Subject: [PATCH] - added CAN support for HCS12. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@61 5dc33758-31d5-4daf-9ae8-b24bf3d40d73 --- .../Boot/bin/openblt_evbplus_dragon12p.abs | Bin 245432 -> 245904 bytes .../bin/openblt_evbplus_dragon12p.abs.phy | 276 +++---- .../bin/openblt_evbplus_dragon12p.abs.s19 | 276 +++---- .../Boot/bin/openblt_evbplus_dragon12p.map | 714 +++++++++--------- .../Boot/blt_conf.h | 29 +- .../Boot/ide/hcs12.mcp | Bin 60518 -> 60518 bytes .../Boot/ide/hcs12_Data/CWSettingsWindows.stg | Bin 4179 -> 4183 bytes .../hcs12_Data/Standard/TargetDataWindows.tdt | Bin 548025 -> 561062 bytes .../Boot/main.c | 5 - .../Prog/bin/demoprog_evbplus_dragon12p.abs | Bin 207573 -> 213605 bytes .../bin/demoprog_evbplus_dragon12p.abs.sx | 43 +- .../Prog/bin/demoprog_evbplus_dragon12p.map | 270 +++---- .../Prog/boot.c | 221 ++++++ .../hcs12_Data/Standard/TargetDataWindows.tdt | Bin 517682 -> 525932 bytes Target/Source/HCS12/can.c | 442 +++++++++++ Target/Source/HCS12/can.h | 47 ++ Target/Source/HCS12/uart.c | 2 +- 17 files changed, 1541 insertions(+), 784 deletions(-) create mode 100644 Target/Source/HCS12/can.c create mode 100644 Target/Source/HCS12/can.h diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/bin/openblt_evbplus_dragon12p.abs b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/bin/openblt_evbplus_dragon12p.abs index 5686e7c82532fe981ea259d432b48b43e95ce4e9..c3cead79d83803b33ffa27e0e0c5f7d8ec266f4f 100644 GIT binary patch delta 26968 zcmc(Hdt6l28unUy&z|8XAi~Jq0q>TI3hGEGYFe6>nwh1kpyZA4nw64+hvsUb2qfh4E>(rkDu?;@QssMhHaRCu)U^O6{~7f1Jpn@&=O<` zwuD$hv=&;Z7N&(+!>!@A@BpTdo}HwJ&q&i(^X!PJS$W;2QaSbu=j@dw_R9D58$3C< zp*%g+T~wB1Z`iAMQM$V>B&3%=xw1^NdymEyRuoJ~tynf8?SVc4*GD)D;#Ovq^CeDZ z_w>zos!N^RS~dzsyR%P|E>)kw!9#LhX!5PRKmAF(5jyD2%~$e`p+M{i1AbaXFsjkQ-* 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zo9%CRGo%!M=flr_V7BnSKaUGRJ-e;oy=(Xt-m&&5!KZ%Ii~$|(d4ii$TIvCNtKgge zscC83?T^96gk^T|2i!kpcefKiBz@>_g*Sa@4)x%pm3z&5@A!zC<*0EqofTg>(I$=h v-_GMa=Lb4CoxpY#Ie6U``Xhh62)oxlv#CMn?host. */ +#define BOOT_COM_CAN_TX_MSG_ID (0x7E1) +/** \brief Configure number of bytes in the target->host CAN message. */ +#define BOOT_COM_CAN_TX_MAX_DATA (8) +/** \brief Configure CAN message ID host->target. */ +#define BOOT_COM_CAN_RX_MSG_ID (0x667) +/** \brief Configure number of bytes in the host->target CAN message. */ +#define BOOT_COM_CAN_RX_MAX_DATA (8) +/** \brief Select the desired CAN peripheral as a zero based index. */ +#define BOOT_COM_CAN_CHANNEL_INDEX (0) + /* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE * configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed * in bits/second. The maximum amount of data bytes in a message for data transmission @@ -70,7 +97,7 @@ * */ /** \brief Enable/disable UART transport layer. */ -#define BOOT_COM_UART_ENABLE (1) +#define BOOT_COM_UART_ENABLE (0) /** \brief Configure the desired communication speed. */ #define BOOT_COM_UART_BAUDRATE (57600) /** \brief Configure number of bytes in the target->host data packet. */ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/hcs12.mcp b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/hcs12.mcp index 62ee82fa754a7a025f7f46b59e96691c5589e724..e524352262db3596a9d8c3b44f4525d776a66885 100644 GIT binary patch delta 296 zcmaEMgZbGF<_#`_f*LFg3}Flqpa*1!PjoEi)d2DxfS3`8oi<+;e8I>X3S@?D-X$#0 zIQgN-3|2KDSAC*m^5lo2Gb9~>DxH8h94MFo#3n#<7&yRYiBB#NVwt>DOoDBOb^195 z!OagPelbq=xxSK-Z}PY6-JBq;u0Eb_PLr!{Jlp(IN|%i@IWbQ!nE^;nPF(hJ^9QYa zOq<`Sd|+h-DGi$}t*Xolwrg^>sxnaa0Q2T|dT}d+nSoXc05OQ>0b)tp^vxF}B$*}# z9NBDh>l`2Bg2~)3wIv(H7#Kjl%Pc9*eF0Jn1uG}}zZ7TkxxP8$6fB(V|5BW3uf*nzm*<#R OeXcVw+?s6tMjHTMz)OVy diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/hcs12_Data/CWSettingsWindows.stg b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/hcs12_Data/CWSettingsWindows.stg index bc0bc92b27628393b8e33ed297475b36bdb7cfd1..6ab5086ed1548987cdeaa2e4c98510ce568efdb3 100644 GIT binary patch delta 215 zcmcbta9u$#CqF-#nSp^pgOPzjosWURf1{v1yC4ft1O&K%m>YuFfFSc?rFhRv9Pkz8JE;$V-D-D&+m*Qezfy!>2EFd5*Y0AUEAOh3? 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zNAS)j^stk#nQh2}g0}2`wL7byzXq(THbvweU)9urnxdC-o*u8@w4~`IpK(ZPU=I7WT5aB8qPEYxO7UDa$v 0 */ +#if (BOOT_COM_CAN_ENABLE > 0) +/**************************************************************************************** +* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E +****************************************************************************************/ + +/**************************************************************************************** +* Type definitions +****************************************************************************************/ +/** \brief Structure type with the layout of the CAN bus timing registers. */ +typedef struct +{ + unsigned char tseg1; /**< CAN time segment 1 */ + unsigned char tseg2; /**< CAN time segment 2 */ +} tCanBusTiming; + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +#define CONVERT_STD_ID_TO_REG0(id) ((unsigned char)(((unsigned short)id & 0x07f8) >> 3)) +#define CONVERT_STD_ID_TO_REG1(id) ((unsigned char)(id & 0x07) << 5) +#define CONVERT_STD_ID_TO_REG2(id) (0) +#define CONVERT_STD_ID_TO_REG3(id) (0) +#define CONVERT_EXT_ID_TO_REG0(id) ((unsigned char)(id >> 21)) +#define CONVERT_EXT_ID_TO_REG1(id) ((((unsigned char)(id >> 15)) & 0x07) | \ + (((unsigned char)(id >> 13)) & 0xe0) | CAN0RXIDR1_IDE_MASK) +#define CONVERT_EXT_ID_TO_REG2(id) ((unsigned char)(((unsigned short)id & 0x7f80) >> 7)) +#define CONVERT_EXT_ID_TO_REG3(id) ((unsigned char)(id & 0x7f) << 1) + + +/**************************************************************************************** +* Local constant declarations +****************************************************************************************/ +/** +* \brief Array with possible time quanta configurations. +* \details According to the CAN protocol 1 bit-time can be made up of between 8..25 +* time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC +* always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) +* * 100%. This array contains possible and valid time quanta configurations +* with a sample point between 68..78%. +*/ +static const tCanBusTiming canTiming[] = +{ /* TQ | TSEG1 | TSEG2 | SP */ + /* ------------------------- */ + { 5, 2 }, /* 8 | 5 | 2 | 75% */ + { 6, 2 }, /* 9 | 6 | 2 | 78% */ + { 6, 3 }, /* 10 | 6 | 3 | 70% */ + { 7, 3 }, /* 11 | 7 | 3 | 73% */ + { 8, 3 }, /* 12 | 8 | 3 | 75% */ + { 9, 3 }, /* 13 | 9 | 3 | 77% */ + { 9, 4 }, /* 14 | 9 | 4 | 71% */ + { 10, 4 }, /* 15 | 10 | 4 | 73% */ + { 11, 4 }, /* 16 | 11 | 4 | 75% */ + { 12, 4 }, /* 17 | 12 | 4 | 76% */ + { 12, 5 }, /* 18 | 12 | 5 | 72% */ + { 13, 5 }, /* 19 | 13 | 5 | 74% */ + { 14, 5 }, /* 20 | 14 | 5 | 75% */ + { 15, 5 }, /* 21 | 15 | 5 | 76% */ + { 15, 6 }, /* 22 | 15 | 6 | 73% */ + { 16, 6 }, /* 23 | 16 | 6 | 74% */ + { 16, 7 }, /* 24 | 16 | 7 | 71% */ + { 16, 8 } /* 25 | 16 | 8 | 68% */ +}; + + +/************************************************************************************//** +** \brief Search algorithm to match the desired baudrate to a possible bus timing +** configuration. +** \param baud The desired baudrate in kbps. Valid values are 10..1000. +** \param btr0 Pointer to where the value for register CANxBTR0 will be stored. +** \param btr1 Pointer to where the value for register CANxBTR1 will be stored. +** \return 1 if the CAN bustiming register values were found, 0 otherwise. +** +****************************************************************************************/ +static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned char *btr0, unsigned char *btr1) +{ + unsigned char prescaler; + unsigned char cnt; + + /* loop through all possible time quanta configurations to find a match */ + for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++) + { + if ((BOOT_CPU_XTAL_SPEED_KHZ % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0) + { + /* compute the prescaler that goes with this TQ configuration */ + prescaler = (unsigned char)(BOOT_CPU_XTAL_SPEED_KHZ/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))); + + /* make sure the prescaler is valid */ + if ( (prescaler > 0) && (prescaler <= 64) ) + { + /* store the MSCAN bustiming register values */ + *btr0 = prescaler - 1; + *btr1 = ((canTiming[cnt].tseg2 - 1) << 4) | (canTiming[cnt].tseg1 - 1); + /* found a good bus timing configuration */ + return 1; + } + } + } + /* could not find a good bus timing configuration */ + return 0; +} /*** end of CanGetSpeedConfig ***/ + + +/************************************************************************************//** +** \brief Initializes the CAN communication interface. +** \return none. +** +****************************************************************************************/ +void BootComInit(void) +{ + unsigned char btrRegValues[2]; + unsigned long accept_code; + unsigned long accept_mask; + + /* enter initialization mode. note that this automatically disables CAN interrupts */ + CAN0CTL0 = CAN0CTL0_INITRQ_MASK; + /* wait for initialization mode entry handshake from the hardware */ + while ((CAN0CTL1 & CAN0CTL1_INITAK_MASK) == 0) + { + ; + } + + /* enable the CAN controller, disable wake up and listen modes and set the + * crystal oscillator as the clock source. + */ + CAN0CTL1 = CAN0CTL1_CANE_MASK; + + /* configure baudrate */ + if (CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &btrRegValues[0], &btrRegValues[1]) == 1) + { + /* configure the baudrate */ + CAN0BTR0 = btrRegValues[0]; + CAN0BTR1 = btrRegValues[1]; + } + + /* enable 2 32-bit acceptance filters. both will be configured for the same code and + * mask. the only difference is that filter 0 will be setup to receive extended 29-bit + * identifiers and filter 0 to receive standard 11-bit identifiers. + */ + CAN0IDAC_IDAM0 = 0; + CAN0IDAC_IDAM1 = 0; + + /* set the acceptance filter code and mask to receive all messages */ + accept_code = 0x00000000; + accept_mask = 0x1fffffff; + + /* configure acceptance filter 0 for 29-bit extended identifiers */ + CAN0IDAR0 = CONVERT_EXT_ID_TO_REG0(accept_code); + CAN0IDAR1 = CONVERT_EXT_ID_TO_REG1(accept_code); + CAN0IDAR2 = CONVERT_EXT_ID_TO_REG2(accept_code); + CAN0IDAR3 = CONVERT_EXT_ID_TO_REG3(accept_code); + CAN0IDMR0 = CONVERT_EXT_ID_TO_REG0(accept_mask); + CAN0IDMR1 = (CONVERT_EXT_ID_TO_REG1(accept_mask) | 0x10) & (unsigned char)(~0x08); + CAN0IDMR2 = CONVERT_EXT_ID_TO_REG2(accept_mask); + CAN0IDMR3 = CONVERT_EXT_ID_TO_REG3(accept_mask); + + /* configure acceptance filter 1 for 11-bit standard identifiers */ + CAN0IDAR4 = CONVERT_STD_ID_TO_REG0(accept_code); + CAN0IDAR5 = CONVERT_STD_ID_TO_REG1(accept_code); + CAN0IDAR6 = CONVERT_STD_ID_TO_REG2(accept_code); + CAN0IDAR7 = CONVERT_STD_ID_TO_REG3(accept_code); + CAN0IDMR4 = CONVERT_STD_ID_TO_REG0(accept_mask); + CAN0IDMR5 = CONVERT_STD_ID_TO_REG1(accept_mask) | (0x04 | 0x02 | 0x01); + CAN0IDMR6 = CONVERT_STD_ID_TO_REG2(accept_mask); + CAN0IDMR7 = CONVERT_STD_ID_TO_REG3(accept_mask); + + /* leave initialization mode and synchronize to the CAN bus */ + CAN0CTL0_INITRQ = 0; + /* wait for CAN bus synchronization handshake from the hardware */ + while ((CAN0CTL1 & CAN0CTL1_INITAK_MASK) != 0) + { + ; + } +} /*** end of BootComInit ***/ + + +/************************************************************************************//** +** \brief Receives the CONNECT request from the host, which indicates that the +** bootloader should be activated and, if so, activates it. +** \return none. +** +****************************************************************************************/ +void BootComCheckActivationRequest(void) +{ + unsigned long rxMsgId; + + /* check if a new message was received */ + if ((CAN0RFLG & CAN0RFLG_RXF_MASK) == CAN0RFLG_RXF_MASK) + { + /* check IDE-bit to determine if it is a 11-bit or 29-bit identifier */ + if ((CAN0RXIDR1 & CAN0RXIDR1_IDE_MASK) == 0) + { + /* 11-bit id */ + rxMsgId = (*(unsigned short*)(&CAN0RXIDR0)) >> 5; + } + else + { + /* 29-bit id */ + rxMsgId = (unsigned long)(((*(unsigned long*)(&CAN0RXIDR0)) & 0x0007ffff) >> 1) | + (unsigned long)(((*(unsigned long*)(&CAN0RXIDR0)) & 0xffe00000) >> 3); + } + /* is this the packet identifier? */ + if (rxMsgId == BOOT_COM_CAN_RX_MSG_ID) + { + /* check if this was an XCP CONNECT command */ + if ( (CAN0RXDSR0 == 0xff) && (CAN0RXDSR1 == 0x00) ) + { + /* release the receive object by clearing the rx flag */ + CAN0RFLG &= CAN0RFLG_RXF_MASK; + /* connection request received so start the bootloader */ + BootActivate(); + } + + } + /* release the receive object by clearing the rx flag */ + CAN0RFLG &= CAN0RFLG_RXF_MASK; + } +} /*** end of BootComCheckActivationRequest ***/ +#endif /* BOOT_COM_CAN_ENABLE > 0 */ + + /*********************************** end of boot.c *************************************/ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/ide/hcs12_Data/Standard/TargetDataWindows.tdt b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/ide/hcs12_Data/Standard/TargetDataWindows.tdt index d0187ce186900b7c8900858578c2d79621d4ae74..6735bcc66d5dd90fa02a78d9ebaa2917bf44c97b 100644 GIT binary patch delta 2977 zcmbtWeNa?Y6n}TQZ{My9Y9PY8!cu^u5b@DBHThUTD1qGFY>jFq#MK!^6ilm`h^fZL z%37{@sax(c<&;t*wKJ`aj?sss6ShTKu_#l}I8LQ}2qH?;bnbr0F7EhGcjgE0oZs)B zbMAfTzPq2D(4T)TC3gMBjWtn%AY>pxcz03~zWwLZ*u`3;Z8=^*wrLZ!df-w3^8gD0 zHv?_~q!PO}jvUn1ldO5AS}l0u0CNEGfVqGKKq9DgXd&6B)rmZU&MsR?hAt1~x~g=R zkK>cTmkgNCIRMvaNt;%uUI0%#UphH|tP;h-JQq9eR*>CY`WYx$iJBjiQ1i3oxh~y; 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OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ + + +#if (BOOT_COM_CAN_ENABLE > 0) +/**************************************************************************************** +* Type definitions +****************************************************************************************/ +/** \brief Structure type with the layout of a CAN reception message slot. */ +typedef volatile struct +{ + volatile blt_int8u idr[4]; /**< identifier register 0..3 */ + volatile blt_int8u dsr[8]; /**< data segment register 0..7 */ + volatile blt_int8u dlr; /**< data length register */ + volatile blt_int8u dummy; /**< unused */ + volatile blt_int16u tstamp; /**< timestamp register */ +} tCanRxMsgSlot; + +/** \brief Structure type with the layout of a CAN transmit message slot. */ +typedef volatile struct +{ + volatile blt_int8u idr[4]; /**< identifier register 0..3 */ + volatile blt_int8u dsr[8]; /**< data segment register 0..7 */ + volatile blt_int8u dlr; /**< data length register */ + volatile blt_int8u tbpr; /**< transmit buffer priority register */ + volatile blt_int16u tstamp; /**< timestamp register */ +} tCanTxMsgSlot; + +/** \brief Structure type with the layout of the CAN related control registers. */ +typedef volatile struct +{ + volatile blt_int8u cctl0; /**< control register 0 */ + volatile blt_int8u cctl1; /**< control register 1 */ + volatile blt_int8u cbtr0; /**< bus timing register 0 */ + volatile blt_int8u cbtr1; /**< bus timing register 1 */ + volatile blt_int8u crflg; /**< receiver flag register */ + volatile blt_int8u crier; /**< receiver interrupt enable register */ + volatile blt_int8u ctflg; /**< transmitter flag register */ + volatile blt_int8u ctier; /**< transmitter interrupt enable register */ + volatile blt_int8u ctarq; /**< transmitter message abort control */ + volatile blt_int8u ctaak; /**< transmitter message abort control */ + volatile blt_int8u ctbsel; /**< transmit buffer selection */ + volatile blt_int8u cidac; /**< identifier acceptance control register */ + volatile blt_int8u dummy1[2]; /**< reserved (2) */ + volatile blt_int8u crxerr; /**< receive error counter */ + volatile blt_int8u ctxerr; /**< transmit error counter */ + volatile blt_int8u cidar0; /**< identifier acceptance register 0 */ + volatile blt_int8u cidar1; /**< identifier acceptance register 1 */ + volatile blt_int8u cidar2; /**< identifier acceptance register 2 */ + volatile blt_int8u cidar3; /**< identifier acceptance register 3 */ + volatile blt_int8u cidmr0; /**< identifier mask register 0 */ + volatile blt_int8u cidmr1; /**< identifier mask register 1 */ + volatile blt_int8u cidmr2; /**< identifier mask register 2 */ + volatile blt_int8u cidmr3; /**< identifier mask register 3 */ + volatile blt_int8u cidar4; /**< identifier acceptance register 4 */ + volatile blt_int8u cidar5; /**< identifier acceptance register 5 */ + volatile blt_int8u cidar6; /**< identifier acceptance register 6 */ + volatile blt_int8u cidar7; /**< identifier acceptance register 7 */ + volatile blt_int8u cidmr4; /**< identifier mask register 4 */ + volatile blt_int8u cidmr5; /**< identifier mask register 5 */ + volatile blt_int8u cidmr6; /**< identifier mask register 6 */ + volatile blt_int8u cidmr7; /**< identifier mask register 7 */ + volatile tCanRxMsgSlot rxSlot; /**< foreground receive message slot */ + volatile tCanTxMsgSlot txSlot; /**< foreground transmit message slot */ +} tCanRegs; + + +/** \brief Structure type with the layout of the CAN bus timing registers. */ +typedef struct +{ + blt_int8u tseg1; /**< CAN time segment 1 */ + blt_int8u tseg2; /**< CAN time segment 2 */ +} tCanBusTiming; + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +#if (BOOT_COM_CAN_CHANNEL_INDEX == 0) +/** \brief Set CAN base address to CAN0. */ +#define CAN_REGS_BASE_ADDRESS (0x0140) +#elif (BOOT_COM_CAN_CHANNEL_INDEX == 1) +/** \brief Set CAN base address to CAN1. */ +#define CAN_REGS_BASE_ADDRESS (0x0180) +#elif (BOOT_COM_CAN_CHANNEL_INDEX == 2) +/** \brief Set CAN base address to CAN2. */ +#define CAN_REGS_BASE_ADDRESS (0x01c0) +#elif (BOOT_COM_CAN_CHANNEL_INDEX == 3) +/** \brief Set CAN base address to CAN3. */ +#define CAN_REGS_BASE_ADDRESS (0x0200) +#elif (BOOT_COM_CAN_CHANNEL_INDEX == 4) +/** \brief Set CAN base address to CAN4. */ +#define CAN_REGS_BASE_ADDRESS (0x0280) +#endif +/** \brief Macro for accessing the CAN related control registers. */ +#define CAN ((volatile tCanRegs *)CAN_REGS_BASE_ADDRESS) +/** \brief Configures a CAN message id for 29-bit (extended). */ +#define EXTIDMASK_BIT (0x80000000) +/* macros for conveniently converting standard and extended message identifiers to the + * format specified by the MSCAN message slot. + */ +#define CONVERT_STD_ID_TO_REG0(id) ((blt_int8u)(((blt_int16u)id & 0x07f8) >> 3)) +#define CONVERT_STD_ID_TO_REG1(id) ((blt_int8u)(id & 0x07) << 5) +#define CONVERT_STD_ID_TO_REG2(id) (0) +#define CONVERT_STD_ID_TO_REG3(id) (0) +#define CONVERT_EXT_ID_TO_REG0(id) ((blt_int8u)(id >> 21)) +#define CONVERT_EXT_ID_TO_REG1(id) ((((blt_int8u)(id >> 15)) & 0x07) | \ + (((blt_int8u)(id >> 13)) & 0xe0) | (IDE_BIT)) +#define CONVERT_EXT_ID_TO_REG2(id) ((blt_int8u)(((blt_int16u)id & 0x7f80) >> 7)) +#define CONVERT_EXT_ID_TO_REG3(id) ((blt_int8u)(id & 0x7f) << 1) + + +/**************************************************************************************** +* Register definitions +****************************************************************************************/ +/** \brief Initialization mode request bit. */ +#define INITRQ_BIT (0x01) +/** \brief Initialization mode handshake bit. */ +#define INITAK_BIT (0x01) +/** \brief CAN controller enable bit. */ +#define CANE_BIT (0x80) +/** \brief Filter mode bit 0. */ +#define IDAM0_BIT (0x10) +/** \brief Filter mode bit 1. */ +#define IDAM1_BIT (0x20) +/** \brief Transmit buffer 0 select bit. */ +#define TX0_BIT (0x01) +/** \brief Transmit buffer 0 empty bit. */ +#define TXE0_BIT (0x01) +/** \brief 29-bit extended id bit. */ +#define IDE_BIT (0x08) +/** \brief Receive buffer full flag bit. */ +#define RXF_BIT (0x01) + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static blt_bool CanGetSpeedConfig(blt_int16u baud, blt_int8u *btr0, blt_int8u *btr1); + + +/**************************************************************************************** +* Local constant declarations +****************************************************************************************/ +/** +* \brief Array with possible time quanta configurations. +* \details According to the CAN protocol 1 bit-time can be made up of between 8..25 +* time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC +* always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) +* * 100%. This array contains possible and valid time quanta configurations +* with a sample point between 68..78%. +*/ +static const tCanBusTiming canTiming[] = +{ /* TQ | TSEG1 | TSEG2 | SP */ + /* ------------------------- */ + { 5, 2 }, /* 8 | 5 | 2 | 75% */ + { 6, 2 }, /* 9 | 6 | 2 | 78% */ + { 6, 3 }, /* 10 | 6 | 3 | 70% */ + { 7, 3 }, /* 11 | 7 | 3 | 73% */ + { 8, 3 }, /* 12 | 8 | 3 | 75% */ + { 9, 3 }, /* 13 | 9 | 3 | 77% */ + { 9, 4 }, /* 14 | 9 | 4 | 71% */ + { 10, 4 }, /* 15 | 10 | 4 | 73% */ + { 11, 4 }, /* 16 | 11 | 4 | 75% */ + { 12, 4 }, /* 17 | 12 | 4 | 76% */ + { 12, 5 }, /* 18 | 12 | 5 | 72% */ + { 13, 5 }, /* 19 | 13 | 5 | 74% */ + { 14, 5 }, /* 20 | 14 | 5 | 75% */ + { 15, 5 }, /* 21 | 15 | 5 | 76% */ + { 15, 6 }, /* 22 | 15 | 6 | 73% */ + { 16, 6 }, /* 23 | 16 | 6 | 74% */ + { 16, 7 }, /* 24 | 16 | 7 | 71% */ + { 16, 8 } /* 25 | 16 | 8 | 68% */ +}; + + +/************************************************************************************//** +** \brief Initializes the CAN controller and synchronizes it to the CAN bus. +** \return none. +** +****************************************************************************************/ +void CanInit(void) +{ + blt_int8u btrRegValues[2]; + blt_bool result; + blt_int32u accept_code; + blt_int32u accept_mask; + + /* the current implementation supports CAN0..4. throw an assertion error in case a + * different CAN channel is configured. + */ + ASSERT_CT((BOOT_COM_CAN_CHANNEL_INDEX >= 0) && (BOOT_COM_CAN_CHANNEL_INDEX <= 4)); + + /* enter initialization mode. note that this automatically disables CAN interrupts */ + CAN->cctl0 = INITRQ_BIT; + /* wait for initialization mode entry handshake from the hardware */ + while ((CAN->cctl1 & INITAK_BIT) == 0) + { + ; + } + + /* enable the CAN controller, disable wake up and listen modes and set the + * crystal oscillator as the clock source. + */ + CAN->cctl1 = CANE_BIT; + + /* configure baudrate */ + result = CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &btrRegValues[0], &btrRegValues[1]); + ASSERT_RT(result == BLT_TRUE); + + /* configure the baudrate */ + CAN->cbtr0 = btrRegValues[0]; + CAN->cbtr1 = btrRegValues[1]; + + /* enable 2 32-bit acceptance filters. both will be configured for the same code and + * mask. the only difference is that filter 0 will be setup to receive extended 29-bit + * identifiers and filter 0 to receive standard 11-bit identifiers. + */ + CAN->cidac &= ~(IDAM1_BIT | IDAM0_BIT); + + /* set the acceptance filter code and mask to a value that only BOOT_COM_CAN_RX_MSG_ID + * is received. + */ + accept_code = BOOT_COM_CAN_RX_MSG_ID; + accept_mask = 0; + + /* configure acceptance filter 0 for 29-bit extended identifiers */ + CAN->cidar0 = CONVERT_EXT_ID_TO_REG0(accept_code); + CAN->cidar1 = CONVERT_EXT_ID_TO_REG1(accept_code); + CAN->cidar2 = CONVERT_EXT_ID_TO_REG2(accept_code); + CAN->cidar3 = CONVERT_EXT_ID_TO_REG3(accept_code); + CAN->cidmr0 = CONVERT_EXT_ID_TO_REG0(accept_mask); + CAN->cidmr1 = (CONVERT_EXT_ID_TO_REG1(accept_mask) | 0x10) & ~IDE_BIT; + CAN->cidmr2 = CONVERT_EXT_ID_TO_REG2(accept_mask); + CAN->cidmr3 = CONVERT_EXT_ID_TO_REG3(accept_mask); + + /* configure acceptance filter 1 for 11-bit standard identifiers */ + CAN->cidar4 = CONVERT_STD_ID_TO_REG0(accept_code); + CAN->cidar5 = CONVERT_STD_ID_TO_REG1(accept_code); + CAN->cidar6 = CONVERT_STD_ID_TO_REG2(accept_code); + CAN->cidar7 = CONVERT_STD_ID_TO_REG3(accept_code); + CAN->cidmr4 = CONVERT_STD_ID_TO_REG0(accept_mask); + CAN->cidmr5 = CONVERT_STD_ID_TO_REG1(accept_mask) | (0x04 | 0x02 | 0x01); + CAN->cidmr6 = CONVERT_STD_ID_TO_REG2(accept_mask); + CAN->cidmr7 = CONVERT_STD_ID_TO_REG3(accept_mask); + + /* leave initialization mode and synchronize to the CAN bus */ + CAN->cctl0 &= ~INITRQ_BIT; + /* wait for CAN bus synchronization handshake from the hardware */ + while ((CAN->cctl1 & INITAK_BIT) != 0) + { + ; + } + + /* bring transmit buffer 0 in the foreground as this is the only one used by this + * driver. + */ + CAN->ctbsel = TX0_BIT; +} /*** end of CanInit ***/ + + +/************************************************************************************//** +** \brief Transmits a packet formatted for the communication interface. +** \param data Pointer to byte array with data that it to be transmitted. +** \param len Number of bytes that are to be transmitted. +** \return none. +** +****************************************************************************************/ +void CanTransmitPacket(blt_int8u *data, blt_int8u len) +{ + blt_int8u byte_idx; + + /* double check that the transmit slot is really available */ + ASSERT_RT((CAN->ctflg & TXE0_BIT) != 0); + + /* is this a message with an 11-bit identifier? */ + if ((BOOT_COM_CAN_TX_MSG_ID & EXTIDMASK_BIT) == 0) + { + /* store the identifier */ + CAN->txSlot.idr[0] = CONVERT_STD_ID_TO_REG0(BOOT_COM_CAN_TX_MSG_ID); + CAN->txSlot.idr[1] = CONVERT_STD_ID_TO_REG1(BOOT_COM_CAN_TX_MSG_ID); + CAN->txSlot.idr[2] = CONVERT_STD_ID_TO_REG2(BOOT_COM_CAN_TX_MSG_ID); + CAN->txSlot.idr[3] = CONVERT_STD_ID_TO_REG3(BOOT_COM_CAN_TX_MSG_ID); + } + else + { + /* store the identifier */ + CAN->txSlot.idr[0] = CONVERT_EXT_ID_TO_REG0(BOOT_COM_CAN_TX_MSG_ID); + CAN->txSlot.idr[1] = CONVERT_EXT_ID_TO_REG1(BOOT_COM_CAN_TX_MSG_ID); + CAN->txSlot.idr[2] = CONVERT_EXT_ID_TO_REG2(BOOT_COM_CAN_TX_MSG_ID); + CAN->txSlot.idr[3] = CONVERT_EXT_ID_TO_REG3(BOOT_COM_CAN_TX_MSG_ID); + } + + /* store the data length code */ + CAN->txSlot.dlr = len; + + /* store the message data */ + for (byte_idx=0; byte_idxtxSlot.dsr[byte_idx] = data[byte_idx]; + } + + /* start the transmission by clearing the buffer empty flag. must be done + * by writing a 1 value. + */ + CAN->ctflg = TXE0_BIT; + + /* wait for transmit completion */ + while ((CAN->ctflg & TXE0_BIT) == 0) + { + /* keep the watchdog happy */ + CopService(); + } +} /*** end of CanTransmitPacket ***/ + + +/************************************************************************************//** +** \brief Receives a communication interface packet if one is present. +** \param data Pointer to byte array where the data is to be stored. +** \return BLT_TRUE is a packet was received, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool CanReceivePacket(blt_int8u *data) +{ + blt_int32u rxMsgId; + blt_int8u rxMsgLen; + blt_int8u byte_idx; + blt_bool result = BLT_FALSE; + + /* check if a new message was received */ + if ((CAN->crflg & RXF_BIT) == RXF_BIT) + { + /* check IDE-bit to determine if it is a 11-bit or 29-bit identifier */ + if ((CAN->rxSlot.idr[1] & IDE_BIT) == 0) + { + /* 11-bit id */ + rxMsgId = (*(blt_int16u*)(&CAN->rxSlot.idr[0])) >> 5; + } + else + { + /* 29-bit id */ + rxMsgId = (blt_int32u)(((*(blt_int32u*)(&CAN->rxSlot.idr[0])) & 0x0007ffff) >> 1) | + (blt_int32u)(((*(blt_int32u*)(&CAN->rxSlot.idr[0])) & 0xffe00000) >> 3); + } + /* is this the packet identifier? */ + if (rxMsgId == BOOT_COM_CAN_RX_MSG_ID) + { + result = BLT_TRUE; + /* store the dlc */ + rxMsgLen = CAN->rxSlot.dlr & 0xf; + /* copy message data */ + for (byte_idx=0; byte_idxrxSlot.dsr[byte_idx]; + } + } + /* release the receive object by clearing the rx flag */ + CAN->crflg &= RXF_BIT; + } + return result; +} /*** end of CanReceivePacket ***/ + + +/************************************************************************************//** +** \brief Search algorithm to match the desired baudrate to a possible bus timing +** configuration. +** \param baud The desired baudrate in kbps. Valid values are 10..1000. +** \param btr0 Pointer to where the value for register CANxBTR0 will be stored. +** \param btr1 Pointer to where the value for register CANxBTR1 will be stored. +** \return BLT_TRUE if the CAN bustiming register values were found, BLT_FALSE +** otherwise. +** +****************************************************************************************/ +static blt_bool CanGetSpeedConfig(blt_int16u baud, blt_int8u *btr0, blt_int8u *btr1) +{ + blt_int8u prescaler; + blt_int8u cnt; + + /* loop through all possible time quanta configurations to find a match */ + for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++) + { + if ((BOOT_CPU_XTAL_SPEED_KHZ % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0) + { + /* compute the prescaler that goes with this TQ configuration */ + prescaler = (blt_int8u)(BOOT_CPU_XTAL_SPEED_KHZ/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))); + + /* make sure the prescaler is valid */ + if ( (prescaler > 0) && (prescaler <= 64) ) + { + /* store the MSCAN bustiming register values */ + *btr0 = prescaler - 1; + *btr1 = ((canTiming[cnt].tseg2 - 1) << 4) | (canTiming[cnt].tseg1 - 1); + /* found a good bus timing configuration */ + return BLT_TRUE; + } + } + /* service the watchdog */ + CopService(); + } + /* could not find a good bus timing configuration */ + return BLT_FALSE; +} /*** end of CanGetSpeedConfig ***/ +#endif /* BOOT_COM_CAN_ENABLE > 0 */ + + +/*********************************** end of can.c **************************************/ diff --git a/Target/Source/HCS12/can.h b/Target/Source/HCS12/can.h new file mode 100644 index 00000000..de5debe8 --- /dev/null +++ b/Target/Source/HCS12/can.h @@ -0,0 +1,47 @@ +/************************************************************************************//** +* \file Source\HCS12\can.h +* \brief Bootloader CAN communication interface header file. +* \ingroup Target_HCS12 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ +#ifndef CAN_H +#define CAN_H + +#if (BOOT_COM_CAN_ENABLE > 0) +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void CanInit(void); +void CanTransmitPacket(blt_int8u *data, blt_int8u len); +blt_bool CanReceivePacket(blt_int8u *data); +#endif /* BOOT_COM_CAN_ENABLE > 0 */ + + +#endif /* CAN_H */ +/*********************************** end of can.h **************************************/ diff --git a/Target/Source/HCS12/uart.c b/Target/Source/HCS12/uart.c index 4f91e6c9..95b22c8d 100644 --- a/Target/Source/HCS12/uart.c +++ b/Target/Source/HCS12/uart.c @@ -41,7 +41,7 @@ /**************************************************************************************** * Type definitions ****************************************************************************************/ -/** \brief Structure type with the layout of the UART related controler registers. */ +/** \brief Structure type with the layout of the UART related control registers. */ typedef volatile struct { volatile blt_int8u scibdh; /**< baudrate control register [SBR 12..8] */