From d9f50cb7d6a8b60cf425d8f87ba0907bffd15233 Mon Sep 17 00:00:00 2001 From: oharboe Date: Sun, 13 Apr 2008 10:09:27 +0000 Subject: [PATCH] - Set up ICE registers after TRST - Work in progress to allow launching GDB/telnet server *before* jtag chain enum, validate & examine git-svn-id: svn://svn.berlios.de/openocd/trunk@569 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/jtag/jtag.c | 10 +++++--- src/target/arm7tdmi.c | 42 ++++++++++++++++++++---------- src/target/arm9tdmi.c | 44 ++++++++++++++++++++++---------- src/target/embeddedice.c | 35 ++++++++++++++++++++----- src/target/etm.c | 55 +++++++++++++++++++++++++--------------- 5 files changed, 129 insertions(+), 57 deletions(-) diff --git a/src/jtag/jtag.c b/src/jtag/jtag.c index fa439ec5a..fe76a3221 100644 --- a/src/jtag/jtag.c +++ b/src/jtag/jtag.c @@ -1518,9 +1518,6 @@ static int jtag_init_inner(struct command_context_s *cmd_ctx) LOG_DEBUG("-"); - if ((retval=jtag_interface_init(cmd_ctx)) != ERROR_OK) - return retval; - device = jtag_devices; jtag_ir_scan_size = 0; jtag_num_devices = 0; @@ -1559,6 +1556,10 @@ static int jtag_init_inner(struct command_context_s *cmd_ctx) int jtag_init_reset(struct command_context_s *cmd_ctx) { int retval; + + if ((retval=jtag_interface_init(cmd_ctx)) != ERROR_OK) + return retval; + LOG_DEBUG("Trying to bring the JTAG controller to life by asserting TRST / tms"); /* Reset can happen after a power cycle. @@ -1599,6 +1600,9 @@ int jtag_init_reset(struct command_context_s *cmd_ctx) int jtag_init(struct command_context_s *cmd_ctx) { + int retval; + if ((retval=jtag_interface_init(cmd_ctx)) != ERROR_OK) + return retval; if (jtag_init_inner(cmd_ctx)==ERROR_OK) { return ERROR_OK; diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index f331bd2fe..214eea05a 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -738,26 +738,42 @@ void arm7tdmi_build_reg_cache(target_t *target) reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; (*cache_p) = armv4_5_build_reg_cache(target, armv4_5); armv4_5->core_cache = (*cache_p); - - (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9); - arm7_9->eice_cache = (*cache_p)->next; - - if (arm7_9->etm_ctx) - { - (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx); - arm7_9->etm_ctx->reg_cache = (*cache_p)->next->next; - } } int arm7tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target) { - target->type->examined = 1; - + int retval; + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + if (!target->type->examined) + { + /* get pointers to arch-specific information */ + reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); + reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9); + if (t==NULL) + return ERROR_FAIL; + + (*cache_p) = t; + arm7_9->eice_cache = (*cache_p); + + if (arm7_9->etm_ctx) + { + arm_jtag_t *jtag_info = &arm7_9->jtag_info; + (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx); + arm7_9->etm_ctx->reg_cache = (*cache_p)->next; + } + target->type->examined = 1; + } + if ((retval=embeddedice_setup(target))!=ERROR_OK) + return retval; + if (arm7_9->etm_ctx) + { + if ((retval=etm_setup(target))!=ERROR_OK) + return retval; + } return ERROR_OK; } diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index 0df6a14b1..30034311f 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -843,26 +843,44 @@ void arm9tdmi_build_reg_cache(target_t *target) reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; (*cache_p) = armv4_5_build_reg_cache(target, armv4_5); armv4_5->core_cache = (*cache_p); - - /* one extra register (vector catch) */ - (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9); - arm7_9->eice_cache = (*cache_p)->next; - - if (arm7_9->etm_ctx) - { - (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx); - arm7_9->etm_ctx->reg_cache = (*cache_p)->next->next; - } } + int arm9tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target) { - target->type->examined = 1; + /* get pointers to arch-specific information */ + int retval; + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + if (!target->type->examined) + { + reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); + reg_cache_t *t; + /* one extra register (vector catch) */ + t=embeddedice_build_reg_cache(target, arm7_9); + if (t==NULL) + return ERROR_FAIL; + (*cache_p) = t; + arm7_9->eice_cache = (*cache_p); + + if (arm7_9->etm_ctx) + { + arm_jtag_t *jtag_info = &arm7_9->jtag_info; + (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx); + arm7_9->etm_ctx->reg_cache = (*cache_p)->next; + } + target->type->examined = 1; + } + if ((retval=embeddedice_setup(target))!=ERROR_OK) + return retval; + if (arm7_9->etm_ctx) + { + if ((retval=etm_setup(target))!=ERROR_OK) + return retval; + } return ERROR_OK; } diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 2f1a237fe..5e6f3db62 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -88,6 +88,7 @@ int embeddedice_read_reg(reg_t *reg); reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9) { + int retval; reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t)); reg_t *reg_list = NULL; embeddedice_reg_t *arch_info = NULL; @@ -133,7 +134,16 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 /* identify EmbeddedICE version by reading DCC control register */ embeddedice_read_reg(®_list[EICE_COMMS_CTRL]); - jtag_execute_queue(); + if ((retval=jtag_execute_queue())!=ERROR_OK) + { + for (i = 0; i < num_regs; i++) + { + free(reg_list[i].value); + } + free(reg_list); + free(arch_info); + return NULL; + } eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4); @@ -181,16 +191,27 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32)); } + return reg_cache; +} + +int embeddedice_setup(target_t *target) +{ + int retval; + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + /* explicitly disable monitor mode */ if (arm7_9->has_monitor_mode) { - embeddedice_read_reg(®_list[EICE_DBG_CTRL]); - jtag_execute_queue(); - buf_set_u32(reg_list[EICE_DBG_CTRL].value, 4, 1, 0); - embeddedice_set_reg_w_exec(®_list[EICE_DBG_CTRL], reg_list[EICE_DBG_CTRL].value); + reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + + embeddedice_read_reg(dbg_ctrl); + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; + buf_set_u32(dbg_ctrl->value, 4, 1, 0); + embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value); } - - return reg_cache; + return jtag_execute_queue(); } int embeddedice_get_reg(reg_t *reg) diff --git a/src/target/etm.c b/src/target/etm.c index c6749c5cd..8e39a4f63 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -223,7 +223,6 @@ reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_co etm_reg_t *arch_info = NULL; int num_regs = sizeof(etm_reg_arch_info)/sizeof(int); int i; - u32 etm_ctrl_value; /* register a register arch-type for etm registers only once */ if (etm_reg_arch_type == -1) @@ -256,21 +255,6 @@ reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_co arch_info[i].jtag_info = jtag_info; } - /* initialize some ETM control register settings */ - etm_get_reg(®_list[ETM_CTRL]); - etm_ctrl_value = buf_get_u32(reg_list[ETM_CTRL].value, 0, reg_list[ETM_CTRL].size); - - /* clear the ETM powerdown bit (0) */ - etm_ctrl_value &= ~0x1; - - /* configure port width (6:4), mode (17:16) and clocking (13) */ - etm_ctrl_value = (etm_ctrl_value & - ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK) - | etm_ctx->portmode; - - buf_set_u32(reg_list[ETM_CTRL].value, 0, reg_list[ETM_CTRL].size, etm_ctrl_value); - etm_store_reg(®_list[ETM_CTRL]); - /* the ETM might have an ETB connected */ if (strcmp(etm_ctx->capture_driver->name, "etb") == 0) { @@ -287,15 +271,44 @@ reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_co etb->reg_cache = reg_cache->next; } - if (etm_ctx->capture_driver->init(etm_ctx) != ERROR_OK) - { - LOG_ERROR("ETM capture driver initialization failed"); - exit(-1); - } return reg_cache; } +int etm_setup(target_t *target) +{ + int retval; + u32 etm_ctrl_value; + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + etm_context_t *etm_ctx = arm7_9->etm_ctx; + reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL]; + /* initialize some ETM control register settings */ + etm_get_reg(etm_ctrl_reg); + etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size); + + /* clear the ETM powerdown bit (0) */ + etm_ctrl_value &= ~0x1; + + /* configure port width (6:4), mode (17:16) and clocking (13) */ + etm_ctrl_value = (etm_ctrl_value & + ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK) + | etm_ctx->portmode; + + buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value); + etm_store_reg(etm_ctrl_reg); + + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; + + if ((retval=etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK) + { + LOG_ERROR("ETM capture driver initialization failed"); + return retval; + } + return ERROR_OK; +} + int etm_get_reg(reg_t *reg) { if (etm_read_reg(reg) != ERROR_OK)