mirror of https://github.com/rusefi/rusefi-1.git
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This commit is contained in:
rusEfi
parent
e0f081dc0a
commit
10b3fcb21a
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@ -401,7 +401,7 @@
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#define STM32_CAN_MAX_FILTERS 28
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/* DAC attributes.*/
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#define STM32_HAS_DAC TRUE
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#define STM32_HAS_DAC FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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@ -409,7 +409,11 @@
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#define STM32_HAS_DMA2 TRUE
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/* ETH attributes.*/
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#if !defined(STM32F401xx)
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#define STM32_HAS_ETH TRUE
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#else /* defined(STM32F401xx) */
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#define STM32_HAS_ETH FALSE
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#endif /* defined(STM32F401xx) */
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_CHANNELS 23
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@ -425,11 +429,11 @@
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOI TRUE
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#else
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#else /* defined(STM32F401xx) */
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOI FALSE
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#endif
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#endif /* defined(STM32F401xx) */
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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@ -491,7 +495,8 @@
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STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_SPI3_TX_DMA_CHN 0x00000000
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#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
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#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || \
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defined(STM32F401xx)
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#define STM32_HAS_SPI4 TRUE
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#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \
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STM32_DMA_STREAM_ID_MSK(2, 3))
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@ -499,7 +504,11 @@
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#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_SPI4_TX_DMA_CHN 0x00050040
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#else
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#define STM32_HAS_SPI4 FALSE
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#endif
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#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
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#define STM32_HAS_SPI5 TRUE
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#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \
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STM32_DMA_STREAM_ID_MSK(2, 5))
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@ -515,7 +524,6 @@
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#define STM32_SPI6_TX_DMA_CHN 0x00100000
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#else /* !(defined(STM32F427_437xx) || defined(STM32F429_439xx)) */
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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#endif /* !(defined(STM32F427_437xx) || defined(STM32F429_439xx)) */
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@ -526,15 +534,27 @@
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#define STM32_HAS_TIM3 TRUE
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#define STM32_HAS_TIM4 TRUE
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#define STM32_HAS_TIM5 TRUE
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#if !defined(STM32F401xx)
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#define STM32_HAS_TIM6 TRUE
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#define STM32_HAS_TIM7 TRUE
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#define STM32_HAS_TIM8 TRUE
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#else /* defined(STM32F401xx) */
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#define STM32_HAS_TIM6 FALSE
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#define STM32_HAS_TIM7 FALSE
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#define STM32_HAS_TIM8 FALSE
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#endif /* defined(STM32F401xx) */
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#define STM32_HAS_TIM9 TRUE
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#define STM32_HAS_TIM10 TRUE
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#define STM32_HAS_TIM11 TRUE
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#if !defined(STM32F401xx)
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#define STM32_HAS_TIM12 TRUE
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#define STM32_HAS_TIM13 TRUE
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#define STM32_HAS_TIM14 TRUE
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#else /* defined(STM32F401xx) */
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#endif /* defined(STM32F401xx) */
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#define STM32_HAS_TIM15 FALSE
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#define STM32_HAS_TIM16 FALSE
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#define STM32_HAS_TIM17 FALSE
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@ -555,6 +575,7 @@
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#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_USART2_TX_DMA_CHN 0x04000000
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#if !defined(STM32F401xx)
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#define STM32_HAS_USART3 TRUE
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#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
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#define STM32_USART3_RX_DMA_CHN 0x00000040
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@ -574,6 +595,12 @@
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#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_UART5_TX_DMA_CHN 0x40000000
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#else /* defined(STM32F401xx) */
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#define STM32_HAS_USART3 FALSE
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART5 FALSE
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#endif /* defined(STM32F401xx) */
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#define STM32_HAS_USART6 TRUE
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#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \
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STM32_DMA_STREAM_ID_MSK(2, 2))
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@ -585,7 +612,11 @@
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/* USB attributes.*/
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#define STM32_HAS_USB FALSE
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#define STM32_HAS_OTG1 TRUE
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#if !defined(STM32F401xx)
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#define STM32_HAS_OTG2 TRUE
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#else /* defined(STM32F401xx) */
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#define STM32_HAS_OTG2 FALSE
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#endif /* defined(STM32F401xx) */
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/** @} */
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/*===========================================================================*/
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@ -36,23 +36,41 @@
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/*
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* CAN units.
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*/
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#define STM32_CAN1_TX_HANDLER CAN1_TX_IRQHandler
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#define STM32_CAN1_RX0_HANDLER CAN1_RX0_IRQHandler
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#define STM32_CAN1_RX1_HANDLER CAN1_RX1_IRQHandler
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#define STM32_CAN1_SCE_HANDLER CAN1_SCE_IRQHandler
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#define STM32_CAN2_TX_HANDLER CAN2_TX_IRQHandler
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#define STM32_CAN2_RX0_HANDLER CAN2_RX0_IRQHandler
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#define STM32_CAN2_RX1_HANDLER CAN2_RX1_IRQHandler
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#define STM32_CAN2_SCE_HANDLER CAN2_SCE_IRQHandler
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#define STM32_CAN1_TX_HANDLER Vector8C
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#define STM32_CAN1_RX0_HANDLER Vector90
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#define STM32_CAN1_RX1_HANDLER Vector94
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#define STM32_CAN1_SCE_HANDLER Vector98
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#define STM32_CAN2_TX_HANDLER Vector13C
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#define STM32_CAN2_RX0_HANDLER Vector140
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#define STM32_CAN2_RX1_HANDLER Vector144
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#define STM32_CAN2_SCE_HANDLER Vector148
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#define STM32_CAN1_TX_NUMBER CAN1_TX_IRQn
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#define STM32_CAN1_RX0_NUMBER CAN1_RX0_IRQn
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#define STM32_CAN1_RX1_NUMBER CAN1_RX1_IRQn
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#define STM32_CAN1_SCE_NUMBER CAN1_SCE_IRQn
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#define STM32_CAN2_TX_NUMBER CAN2_TX_IRQn
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#define STM32_CAN2_RX0_NUMBER CAN2_RX0_IRQn
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#define STM32_CAN2_RX1_NUMBER CAN2_RX1_IRQn
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#define STM32_CAN2_SCE_NUMBER CAN2_SCE_IRQn
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#define STM32_CAN1_TX_NUMBER 19
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#define STM32_CAN1_RX0_NUMBER 20
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#define STM32_CAN1_RX1_NUMBER 21
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#define STM32_CAN1_SCE_NUMBER 22
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#define STM32_CAN2_TX_NUMBER 63
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#define STM32_CAN2_RX0_NUMBER 64
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#define STM32_CAN2_RX1_NUMBER 65
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#define STM32_CAN2_SCE_NUMBER 66
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/*
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* I2C units.
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*/
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#define STM32_I2C1_EVENT_HANDLER VectorBC
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#define STM32_I2C1_ERROR_HANDLER VectorC0
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#define STM32_I2C1_EVENT_NUMBER 31
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#define STM32_I2C1_ERROR_NUMBER 32
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#define STM32_I2C2_EVENT_HANDLER VectorC4
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#define STM32_I2C2_ERROR_HANDLER VectorC8
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#define STM32_I2C2_EVENT_NUMBER 33
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#define STM32_I2C2_ERROR_NUMBER 34
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#define STM32_I2C3_EVENT_HANDLER Vector160
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#define STM32_I2C3_ERROR_HANDLER Vector164
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#define STM32_I2C3_EVENT_NUMBER 72
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#define STM32_I2C3_ERROR_NUMBER 73
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/*
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* OTG units.
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#define STM32_OTG2_EP1OUT_HANDLER Vector168
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#define STM32_OTG2_EP1IN_HANDLER Vector16C
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#define STM32_OTG1_NUMBER OTG_FS_IRQn
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#define STM32_OTG2_NUMBER OTG_HS_IRQn
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#define STM32_OTG2_EP1OUT_NUMBER OTG_HS_EP1_OUT_IRQn
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#define STM32_OTG2_EP1IN_NUMBER OTG_HS_EP1_IN_IRQn
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#define STM32_OTG1_NUMBER 67
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#define STM32_OTG2_NUMBER 77
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#define STM32_OTG2_EP1OUT_NUMBER 74
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#define STM32_OTG2_EP1IN_NUMBER 75
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/*
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* SDIO unit.
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*/
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#define STM32_SDIO_HANDLER SDIO_IRQHandler
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#define STM32_SDIO_HANDLER Vector104
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#define STM32_SDIO_NUMBER SDIO_IRQn
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#define STM32_SDIO_NUMBER 49
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/*
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* TIM units.
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*/
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#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler
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#define STM32_TIM1_CC_HANDLER TIM1_CC_IRQHandler
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#define STM32_TIM2_HANDLER TIM2_IRQHandler
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#define STM32_TIM3_HANDLER TIM3_IRQHandler
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#define STM32_TIM4_HANDLER TIM4_IRQHandler
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#define STM32_TIM5_HANDLER TIM5_IRQHandler
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#define STM32_TIM6_HANDLER TIM6_IRQHandler
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#define STM32_TIM7_HANDLER TIM7_IRQHandler
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#define STM32_TIM8_UP_HANDLER TIM8_UP_IRQHandler
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#define STM32_TIM8_CC_HANDLER TIM8_CC_IRQHandler
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#define STM32_TIM9_HANDLER TIM1_BRK_IRQHandler
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#define STM32_TIM11_HANDLER TIM1_TRG_COM_IRQHandler
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#define STM32_TIM12_HANDLER TIM8_BRK_IRQHandler
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#define STM32_TIM14_HANDLER TIM8_TRG_COM_IRQHandler
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#define STM32_TIM1_UP_HANDLER VectorA4
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#define STM32_TIM1_CC_HANDLER VectorAC
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#define STM32_TIM2_HANDLER VectorB0
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#define STM32_TIM3_HANDLER VectorB4
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#define STM32_TIM4_HANDLER VectorB8
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#define STM32_TIM5_HANDLER Vector108
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#define STM32_TIM6_HANDLER Vector118
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#define STM32_TIM7_HANDLER Vector11C
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#define STM32_TIM8_UP_HANDLER VectorF0
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#define STM32_TIM8_CC_HANDLER VectorF8
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#define STM32_TIM9_HANDLER VectorA0
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#define STM32_TIM11_HANDLER VectorA8
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#define STM32_TIM12_HANDLER VectorEC
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#define STM32_TIM14_HANDLER VectorF4
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#define STM32_TIM1_UP_NUMBER TIM1_UP_TIM10_IRQn
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#define STM32_TIM1_CC_NUMBER TIM1_CC_IRQn
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#define STM32_TIM2_NUMBER TIM2_IRQn
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#define STM32_TIM3_NUMBER TIM3_IRQn
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#define STM32_TIM4_NUMBER TIM4_IRQn
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#define STM32_TIM5_NUMBER TIM5_IRQn
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#define STM32_TIM6_NUMBER TIM6_IRQn
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#define STM32_TIM7_NUMBER TIM7_IRQn
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#define STM32_TIM8_UP_NUMBER TIM8_UP_TIM13_IRQn
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#define STM32_TIM8_CC_NUMBER TIM8_CC_IRQn
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#define STM32_TIM9_NUMBER TIM1_BRK_TIM9_IRQn
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#define STM32_TIM11_NUMBER TIM1_TRG_COM_TIM11_IRQn
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#define STM32_TIM12_NUMBER TIM8_BRK_TIM12_IRQn
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#define STM32_TIM14_NUMBER TIM8_TRG_COM_TIM14_IRQn
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#define STM32_TIM1_UP_NUMBER 25
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#define STM32_TIM1_CC_NUMBER 27
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#define STM32_TIM2_NUMBER 28
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#define STM32_TIM3_NUMBER 29
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#define STM32_TIM4_NUMBER 30
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#define STM32_TIM5_NUMBER 50
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#define STM32_TIM6_NUMBER 54
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#define STM32_TIM7_NUMBER 55
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#define STM32_TIM8_UP_NUMBER 44
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#define STM32_TIM8_CC_NUMBER 46
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#define STM32_TIM9_NUMBER 24
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#define STM32_TIM11_NUMBER 26
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#define STM32_TIM12_NUMBER 43
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#define STM32_TIM14_NUMBER 45
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/*
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* USART units.
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*/
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#define STM32_USART1_HANDLER USART1_IRQHandler
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#define STM32_USART2_HANDLER USART2_IRQHandler
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#define STM32_USART3_HANDLER USART3_IRQHandler
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#define STM32_UART4_HANDLER UART4_IRQHandler
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#define STM32_UART5_HANDLER UART5_IRQHandler
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#define STM32_USART6_HANDLER USART6_IRQHandler
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#define STM32_USART1_HANDLER VectorD4
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#define STM32_USART2_HANDLER VectorD8
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#define STM32_USART3_HANDLER VectorDC
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#define STM32_UART4_HANDLER Vector110
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#define STM32_UART5_HANDLER Vector114
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#define STM32_USART6_HANDLER Vector15C
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#define STM32_USART1_NUMBER 37
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#define STM32_USART2_NUMBER 38
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#define STM32_USART3_NUMBER 39
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#define STM32_UART4_NUMBER 52
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#define STM32_UART5_NUMBER 53
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#define STM32_USART6_NUMBER 71
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/*
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* Ethernet
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*/
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#define ETH_IRQHandler Vector134
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#define STM32_USART1_NUMBER USART1_IRQn
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#define STM32_USART2_NUMBER USART2_IRQn
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#define STM32_USART3_NUMBER USART3_IRQn
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#define STM32_UART4_NUMBER UART4_IRQn
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#define STM32_UART5_NUMBER UART5_IRQn
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#define STM32_USART6_NUMBER USART6_IRQn
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/** @} */
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/*===========================================================================*/
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@ -47,7 +47,7 @@
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/**
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* @brief Kernel version string.
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*/
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#define CH_KERNEL_VERSION "2.6.3"
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#define CH_KERNEL_VERSION "2.6.6"
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/**
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* @name Kernel version
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@ -66,7 +66,7 @@
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/**
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* @brief Kernel version patch number.
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*/
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#define CH_KERNEL_PATCH 3
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#define CH_KERNEL_PATCH 6
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/** @} */
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/**
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@ -62,7 +62,7 @@ typedef struct {
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irq_vector_t vector34;
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irq_vector_t pendsv_vector;
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irq_vector_t systick_vector;
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irq_vector_t vectors[82];
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irq_vector_t vectors[91];
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} vectors_t;
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#if !defined(__DOXYGEN__)
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@ -164,6 +164,15 @@ extern void Vector178(void);
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extern void Vector17C(void);
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extern void Vector180(void);
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extern void Vector184(void);
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extern void Vector188(void);
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extern void Vector18C(void);
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extern void Vector190(void);
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extern void Vector194(void);
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extern void Vector198(void);
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extern void Vector19C(void);
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extern void Vector1A0(void);
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extern void Vector1A4(void);
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extern void Vector1A8(void);
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#endif
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/**
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@ -198,7 +207,9 @@ vectors_t _vectors = {
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Vector150, Vector154, Vector158, Vector15C,
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Vector160, Vector164, Vector168, Vector16C,
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Vector170, Vector174, Vector178, Vector17C,
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Vector180, Vector184
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Vector180, Vector184, Vector188, Vector18C,
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Vector190, Vector194, Vector198, Vector19C,
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Vector1A0, Vector1A4, Vector1A8
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}
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};
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@ -314,5 +325,14 @@ void Vector178(void) __attribute__((weak, alias("_unhandled_exception")));
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void Vector17C(void) __attribute__((weak, alias("_unhandled_exception")));
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void Vector180(void) __attribute__((weak, alias("_unhandled_exception")));
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void Vector184(void) __attribute__((weak, alias("_unhandled_exception")));
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void Vector188(void) __attribute__((weak, alias("_unhandled_exception")));
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void Vector18C(void) __attribute__((weak, alias("_unhandled_exception")));
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void Vector190(void) __attribute__((weak, alias("_unhandled_exception")));
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void Vector194(void) __attribute__((weak, alias("_unhandled_exception")));
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void Vector198(void) __attribute__((weak, alias("_unhandled_exception")));
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void Vector19C(void) __attribute__((weak, alias("_unhandled_exception")));
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void Vector1A0(void) __attribute__((weak, alias("_unhandled_exception")));
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void Vector1A4(void) __attribute__((weak, alias("_unhandled_exception")));
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void Vector1A8(void) __attribute__((weak, alias("_unhandled_exception")));
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/** @} */
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@ -39,21 +39,6 @@
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/* Port interrupt handlers. */
|
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/*===========================================================================*/
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int getRemainingStack(Thread *otp) {
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#if CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
|
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int remainingStack;
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if (dbg_isr_cnt > 0) {
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remainingStack = 999; // todo
|
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} else {
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remainingStack = (stkalign_t *)(__get_SP() - sizeof(struct intctx)) - otp->p_stklimit;
|
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}
|
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otp->remainingStack = remainingStack;
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return remainingStack;
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#else
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return 999999;
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#endif
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}
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/**
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* @brief System Timer vector.
|
||||
* @details This interrupt is used as system tick.
|
||||
|
|
@ -80,6 +65,11 @@ CH_IRQ_HANDLER(SysTickVector) {
|
|||
void SVCallVector(void) {
|
||||
struct extctx *ctxp;
|
||||
|
||||
#if CORTEX_USE_FPU
|
||||
/* Enforcing unstacking of the FP part of the context.*/
|
||||
SCB_FPCCR &= ~FPCCR_LSPACT;
|
||||
#endif
|
||||
|
||||
/* Current PSP value.*/
|
||||
ctxp = (struct extctx *)__get_PSP();
|
||||
|
||||
|
|
@ -87,11 +77,7 @@ void SVCallVector(void) {
|
|||
point to the real one.*/
|
||||
ctxp++;
|
||||
|
||||
#if CORTEX_USE_FPU
|
||||
/* Restoring the special register SCB_FPCCR.*/
|
||||
SCB_FPCCR = (uint32_t)ctxp->fpccr;
|
||||
SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx);
|
||||
#endif
|
||||
/* Restoring real position of the original stack frame.*/
|
||||
__set_PSP((unsigned long)ctxp);
|
||||
port_unlock_from_isr();
|
||||
}
|
||||
|
|
@ -107,6 +93,11 @@ void SVCallVector(void) {
|
|||
void PendSVVector(void) {
|
||||
struct extctx *ctxp;
|
||||
|
||||
#if CORTEX_USE_FPU
|
||||
/* Enforcing unstacking of the FP part of the context.*/
|
||||
SCB_FPCCR &= ~FPCCR_LSPACT;
|
||||
#endif
|
||||
|
||||
/* Current PSP value.*/
|
||||
ctxp = (struct extctx *)__get_PSP();
|
||||
|
||||
|
|
@ -114,11 +105,7 @@ void PendSVVector(void) {
|
|||
point to the real one.*/
|
||||
ctxp++;
|
||||
|
||||
#if CORTEX_USE_FPU
|
||||
/* Restoring the special register SCB_FPCCR.*/
|
||||
SCB_FPCCR = (uint32_t)ctxp->fpccr;
|
||||
SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx);
|
||||
#endif
|
||||
/* Restoring real position of the original stack frame.*/
|
||||
__set_PSP((unsigned long)ctxp);
|
||||
}
|
||||
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
|
||||
|
|
@ -171,24 +158,29 @@ void _port_irq_epilogue(void) {
|
|||
if ((SCB_ICSR & ICSR_RETTOBASE) != 0) {
|
||||
struct extctx *ctxp;
|
||||
|
||||
#if CORTEX_USE_FPU
|
||||
/* Enforcing a lazy FPU state save. Note, it goes in the original
|
||||
context because the FPCAR register has not been modified.*/
|
||||
(void)__get_FPSCR();
|
||||
#endif
|
||||
|
||||
/* Current PSP value.*/
|
||||
ctxp = (struct extctx *)__get_PSP();
|
||||
|
||||
/* Adding an artificial exception return context, there is no need to
|
||||
populate it fully.*/
|
||||
ctxp--;
|
||||
__set_PSP((unsigned long)ctxp);
|
||||
ctxp->xpsr = (regarm_t)0x01000000;
|
||||
#if CORTEX_USE_FPU
|
||||
ctxp->fpscr = (regarm_t)SCB_FPDSCR;
|
||||
#endif
|
||||
__set_PSP((unsigned long)ctxp);
|
||||
|
||||
/* The exit sequence is different depending on if a preemption is
|
||||
required or not.*/
|
||||
if (chSchIsPreemptionRequired()) {
|
||||
/* Preemption is required we need to enforce a context switch.*/
|
||||
ctxp->pc = (regarm_t)_port_switch_from_isr;
|
||||
#if CORTEX_USE_FPU
|
||||
/* Triggering a lazy FPU state save.*/
|
||||
(void)__get_FPSCR();
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
/* Preemption not required, we just need to exit the exception
|
||||
|
|
@ -196,20 +188,6 @@ void _port_irq_epilogue(void) {
|
|||
ctxp->pc = (regarm_t)_port_exit_from_isr;
|
||||
}
|
||||
|
||||
#if CORTEX_USE_FPU
|
||||
{
|
||||
uint32_t fpccr;
|
||||
|
||||
/* Saving the special register SCB_FPCCR into the reserved offset of
|
||||
the Cortex-M4 exception frame.*/
|
||||
(ctxp + 1)->fpccr = (regarm_t)(fpccr = SCB_FPCCR);
|
||||
|
||||
/* Now the FPCCR is modified in order to not restore the FPU status
|
||||
from the artificial return context.*/
|
||||
SCB_FPCCR = fpccr | FPCCR_LSPACT;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Note, returning without unlocking is intentional, this is done in
|
||||
order to keep the rest of the context switch atomic.*/
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -267,7 +267,7 @@ struct extctx {
|
|||
regarm_t s14;
|
||||
regarm_t s15;
|
||||
regarm_t fpscr;
|
||||
regarm_t fpccr;
|
||||
regarm_t reserved;
|
||||
#endif /* CORTEX_USE_FPU */
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -15,7 +15,11 @@ int getRemainingStack(Thread *otp);
|
|||
|
||||
extern stkalign_t __main_stack_base__;
|
||||
|
||||
#if defined __GNUC__
|
||||
// GCC version
|
||||
|
||||
int getRemainingStack(Thread *otp) {
|
||||
|
||||
#if CH_DBG_ENABLE_STACK_CHECK
|
||||
register struct intctx *r13 asm ("r13");
|
||||
otp->activeStack = r13;
|
||||
|
|
@ -35,6 +39,31 @@ int getRemainingStack(Thread *otp) {
|
|||
#endif /* CH_DBG_ENABLE_STACK_CHECK */
|
||||
}
|
||||
|
||||
#else /* __GNUC__ */
|
||||
|
||||
|
||||
int getRemainingStack(Thread *otp) {
|
||||
#if CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
|
||||
int remainingStack;
|
||||
if (dbg_isr_cnt > 0) {
|
||||
remainingStack = 999; // todo
|
||||
} else {
|
||||
remainingStack = (stkalign_t *)(__get_SP() - sizeof(struct intctx)) - otp->p_stklimit;
|
||||
}
|
||||
otp->remainingStack = remainingStack;
|
||||
return remainingStack;
|
||||
#else
|
||||
return 999999;
|
||||
#endif
|
||||
}
|
||||
|
||||
// IAR version
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
void baseHardwareInit(void) {
|
||||
// looks like this holds a random value on start? Let's set a nice clean zero
|
||||
|
|
|
|||
Loading…
Reference in New Issue