mirror of https://github.com/rusefi/rusefi-1.git
Better Windows build-in DFU #3338
those are needed for DFU to be able to verify
This commit is contained in:
rusefillc
parent
a60d9c00b5
commit
4ce721846d
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@ -0,0 +1,322 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
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<Device>
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<DeviceID>0x413</DeviceID>
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<Vendor>STMicroelectronics</Vendor>
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<Type>MCU</Type>
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<CPU>Cortex-M4</CPU>
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<Name>STM32F405xx/F407xx/F415xx/F417xx</Name>
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<Series>STM32F4</Series>
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<Description>ARM 32-bit Cortex-M4 based device</Description>
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<Configurations>
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<!-- JTAG_SWD Interface -->
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<Interface name="JTAG_SWD"/>
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<!-- Bootloader Interface -->
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<Interface name="Bootloader"/>
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</Configurations>
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<!-- Peripherals -->
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<Peripherals>
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<!-- Embedded SRAM -->
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<Peripheral>
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<Name>Embedded SRAM</Name>
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<Type>Storage</Type>
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<Description/>
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<ErasedValue>0x00</ErasedValue>
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<Access>RWE</Access>
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<!-- 112 KB 0x1c000-->
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<Configuration>
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<Parameters address="0x20000000" name="SRAM" size="0x20000"/>
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<Description/>
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<Organization>Single</Organization>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x20000"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Embedded Flash -->
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<Peripheral>
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<Name>Embedded Flash</Name>
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<Type>Storage</Type>
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<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RWE</Access>
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<FlashSize address="0x1FFFF7CC" default="0x100000"/>
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<!-- 1024KB Single Bank -->
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<Configuration>
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<Parameters address="0x08000000" name=" 1024 Kbytes Embedded Flash" size="0x100000"/>
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<Description/>
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<Organization>Single</Organization>
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<Allignement>0x4</Allignement>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
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</Field>
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<Field>
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<Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
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</Field>
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<Field>
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<Parameters address="0x08020000" name="sector5" occurence="0x7" size="0x20000"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- OTP -->
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<Peripheral>
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<Name>OTP</Name>
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<Type>Storage</Type>
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<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RW</Access>
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<!-- 512 Bytes single bank -->
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<Configuration>
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<Parameters address="0x1FFF7800" name=" 512 Bytes Data OTP" size="0x200"/>
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<Description/>
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<Organization>Single</Organization>
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<Allignement>0x4</Allignement>
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<Bank name="OTP">
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<Field>
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<Parameters address="0x1FFF7800" name="OTP" occurence="0x1" size="0x200"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Mirror Option Bytes -->
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<Peripheral>
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<Name>MirrorOptionBytes</Name>
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<Type>Storage</Type>
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<Description>Mirror Option Bytes contains the extra area.</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RW</Access>
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<!-- 8 Bytes single bank -->
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<Configuration>
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<Parameters address="0x1FFFC000" name=" 8 Bytes Data MirrorOptionBytes" size="0x8"/>
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<Description/>
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<Organization>Single</Organization>
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<Allignement>0x4</Allignement>
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<Bank name="MirrorOptionBytes">
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<Field>
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<Parameters address="0x1FFFC000" name="MirrorOptionBytes" occurence="0x1" size="0x8"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Option Bytes -->
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<Peripheral>
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<Name>Option Bytes</Name>
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<Type>Configuration</Type>
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<Description/>
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<Access>RW</Access>
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<Bank interface="JTAG_SWD">
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<Parameters address="0x40023c14" name="Bank 1" size="0x4"/>
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<Category>
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<Name>Read Out Protection</Name>
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<Field>
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<Parameters address="0x40023c14" name="RDP" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>RDP</Name>
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<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
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<BitOffset>0x8</BitOffset>
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<BitWidth>0x8</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0xAA">Level 0, no protection</Val>
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<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
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<Val value="0xCC">Level 2, chip protection</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>BOR Level</Name>
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<Field>
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<Parameters address="0x40023c14" name="USER" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>BOR_LEV</Name>
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<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
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<BitOffset>0x2</BitOffset>
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<BitWidth>0x2</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
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<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
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<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
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<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>User Configuration</Name>
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<Field>
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<Parameters address="0x40023c14" name="USER" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>WDG_SW</Name>
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<Description/>
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<BitOffset>0x5</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Hardware watchdog</Val>
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<Val value="0x1">Software watchdog</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nRST_STOP</Name>
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<Description/>
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<BitOffset>0x6</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Reset generated when entering Stop mode</Val>
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<Val value="0x1">No reset generated</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nRST_STDBY</Name>
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<Description/>
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<BitOffset>0x7</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Reset generated when entering Standby mode</Val>
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<Val value="0x1">No reset generated</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>Write Protection</Name>
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<Field>
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<Parameters address="0x40023c14" name="WRP1" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>WRP0</Name>
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<Description/>
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<BitOffset>0x10</BitOffset>
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<BitWidth>0xC</BitWidth>
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<Access>RW</Access>
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<Values ByBit="true">
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<Val value="0x0">Write protection active</Val>
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<Val value="0x1">Write protection not active</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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</Bank>
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<Bank interface="Bootloader">
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<Parameters address="0x1FFFC000" name="Bank 1" size="0x10"/>
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<Category>
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<Name>Read Out Protection</Name>
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<Field>
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<Parameters address="0x1FFFC000" name="RDP" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>RDP</Name>
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<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
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<BitOffset>0x8</BitOffset>
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<BitWidth>0x8</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0xAA">Level 0, no protection</Val>
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<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
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<Val value="0xCC">Level 2, chip protection</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>BOR Level</Name>
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<Field>
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<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>BOR_LEV</Name>
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<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
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<BitOffset>0x2</BitOffset>
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<BitWidth>0x2</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
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<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
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<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
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<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>User Configuration</Name>
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<Field>
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<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>WDG_SW</Name>
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<Description/>
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<BitOffset>0x5</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Hardware watchdog</Val>
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<Val value="0x1">Software watchdog</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nRST_STOP</Name>
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<Description/>
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<BitOffset>0x6</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Reset generated when entering Stop mode</Val>
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<Val value="0x1">No reset generated</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nRST_STDBY</Name>
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<Description/>
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<BitOffset>0x7</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Reset generated when entering Standby mode</Val>
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<Val value="0x1">No reset generated</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>Write Protection</Name>
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<Field>
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<Parameters address="0x1FFFC008" name="WRP1" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>WRP0</Name>
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<Description/>
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<BitOffset>0x0</BitOffset>
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<BitWidth>0xC</BitWidth>
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<Access>RW</Access>
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<Values ByBit="true">
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<Val value="0x0">Write protection active</Val>
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<Val value="0x1">Write protection not active</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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</Bank>
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</Peripheral>
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</Peripherals>
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</Device>
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</Root>
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@ -0,0 +1,599 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
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<Device>
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<DeviceID>0x419</DeviceID>
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<Vendor>STMicroelectronics</Vendor>
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<Type>MCU</Type>
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<CPU>Cortex-M4</CPU>
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<Name>STM32F42xxx/F43xxx</Name>
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<Series>STM32F4</Series>
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<Description>ARM 32-bit Cortex-M4 based device</Description>
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<Configurations>
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<!-- JTAG_SWD Interface -->
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<Interface name="JTAG_SWD">
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<Configuration number="0x0">
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<SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
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<flashSize> <!-- 2M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x800"/> </flashSize>
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</Configuration>
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<Configuration number="0x1">
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<SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x80000000"/> </SPRMode>
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<flashSize> <!-- 2M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0"/> </flashSize>
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</Configuration>
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<Configuration number="0x2">
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<SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
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<flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x400"/> </flashSize>
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<DB1M reference="0x0"> <ReadRegister address="0x40023C14" mask="0x40000000" value="0x0"/> </DB1M>
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</Configuration>
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<Configuration number="0x3">
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<SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x80000000"/> </SPRMode>
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<flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x400"/> </flashSize>
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<DB1M reference="0x0"> <ReadRegister address="0x40023C14" mask="0x40000000" value="0x0"/> </DB1M>
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</Configuration>
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<Configuration number="0x4">
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<SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
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<flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x400"/> </flashSize>
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<DB1M reference="0x1"> <ReadRegister address="0x40023C14" mask="0x40000000" value="0x40000000"/> </DB1M>
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</Configuration>
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<Configuration number="0x5">
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<SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x80000000"/> </SPRMode>
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<flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x400"/> </flashSize>
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<DB1M reference="0x1"> <ReadRegister address="0x40023C14" mask="0x40000000" value="0x40000000"/> </DB1M>
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</Configuration>
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<Configuration number="0x6"> <!-- dummy config ></!-->
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<dummy> <ReadRegister address="0x20000000" mask="0" value="0"/> </dummy>
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</Configuration>
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</Interface>
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<!-- Bootloader Interface -->
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<Interface name="Bootloader">
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<Configuration number="0x0">
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<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
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</Configuration>
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<Configuration number="0x1">
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<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
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</Configuration>
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<Configuration number="0x2">
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<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
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<DB1M reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x4000" value="0x0"/> </DB1M>
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</Configuration>
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<Configuration number="0x3">
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<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
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<DB1M reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x4000" value="0x0"/> </DB1M>
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</Configuration>
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<Configuration number="0x4">
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<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
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<DB1M reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x4000" value="0x4000"/> </DB1M>
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</Configuration>
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<Configuration number="0x5">
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<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
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<DB1M reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x4000" value="0x4000"/> </DB1M>
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</Configuration>
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<Configuration number="0x6"> <!-- dummy config ></!-->
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<dummy> <ReadRegister address="0x20000000" mask="0" value="0"/> </dummy>
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</Configuration>
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</Interface>
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</Configurations>
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<!-- Peripherals -->
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<Peripherals>
|
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<!-- Embedded SRAM -->
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<Peripheral>
|
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<Name>Embedded SRAM</Name>
|
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<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
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<!-- 112 KB 0x1c000-->
|
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<Configuration>
|
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<Parameters address="0x20000000" name="SRAM" size="0x30000"/>
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<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x30000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x1FFF7A22" default="0x200000"/>
|
||||
<!-- 1024KB Single Bank -->
|
||||
<Configuration config="0,1,6">
|
||||
<Parameters address="0x08000000" name=" 2048 Kbytes Embedded Flash" size="0x200000"/>
|
||||
<Description/>
|
||||
<Organization>Dual</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08020000" name="sector5" occurence="0x7" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
<Bank name="Bank 2">
|
||||
<Field>
|
||||
<Parameters address="0x08100000" name="sector12" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08110000" name="sector16" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08120000" name="sector17" occurence="0x7" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
<Configuration config="4,5">
|
||||
<Parameters address="0x08000000" name=" 1024 Kbytes Embedded Flash" size="0x100000"/>
|
||||
<Description/>
|
||||
<Organization>Dual</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08020000" name="sector5" occurence="0x3" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
<Bank name="Bank 2">
|
||||
<Field>
|
||||
<Parameters address="0x08080000" name="sector8" occurence="0x4" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
<Configuration config="2,3">
|
||||
<Parameters address="0x08000000" name=" 1024 Kbytes Embedded Flash" size="0x100000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08020000" name="sector5" occurence="0x7" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- OTP -->
|
||||
<Peripheral>
|
||||
<Name>OTP</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 512 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFF7800" name=" 512 Bytes Data OTP" size="0x200"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="OTP">
|
||||
<Field>
|
||||
<Parameters address="0x1FFF7800" name="OTP" occurence="0x1" size="0x200"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Mirror Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>MirrorOptionBytes</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>Mirror Option Bytes contains the extra area.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 24 Bytes Dual bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFF7800" name=" 24 Bytes Data MirrorOptionBytes" size="0x18"/>
|
||||
<Description/>
|
||||
<Organization>Dual</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="Bank1" occurence="0x1" size="0x10"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
<Bank name="Bank 2">
|
||||
<Field>
|
||||
<Parameters address="0x1FFEC008" name="Bank2" occurence="0x1" size="0x8"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank interface="JTAG_SWD">
|
||||
<Parameters address="0x40023C14" name="Bank 1" size="0x8"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BFB2</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x4</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default)</Val>
|
||||
<Val value="0x1">Dual-bank boot enabled. Boot is always performed from system memory.</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="2,3,4,5">
|
||||
<Name>DB1M</Name>
|
||||
<Description>Dual-bank on 1 Mbyte Flash memory devices</Description>
|
||||
<BitOffset>0x1E</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">1 Mbyte single bank Flash memory (contiguous addresses in bank1)</Val>
|
||||
<Val value="0x1">1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0,2,4">
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1,3,5,6">
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x40023C18" name="FLASH_OPTCR1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0,2,4">
|
||||
<Name>nWRP12</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1,3,5,6">
|
||||
<Name>nWRP12</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
<Bank interface="Bootloader">
|
||||
<Parameters address="0x1FFFC000" name="Bank 1" size="0x10"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0xF</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BFB2</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x4</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default)</Val>
|
||||
<Val value="0x1">Dual-bank boot enabled. Boot is always performed from system memory.</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="2,3,4,5">
|
||||
<Name>DB1M</Name>
|
||||
<Description>Dual-bank on 1 Mbyte Flash memory devices</Description>
|
||||
<BitOffset>0x1E</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">1 Mbyte single bank Flash memory (contiguous addresses in bank1)</Val>
|
||||
<Val value="0x1">1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection (Bank 1)</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="WRP0" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0,2,4">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1,3,5,6">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
<Bank interface="Bootloader">
|
||||
<Parameters address="0x1FFEC008" name="Bank 2" size="0x8"/>
|
||||
<Category>
|
||||
<Name>Write Protection (Bank 2)</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFEC008" name="WRP1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0,2,4">
|
||||
<Name>WRP12</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1,3,5,6">
|
||||
<Name>WRP12</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,396 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x421</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M4</CPU>
|
||||
<Name>STM32F446xx</Name>
|
||||
<Series>STM32F4</Series>
|
||||
<Description>ARM 32-bit Cortex-M4 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD">
|
||||
<Configuration number="0x0">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
|
||||
</Configuration>
|
||||
<Configuration number="0x1">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x80000000"/> </SPRMode>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader">
|
||||
<Configuration number="0x0">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
|
||||
</Configuration>
|
||||
<Configuration number="0x1">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 128 KB 0x20000-->
|
||||
<Configuration>
|
||||
<Parameters address="0x20000000" name="SRAM" size="0x20000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x1FFF7A22" default="0x80000"/>
|
||||
<!-- 512KB Single Bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x08000000" name=" 512 Kbytes Embedded Flash" size="0x80000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08020000" name="sector5" occurence="0x3" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- OTP -->
|
||||
<Peripheral>
|
||||
<Name>OTP</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 512 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFF7800" name=" 512 Bytes Data OTP" size="0x200"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="OTP">
|
||||
<Field>
|
||||
<Parameters address="0x1FFF7800" name="OTP" occurence="0x1" size="0x200"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Mirror Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>MirrorOptionBytes</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>Mirror Option Bytes contains the extra area.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 16 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFFC000" name=" 16 Bytes Data MirrorOptionBytes" size="0x10"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="MirrorOptionBytes">
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="MirrorOptionBytes" occurence="0x1" size="0x10"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank interface="JTAG_SWD">
|
||||
<Parameters address="0x40023C14" name="Bank 1" size="0x4"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
<Bank interface="Bootloader">
|
||||
<Parameters address="0x1FFFC000" name="Bank 1" size="0x10"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0xF</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="WRP1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,396 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x423</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M4</CPU>
|
||||
<Name>STM32F401xB/C</Name>
|
||||
<Series>STM32F4</Series>
|
||||
<Description>ARM 32-bit Cortex-M4 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD">
|
||||
<Configuration number="0x0">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
|
||||
</Configuration>
|
||||
<Configuration number="0x1">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x80000000"/> </SPRMode>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader">
|
||||
<Configuration number="0x0">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
|
||||
</Configuration>
|
||||
<Configuration number="0x1">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 112 KB 0x1c000-->
|
||||
<Configuration>
|
||||
<Parameters address="0x20000000" name="SRAM" size="0x10000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x1FFF7A22" default="0x40000"/>
|
||||
<!-- 1024KB Single Bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x08000000" name=" 256 Kbytes Embedded Flash" size="0x40000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08020000" name="sector5" occurence="0x1" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- OTP -->
|
||||
<Peripheral>
|
||||
<Name>OTP</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 512 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFF7800" name=" 512 Bytes Data OTP" size="0x200"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="OTP">
|
||||
<Field>
|
||||
<Parameters address="0x1FFF7800" name="OTP" occurence="0x1" size="0x200"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Mirror Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>MirrorOptionBytes</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>Mirror Option Bytes contains the extra area.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 16 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFFC000" name=" 16 Bytes Data MirrorOptionBytes" size="0x10"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="MirrorOptionBytes">
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="MirrorOptionBytes" occurence="0x1" size="0x10"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank interface="JTAG_SWD">
|
||||
<Parameters address="0x40023C14" name="Bank 1" size="0x8"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x6</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x6</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
<Bank interface="Bootloader">
|
||||
<Parameters address="0x1FFFC000" name="Bank 1" size="0x10"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0xF</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="WRP1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x6</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x6</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,396 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x431</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M4</CPU>
|
||||
<Name>STM32F411xC/E</Name>
|
||||
<Series>STM32F4</Series>
|
||||
<Description>ARM 32-bit Cortex-M4 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD">
|
||||
<Configuration number="0x0">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
|
||||
</Configuration>
|
||||
<Configuration number="0x1">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x80000000"/> </SPRMode>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader">
|
||||
<Configuration number="0x0">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
|
||||
</Configuration>
|
||||
<Configuration number="0x1">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 128 KB 0x20000-->
|
||||
<Configuration>
|
||||
<Parameters address="0x20000000" name="SRAM" size="0x10000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x1FFF7A22" default="0x80000"/>
|
||||
<!-- 512KB Single Bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x08000000" name=" 512 Kbytes Embedded Flash" size="0x80000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08020000" name="sector5" occurence="0x3" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- OTP -->
|
||||
<Peripheral>
|
||||
<Name>OTP</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 512 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFF7800" name=" 512 Bytes Data OTP" size="0x200"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="OTP">
|
||||
<Field>
|
||||
<Parameters address="0x1FFF7800" name="OTP" occurence="0x1" size="0x200"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Mirror Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>MirrorOptionBytes</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>Mirror Option Bytes contains the extra area.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 16 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFFC000" name=" 16 Bytes Data MirrorOptionBytes" size="0x10"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="MirrorOptionBytes">
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="MirrorOptionBytes" occurence="0x1" size="0x10"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank interface="JTAG_SWD">
|
||||
<Parameters address="0x40023C14" name="Bank 1" size="0x8"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
<Bank interface="Bootloader">
|
||||
<Parameters address="0x1FFFC000" name="Bank 1" size="0x10"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0xF</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="WRP1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,396 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x433</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M4</CPU>
|
||||
<Name>STM32F401xD/E</Name>
|
||||
<Series>STM32F4</Series>
|
||||
<Description>ARM 32-bit Cortex-M4 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD">
|
||||
<Configuration number="0x0">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
|
||||
</Configuration>
|
||||
<Configuration number="0x1">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x80000000"/> </SPRMode>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader">
|
||||
<Configuration number="0x0">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
|
||||
</Configuration>
|
||||
<Configuration number="0x1">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 96 KB 0x1c000-->
|
||||
<Configuration>
|
||||
<Parameters address="0x20000000" name="SRAM" size="0x10000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x1FFF7A22" default="0x800000"/>
|
||||
<!-- 384KB Single Bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x08000000" name=" 384 Kbytes Embedded Flash" size="0x800000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08020000" name="sector5" occurence="0x3" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- OTP -->
|
||||
<Peripheral>
|
||||
<Name>OTP</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 512 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFF7800" name=" 512 Bytes Data OTP" size="0x200"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="OTP">
|
||||
<Field>
|
||||
<Parameters address="0x1FFF7800" name="OTP" occurence="0x1" size="0x200"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Mirror Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>MirrorOptionBytes</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>Mirror Option Bytes contains the extra area.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 16 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFFC000" name=" 16 Bytes Data MirrorOptionBytes" size="0x10"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="MirrorOptionBytes">
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="MirrorOptionBytes" occurence="0x1" size="0x10"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank interface="JTAG_SWD">
|
||||
<Parameters address="0x40023C14" name="Bank 1" size="0x8"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
<Bank interface="Bootloader">
|
||||
<Parameters address="0x1FFFC000" name="Bank 1" size="0x10"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0xF</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="WRP1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,599 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x434</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M4</CPU>
|
||||
<Name>STM32F469xx/F467xx</Name>
|
||||
<Series>STM32F4</Series>
|
||||
<Description>ARM 32-bit Cortex-M4 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD">
|
||||
<Configuration number="0x0">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
|
||||
<flashSize> <!-- 2M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x800"/> </flashSize>
|
||||
</Configuration>
|
||||
<Configuration number="0x1">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
|
||||
<flashSize> <!-- 2M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x800"/> </flashSize>
|
||||
</Configuration>
|
||||
<Configuration number="0x2">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
|
||||
<flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x400"/> </flashSize>
|
||||
<DB1M reference="0x0"> <ReadRegister address="0x40023C14" mask="0x40000000" value="0x0"/> </DB1M>
|
||||
</Configuration>
|
||||
<Configuration number="0x3">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
|
||||
<flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x400"/> </flashSize>
|
||||
<DB1M reference="0x0"> <ReadRegister address="0x40023C14" mask="0x40000000" value="0x0"/> </DB1M>
|
||||
</Configuration>
|
||||
<Configuration number="0x4">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
|
||||
<flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x400"/> </flashSize>
|
||||
<DB1M reference="0x1"> <ReadRegister address="0x40023C14" mask="0x40000000" value="0x40000000"/> </DB1M>
|
||||
</Configuration>
|
||||
<Configuration number="0x5">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
|
||||
<flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x400"/> </flashSize>
|
||||
<DB1M reference="0x1"> <ReadRegister address="0x40023C14" mask="0x40000000" value="0x40000000"/> </DB1M>
|
||||
</Configuration>
|
||||
<Configuration number="0x6">
|
||||
<dummy> <ReadRegister address="0x20000000" mask="0" value="0"/> </dummy>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader">
|
||||
<Configuration number="0x0">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
|
||||
</Configuration>
|
||||
<Configuration number="0x1">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
|
||||
</Configuration>
|
||||
<Configuration number="0x2">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
|
||||
<DB1M reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x4000" value="0x0"/> </DB1M>
|
||||
</Configuration>
|
||||
<Configuration number="0x3">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
|
||||
<DB1M reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x4000" value="0x0"/> </DB1M>
|
||||
</Configuration>
|
||||
<Configuration number="0x4">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
|
||||
<DB1M reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x4000" value="0x4000"/> </DB1M>
|
||||
</Configuration>
|
||||
<Configuration number="0x5">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
|
||||
<DB1M reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x4000" value="0x4000"/> </DB1M>
|
||||
</Configuration>
|
||||
<Configuration number="0x6">
|
||||
<dummy> <ReadRegister address="0x20000000" mask="0" value="0"/> </dummy>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 320 KB 0x50000-->
|
||||
<Configuration>
|
||||
<Parameters address="0x20000000" name="SRAM" size="0x50000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x50000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x1FFF7A22" default="0x200000"/>
|
||||
<!-- 1024KB Single Bank -->
|
||||
<Configuration config="0,1,6">
|
||||
<Parameters address="0x08000000" name=" 2048 Kbytes Embedded Flash" size="0x200000"/>
|
||||
<Description/>
|
||||
<Organization>Dual</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08020000" name="sector5" occurence="0x7" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
<Bank name="Bank 2">
|
||||
<Field>
|
||||
<Parameters address="0x08100000" name="sector12" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08110000" name="sector16" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08120000" name="sector17" occurence="0x7" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
<Configuration config="4,5">
|
||||
<Parameters address="0x08000000" name=" 1024 Kbytes Embedded Flash" size="0x100000"/>
|
||||
<Description/>
|
||||
<Organization>Dual</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08020000" name="sector5" occurence="0x3" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
<Bank name="Bank 2">
|
||||
<Field>
|
||||
<Parameters address="0x08080000" name="sector8" occurence="0x4" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
<Configuration config="2,3">
|
||||
<Parameters address="0x08000000" name=" 1024 Kbytes Embedded Flash" size="0x100000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08020000" name="sector5" occurence="0x7" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- OTP -->
|
||||
<Peripheral>
|
||||
<Name>OTP</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 512 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFF7800" name=" 512 Bytes Data OTP" size="0x200"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="OTP">
|
||||
<Field>
|
||||
<Parameters address="0x1FFF7800" name="OTP" occurence="0x1" size="0x200"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Mirror Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>MirrorOptionBytes</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>Mirror Option Bytes contains the extra area.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 20 Bytes Dual bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFEC008" name=" 20 Bytes Data MirrorOptionBytes" size="0x14"/>
|
||||
<Description/>
|
||||
<Organization>Dual</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x1FFEC008" name="Bank1" occurence="0x1" size="0x4"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
<Bank name="Bank 2">
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="Bank2" occurence="0x1" size="0x10"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank interface="JTAG_SWD">
|
||||
<Parameters address="0x40023C14" name="Bank 1" size="0x8"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BFB2</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x4</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default)</Val>
|
||||
<Val value="0x1">Dual-bank boot enabled. Boot is always performed from system memory.</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="2,3,4,5">
|
||||
<Name>DB1M</Name>
|
||||
<Description>Dual-bank on 1 Mbyte Flash memory devices</Description>
|
||||
<BitOffset>0x1E</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">1 Mbyte single bank Flash memory (contiguous addresses in bank1)</Val>
|
||||
<Val value="0x1">1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0,2,4">
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1,3,5,6">
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x40023C18" name="FLASH_OPTCR1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0,2,4">
|
||||
<Name>nWRP12</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1,3,5,6">
|
||||
<Name>nWRP12</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
<Bank interface="Bootloader">
|
||||
<Parameters address="0x1FFFC000" name="Bank 1" size="0x10"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0xF</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BFB2</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x4</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default)</Val>
|
||||
<Val value="0x1">Dual-bank boot enabled. Boot is always performed from system memory.</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="2,3,4,5">
|
||||
<Name>DB1M</Name>
|
||||
<Description>Dual-bank on 1 Mbyte Flash memory devices</Description>
|
||||
<BitOffset>0x1E</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">1 Mbyte single bank Flash memory (contiguous addresses in bank1)</Val>
|
||||
<Val value="0x1">1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="WRP0" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0,2,4">
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1,3,5,6">
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
<Bank interface="Bootloader">
|
||||
<Parameters address="0x1FFEC008" name="Bank 2" size="0x4"/>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFEC008" name="WRP1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0,2,4">
|
||||
<Name>nWRP12</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1,3,5,6">
|
||||
<Name>nWRP12</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x440</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M0</CPU>
|
||||
<Name>STM32F05x/F030x8</Name>
|
||||
<Series>STM32F0</Series>
|
||||
<Description>ARM 32-bit Cortex-M0 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD"/>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader"/>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 8 KB -->
|
||||
<Configuration>
|
||||
<Parameters address="0x20000000" name="SRAM" size="0x1FF8"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x1FF8"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x1FFFF7CC" default="0x10000"/>
|
||||
<!-- 64KB single Bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x08000000" name=" 64 Kbytes Embedded Flash" size="0x10000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x40" size="0x400"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank>
|
||||
<Parameters address="0x1FFFF800" name="Bank 1" size="0x10"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF800" name="USR_RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF800" name="USR_RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x11</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x12</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nBOOT1</Name>
|
||||
<Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. </Description>
|
||||
<BitOffset>0x14</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
|
||||
<Val value="0x1">Boot from system memory when BOOT0=1</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>VDDA_MONITOR</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x15</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">VDDA power supply supervisor disabled</Val>
|
||||
<Val value="0x1">VDDA power supply supervisor enabled</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>RAM_PARITY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x16</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">RAM parity check enabled</Val>
|
||||
<Val value="0x1">RAM parity check disabled</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Data</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF804" name="USR_DATA" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>Data0</Name>
|
||||
<Description>User data 0 (8-bit)</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>Data1</Name>
|
||||
<Description>User data 1 (8-bit)</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF808" name="WRP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nWRP8</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,396 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x441</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M4</CPU>
|
||||
<Name>STM32F412</Name>
|
||||
<Series>STM32F4</Series>
|
||||
<Description>ARM 32-bit Cortex-M4 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD">
|
||||
<Configuration number="0x0">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
|
||||
</Configuration>
|
||||
<Configuration number="0x1">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x80000000"/> </SPRMode>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader">
|
||||
<Configuration number="0x0">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
|
||||
</Configuration>
|
||||
<Configuration number="0x1">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 256 KB 0x40000-->
|
||||
<Configuration>
|
||||
<Parameters address="0x20000000" name="SRAM" size="0x40000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x40000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address=" 0x1FFF7A22" default="0x100000"/>
|
||||
<!-- 512KB Single Bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x08000000" name=" 1 Mbytes Embedded Flash" size="0x100000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08020000" name="sector5" occurence="0x7" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- OTP -->
|
||||
<Peripheral>
|
||||
<Name>OTP</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 512 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFF7800" name=" 512 Bytes Data OTP" size="0x200"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="OTP">
|
||||
<Field>
|
||||
<Parameters address="0x1FFF7800" name="OTP" occurence="0x1" size="0x200"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Mirror Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>MirrorOptionBytes</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>Mirror Option Bytes contains the extra area.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 16 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFFC000" name=" 16 Bytes Data MirrorOptionBytes" size="0x10"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="MirrorOptionBytes">
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="MirrorOptionBytes" occurence="0x1" size="0x10"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank interface="JTAG_SWD">
|
||||
<Parameters address="0x40023C14" name="Bank 1" size="0x8"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
<Bank interface="Bootloader">
|
||||
<Parameters address="0x1FFFC000" name="Bank 1" size="0x10"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0xF</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="WRP1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,266 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x442</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M0</CPU>
|
||||
<Name>STM32F09x/F030xC</Name>
|
||||
<Series>STM32F0</Series>
|
||||
<Description>ARM 32-bit Cortex-M0 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD"/>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader"/>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 32 KB -->
|
||||
<Configuration>
|
||||
<Parameters address="0x20000000" name="SRAM" size="0x8000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x8000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x1FFFF7CC" default="0x40000"/>
|
||||
<!-- 256KB single Bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x08000000" name=" 256 Kbytes Embedded Flash" size="0x40000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x800"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank>
|
||||
<Parameters address="0x1FFFF800" name="Bank 1" size="0x10"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF800" name="USR_RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF800" name="USR_RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x11</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x12</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nBOOT0</Name>
|
||||
<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
|
||||
<BitOffset>0x13</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
|
||||
<Val value="0x1">BOOT0 = 0, boot from main flash memory</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nBOOT1</Name>
|
||||
<Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory.</Description>
|
||||
<BitOffset>0x14</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
|
||||
<Val value="0x1">Boot from system memory when BOOT0=1</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>VDDA_MONITOR</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x15</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">VDDA power supply supervisor disabled</Val>
|
||||
<Val value="0x1">VDDA power supply supervisor enabled</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>RAM_PARITY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x16</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">RAM parity check enabled</Val>
|
||||
<Val value="0x1">RAM parity check disabled</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>BOOT_SEL</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x17</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOOT0 signal is defined by nBOOT0 option bit</Val>
|
||||
<Val value="0x1">BOOT0 signal is defined by BOOT0 pin value</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Data</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF804" name="USR_DATA" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>Data0</Name>
|
||||
<Description>User data 0 (8-bit)</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>Data1</Name>
|
||||
<Description>User data 1 (8-bit)</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF808" name="WRP_0_1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nWRP8</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF80C" name="WRP_2_3" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>nWRP16</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nWRP24</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,206 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x444</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M0</CPU>
|
||||
<Name>STM32F03x</Name>
|
||||
<Series>STM32F0</Series>
|
||||
<Description>ARM 32-bit Cortex-M0 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD"/>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader"/>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 4 KB -->
|
||||
<Configuration>
|
||||
<Parameters address="0x20000000" name="SRAM" size="0x1000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x1000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x1FFFF7CC" default="0x8000"/>
|
||||
<!-- 32KB single Bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x08000000" name=" 32 Kbytes Embedded Flash" size="0x8000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x20" size="0x400"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank>
|
||||
<Parameters address="0x1FFFF800" name="Bank 1" size="0x10"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF800" name="USR_RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF800" name="USR_RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x11</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x12</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nBOOT1</Name>
|
||||
<Description>Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. </Description>
|
||||
<BitOffset>0x14</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Boot from embedded SRAM when BOOT0=1</Val>
|
||||
<Val value="0x1">Boot from system flash when BOOT0=1</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>VDDA_MONITOR</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x15</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">VDDA power supply supervisor disabled</Val>
|
||||
<Val value="0x1">VDDA power supply supervisor enabled</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>RAM_PARITY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x16</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">RAM parity check enabled</Val>
|
||||
<Val value="0x1">RAM parity check disabled</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Data</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF804" name="USR_DATA" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>Data0</Name>
|
||||
<Description>User data 0 (8-bit)</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>Data1</Name>
|
||||
<Description>User data 1 (8-bit)</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF808" name="WRP_0_1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,228 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x445</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M0</CPU>
|
||||
<Name>STM32F04x/F070x6</Name>
|
||||
<Series>STM32F0</Series>
|
||||
<Description>ARM 32-bit Cortex-M0 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD"/>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader"/>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 6 KB -->
|
||||
<Configuration>
|
||||
<Parameters address="0x20000000" name="SRAM" size="0x1800"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x1800"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x1FFFF7CC" default="0x8000"/>
|
||||
<!-- 32KB single Bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x08000000" name=" 32 Kbytes Embedded Flash" size="0x8000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x20" size="0x400"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank>
|
||||
<Parameters address="0x1FFFF800" name="Bank 1" size="0x10"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF800" name="USR_RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF800" name="USR_RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x11</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x12</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nBOOT0</Name>
|
||||
<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
|
||||
<BitOffset>0x13</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
|
||||
<Val value="0x1">BOOT0 = 0, boot from main flash memory</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nBOOT1</Name>
|
||||
<Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. </Description>
|
||||
<BitOffset>0x14</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Boot from embedded SRAM when BOOT0=1</Val>
|
||||
<Val value="0x1">Boot from system memory when BOOT0=1</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>VDDA_MONITOR</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x15</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">VDDA power supply supervisor disabled</Val>
|
||||
<Val value="0x1">VDDA power supply supervisor enabled</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>RAM_PARITY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x16</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">RAM parity check enabled</Val>
|
||||
<Val value="0x1">RAM parity check disabled</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>BOOT_SEL</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x17</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOOT0 signal is defined by nBOOT0 option bit</Val>
|
||||
<Val value="0x1">BOOT0 signal is defined by BOOT0 pin value</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Data</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF804" name="USR_DATA" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>Data0</Name>
|
||||
<Description>User data 0 (8-bit)</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>Data1</Name>
|
||||
<Description>User data 1 (8-bit)</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF808" name="WRP_0_1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,244 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x448</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M0</CPU>
|
||||
<Name>STM32F07x</Name>
|
||||
<Series>STM32F0</Series>
|
||||
<Description>ARM 32-bit Cortex-M0 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD"/>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader"/>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 16 KB -->
|
||||
<Configuration>
|
||||
<Parameters address="0x20000000" name="SRAM" size="0x4000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x4000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x1FFFF7CC" default="0x20000"/>
|
||||
<!-- 128KB single Bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x08000000" name=" 128 Kbytes Embedded Flash" size="0x20000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x40" size="0x800"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank>
|
||||
<Parameters address="0x1FFFF800" name="Bank 1" size="0x10"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF800" name="USR_RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF800" name="USR_RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x11</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x12</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nBOOT1</Name>
|
||||
<Description>Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. </Description>
|
||||
<BitOffset>0x14</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Boot from embedded SRAM when BOOT0=1</Val>
|
||||
<Val value="0x1">Boot from system flash when BOOT0=1</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>VDDA_MONITOR</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x15</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">VDDA power supply supervisor disabled</Val>
|
||||
<Val value="0x1">VDDA power supply supervisor enabled</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>RAM_PARITY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x16</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">RAM parity check enabled</Val>
|
||||
<Val value="0x1">RAM parity check disabled</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Data</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF804" name="USR_DATA" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>Data0</Name>
|
||||
<Description>User data 0 (8-bit)</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>Data1</Name>
|
||||
<Description>User data 1 (8-bit)</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF808" name="WRP_0_1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nWRP8</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFF80C" name="WRP_2_3" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>nWRP16</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nWRP24</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,529 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x449</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M7</CPU>
|
||||
<Name>STM32F74x/STM32F75x</Name>
|
||||
<Series>STM32F7</Series>
|
||||
<Description>ARM 32-bit Cortex-M7 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD">
|
||||
<Configuration number="0x0"> <!-- ROM Die -->
|
||||
<RomLess>
|
||||
<ReadRegister address="0x1FF0F442" mask="0x40" value="0x00"/>
|
||||
</RomLess>
|
||||
</Configuration>
|
||||
<Configuration number="0x0"> <!-- ROM Die -->
|
||||
<RomLess>
|
||||
<ReadRegister address="0x1FF0F442" mask="0xFFFFFFFF" value="0xFFFFFFFF"/>
|
||||
</RomLess>
|
||||
</Configuration>
|
||||
<Configuration number="0x1"> <!-- RomLess Die -->
|
||||
<RomLess>
|
||||
<ReadRegister address="0x1FF0F442" mask="0x40" value="0x40"/>
|
||||
</RomLess>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader">
|
||||
<Configuration number="0x0"> <!-- ROM Die -->
|
||||
<RomLess>
|
||||
<ReadRegister address="0x0x08000000" mask="0x00" value="0x00"/>
|
||||
</RomLess>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 320 KB -->
|
||||
<Configuration>
|
||||
<Parameters address="0x20000000" name="SRAM" size="0x50000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x20000000" name="SRAM1" occurence="0x1" size="0x50000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x1FF0F442" default="0x100000"/>
|
||||
<DBGMCU_CR address="0xE0042004" mask="0x007"/>
|
||||
<DBGMCU_APB1_FZ address="0xE0042008" mask="0x1800"/>
|
||||
<!-- 1MB single Bank -->
|
||||
<Configuration config="0">
|
||||
<Parameters address="0x08000000" name=" 1 Mbytes Embedded Flash" size="0x100000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x10</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x8000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08020000" name="sector4" occurence="0x1" size="0x20000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08040000" name="sector5" occurence="0x3" size="0x40000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
<Configuration config="1">
|
||||
<Parameters address="0x08000000" name=" 64 KByte Embedded Flash" size="0x10000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x10</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x2" size="0x8000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- ITCM Flash-->
|
||||
<Peripheral>
|
||||
<Name>ITCM Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 1MB single Bank -->
|
||||
<Configuration config="0">
|
||||
<Parameters address="0x00200000" name=" 1 Mbytes Embedded Flash" size="0x100000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x10</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x00200000" name="sector0" occurence="0x4" size="0x8000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x00220000" name="sector4" occurence="0x1" size="0x20000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x00240000" name="sector5" occurence="0x3" size="0x40000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
<Configuration config="1">
|
||||
<Parameters address="0x00200000" name=" 64 KByte Embedded Flash" size="0x10000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x10</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x00200000" name="sector0" occurence="0x2" size="0x8000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- OTP -->
|
||||
<Peripheral>
|
||||
<Name>OTP</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 1 KBytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FF0F000" name=" 1 KBytes Data OTP" size="0x200"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="OTP">
|
||||
<Field>
|
||||
<Parameters address="0x1FF0F000" name="OTP" occurence="0x1" size="0x200"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Mirror Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>MirrorOptionBytes</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>Mirror Option Bytes contains the extra area.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 44 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFF0000" name=" 44 Bytes Data MirrorOptionBytes" size="0x2C"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="MirrorOptionBytes">
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0000" name="MirrorOptionBytes" occurence="0x1" size="0x2C"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank interface="JTAG_SWD">
|
||||
<Parameters address="0x40023C14" name="Bank 1" size="0x8"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
|
||||
<Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
|
||||
<Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
|
||||
<Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>IWDG_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Freeze IWDG counter in stop mode</Val>
|
||||
<Val value="0x1">IWDG counter active in stop mode</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>IWDG_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1E</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Freeze IWDG counter in standby mode</Val>
|
||||
<Val value="0x1">IWDG counter active in standby mode</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>WWDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x4</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware window watchdog</Val>
|
||||
<Val value="0x1">Software window watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>IWDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware independant watchdog</Val>
|
||||
<Val value="0x1">Software independant watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Boot address Option Bytes</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C18" name="FLASH_OPTCR1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOOT_ADD0</Name>
|
||||
<Description>Define the boot address when BOOT0=0</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x10</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Equation multiplier="0x4000" offset="0x0"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>BOOT_ADD1</Name>
|
||||
<Description>Define the boot address when BOOT0=1</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x10</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Equation multiplier="0x4000" offset="0x0"/>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
<Bank interface="Bootloader">
|
||||
<Parameters address="0x1FFF0000" name="Bank 1" size="0x2C"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
|
||||
<Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
|
||||
<Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
|
||||
<Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0008" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>IWDG_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0xF</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Freeze IWDG counter in stop mode</Val>
|
||||
<Val value="0x1">IWDG counter active in stop mode</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>IWDG_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0xE</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Freeze IWDG counter in standby mode</Val>
|
||||
<Val value="0x1">IWDG counter active in standby mode</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WWDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x4</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware window watchdog</Val>
|
||||
<Val value="0x1">Software window watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>IWDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware independant watchdog</Val>
|
||||
<Val value="0x1">Software independant watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Boot address Option Bytes</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0010" name="FLASH_OPTCR1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOOT_ADD0</Name>
|
||||
<Description>Define the boot address when BOOT0=0</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x10</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Equation multiplier="0x4000" offset="0x0"/>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0018" name="FLASH_OPTCR1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOOT_ADD1</Name>
|
||||
<Description>Define the boot address when BOOT0=1</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x10</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Equation multiplier="0x4000" offset="0x0"/>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0008" name="FLASH_OPTCR1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,605 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x452</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M7</CPU>
|
||||
<Name>STM32F72x/STM32F73x</Name>
|
||||
<Series>STM32F7</Series>
|
||||
<Description>ARM 32-bit Cortex-M7 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD">
|
||||
<Configuration number="0x0"> <!-- ROM Die -->
|
||||
<RomLess>
|
||||
<ReadRegister address="0x1FF07A22" mask="0x40" value="0x00"/>
|
||||
</RomLess>
|
||||
</Configuration>
|
||||
<Configuration number="0x1"> <!-- RomLess Die -->
|
||||
<RomLess>
|
||||
<ReadRegister address="0x1FF07A22" mask="0x40" value="0x40"/>
|
||||
</RomLess>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader">
|
||||
<Configuration number="0x0"> <!-- ROM Die -->
|
||||
<RomLess>
|
||||
<ReadRegister address="0x0x08000000" mask="0x00" value="0x00"/>
|
||||
</RomLess>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 512 KB -->
|
||||
<Configuration>
|
||||
<Parameters address="0x20000000" name="SRAM" size="0x40000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x40000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x1FF07A22" default="0x80000"/>
|
||||
<!-- 512KB single Bank -->
|
||||
<Configuration config="0">
|
||||
<Parameters address="0x08000000" name=" 512 Kbytes Embedded Flash" size="0x80000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x10</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08020000" name="sector5" occurence="0x3" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
<!-- 64KB RomLess -->
|
||||
<Configuration config="1">
|
||||
<Parameters address="0x08000000" name=" 64 Kbytes Embedded Flash" size="0x10000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x10</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- ITCM Bytes -->
|
||||
<Peripheral>
|
||||
<Name>ITCM Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 512KB single Bank -->
|
||||
<Configuration config="0">
|
||||
<Parameters address="0x00200000" name=" 512 Kbytes ITCM Flash" size="0x80000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x10</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x00200000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x00210000" name="sector4" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x00220000" name="sector5" occurence="0x3" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
<!-- 64KB RomLess -->
|
||||
<Configuration config="1">
|
||||
<Parameters address="0x00200000" name=" 64 Kbytes ITCM Flash" size="0x10000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x10</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x00200000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- OTP -->
|
||||
<Peripheral>
|
||||
<Name>OTP</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 512 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FF07800" name=" 512 Bytes Data OTP" size="0x200"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="OTP">
|
||||
<Field>
|
||||
<Parameters address="0x1FF07800" name="OTP" occurence="0x1" size="0x200"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Mirror Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>MirrorOptionBytes</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>Mirror Option Bytes contains the extra area.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 44 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFF0000" name=" 44 Bytes Data MirrorOptionBytes" size="0x2C"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="MirrorOptionBytes">
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0000" name="MirrorOptionBytes" occurence="0x1" size="0x2C"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank interface="JTAG_SWD">
|
||||
<Parameters address="0x40023C14" name="Bank 1" size="0xC"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
|
||||
<Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
|
||||
<Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
|
||||
<Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>IWDG_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Freeze IWDG counter in stop mode</Val>
|
||||
<Val value="0x1">IWDG counter active in stop mode</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>IWDG_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1E</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Freeze IWDG counter in standby mode</Val>
|
||||
<Val value="0x1">IWDG counter active in standby mode</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>WWDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x4</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware window watchdog</Val>
|
||||
<Val value="0x1">Software window watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>IWDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware independant watchdog</Val>
|
||||
<Val value="0x1">Software independant watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x40023C1C" name="FLASH_OPTCR2" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>PCROP_RDP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
|
||||
<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Boot address Option Bytes</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C18" name="FLASH_OPTCR1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOOT_ADD0</Name>
|
||||
<Description>Define the boot address when BOOT0=0</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x10</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Equation multiplier="0x4000" offset="0x0"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>BOOT_ADD1</Name>
|
||||
<Description>Define the boot address when BOOT0=1</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x10</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Equation multiplier="0x4000" offset="0x0"/>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x4</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Read/Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C1C" name="FLASH_OPTCR2" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>PCROP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on this sector</Val>
|
||||
<Val value="0x1">PCROP protection active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>PCROP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x4</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on this sector</Val>
|
||||
<Val value="0x1">PCROP protection active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
<Bank interface="Bootloader">
|
||||
<Parameters address="0x1FFF0000" name="Bank 1" size="0x2C"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
|
||||
<Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
|
||||
<Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
|
||||
<Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0008" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>IWDG_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0xF</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Freeze IWDG counter in stop mode</Val>
|
||||
<Val value="0x1">IWDG counter active in stop mode</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>IWDG_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0xE</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Freeze IWDG counter in standby mode</Val>
|
||||
<Val value="0x1">IWDG counter active in standby mode</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WWDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x4</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware window watchdog</Val>
|
||||
<Val value="0x1">Software window watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>IWDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware independant watchdog</Val>
|
||||
<Val value="0x1">Software independant watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0028" name="FLASH_OPTCR2" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>PCROP_RDP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0xF</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
|
||||
<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Boot address Option Bytes</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0010" name="FLASH_OPTCR1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOOT_ADD0</Name>
|
||||
<Description>Define the boot address when BOOT0=0</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x10</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Equation multiplier="0x4000" offset="0x0"/>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0018" name="FLASH_OPTCR1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOOT_ADD1</Name>
|
||||
<Description>Define the boot address when BOOT0=1</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x10</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Equation multiplier="0x4000" offset="0x0"/>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0008" name="FLASH_OPTCR1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active on this sector</Val>
|
||||
<Val value="0x1">Write protection not active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Read/Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFF0020" name="FLASH_OPTCR2" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>PCROP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on this sector</Val>
|
||||
<Val value="0x1">PCROP protection active on this sector</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,393 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x458</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M4</CPU>
|
||||
<Name>STM32F410</Name>
|
||||
<Series>STM32F4</Series>
|
||||
<Description>ARM 32-bit Cortex-M4 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD">
|
||||
<Configuration number="0x0">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
|
||||
</Configuration>
|
||||
<Configuration number="0x1">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x80000000"/> </SPRMode>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader">
|
||||
<Configuration number="0x0">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
|
||||
</Configuration>
|
||||
<Configuration number="0x1">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 32 KB 0x8000-->
|
||||
<Configuration>
|
||||
<Parameters address="0x20000000" name="SRAM" size="0x8000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x8000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x1FFF7A22" default="0x20000"/>
|
||||
<!-- 128K Single Bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x08000000" name=" 128 Kbytes Embedded Flash" size="0x20000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- OTP -->
|
||||
<Peripheral>
|
||||
<Name>OTP</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 512 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFF7800" name=" 512 Bytes Data OTP" size="0x200"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="OTP">
|
||||
<Field>
|
||||
<Parameters address="0x1FFF7800" name="OTP" occurence="0x1" size="0x200"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Mirror Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>MirrorOptionBytes</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>Mirror Option Bytes contains the extra area.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 16 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFFC000" name=" 16 Bytes Data MirrorOptionBytes" size="0x10"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="MirrorOptionBytes">
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="MirrorOptionBytes" occurence="0x1" size="0x10"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank interface="JTAG_SWD">
|
||||
<Parameters address="0x40023C14" name="Bank 1" size="0x8"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x5</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x5</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
<Bank interface="Bootloader">
|
||||
<Parameters address="0x1FFFC000" name="Bank 1" size="0x10"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0xF</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="WRP1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x5</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x5</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,396 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x463</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M4</CPU>
|
||||
<Name>STM32F413/F423</Name>
|
||||
<Series>STM32F4</Series>
|
||||
<Description>ARM 32-bit Cortex-M4 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD">
|
||||
<Configuration number="0x0">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
|
||||
</Configuration>
|
||||
<Configuration number="0x1">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x80000000"/> </SPRMode>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader">
|
||||
<Configuration number="0x0">
|
||||
<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
|
||||
</Configuration>
|
||||
<Configuration number="0x1">
|
||||
<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 320 KB 0x50000-->
|
||||
<Configuration>
|
||||
<Parameters address="0x20000000" name="SRAM" size="0x50000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x50000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x1FFF7A22" default="0x180000"/>
|
||||
<!-- 512KB Single Bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x08000000" name=" 1.5 Mbytes Embedded Flash" size="0x180000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x08020000" name="sector5" occurence="0xB" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- OTP -->
|
||||
<Peripheral>
|
||||
<Name>OTP</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 512 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFF7800" name=" 512 Bytes Data OTP" size="0x200"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="OTP">
|
||||
<Field>
|
||||
<Parameters address="0x1FFF7800" name="OTP" occurence="0x1" size="0x200"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Mirror Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>MirrorOptionBytes</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>Mirror Option Bytes contains the extra area.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 16 Bytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x1FFFC000" name=" 16 Bytes Data MirrorOptionBytes" size="0x10"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x4</Allignement>
|
||||
<Bank name="MirrorOptionBytes">
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="MirrorOptionBytes" occurence="0x1" size="0x10"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank interface="JTAG_SWD">
|
||||
<Parameters address="0x40023C14" name="Bank 1" size="0x8"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xF</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xF</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
<Bank interface="Bootloader">
|
||||
<Parameters address="0x1FFFC000" name="Bank 1" size="0x10"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="RDP" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="FLASH_OPTCR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit reference="SPRMode">
|
||||
<Name>SPRMOD</Name>
|
||||
<Description>Selection of protection mode for nWPRi bits.</Description>
|
||||
<BitOffset>0xF</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
|
||||
<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
|
||||
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
|
||||
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
|
||||
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>WDG_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x5</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Hardware watchdog</Val>
|
||||
<Val value="0x1">Software watchdog</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>nRST_STDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
||||
<Val value="0x1">No reset generated</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x1FFFC008" name="WRP1" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xF</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="1">
|
||||
<Name>WRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xF</BitWidth>
|
||||
<Access>RW</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">PCROP protection not active on sector i</Val>
|
||||
<Val value="0x1">PCROP protection active on sector i</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,847 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x480</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M7</CPU>
|
||||
<Name>STM32H7A/B</Name>
|
||||
<Series>STM32H7</Series>
|
||||
<Description>ARM 32-bit Cortex-M7 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD">
|
||||
<Configuration number="0xA">
|
||||
<SecurityEx>
|
||||
<WriteRegister address="0x580244F4" value="0x2"/>
|
||||
<ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
|
||||
<ReadRegister address="0x08fff80c" mask="0x00000FFF" value="0x400"/>
|
||||
</SecurityEx>
|
||||
</Configuration>
|
||||
<Configuration number="0xB">
|
||||
<SecurityEx>
|
||||
<WriteRegister address="0x580244F4" value="0x2"/>
|
||||
<ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
|
||||
<ReadRegister address="0x08fff80c" mask="0x00000FFF" value="0x400"/>
|
||||
</SecurityEx>
|
||||
</Configuration>
|
||||
<Configuration number="0x0"> <!-- Security extension available -->
|
||||
<SecurityEx>
|
||||
<WriteRegister address="0x580244F4" value="0x2"/>
|
||||
<ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
|
||||
</SecurityEx>
|
||||
</Configuration>
|
||||
<Configuration number="0x1"> <!-- Security extension not available -->
|
||||
<SecurityEx>
|
||||
<WriteRegister address="0x580244F4" value="0x2"/>
|
||||
<ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
|
||||
</SecurityEx>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader">
|
||||
<Configuration number="0x0"> <!-- dummy always true, security extension is checked using dedicated cmd -->
|
||||
<Dummy>
|
||||
<ReadRegister address="0x08000000" mask="0x0" value="0x0"/>
|
||||
</Dummy>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 1024 KB -->
|
||||
<Configuration>
|
||||
<Parameters address="0x24000000" name="SRAM" size="0x100000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x24000000" name="SRAM" occurence="0x1" size="0x100000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x08fff80c" default="0x200000"/>
|
||||
<BootloaderVersion address="0x1FF13FFE"/>
|
||||
<!-- 2MB Dual Bank -->
|
||||
<Configuration config="0,1">
|
||||
<Parameters address="0x08000000" name="2 MBytes Dual Bank Embedded Flash" size="0x200000"/>
|
||||
<Description/>
|
||||
<Organization>Dual</Organization>
|
||||
<Allignement>0x20</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
<Bank name="Bank 2">
|
||||
<Field>
|
||||
<Parameters address="0x08100000" name="sector128" occurence="0x80" size="0x2000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
<!-- 1MB Dual Bank -->
|
||||
<Configuration config="10,11">
|
||||
<Parameters address="0x08000000" name="1 MBytes Dual Bank Embedded Flash" size="0x200000"/>
|
||||
<Description/>
|
||||
<Organization>Dual</Organization>
|
||||
<Allignement>0x20</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
<Bank name="Bank 2">
|
||||
<Field>
|
||||
<Parameters address="0x08080000" name="sector64" occurence="0x80" size="0x2000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- OTP -->
|
||||
<Peripheral>
|
||||
<Name>OTP</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RW</Access>
|
||||
<!-- 1 KBytes single bank -->
|
||||
<Configuration>
|
||||
<Parameters address="0x08FFF000" name=" 1 KBytes Data OTP" size="0x400"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x20</Allignement>
|
||||
<Bank name="OTP">
|
||||
<Field>
|
||||
<Parameters address="0x08FFF000" name="OTP" occurence="0x1" size="0x400"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank>
|
||||
<Parameters address="0x5200201C" name="Bank 1" size="0x134"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">reset level OFF</Val>
|
||||
<Val value="0x1">reset level is set to 2.1 V</Val>
|
||||
<Val value="0x2">reset level is set to 2.4 V</Val>
|
||||
<Val value="0x3">reset level is set to 2.7 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">reset level OFF</Val>
|
||||
<Val value="0x1">reset level is set to 2.1 V</Val>
|
||||
<Val value="0x2">reset level is set to 2.4 V</Val>
|
||||
<Val value="0x3">reset level is set to 2.7 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>IWDG1_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x4</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Independent watchdog is controlled by hardware</Val>
|
||||
<Val value="0x1">Independent watchdog is controlled by software</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>NRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
|
||||
<Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>NRST_STBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
|
||||
<Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>VDDMMC_HSLV</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">I/O speed optimization at low-voltage disabled</Val>
|
||||
<Val value="0x1">VDDMMC power rail operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>IWDG_FZ_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x11</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
|
||||
<Val value="0x1">Independent watchdog is running in STOP mode</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>IWDG_FZ_SDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x12</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
|
||||
<Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="0,10">
|
||||
<Name>SECURITY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x15</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Security feature disabled</Val>
|
||||
<Val value="0x1">Security feature enabled</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>VDDIO_HSLV</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1D</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Product working in the full voltage range,I/O speed optimization at low-voltage disabled</Val>
|
||||
<Val value="0x1">VDD I/O below 2.5 V,I/O speed optimization at low-voltage feature allowed</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>SWAP_BANK_OPT</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">after boot loading, no swap for user sectors</Val>
|
||||
<Val value="0x1">after boot loading, user sectors swapped</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>IWDG1_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x4</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Independent watchdog is controlled by hardware</Val>
|
||||
<Val value="0x1">Independent watchdog is controlled by software</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>NRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
|
||||
<Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>NRST_STBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
|
||||
<Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>VDDMMC_HSLV</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">I/O speed optimization at low-voltage disabled</Val>
|
||||
<Val value="0x1">VDDMMC power rail operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>IWDG_FZ_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x11</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
|
||||
<Val value="0x1">Independent watchdog is running in STOP mode</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>IWDG_FZ_SDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x12</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
|
||||
<Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="0,10">
|
||||
<Name>SECURITY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x15</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Security feature disabled</Val>
|
||||
<Val value="0x1">Security feature enabled</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>VDDIO_HSLV</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1D</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Product working in the full voltage range,I/O speed optimization at low-voltage disabled</Val>
|
||||
<Val value="0x1">VDD I/O below 2.5 V,I/O speed optimization at low-voltage feature allowed</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>SWAP_BANK_OPT</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">after boot loading, no swap for user sectors</Val>
|
||||
<Val value="0x1">after boot loading, user sectors swapped</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Boot address Option Bytes</Name>
|
||||
<Field>
|
||||
<Parameters address="0x52002040" name="FBOOT7_CUR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOOT_CM7_ADD0</Name>
|
||||
<Description>Define the boot address for Cortex-M7 when BOOT0=0</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x10</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Equation multiplier="0x10000" offset="0x0"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>BOOT_CM7_ADD1</Name>
|
||||
<Description>Define the boot address for Cortex-M7 when BOOT0=1</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x10</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Equation multiplier="0x10000" offset="0x0"/>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002044" name="FBOOT7_PRG" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOOT_CM7_ADD0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x10</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Equation multiplier="0x10000" offset="0x0"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>BOOT_CM7_ADD1</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x10</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Equation multiplier="0x10000" offset="0x0"/>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x52002028" name="FPRAR_CUR_A" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>PROT_AREA_START1</Name>
|
||||
<Description>Flash Bank 1 PCROP start address</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Equation multiplier="0x100" offset="0x08000000"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>PROT_AREA_END1</Name>
|
||||
<Description>Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address.</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Equation multiplier="0x100" offset="0x080000FF"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>DMEP1</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
<Val value="0x1">Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x5200202C" name="FPRAR_PRG_A" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>PROT_AREA_START1</Name>
|
||||
<Description>Flash Bank 1 PCROP start address</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Equation multiplier="0x100" offset="0x08000000"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>PROT_AREA_END1</Name>
|
||||
<Description>Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Equation multiplier="0x100" offset="0x080000FF"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>DMEP1</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
<Val value="0x1">Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002128" name="FPRAR_CUR_B" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>PROT_AREA_START2</Name>
|
||||
<Description>Flash Bank 2 PCROP start address</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Equation multiplier="0x100" offset="0x08100000"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>PROT_AREA_END2</Name>
|
||||
<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Equation multiplier="0x100" offset="0x081000FF"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>DMEP2</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
<Val value="0x1">Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x5200212C" name="FPRAR_PRG_B" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>PROT_AREA_START2</Name>
|
||||
<Description>Flash Bank 2 PCROP start address</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Equation multiplier="0x100" offset="0x08100000"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>PROT_AREA_END2</Name>
|
||||
<Description>Flash Bank 2 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Equation multiplier="0x100" offset="0x081000FF"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>DMEP2</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
<Val value="0x1">Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Secure Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x52002030" name="FSCAR_CUR_A" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0,10">
|
||||
<Name>SEC_AREA_START1</Name>
|
||||
<Description>Flash Bank 1 secure area start address</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Equation multiplier="0x100" offset="0x08000000"/>
|
||||
</Bit>
|
||||
<Bit config="0,10">
|
||||
<Name>SEC_AREA_END1</Name>
|
||||
<Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Equation multiplier="0x100" offset="0x080000FF"/>
|
||||
</Bit>
|
||||
<Bit config="0,10">
|
||||
<Name>DMES1</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
<Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002034" name="FSCAR_PRG_A" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0,10">
|
||||
<Name>SEC_AREA_START1</Name>
|
||||
<Description>Flash Bank 1 secure area start address</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Equation multiplier="0x100" offset="0x08000000"/>
|
||||
</Bit>
|
||||
<Bit config="0,10">
|
||||
<Name>SEC_AREA_END1</Name>
|
||||
<Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Equation multiplier="0x100" offset="0x080000FF"/>
|
||||
</Bit>
|
||||
<Bit config="0,10">
|
||||
<Name>DMES1</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
<Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002130" name="FSCAR_CUR_B" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0,10">
|
||||
<Name>SEC_AREA_START2</Name>
|
||||
<Description>Flash Bank 2 secure area start address</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Equation multiplier="0x100" offset="0x08100000"/>
|
||||
</Bit>
|
||||
<Bit config="0,10">
|
||||
<Name>SEC_AREA_END2</Name>
|
||||
<Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Equation multiplier="0x100" offset="0x081000FF"/>
|
||||
</Bit>
|
||||
<Bit config="0,10">
|
||||
<Name>DMES2</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
<Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002134" name="FSCAR_PRG_B" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0,10">
|
||||
<Name>SEC_AREA_START2</Name>
|
||||
<Description>Flash Bank 2 secure area start address</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Equation multiplier="0x100" offset="0x08100000"/>
|
||||
</Bit>
|
||||
<Bit config="0,10">
|
||||
<Name>SEC_AREA_END2</Name>
|
||||
<Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Equation multiplier="0x100" offset="0x081000FF"/>
|
||||
</Bit>
|
||||
<Bit config="0,10">
|
||||
<Name>DMES2</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
<Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>DTCM RAM Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>ST_RAM_SIZE</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x13</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">2 KB</Val>
|
||||
<Val value="0x1">4 KB</Val>
|
||||
<Val value="0x2">8 KB</Val>
|
||||
<Val value="0x3">16 KB</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>ST_RAM_SIZE</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x13</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">2 KB</Val>
|
||||
<Val value="0x1">4 KB</Val>
|
||||
<Val value="0x2">8 KB</Val>
|
||||
<Val value="0x3">16 KB</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x52002038" name="FWPSN_CUR_A" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x20</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x5200203C" name="FWPSN_PRG_A" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x20</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002138" name="FWPSN_CUR_B" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>nWRP32</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x20</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x5200213C" name="FWPSN_PRG_B" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>nWRP32</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x20</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,656 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
|
||||
<Device>
|
||||
<DeviceID>0x483</DeviceID>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<Type>MCU</Type>
|
||||
<CPU>Cortex-M7</CPU>
|
||||
<Name>STM32H72x/STM32H73x</Name>
|
||||
<Series>STM32H7</Series>
|
||||
<Description>ARM 32-bit Cortex-M7 based device</Description>
|
||||
<Configurations>
|
||||
<!-- JTAG_SWD Interface -->
|
||||
<Interface name="JTAG_SWD">
|
||||
<Configuration number="0x0"> <!-- Security extension available -->
|
||||
<SecurityEx>
|
||||
<WriteRegister address="0x580244F4" value="0x2"/>
|
||||
<ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
|
||||
</SecurityEx>
|
||||
</Configuration>
|
||||
<Configuration number="0x1"> <!-- Security extension not available -->
|
||||
<SecurityEx>
|
||||
<WriteRegister address="0x580244F4" value="0x2"/>
|
||||
<ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
|
||||
</SecurityEx>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
<!-- Bootloader Interface -->
|
||||
<Interface name="Bootloader">
|
||||
<Configuration number="0x0"> <!-- dummy always true, security extension is checked using dedicated cmd -->
|
||||
<Dummy>
|
||||
<ReadRegister address="0x08000000" mask="0x0" value="0x0"/>
|
||||
</Dummy>
|
||||
</Configuration>
|
||||
</Interface>
|
||||
</Configurations>
|
||||
<!-- Peripherals -->
|
||||
<Peripherals>
|
||||
<!-- Embedded SRAM -->
|
||||
<Peripheral>
|
||||
<Name>Embedded SRAM</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description/>
|
||||
<ErasedValue>0x00</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<!-- 1024 KB -->
|
||||
<Configuration>
|
||||
<Parameters address="0x24000000" name="SRAM" size="0x20000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x24000000" name="SRAM" occurence="0x1" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Embedded Flash -->
|
||||
<Peripheral>
|
||||
<Name>Embedded Flash</Name>
|
||||
<Type>Storage</Type>
|
||||
<Description>The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
|
||||
<ErasedValue>0xFF</ErasedValue>
|
||||
<Access>RWE</Access>
|
||||
<FlashSize address="0x1FF1E880" default="0x100000"/>
|
||||
<BootloaderVersion address="0x1FF1E7FE"/>
|
||||
<!-- 1MB Single Bank -->
|
||||
<Configuration config="0,1">
|
||||
<Parameters address="0x08000000" name="1 MBytes Single Bank Embedded Flash" size="0x100000"/>
|
||||
<Description/>
|
||||
<Organization>Single</Organization>
|
||||
<Allignement>0x20</Allignement>
|
||||
<Bank name="Bank 1">
|
||||
<Field>
|
||||
<Parameters address="0x08000000" name="sector0" occurence="0x8" size="0x20000"/>
|
||||
</Field>
|
||||
</Bank>
|
||||
</Configuration>
|
||||
</Peripheral>
|
||||
<!-- Option Bytes -->
|
||||
<Peripheral>
|
||||
<Name>Option Bytes</Name>
|
||||
<Type>Configuration</Type>
|
||||
<Description/>
|
||||
<Access>RW</Access>
|
||||
<Bank>
|
||||
<Parameters address="0x5200201C" name="Bank 1" size="0x5C"/>
|
||||
<Category>
|
||||
<Name>Read Out Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>RDP</Name>
|
||||
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
||||
<BitOffset>0x8</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0xAA">Level 0, no protection</Val>
|
||||
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
||||
<Val value="0xCC">Level 2, chip protection</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>BOR Level</Name>
|
||||
<Field>
|
||||
<Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">BOR OFF</Val>
|
||||
<Val value="0x1">BOR level1: 2.1V</Val>
|
||||
<Val value="0x2">BOR level2: 2.4 V</Val>
|
||||
<Val value="0x3">BOR level3: 2.7 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOR_LEV</Name>
|
||||
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">reset level is set to 0.0 V</Val>
|
||||
<Val value="0x1">reset level is set to 2.1 V</Val>
|
||||
<Val value="0x2">reset level is set to 2.4 V</Val>
|
||||
<Val value="0x3">reset level is set to 2.7 V</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>User Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>IWDG1_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x4</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Independent watchdog is controlled by hardware</Val>
|
||||
<Val value="0x1">Independent watchdog is controlled by software</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>NRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
|
||||
<Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>NRST_STBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
|
||||
<Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>IO_HSLV</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1D</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
|
||||
<Val value="0x1">Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>FZ_IWDG_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x11</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
|
||||
<Val value="0x1">Independent watchdog is running in STOP mode</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>FZ_IWDG_SDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x12</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
|
||||
<Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="0">
|
||||
<Name>SECURITY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x15</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Security feature disabled</Val>
|
||||
<Val value="0x1">Security feature enabled</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>IWDG1_SW</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x4</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Independent watchdog is controlled by hardware</Val>
|
||||
<Val value="0x1">Independent watchdog is controlled by software</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>NRST_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x6</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
|
||||
<Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>NRST_STBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x7</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
|
||||
<Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>IO_HSLV</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1D</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
|
||||
<Val value="0x1">Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>FZ_IWDG_STOP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x11</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
|
||||
<Val value="0x1">Independent watchdog is running in STOP mode</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>FZ_IWDG_SDBY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x12</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
|
||||
<Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="0">
|
||||
<Name>SECURITY</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x15</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Security feature disabled</Val>
|
||||
<Val value="0x1">Security feature enabled</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit config="0,1">
|
||||
<Name>SWAP_BANK_OPT</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">after boot loading, no swap for user sectors</Val>
|
||||
<Val value="0x1">after boot loading, user sectors swapped</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Boot address Option Bytes</Name>
|
||||
<Field>
|
||||
<Parameters address="0x52002040" name="FBOOT7_CUR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOOT_CM7_ADD0</Name>
|
||||
<Description>Define the boot address for Cortex-M7 when BOOT0=0</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x10</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Equation multiplier="0x10000" offset="0x0"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>BOOT_CM7_ADD1</Name>
|
||||
<Description>Define the boot address for Cortex-M7 when BOOT0=1</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x10</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Equation multiplier="0x10000" offset="0x0"/>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002044" name="FBOOT7_PRG" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>BOOT_CM7_ADD0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x10</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Equation multiplier="0x10000" offset="0x0"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>BOOT_CM7_ADD1</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0x10</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Equation multiplier="0x10000" offset="0x0"/>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>PCROP Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x52002028" name="FPRAR_CUR_A" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>PROT_AREA_START</Name>
|
||||
<Description>Flash Bank PCROP start address</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Equation multiplier="0x100" offset="0x08000000"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>PROT_AREA_END</Name>
|
||||
<Description>Flash Bank PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP bit and changing RDP from level 1 to level 0 while putting end address greater than start address.</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Equation multiplier="0x100" offset="0x080000FF"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>DMEP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Flash Bank PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
<Val value="0x1">Flash Bank PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x5200202C" name="FPRAR_PRG_A" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>PROT_AREA_START</Name>
|
||||
<Description>Flash Bank PCROP start address</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Equation multiplier="0x100" offset="0x08000000"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>PROT_AREA_END</Name>
|
||||
<Description>Flash Bank PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Equation multiplier="0x100" offset="0x080000FF"/>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>DMEP</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Flash Bank PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
<Val value="0x1">Flash Bank PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Secure Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>ST_RAM_SIZE</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x13</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">2 KB reserved to ST code</Val>
|
||||
<Val value="0x1">4 KB reserved to ST code</Val>
|
||||
<Val value="0x2">8 KB reserved to ST code</Val>
|
||||
<Val value="0x3">16 KB reserved to ST code</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>ST_RAM_SIZE</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x13</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">2 KB reserved to ST code</Val>
|
||||
<Val value="0x1">4 KB reserved to ST code</Val>
|
||||
<Val value="0x2">8 KB reserved to ST code</Val>
|
||||
<Val value="0x3">16 KB reserved to ST code</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002030" name="FLASH_SCAR_CUR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>SEC_AREA_START</Name>
|
||||
<Description>Flash secure area start address</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Equation multiplier="0x100" offset="0x08000000"/>
|
||||
</Bit>
|
||||
<Bit config="0">
|
||||
<Name>SEC_AREA_END</Name>
|
||||
<Description>Flash secure area end address. If this address is equal to SEC_AREA_START, the whole flash memory is secure protected.If this address is lower than SEC_AREA_START, no protection is set on flash memory.</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Equation multiplier="0x100" offset="0x080000FF"/>
|
||||
</Bit>
|
||||
<Bit config="0">
|
||||
<Name>DMES</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Flash secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
<Val value="0x1">Flash secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002034" name="FLASH_SCAR_PRG" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0">
|
||||
<Name>SEC_AREA_START</Name>
|
||||
<Description>Flash secure area start address</Description>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Equation multiplier="0x100" offset="0x08000000"/>
|
||||
</Bit>
|
||||
<Bit config="0">
|
||||
<Name>SEC_AREA_END</Name>
|
||||
<Description>Flash secure area end address. If this address is equal to SEC_AREA_START, the whole flash memory is secure protected.If this address is lower than SEC_AREA_START, no protection is set on flash memory.</Description>
|
||||
<BitOffset>0x10</BitOffset>
|
||||
<BitWidth>0xC</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Equation multiplier="0x100" offset="0x080000FF"/>
|
||||
</Bit>
|
||||
<Bit config="0">
|
||||
<Name>DMES</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x1F</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Flash secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
<Val value="0x1">Flash secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>Write Protection</Name>
|
||||
<Field>
|
||||
<Parameters address="0x52002038" name="FWPSN_CUR_A" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0,1">
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x5200203C" name="FWPSN_PRG_A" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit config="0,1">
|
||||
<Name>nWRP0</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x8</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values ByBit="true">
|
||||
<Val value="0x0">Write protection active</Val>
|
||||
<Val value="0x1">Write protection not active</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
<Category>
|
||||
<Name>TCM_AXI Shared Configuration</Name>
|
||||
<Field>
|
||||
<Parameters address="0x52002070" name="FLASH_OPTSR2_CUR" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>TCM_AXI_SHARED</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">64 KB ITCM : 320KB system AXI</Val>
|
||||
<Val value="0x1">128KB ITCM : 256KB system AXI</Val>
|
||||
<Val value="0x2">192KB ITCM : 192KB system AXI</Val>
|
||||
<Val value="0x3">256KB ITCM : 128KB system AXI</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>CPU_FREQ_BOOST</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>R</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Feature disabled</Val>
|
||||
<Val value="0x1">CPU can operate at a boosted Fmax frequency (no more ECC on I/DTCM)</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
<Field>
|
||||
<Parameters address="0x52002074" name="FLASH_OPTSR2_PRG" size="0x4"/>
|
||||
<AssignedBits>
|
||||
<Bit>
|
||||
<Name>TCM_AXI_SHARED</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x0</BitOffset>
|
||||
<BitWidth>0x2</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">64KB ITCM : 320KB system AXI</Val>
|
||||
<Val value="0x1">128KB ITCM : 256KB system AXI</Val>
|
||||
<Val value="0x2">192KB ITCM : 192KB system AXI</Val>
|
||||
<Val value="0x3">256KB ITCM : 128KB system AXI</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
<Bit>
|
||||
<Name>CPU_FREQ_BOOST</Name>
|
||||
<Description/>
|
||||
<BitOffset>0x2</BitOffset>
|
||||
<BitWidth>0x1</BitWidth>
|
||||
<Access>W</Access>
|
||||
<Values>
|
||||
<Val value="0x0">Feature disabled</Val>
|
||||
<Val value="0x1">CPU can operate at a boosted Fmax frequency (no more ECC on I/DTCM)</Val>
|
||||
</Values>
|
||||
</Bit>
|
||||
</AssignedBits>
|
||||
</Field>
|
||||
</Category>
|
||||
</Bank>
|
||||
</Peripheral>
|
||||
</Peripherals>
|
||||
</Device>
|
||||
</Root>
|
||||
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Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue