mirror of https://github.com/rusefi/rusefi-1.git
merge mcuconf for f4/f7 (#2375)
* merge for f4/f7 * more * include efifeatures * s * no TS serial on f7 for now Co-authored-by: Matthew Kennedy <makenne@microsoft.com>
This commit is contained in:
Matthew Kennedy
GitHub
parent
e984b479e2
commit
90ef4c93ad
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@ -48,7 +48,6 @@
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//#define TS_UART_DEVICE (&UARTD3)
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#undef TS_SERIAL_DEVICE
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#define TS_SERIAL_DEVICE (&SD3)
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#define AUX_SERIAL_DEVICE (&SD6)
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@ -0,0 +1,313 @@
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/**
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* @file mcuconf_common_f4_f7.cpp
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* @brief Common MCU definitions for both the STM32F4 and STM32F7
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*
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* @date Feb 18, 2021
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* @author Matthew Kennedy
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*/
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#pragma once
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#include "efifeatures.h"
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/**
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* This is about SingleTimerExecutor - rusEfi 12MHz precise scheduling timer
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* this is not about ChibiOS virtual timer which rusEfi uses for
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* periodicFastCallback and periodicSlowCallback
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* See STM32_ST_IRQ_PRIORITY
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*
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* http://www.chibios.org/dokuwiki/doku.php?id=chibios:kb:priority
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*/
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#define PRECISE_SCHEDULING_TIMER_PRIORITY 4
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/**
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* Input Capture Unit is how we capture shaft position sensors output
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*/
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#define ICU_PRIORITY 3
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/**
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* UART DMA-mode byte capture (low latency)
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*/
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#define UART_DMA_IRQ_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
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/*
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* SysTick driver system settings.
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*/
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#define STM32_ST_IRQ_PRIORITY 8
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#define STM32_ST_USE_TIMER 2
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
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#ifndef STM32_ADC_USE_ADC1
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#define STM32_ADC_USE_ADC1 TRUE
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#endif /* STM32_ADC_USE_ADC1 */
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#ifndef STM32_ADC_USE_ADC2
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#define STM32_ADC_USE_ADC2 TRUE
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#endif /* STM32_ADC_USE_ADC2 */
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#ifndef STM32_ADC_USE_ADC3
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#define STM32_ADC_USE_ADC3 FALSE
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#endif /* STM32_ADC_USE_ADC3 */
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
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#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_ADC2_DMA_PRIORITY 2
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#define STM32_ADC_ADC3_DMA_PRIORITY 2
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#define STM32_ADC_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 2
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 2
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#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 2
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#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 2
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/*
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* CAN driver system settings.
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*/
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#define STM32_CAN_USE_CAN1 TRUE
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#define STM32_CAN_USE_CAN2 TRUE
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#define STM32_CAN_USE_CAN3 FALSE
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#define STM32_CAN_CAN1_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 7
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#define STM32_CAN_CAN2_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 7
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#define STM32_CAN_CAN3_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 7
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/*
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* DAC driver system settings.
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*/
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#define STM32_DAC_DUAL_MODE FALSE
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#define STM32_DAC_USE_DAC1_CH1 FALSE
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#define STM32_DAC_USE_DAC1_CH2 FALSE
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 6
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 6
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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/*
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* EXT driver system settings.
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*/
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#define STM32_IRQ_EXTI_PRIORITY ICU_PRIORITY
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#define STM32_IRQ_EXTI0_PRIORITY STM32_IRQ_EXTI_PRIORITY
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#define STM32_IRQ_EXTI1_PRIORITY STM32_IRQ_EXTI_PRIORITY
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#define STM32_IRQ_EXTI2_PRIORITY STM32_IRQ_EXTI_PRIORITY
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#define STM32_IRQ_EXTI3_PRIORITY STM32_IRQ_EXTI_PRIORITY
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#define STM32_IRQ_EXTI4_PRIORITY STM32_IRQ_EXTI_PRIORITY
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#define STM32_IRQ_EXTI5_9_PRIORITY STM32_IRQ_EXTI_PRIORITY
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#define STM32_IRQ_EXTI10_15_PRIORITY STM32_IRQ_EXTI_PRIORITY
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#define STM32_IRQ_EXTI16_PRIORITY STM32_IRQ_EXTI_PRIORITY
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#define STM32_IRQ_EXTI17_PRIORITY 15 /* why? */
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#define STM32_IRQ_EXTI18_PRIORITY STM32_IRQ_EXTI_PRIORITY
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#define STM32_IRQ_EXTI19_PRIORITY STM32_IRQ_EXTI_PRIORITY
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#define STM32_IRQ_EXTI20_PRIORITY STM32_IRQ_EXTI_PRIORITY
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#define STM32_IRQ_EXTI21_PRIORITY 15 /* why? */
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#define STM32_IRQ_EXTI22_PRIORITY 15 /* why? */
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#define STM32_IRQ_EXTI23_PRIORITY STM32_IRQ_EXTI_PRIORITY
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/*
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* GPT driver system settings.
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*/
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#define STM32_GPT_USE_TIM1 FALSE
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#define STM32_GPT_USE_TIM2 FALSE
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#define STM32_GPT_USE_TIM3 FALSE
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#define STM32_GPT_USE_TIM4 FALSE
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#define STM32_GPT_USE_TIM5 FALSE
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#define STM32_GPT_USE_TIM6 TRUE
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#define STM32_GPT_USE_TIM7 FALSE
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#define STM32_GPT_USE_TIM8 FALSE
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#define STM32_GPT_USE_TIM9 FALSE
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#define STM32_GPT_USE_TIM11 FALSE
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#define STM32_GPT_USE_TIM12 FALSE
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#define STM32_GPT_USE_TIM14 FALSE
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/*
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* I2C driver system settings.
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*/
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#define STM32_I2C_USE_I2C1 FALSE
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#define STM32_I2C_USE_I2C2 FALSE
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#define STM32_I2C_USE_I2C3 FALSE
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#define STM32_I2C_USE_I2C4 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_I2C_I2C1_IRQ_PRIORITY 5
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#define STM32_I2C_I2C2_IRQ_PRIORITY 5
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#define STM32_I2C_I2C3_IRQ_PRIORITY 5
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#define STM32_I2C_I2C4_IRQ_PRIORITY 5
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#define STM32_I2C_I2C1_DMA_PRIORITY 3
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#define STM32_I2C_I2C2_DMA_PRIORITY 3
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#define STM32_I2C_I2C3_DMA_PRIORITY 3
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#define STM32_I2C_I2C4_DMA_PRIORITY 3
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM1 TRUE
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#define STM32_ICU_USE_TIM2 TRUE
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#define STM32_ICU_USE_TIM3 TRUE
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#define STM32_ICU_USE_TIM4 FALSE
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#define STM32_ICU_USE_TIM5 FALSE
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#define STM32_ICU_USE_TIM8 FALSE
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#define STM32_ICU_USE_TIM9 FALSE
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#define STM32_ICU_TIM1_IRQ_PRIORITY ICU_PRIORITY
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#define STM32_ICU_TIM2_IRQ_PRIORITY ICU_PRIORITY
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#define STM32_ICU_TIM3_IRQ_PRIORITY ICU_PRIORITY
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#define STM32_ICU_TIM4_IRQ_PRIORITY ICU_PRIORITY
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#define STM32_ICU_TIM5_IRQ_PRIORITY ICU_PRIORITY
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#define STM32_ICU_TIM8_IRQ_PRIORITY ICU_PRIORITY
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#define STM32_ICU_TIM9_IRQ_PRIORITY ICU_PRIORITY
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/*
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* MAC driver system settings.
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*/
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#define STM32_MAC_TRANSMIT_BUFFERS 2
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#define STM32_MAC_RECEIVE_BUFFERS 4
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#define STM32_MAC_BUFFERS_SIZE 1522
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#define STM32_MAC_PHY_TIMEOUT 100
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#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
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#define STM32_MAC_ETH1_IRQ_PRIORITY 13
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#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
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/*
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* PWM driver system settings.
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*/
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#define STM32_PWM_USE_ADVANCED FALSE
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#define STM32_PWM_USE_TIM1 FALSE
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#define STM32_PWM_USE_TIM2 FALSE
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#define STM32_PWM_USE_TIM3 FALSE
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#define STM32_PWM_USE_TIM4 TRUE
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#define STM32_PWM_USE_TIM5 TRUE
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#define STM32_PWM_USE_TIM8 TRUE
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#define STM32_PWM_USE_TIM9 FALSE
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#define STM32_PWM_TIM1_IRQ_PRIORITY 7
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#define STM32_PWM_TIM2_IRQ_PRIORITY 7
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#define STM32_PWM_TIM3_IRQ_PRIORITY 7
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#define STM32_PWM_TIM4_IRQ_PRIORITY 7
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#define STM32_PWM_TIM5_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY
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#define STM32_PWM_TIM8_IRQ_PRIORITY 7
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#define STM32_PWM_TIM9_IRQ_PRIORITY 7
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/*
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* SERIAL driver system settings.
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*/
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#define STM32_SERIAL_USE_USART1 TRUE
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#define STM32_SERIAL_USE_USART2 TRUE
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#define STM32_SERIAL_USE_USART3 FALSE
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#define STM32_SERIAL_USE_UART4 FALSE
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#define STM32_SERIAL_USE_UART5 FALSE
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#define STM32_SERIAL_USE_USART6 TRUE
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#define STM32_SERIAL_USE_UART7 FALSE
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#define STM32_SERIAL_USE_UART8 FALSE
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#define STM32_IRQ_USART1_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
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#define STM32_IRQ_USART2_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
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#define STM32_IRQ_USART3_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
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#define STM32_IRQ_UART4_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
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#define STM32_IRQ_UART5_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
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#define STM32_IRQ_USART6_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
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#define STM32_IRQ_UART7_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
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#define STM32_IRQ_UART8_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
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/*
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* SPI driver system settings.
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*/
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#define STM32_SPI_USE_SPI1 TRUE
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#define STM32_SPI_USE_SPI2 TRUE
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#define STM32_SPI_USE_SPI3 TRUE
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#define STM32_SPI_USE_SPI4 FALSE
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#define STM32_SPI_USE_SPI5 FALSE
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#define STM32_SPI_USE_SPI6 FALSE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
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#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
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#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
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#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
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#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI3_DMA_PRIORITY 1
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#define STM32_SPI_SPI4_DMA_PRIORITY 1
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#define STM32_SPI_SPI5_DMA_PRIORITY 1
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#define STM32_SPI_SPI6_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
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#define STM32_SPI_SPI2_IRQ_PRIORITY 10
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#define STM32_SPI_SPI3_IRQ_PRIORITY 10
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#define STM32_SPI_SPI4_IRQ_PRIORITY 10
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#define STM32_SPI_SPI5_IRQ_PRIORITY 10
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#define STM32_SPI_SPI6_IRQ_PRIORITY 10
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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* UART driver system settings.
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*/
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART3 TRUE
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#define STM32_UART_USE_UART4 FALSE
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#define STM32_UART_USE_UART5 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USE_UART7 FALSE
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#define STM32_UART_USE_UART8 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_UART_USART1_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
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#define STM32_UART_USART2_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
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#define STM32_UART_USART3_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
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#define STM32_UART_UART4_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
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#define STM32_UART_UART5_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
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#define STM32_UART_USART6_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_UART4_DMA_PRIORITY 0
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#define STM32_UART_UART5_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_UART7_DMA_PRIORITY 0
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#define STM32_UART_UART8_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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/*
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* USB driver system settings.
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*/
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#define STM32_USB_USE_OTG1 TRUE
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#define STM32_USB_USE_OTG2 FALSE
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#define STM32_USB_OTG1_IRQ_PRIORITY 14
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#define STM32_USB_OTG2_IRQ_PRIORITY 14
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#define STM32_USB_OTG1_RX_FIFO_SIZE 512
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#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
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#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
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#define STM32_USB_OTG_THREAD_STACK_SIZE 1024
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#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
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/*
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* WDG driver system settings.
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*/
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#define STM32_WDG_USE_IWDG FALSE
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@ -17,33 +17,6 @@
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#ifndef _MCUCONF_H_
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#define _MCUCONF_H_
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#include "efifeatures.h"
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/**
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* This is about SingleTimerExecutor - rusEfi 1MHz precise scheduling timer
|
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* this is not about ChibiOS virtual timer which rusEfi uses for
|
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* periodicFastCallback and periodicSlowCallback
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* See STM32_ST_IRQ_PRIORITY
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*
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* http://www.chibios.org/dokuwiki/doku.php?id=chibios:kb:priority
|
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*/
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#define PRECISE_SCHEDULING_TIMER_PRIORITY 4
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/**
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* Input Capture Unit is how we capture shaft position sensors output
|
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*/
|
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#define ICU_PRIORITY 3
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/**
|
||||
* UART DMA-mode byte capture (low latency)
|
||||
*/
|
||||
#define UART_DMA_IRQ_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
|
||||
|
||||
/*
|
||||
* SysTick driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY 8
|
||||
#define STM32_ST_USE_TIMER 2
|
||||
|
||||
/*
|
||||
* STM32F4xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
|
|
@ -108,89 +81,9 @@
|
|||
#define STM32_PLS STM32_PLS_LEV0
|
||||
#define STM32_BKPRAM_ENABLE FALSE
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
|
||||
|
||||
#ifndef STM32_ADC_USE_ADC1
|
||||
#define STM32_ADC_USE_ADC1 TRUE
|
||||
#endif /* STM32_ADC_USE_ADC1 */
|
||||
|
||||
#ifndef STM32_ADC_USE_ADC2
|
||||
#define STM32_ADC_USE_ADC2 TRUE
|
||||
#endif /* STM32_ADC_USE_ADC2 */
|
||||
|
||||
#ifndef STM32_ADC_USE_ADC3
|
||||
#define STM32_ADC_USE_ADC3 FALSE
|
||||
#endif /* STM32_ADC_USE_ADC3 */
|
||||
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
|
||||
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY 2
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY 2
|
||||
#define STM32_ADC_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 2
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 2
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 2
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 2
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 TRUE
|
||||
#define STM32_CAN_USE_CAN2 TRUE
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 7
|
||||
#define STM32_CAN_CAN2_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 7
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE FALSE
|
||||
#define STM32_DAC_USE_DAC1_CH1 FALSE
|
||||
#define STM32_DAC_USE_DAC1_CH2 FALSE
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 6
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 6
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
|
||||
/*
|
||||
* EXT driver system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI_PRIORITY ICU_PRIORITY
|
||||
#define STM32_IRQ_EXTI0_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI1_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI2_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI3_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI4_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI16_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI17_PRIORITY 15 /* why? */
|
||||
#define STM32_IRQ_EXTI18_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI19_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI20_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI21_PRIORITY 15 /* why? */
|
||||
#define STM32_IRQ_EXTI22_PRIORITY 15 /* why? */
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 FALSE
|
||||
#define STM32_GPT_USE_TIM2 FALSE
|
||||
#define STM32_GPT_USE_TIM3 FALSE
|
||||
#define STM32_GPT_USE_TIM4 FALSE
|
||||
#define STM32_GPT_USE_TIM5 FALSE
|
||||
#define STM32_GPT_USE_TIM6 TRUE
|
||||
#define STM32_GPT_USE_TIM7 FALSE
|
||||
#define STM32_GPT_USE_TIM8 FALSE
|
||||
#define STM32_GPT_USE_TIM9 FALSE
|
||||
#define STM32_GPT_USE_TIM11 FALSE
|
||||
#define STM32_GPT_USE_TIM12 FALSE
|
||||
#define STM32_GPT_USE_TIM14 FALSE
|
||||
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
|
||||
|
|
@ -204,90 +97,6 @@
|
|||
#define STM32_GPT_TIM12_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM14_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 TRUE
|
||||
#define STM32_I2C_USE_I2C2 FALSE
|
||||
#define STM32_I2C_USE_I2C3 FALSE
|
||||
#define STM32_I2C_BUSY_TIMEOUT 50
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 3
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 3
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY 3
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* I2S driver system settings.
|
||||
*/
|
||||
#define STM32_I2S_USE_SPI2 FALSE
|
||||
#define STM32_I2S_USE_SPI3 FALSE
|
||||
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
|
||||
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
|
||||
#define STM32_I2S_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_I2S_SPI3_DMA_PRIORITY 1
|
||||
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 TRUE
|
||||
#define STM32_ICU_USE_TIM2 TRUE
|
||||
#define STM32_ICU_USE_TIM3 TRUE
|
||||
#define STM32_ICU_USE_TIM4 FALSE
|
||||
#define STM32_ICU_USE_TIM5 FALSE
|
||||
#define STM32_ICU_USE_TIM8 FALSE
|
||||
#define STM32_ICU_USE_TIM9 FALSE
|
||||
#define STM32_ICU_TIM1_IRQ_PRIORITY ICU_PRIORITY
|
||||
#define STM32_ICU_TIM2_IRQ_PRIORITY ICU_PRIORITY
|
||||
#define STM32_ICU_TIM3_IRQ_PRIORITY ICU_PRIORITY
|
||||
#define STM32_ICU_TIM4_IRQ_PRIORITY ICU_PRIORITY
|
||||
#define STM32_ICU_TIM5_IRQ_PRIORITY ICU_PRIORITY
|
||||
#define STM32_ICU_TIM8_IRQ_PRIORITY ICU_PRIORITY
|
||||
#define STM32_ICU_TIM9_IRQ_PRIORITY ICU_PRIORITY
|
||||
|
||||
/*
|
||||
* MAC driver system settings.
|
||||
*/
|
||||
#define STM32_MAC_TRANSMIT_BUFFERS 2
|
||||
#define STM32_MAC_RECEIVE_BUFFERS 4
|
||||
#define STM32_MAC_BUFFERS_SIZE 1522
|
||||
#define STM32_MAC_PHY_TIMEOUT 100
|
||||
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
|
||||
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
|
||||
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED FALSE
|
||||
#define STM32_PWM_USE_TIM1 FALSE
|
||||
#define STM32_PWM_USE_TIM2 FALSE
|
||||
#define STM32_PWM_USE_TIM3 FALSE
|
||||
#define STM32_PWM_USE_TIM4 TRUE
|
||||
#define STM32_PWM_USE_TIM5 TRUE
|
||||
#define STM32_PWM_USE_TIM8 TRUE
|
||||
#define STM32_PWM_USE_TIM9 FALSE
|
||||
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM5_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY
|
||||
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
*/
|
||||
|
|
@ -299,97 +108,6 @@
|
|||
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
|
||||
#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 TRUE
|
||||
#define STM32_SERIAL_USE_USART2 TRUE
|
||||
#define STM32_SERIAL_USE_USART3 FALSE
|
||||
#define STM32_SERIAL_USE_UART4 FALSE
|
||||
#define STM32_SERIAL_USE_UART5 FALSE
|
||||
#define STM32_SERIAL_USE_USART6 TRUE
|
||||
/**
|
||||
* UART priority should not be too low so that we do not miss bytes
|
||||
*/
|
||||
#define STM32_SERIAL_USART1_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
|
||||
#define STM32_SERIAL_USART2_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
|
||||
#define STM32_SERIAL_USART3_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
|
||||
#define STM32_SERIAL_UART4_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
|
||||
#define STM32_SERIAL_UART5_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
|
||||
#define STM32_SERIAL_USART6_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 TRUE
|
||||
#define STM32_SPI_USE_SPI2 TRUE
|
||||
#define STM32_SPI_USE_SPI3 TRUE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("STM32_SPI_DMA_ERROR_HOOK")
|
||||
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 FALSE
|
||||
#define STM32_UART_USE_USART2 FALSE
|
||||
#define STM32_UART_USE_USART3 TRUE
|
||||
#define STM32_UART_USE_UART4 FALSE
|
||||
#define STM32_UART_USE_UART5 FALSE
|
||||
#define STM32_UART_USE_USART6 FALSE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
|
||||
#define STM32_UART_USART3_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
|
||||
#define STM32_UART_UART4_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
|
||||
#define STM32_UART_UART5_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
|
||||
#define STM32_UART_USART6_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("STM32_UART_DMA_ERROR_HOOK")
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 TRUE
|
||||
#define STM32_USB_USE_OTG2 FALSE
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY 14
|
||||
#define STM32_USB_OTG2_IRQ_PRIORITY 14
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
|
||||
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
|
||||
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
|
||||
#define STM32_USB_OTG_THREAD_STACK_SIZE 1024
|
||||
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG FALSE
|
||||
#include "mcuconf_common_f4_f7.h"
|
||||
|
||||
#endif /* _MCUCONF_H_ */
|
||||
|
|
|
|||
|
|
@ -43,31 +43,6 @@
|
|||
|
||||
#include "efifeatures.h"
|
||||
|
||||
/**
|
||||
* This is about SingleTimerExecutor - rusEfi 1MHz precise scheduling timer
|
||||
* this is not about ChibiOS virtual timer which rusEfi uses for
|
||||
* periodicFastCallback and periodicSlowCallback
|
||||
* See STM32_ST_IRQ_PRIORITY
|
||||
*
|
||||
* http://www.chibios.org/dokuwiki/doku.php?id=chibios:kb:priority
|
||||
*/
|
||||
#define PRECISE_SCHEDULING_TIMER_PRIORITY 4
|
||||
/**
|
||||
* Input Capture Unit is how we capture shaft position sensors output
|
||||
*/
|
||||
#define ICU_PRIORITY 3
|
||||
|
||||
/**
|
||||
* UART DMA-mode byte capture (low latency)
|
||||
*/
|
||||
#define UART_DMA_IRQ_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
|
||||
|
||||
/*
|
||||
* SysTick driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY 8
|
||||
#define STM32_ST_USE_TIMER 2
|
||||
|
||||
/*
|
||||
* STM32F7xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
|
|
@ -148,92 +123,9 @@
|
|||
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
|
||||
#define STM32_SRAM2_NOCACHE TRUE
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
|
||||
#ifndef STM32_ADC_USE_ADC1
|
||||
#define STM32_ADC_USE_ADC1 TRUE
|
||||
#endif /* STM32_ADC_USE_ADC1 */
|
||||
|
||||
#ifndef STM32_ADC_USE_ADC2
|
||||
#define STM32_ADC_USE_ADC2 TRUE
|
||||
#endif /* STM32_ADC_USE_ADC2 */
|
||||
|
||||
#ifndef STM32_ADC_USE_ADC3
|
||||
#define STM32_ADC_USE_ADC3 FALSE
|
||||
#endif /* STM32_ADC_USE_ADC3 */
|
||||
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
|
||||
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY 2
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY 2
|
||||
#define STM32_ADC_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 2
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 2
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 2
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 2
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 TRUE
|
||||
#define STM32_CAN_USE_CAN2 TRUE
|
||||
#define STM32_CAN_USE_CAN3 FALSE
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 7
|
||||
#define STM32_CAN_CAN2_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 7
|
||||
#define STM32_CAN_CAN3_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 7
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE FALSE
|
||||
#define STM32_DAC_USE_DAC1_CH1 FALSE
|
||||
#define STM32_DAC_USE_DAC1_CH2 FALSE
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 6
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY + 6
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
|
||||
/*
|
||||
* EXT driver system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI_PRIORITY ICU_PRIORITY
|
||||
#define STM32_IRQ_EXTI0_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI1_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI2_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI3_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI4_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI16_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI17_PRIORITY 15 /* why? */
|
||||
#define STM32_IRQ_EXTI18_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI19_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI20_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
#define STM32_IRQ_EXTI21_PRIORITY 15 /* why? */
|
||||
#define STM32_IRQ_EXTI22_PRIORITY 15 /* why? */
|
||||
#define STM32_IRQ_EXTI23_PRIORITY STM32_IRQ_EXTI_PRIORITY
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 FALSE
|
||||
#define STM32_GPT_USE_TIM2 FALSE
|
||||
#define STM32_GPT_USE_TIM3 FALSE
|
||||
#define STM32_GPT_USE_TIM4 FALSE
|
||||
#define STM32_GPT_USE_TIM5 FALSE
|
||||
#define STM32_GPT_USE_TIM6 TRUE
|
||||
#define STM32_GPT_USE_TIM7 FALSE
|
||||
#define STM32_GPT_USE_TIM8 FALSE
|
||||
#define STM32_GPT_USE_TIM9 FALSE
|
||||
#define STM32_GPT_USE_TIM11 FALSE
|
||||
#define STM32_GPT_USE_TIM12 FALSE
|
||||
#define STM32_GPT_USE_TIM14 FALSE
|
||||
|
||||
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
|
||||
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
|
||||
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
|
||||
|
|
@ -248,79 +140,6 @@
|
|||
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
|
||||
#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
|
||||
#define STM32_IRQ_TIM8_CC_PRIORITY 7
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 TRUE
|
||||
#define STM32_I2C_USE_I2C2 FALSE
|
||||
#define STM32_I2C_USE_I2C3 FALSE
|
||||
#define STM32_I2C_USE_I2C4 FALSE
|
||||
#define STM32_I2C_BUSY_TIMEOUT 50
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C4_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 3
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 3
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY 3
|
||||
#define STM32_I2C_I2C4_DMA_PRIORITY 3
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 TRUE
|
||||
#define STM32_ICU_USE_TIM2 TRUE
|
||||
#define STM32_ICU_USE_TIM3 TRUE
|
||||
#define STM32_ICU_USE_TIM4 FALSE
|
||||
#define STM32_ICU_USE_TIM5 FALSE
|
||||
#define STM32_ICU_USE_TIM8 FALSE
|
||||
#define STM32_ICU_USE_TIM9 FALSE
|
||||
#define STM32_ICU_TIM1_IRQ_PRIORITY ICU_PRIORITY
|
||||
#define STM32_ICU_TIM2_IRQ_PRIORITY ICU_PRIORITY
|
||||
#define STM32_ICU_TIM3_IRQ_PRIORITY ICU_PRIORITY
|
||||
#define STM32_ICU_TIM4_IRQ_PRIORITY ICU_PRIORITY
|
||||
#define STM32_ICU_TIM5_IRQ_PRIORITY ICU_PRIORITY
|
||||
#define STM32_ICU_TIM8_IRQ_PRIORITY ICU_PRIORITY
|
||||
#define STM32_ICU_TIM9_IRQ_PRIORITY ICU_PRIORITY
|
||||
|
||||
/*
|
||||
* MAC driver system settings.
|
||||
*/
|
||||
#define STM32_MAC_TRANSMIT_BUFFERS 2
|
||||
#define STM32_MAC_RECEIVE_BUFFERS 4
|
||||
#define STM32_MAC_BUFFERS_SIZE 1522
|
||||
#define STM32_MAC_PHY_TIMEOUT 100
|
||||
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
|
||||
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
|
||||
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED FALSE
|
||||
#define STM32_PWM_USE_TIM1 FALSE
|
||||
#define STM32_PWM_USE_TIM2 FALSE
|
||||
#define STM32_PWM_USE_TIM3 FALSE
|
||||
#define STM32_PWM_USE_TIM4 TRUE
|
||||
#define STM32_PWM_USE_TIM5 TRUE
|
||||
#define STM32_PWM_USE_TIM8 TRUE
|
||||
#define STM32_PWM_USE_TIM9 FALSE
|
||||
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM5_IRQ_PRIORITY PRECISE_SCHEDULING_TIMER_PRIORITY
|
||||
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
|
|
@ -334,121 +153,6 @@
|
|||
#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
|
||||
#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 TRUE
|
||||
#define STM32_SERIAL_USE_USART2 TRUE
|
||||
#define STM32_SERIAL_USE_USART3 TRUE
|
||||
#define STM32_SERIAL_USE_UART4 FALSE
|
||||
#define STM32_SERIAL_USE_UART5 FALSE
|
||||
#define STM32_SERIAL_USE_USART6 TRUE
|
||||
#define STM32_SERIAL_USE_UART7 FALSE
|
||||
#define STM32_SERIAL_USE_UART8 FALSE
|
||||
#define STM32_IRQ_USART1_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
|
||||
#define STM32_IRQ_USART2_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
|
||||
#define STM32_IRQ_USART3_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
|
||||
#define STM32_IRQ_UART4_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
|
||||
#define STM32_IRQ_UART5_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
|
||||
#define STM32_IRQ_USART6_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
|
||||
#define STM32_IRQ_UART7_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
|
||||
#define STM32_IRQ_UART8_PRIORITY (PRECISE_SCHEDULING_TIMER_PRIORITY + 2)
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 TRUE
|
||||
#define STM32_SPI_USE_SPI2 TRUE
|
||||
#define STM32_SPI_USE_SPI3 TRUE
|
||||
#define STM32_SPI_USE_SPI4 FALSE
|
||||
#define STM32_SPI_USE_SPI5 FALSE
|
||||
#define STM32_SPI_USE_SPI6 FALSE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
|
||||
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
||||
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
|
||||
#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
|
||||
#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI4_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI5_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI6_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 FALSE
|
||||
#define STM32_UART_USE_USART2 FALSE
|
||||
#define STM32_UART_USE_USART3 TRUE
|
||||
#define STM32_UART_USE_UART4 FALSE
|
||||
#define STM32_UART_USE_UART5 FALSE
|
||||
#define STM32_UART_USE_USART6 FALSE
|
||||
#define STM32_UART_USE_UART7 FALSE
|
||||
#define STM32_UART_USE_UART8 FALSE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
|
||||
#define STM32_UART_USART3_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
|
||||
#define STM32_UART_UART4_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
|
||||
#define STM32_UART_UART5_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
|
||||
#define STM32_UART_USART6_IRQ_PRIORITY UART_DMA_IRQ_PRIORITY
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||
#define STM32_UART_UART7_DMA_PRIORITY 0
|
||||
#define STM32_UART_UART8_DMA_PRIORITY 0
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 TRUE
|
||||
#define STM32_USB_USE_OTG2 FALSE
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY 14
|
||||
#define STM32_USB_OTG2_IRQ_PRIORITY 14
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
|
||||
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
|
||||
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
|
||||
#define STM32_USB_OTG_THREAD_STACK_SIZE 1024
|
||||
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG FALSE
|
||||
#include "mcuconf_common_f4_f7.h"
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue