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Merge remote-tracking branch 'jared/master' into jared_master

This commit is contained in:
rusefi 2020-02-12 08:04:55 -05:00
parent 5665e43954 3a9be312c4
commit a8ab218888
6 changed files with 6320 additions and 4060 deletions
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7573
hardware/176122-6-connector/176122-6.kicad_pcb
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1198
hardware/176122-6-connector/176122-6.net
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327
hardware/176122-6-connector/176122-6.pro
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@ -1,4 +1,4 @@
update=2/5/2017 2:22:23 PM
update=2/11/2020 12:10:49 PM
version=1
last_client=kicad
[cvpcb]
@ -16,64 +16,281 @@ version=1
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=../rusefi_lib/KICAD_Older_Version
LibName2=power
LibName3=device
LibName4=transistors
LibName5=conn
LibName6=linear
LibName7=regul
LibName8=74xx
LibName9=cmos4000
LibName10=adc-dac
LibName11=memory
LibName12=xilinx
LibName13=microcontrollers
LibName14=dsp
LibName15=microchip
LibName16=analog_switches
LibName17=motorola
LibName18=texas
LibName19=intel
LibName20=audio
LibName21=interface
LibName22=digital-audio
LibName23=philips
LibName24=display
LibName25=cypress
LibName26=siliconi
LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves
LibName31=symbols/0176122-06
[pcbnew]
version=1
PageLayoutDescrFile=C:/Users/Vista_64_D630/Desktop/Jared/code/Hardware/trunk/rusefi.com/rusefi_lib/Border.kicad_wks
LastNetListRead=
PadDrill=1.016
PadDrillOvalY=1.016
PadSizeH=1.4224
PadSizeV=1.4224
PcbTextSizeV=2.032
PcbTextSizeH=1.524
PcbTextThickness=0.3048
ModuleTextSizeV=1.524
ModuleTextSizeH=1.524
ModuleTextSizeThickness=0.3048
SolderMaskClearance=0.254
SolderMaskMinWidth=0
DrawSegmentWidth=0.381
BoardOutlineThickness=0.381
ModuleOutlineThickness=0.381
[schematic_editor]
version=1
PageLayoutDescrFile=C:/Users/Vista_64_D630/Desktop/Jared/code/Hardware/trunk/rusefi.com/rusefi_lib/Border.kicad_wks
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=60
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=C:/Users/Vista_64_D630/Desktop/Jared/code/Hardware/trunk/rusefi.com/rusefi_lib/Border.kicad_wks
LastNetListRead=176122-6.net
CopperLayerCount=2
BoardThickness=1.6002
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2032
MinViaDiameter=0.889
MinViaDrill=0.508
MinMicroViaDiameter=0.508
MinMicroViaDrill=0.127
MinHoleToHole=0.25
TrackWidth1=0.2032
ViaDiameter1=0.889
ViaDrill1=0.635
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.381
SilkTextSizeV=1.524
SilkTextSizeH=1.524
SilkTextSizeThickness=0.3048
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.381
CopperTextSizeV=2.032
CopperTextSizeH=1.524
CopperTextThickness=0.3048
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.381
CourtyardLineWidth=0.05
OthersLineWidth=0.381
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.07619999999999999
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=0
[pcbnew/Layer.B.CrtYd]
Enabled=0
[pcbnew/Layer.F.CrtYd]
Enabled=0
[pcbnew/Layer.B.Fab]
Enabled=0
[pcbnew/Layer.F.Fab]
Enabled=0
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.254
TrackWidth=0.2032
ViaDiameter=0.889
ViaDrill=0.635
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=1.5A
Clearance=0.254
TrackWidth=0.508
ViaDiameter=0.889
ViaDrill=0.635
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=10A
Clearance=0.254
TrackWidth=6.096
ViaDiameter=0.889
ViaDrill=0.635
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/3]
Name=1A
Clearance=0.254
TrackWidth=0.254
ViaDiameter=0.889
ViaDrill=0.635
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/4]
Name=3.75A
Clearance=0.254
TrackWidth=1.778
ViaDiameter=0.889
ViaDrill=0.635
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

1276
hardware/176122-6-connector/176122-6.sch
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3
hardware/176122-6-connector/fp-lib-table Normal file
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@ -0,0 +1,3 @@
(fp_lib_table
(lib (name 0176122-06)(type Legacy)(uri ${KIPRJMOD}/modules/0176122-06.mod)(options "")(descr ""))
)

3
hardware/176122-6-connector/sym-lib-table Normal file
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@ -0,0 +1,3 @@
(sym_lib_table
(lib (name 0176122-06)(type Legacy)(uri ${KIPRJMOD}/symbols/0176122-06.lib)(options "")(descr ""))
)