From a9229d08cb3a0f0c1993b25b274e33356ca73420 Mon Sep 17 00:00:00 2001 From: rusefi Date: Thu, 26 Dec 2019 23:06:31 -0500 Subject: [PATCH] MC33816 default firmware --- .../mc33816/rusefi/Logic_Wave/wave_list.do | 198 ++++++++ .../mc33816/rusefi/MicrocodeCh1/ch1.psc | 202 ++++++++ .../mc33816/rusefi/MicrocodeCh1/dram1.def | 8 + .../mc33816/rusefi/MicrocodeCh2/ch2.psc | 117 +++++ .../mc33816/rusefi/MicrocodeCh2/dram2.def | 8 + .../rusefi/Registers/ch1_config_reg.bin | 19 + .../rusefi/Registers/ch2_config_reg.bin | 19 + .../rusefi/Registers/diag_config_reg.bin | 44 ++ .../mc33816/rusefi/Registers/dram1.bin | 64 +++ .../mc33816/rusefi/Registers/dram1.hex | 72 +++ .../mc33816/rusefi/Registers/dram2.bin | 64 +++ .../mc33816/rusefi/Registers/dram2.hex | 72 +++ .../rusefi/Registers/io_config_reg.bin | 44 ++ .../rusefi/Registers/main_config_reg.bin | 29 ++ .../mc33816/rusefi/Simulator/AutoLoad.xml | 13 + .../hw_layer/mc33816/rusefi/Stimulus/stim.xml | 16 + firmware/hw_layer/mc33816/rusefi/labels.xml | 23 + firmware/hw_layer/mc33816/rusefi/project.xml | 473 ++++++++++++++++++ firmware/hw_layer/mc33816/rusefi/readme.md | 1 + 19 files changed, 1486 insertions(+) create mode 100644 firmware/hw_layer/mc33816/rusefi/Logic_Wave/wave_list.do create mode 100644 firmware/hw_layer/mc33816/rusefi/MicrocodeCh1/ch1.psc create mode 100644 firmware/hw_layer/mc33816/rusefi/MicrocodeCh1/dram1.def create mode 100644 firmware/hw_layer/mc33816/rusefi/MicrocodeCh2/ch2.psc create mode 100644 firmware/hw_layer/mc33816/rusefi/MicrocodeCh2/dram2.def create mode 100644 firmware/hw_layer/mc33816/rusefi/Registers/ch1_config_reg.bin create mode 100644 firmware/hw_layer/mc33816/rusefi/Registers/ch2_config_reg.bin create mode 100644 firmware/hw_layer/mc33816/rusefi/Registers/diag_config_reg.bin create mode 100644 firmware/hw_layer/mc33816/rusefi/Registers/dram1.bin create mode 100644 firmware/hw_layer/mc33816/rusefi/Registers/dram1.hex create mode 100644 firmware/hw_layer/mc33816/rusefi/Registers/dram2.bin create mode 100644 firmware/hw_layer/mc33816/rusefi/Registers/dram2.hex create mode 100644 firmware/hw_layer/mc33816/rusefi/Registers/io_config_reg.bin create mode 100644 firmware/hw_layer/mc33816/rusefi/Registers/main_config_reg.bin create mode 100644 firmware/hw_layer/mc33816/rusefi/Simulator/AutoLoad.xml create mode 100644 firmware/hw_layer/mc33816/rusefi/Stimulus/stim.xml create mode 100644 firmware/hw_layer/mc33816/rusefi/labels.xml create mode 100644 firmware/hw_layer/mc33816/rusefi/project.xml create mode 100644 firmware/hw_layer/mc33816/rusefi/readme.md diff --git a/firmware/hw_layer/mc33816/rusefi/Logic_Wave/wave_list.do b/firmware/hw_layer/mc33816/rusefi/Logic_Wave/wave_list.do new file mode 100644 index 0000000000..c9f06122c3 --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/Logic_Wave/wave_list.do @@ -0,0 +1,198 @@ + + + STARTx + + + Start1 + + PT2000 + + 8 + Input + Decimal + + + Start2 + + PT2000 + + 9 + Input + Decimal + + + Start3 + + PT2000 + + 10 + Input + Decimal + + + Start4 + + PT2000 + + 11 + Input + Decimal + + + Start5 + + PT2000 + + 12 + Input + Decimal + + + Start6 + + PT2000 + + 13 + Input + Decimal + + + Start7 + + PT2000 + + 14 + Input + Decimal + + + INJ1 + + + Hs1Command + + PT2000 + + 6 + Output + Decimal + + + Hs2Command + + PT2000 + + 7 + Output + Decimal + + + Ls1Command + + PT2000 + + 13 + Output + Decimal + + + CurrentFeedback1 + + PT2000 + + 0 + Internal + Decimal + + + FeedbackHs1Vds + + PT2000 + + 10 + Internal + Decimal + + + FeedbackHs1Vsrc + + PT2000 + + 11 + Internal + Decimal + + + FeedbackLs1Vds + + PT2000 + + 24 + Internal + Decimal + + + DCDC + + + BoostFeedback + + PT2000 + + 35 + Internal + Decimal + + + Ls7Command + + PT2000 + + 19 + Output + Decimal + + + Ls8Command + + PT2000 + + 20 + Output + Decimal + + + Flag0Out + + PT2000 + + 4 + Output + Decimal + + + DEBUG + + + Irq + + PT2000 + + 5 + Output + Decimal + + + irqSource + + PT2000 + Injection Channel 1 + ChSequencers + MicroMachineSeq0 + UProgramCounter + + 7 + Output + Decimal + + \ No newline at end of file diff --git a/firmware/hw_layer/mc33816/rusefi/MicrocodeCh1/ch1.psc b/firmware/hw_layer/mc33816/rusefi/MicrocodeCh1/ch1.psc new file mode 100644 index 0000000000..afa20c1402 --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/MicrocodeCh1/ch1.psc @@ -0,0 +1,202 @@ +******************************************************************************** +* Example Code +* +* Copyright(C) 2019 NXP Semiconductors +* NXP Semiconductors Confidential and Proprietary +* +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* NXP products. This software is supplied "AS IS" without any warranties +* of any kind, and NXP Semiconductors and its licensor disclaim any and +* all warranties, express or implied, including all implied warranties of +* merchantability, fitness for a particular purpose and non-infringement of +* intellectual property rights. NXP Semiconductors assumes no responsibility +* or liability for the use of the software, conveys no license or rights +* under any patent, copyright, mask work right, or any other intellectual +* property rights in or to any products. NXP Semiconductors reserves the +* right to make changes in the software without notification. NXP +* Semiconductors also makes no representation or warranty that such +* application will be suitable for the specified use without further testing +* or modification. +* +* IN NO EVENT WILL NXP SEMICONDUCTORS BE LIABLE, WHETHER IN CONTRACT, +* TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL +* OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY +* LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST +* PROFITS, SAVINGS, OR REVENUES, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED +* BY LAW. NXP SEMICONDUCTOR???S TOTAL LIABILITY FOR ALL COSTS, DAMAGES, +* CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THE +* SOFTWARE IS LIMITED TO THE AGGREGATE AMOUNT PAID BY YOU TO NXP SEMICONDUCTORS +* IN CONNECTION WITH THE SOFTWARE TO WHICH LOSSES OR DAMAGES ARE CLAIMED. +* +* Permission to use, copy, modify, and distribute this software and its +* documentation is hereby granted, under NXP Semiconductors' and its +* licensor's relevant copyrights in the software, without fee, provided +* that it is used in conjunction with NXP Semiconductors devices. This +* copyright, permission, and disclaimer notice must appear in all copies +* of this code. +******************************************************************************** + +#include "dram1.def"; + +* ### Channel 1 - uCore0 controls the injectors 1 and 2 ### + +* ### Variables declaration ### + +* Note: The data are stored into the dataRAM of the channel 1. +* Note: The Thold_tot variable defines the current profile time out. +* The active STARTx pin is expected to toggle in is low state before this time out. + +* ### Initialization phase ### +init0: stgn gain8.68 sssc; * Set the gain of the opamp of the current measure block 1 + ldjr1 eoinj0; * Load the eoinj line label Code RAM address into the register jr1 + ldjr2 idle0; * Load the idle line label Code RAM address into the register jr2 + cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase + +* ### Idle phase- the uPC loops here until start signal is present ### +idle0: cwer CheckStart start row2; * Define entry table for high start pin + stoc on sssc; * Turn ON offset compensation +WaitLoop: wait row2; * uPC is stuck here for almost the whole idle time +CheckStart: joslr inj1_start start1; * Jump to inj1 if start 1 is high + joslr inj2_start start2; * Jump to inj2 if start 2 is high + jmpr WaitLoop; + + +* ### Shortcuts definition per the injector to be actuated ### +inj1_start: dfsct hs1 hs2 ls1; * Set the 3 shortcuts: VBAT, VBOOST, LS + jmpr boost0; * Jump to launch phase + +inj2_start: dfsct hs1 hs2 ls2; * Set the 3 shortcuts: VBAT, VBOOST, LS + jmpr boost0; * Jump to launch phase + +* ### Launch phase enable boost ### +boost0: stoc off sssc; * Turn OFF offset compensation + bias all on; * Enable all biasing structures, kept ON even during actuation + load Iboost dac_sssc _ofs; * Load the boost phase current threshold in the current DAC + cwer peak0 ocur row2; * Jump to peak phase when current is over threshold + stf low b0; * set flag0 low to force the DC-DC converter in idle mode + stos off on on; * Turn VBAT off, BOOST on, LS on + wait row12; * Wait for one of the previously defined conditions + +* ### Peak phase continue on Vbat ### +peak0: ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1 + load Ipeak dac_sssc _ofs; * Load the peak current threshold in the current DAC + cwer bypass0 tc1 row2; * Jump to bypass phase when tc1 reaches end of count + cwer peak_on0 tc2 row3; * Jump to peak_on when tc2 reaches end of count + cwer peak_off0 ocur row4; * Jump to peak_off when current is over threshold + stf high b0; * set flag0 high to release the DC-DC converter idle mode + +peak_on0: stos on off on; * Turn VBAT on, BOOST off, LS on + wait row124; * Wait for one of the previously defined conditions + +peak_off0: ldcd rst ofs keep keep Tpeak_off c2; * Load in the counter 2 the length of the peak_off phase + stos off off on; * Turn VBAT off, BOOST off, LS on + wait row123; * Wait for one of the previously defined conditions + +* ### Bypass phase ### +bypass0: ldcd rst ofs keep keep Tbypass c3; * Load in the counter 3 the length of the off_phase phase + stos off off off; * Turn VBAT off, BOOST off, LS off + cwer hold0 tc3 row4; * Jump to hold when tc3 reaches end of count + wait row14; * Wait for one of the previously defined conditions + +* ### Hold phase on Vbat ### +hold0: ldcd rst _ofs keep keep Thold_tot c1; * Load the length of the total hold phase in counter 2 + load Ihold dac_sssc _ofs; * Load the hold current threshold in the DAC + cwer eoinj0 tc1 row2; * Jump to eoinj phase when tc1 reaches end of count + cwer hold_on0 tc2 row3; * Jump to hold_on when tc2 reaches end of count + cwer hold_off0 ocur row4; * Jump to hold_off when current is over threshold + +hold_on0: stos on off on; * Turn VBAT on, BOOST off, LS on + wait row124; * Wait for one of the previously defined conditions + +hold_off0: ldcd rst _ofs keep keep Thold_off c2; * Load the length of the hold_off phase in counter 1 + stos off off on; * Turn VBAT off, BOOST off, LS on + wait row123; * Wait for one of the previously defined conditions + +* ### End of injection phase ### +eoinj0: stos off off off; * Turn VBAT off, BOOST off, LS off + stf high b0; * set flag0 to high to release the DC-DC converter idle mode + jmpf jr2; * Jump back to idle phase + +* ### End of Channel 1 - uCore0 code ### + +********************************************************************************* + +* ### Channel 1 - uCore1 controls the injectors 3 and 4 ### + +* ### Variables declaration ### + +* Note: The data that defines the profiles are shared between the two microcores. + +* ### Initialization phase ### +init1: stgn gain8.68 sssc; * Set the gain of the opamp of the current measure block 1 + ldjr1 eoinj1; * Load the eoinj line label Code RAM address into the register jr1 + ldjr2 idle1; * Load the idle line label Code RAM address into the register jr2 + cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase + + +* ### Idle phase- the uPC loops here until start signal is present ### +idle1: cwer CheckStart1 start row2; * Define entry table for high start pin + stoc on sssc; * Turn ON offset compensation +WaitLoop1: wait row2; * uPC is stuck here for almost the whole idle time +CheckStart1:joslr inj3_start start3; * Jump to inj1 if start 1 is high + joslr inj4_start start4; * Jump to inj2 if start 2 is high + jmpr WaitLoop1; + + +* ### Shortcuts definition per the injector to be actuated ### +inj3_start: dfsct hs3 hs4 ls3; * Set the 3 shortcuts: VBAT, VBOOST, LS + jmpr boost1; * Jump to launch phase + +inj4_start: dfsct hs3 hs4 ls4; * Set the 3 shortcuts: VBAT, VBOOST, LS + jmpr boost1; * Jump to launch phase + +* ### Launch phase enable boost ### +boost1: stoc off sssc; * Turn OFF offset compensation + load Iboost dac_sssc _ofs; * Load the boost phase current threshold in the current DAC + cwer peak1 ocur row2; * Jump to peak phase when current is over threshold + stf low b0; * set flag0 low to force the DC-DC converter in idle mode + stos off on on; * Turn VBAT off, BOOST on, LS on + wait row12; * Wait for one of the previously defined conditions + +* ### Peak phase continue on Vbat ### +peak1: ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1 + load Ipeak dac_sssc _ofs; * Load the peak current threshold in the current DAC + cwer bypass1 tc1 row2; * Jump to bypass phase when tc1 reaches end of count + cwer peak_on1 tc2 row3; * Jump to peak_on when tc2 reaches end of count + cwer peak_off1 ocur row4; * Jump to peak_off when current is over threshold + stf high b0; * set flag0 high to release the DC-DC converter idle mode + +peak_on1: stos on off on; * Turn VBAT on, BOOST off, LS on + wait row124; * Wait for one of the previously defined conditions + +peak_off1: ldcd rst ofs keep keep Tpeak_off c2; * Load in the counter 2 the length of the peak_off phase + stos off off on; * Turn VBAT off, BOOST off, LS on + wait row123; * Wait for one of the previously defined conditions + +* ### Bypass phase ### +bypass1: ldcd rst ofs keep keep Tbypass c3; * Load in the counter 3 the length of the off_phase phase + stos off off off; * Turn VBAT off, BOOST off, LS off + cwer hold1 tc3 row4; * Jump to hold when tc3 reaches end of count + wait row14; * Wait for one of the previously defined conditions + +* ### Hold phase on Vbat ### +hold1: ldcd rst _ofs keep keep Thold_tot c1; * Load the length of the total hold phase in counter 2 + load Ihold dac_sssc _ofs; * Load the hold current threshold in the DAC + cwer eoinj1 tc1 row2; * Jump to eoinj phase when tc1 reaches end of count + cwer hold_on1 tc2 row3; * Jump to hold_on when tc2 reaches end of count + cwer hold_off1 ocur row4; * Jump to hold_off when current is over threshold + +hold_on1: stos on off on; * Turn VBAT on, BOOST off, LS on + wait row124; * Wait for one of the previously defined conditions + +hold_off1: ldcd rst _ofs keep keep Thold_off c2; * Load the length of the hold_off phase in counter 1 + stos off off on; * Turn VBAT off, BOOST off, LS on + wait row123; * Wait for one of the previously defined conditions + +* ### End of injection phase ### +eoinj1: stos off off off; * Turn VBAT off, BOOST off, LS off + stf high b0; * set flag0 to high to release the DC-DC converter idle mode + jmpf jr2; * Jump back to idle phase + +* ### End of Channel 1 - uCore1 code ### diff --git a/firmware/hw_layer/mc33816/rusefi/MicrocodeCh1/dram1.def b/firmware/hw_layer/mc33816/rusefi/MicrocodeCh1/dram1.def new file mode 100644 index 0000000000..c8db1f8aa4 --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/MicrocodeCh1/dram1.def @@ -0,0 +1,8 @@ +#define Iboost 0; +#define Ipeak 1; +#define Ihold 2; +#define Tpeak_off 3; +#define Tpeak_tot 4; +#define Tbypass 5; +#define Thold_off 6; +#define Thold_tot 7; diff --git a/firmware/hw_layer/mc33816/rusefi/MicrocodeCh2/ch2.psc b/firmware/hw_layer/mc33816/rusefi/MicrocodeCh2/ch2.psc new file mode 100644 index 0000000000..8e7d6e921d --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/MicrocodeCh2/ch2.psc @@ -0,0 +1,117 @@ +******************************************************************************** +* Example Code +* +* Copyright(C) 2019 NXP Semiconductors +* NXP Semiconductors Confidential and Proprietary +* +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* NXP products. This software is supplied "AS IS" without any warranties +* of any kind, and NXP Semiconductors and its licensor disclaim any and +* all warranties, express or implied, including all implied warranties of +* merchantability, fitness for a particular purpose and non-infringement of +* intellectual property rights. NXP Semiconductors assumes no responsibility +* or liability for the use of the software, conveys no license or rights +* under any patent, copyright, mask work right, or any other intellectual +* property rights in or to any products. NXP Semiconductors reserves the +* right to make changes in the software without notification. NXP +* Semiconductors also makes no representation or warranty that such +* application will be suitable for the specified use without further testing +* or modification. +* +* IN NO EVENT WILL NXP SEMICONDUCTORS BE LIABLE, WHETHER IN CONTRACT, +* TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL +* OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY +* LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST +* PROFITS, SAVINGS, OR REVENUES, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED +* BY LAW. NXP SEMICONDUCTOR???S TOTAL LIABILITY FOR ALL COSTS, DAMAGES, +* CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THE +* SOFTWARE IS LIMITED TO THE AGGREGATE AMOUNT PAID BY YOU TO NXP SEMICONDUCTORS +* IN CONNECTION WITH THE SOFTWARE TO WHICH LOSSES OR DAMAGES ARE CLAIMED. +* +* Permission to use, copy, modify, and distribute this software and its +* documentation is hereby granted, under NXP Semiconductors' and its +* licensor's relevant copyrights in the software, without fee, provided +* that it is used in conjunction with NXP Semiconductors devices. This +* copyright, permission, and disclaimer notice must appear in all copies +* of this code. +******************************************************************************** + +#include "dram2.def"; + +* ### Channel 2 - uCore0 controls dc-dc ### + + +* ### Initialization phase ### +init0: stgn gain5.8 ossc; * Set the gain of the opamp of the current measure block 4 + load Isense4_low dac_ossc _ofs; * Load Isense4_high current threshold in DAC 4L + load Isense4_high dac4h4n _ofs; * Load Isense4_high current threshold in DAC 4H + stdm null; * Set the boost voltage DAC access mode + cwer dcdc_idle _f0 row1; * Wait table entry for Vboost under Vboost_low threshold condition + cwer dcdc_on _vb row2; * Wait table entry for Vboost under Vboost_low threshold condition + cwer dcdc_off vb row3; * Wait table entry for Vboost over Vboost_high threshold condition + +* ### Asynchronous phase ### +dcdc_on: load Vboost_high dac4h4n _ofs; * Load the upper Vboost threshold in vboost_dac register + stdcctl async; * Enable asynchronous mode + wait row13; * Wait for one of the previously defined conditions + +* ### Synchronous phase ### +dcdc_off: load Vboost_low dac4h4n _ofs; * Load the upper Vboost threshold in vboost_dac register + stdcctl sync; * Enable synchronous mode + wait row12; * Wait for one of the previously defined conditions + +* ### Idle phase ### +dcdc_idle: stdcctl sync; * Enable synchronous mode + jocr dcdc_idle _f0; * jump to previous line while flag 0 is low + jmpr dcdc_on; * force the DC-DC converter on when flag 0 goes high + +* ### End of Channel 2 - uCore0 code ### + +********************************************************************************* + +* ### Channel 2 - uCore1 drives fuel pump ### + + +* ### Initialization phase ### +init1: stgn gain19.4 ossc; * Set the gain of the opamp of the current measure block 1 + ldjr1 eoact1; * Load the eoinj line label Code RAM address into the register jr1 + ldjr2 idle1; * Load the idle line label Code RAM address into the register jr2 + cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase + +* ### Idle phase- the uPC loops here until start signal is present ### +idle1: joslr act5_start start5; * Perform an actuation on act5 if start 5 (only) is active + joslr act6_start start6; * Perform an actuation on act6 if start 6 (only) is active + jmpf jr1; * If more than 1 start active at the same time(or none), no actuation + +* ### Shortcuts definition per the injector to be actuated ### +act5_start: dfsct hs5 ls5 undef; * Set the 2 shortcuts: VBAT, LS + jmpr peak1; * Jump to launch phase + +act6_start: dfsct hs5 ls6 undef; * Set the 2 shortcuts: VBAT, LS + jmpr peak1; * Jump to launch phase + +* ### Launch peak phase on bat ### +peak1: load Ipeak dac_ossc _ofs; * Load the boost phase current threshold in the current DAC + cwer hold1 cur3 row2; * Jump to peak phase when current is over threshold + stos on on keep; * Turn VBAT off, BOOST on, LS on + wait row12; * Wait for one of the previously defined conditions + +* ### Hold phase on Vbat ### +hold1: ldcd rst _ofs keep keep Thold_tot c1; * Load the length of the total hold phase in counter 2 + load Ihold dac_ossc _ofs; * Load the hold current threshold in the DAC + cwer eoact1 tc1 row2; * Jump to eoinj phase when tc1 reaches end of count + cwer hold_on1 tc2 row3; * Jump to hold_on when tc2 reaches end of count + cwer hold_off1 cur3 row4; * Jump to hold_off when current is over threshold + +hold_on1: stos on on keep; * Turn VBAT on, LS on + wait row124; * Wait for one of the previously defined conditions + +hold_off1: ldcd rst _ofs off on Thold_off c2; * Load the length of the hold_off phase in counter 1 and turn VBAT off, LS on + wait row123; * Wait for one of the previously defined conditions + +* ### End of injection phase ### +eoact1: stos off off keep; * Turn VBAT off, LS off + jmpf jr2; * Jump back to idle phase + +* ### End of Channel 2 - uCore1 code ### diff --git a/firmware/hw_layer/mc33816/rusefi/MicrocodeCh2/dram2.def b/firmware/hw_layer/mc33816/rusefi/MicrocodeCh2/dram2.def new file mode 100644 index 0000000000..e0f772d642 --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/MicrocodeCh2/dram2.def @@ -0,0 +1,8 @@ +#define Vboost_low 0; +#define Vboost_high 1; +#define Isense4_low 2; +#define Isense4_high 3; +#define Thold_off 4; +#define Thold_tot 5; +#define Ipeak 6; +#define Ihold 7; diff --git a/firmware/hw_layer/mc33816/rusefi/Registers/ch1_config_reg.bin b/firmware/hw_layer/mc33816/rusefi/Registers/ch1_config_reg.bin new file mode 100644 index 0000000000..6a254f86c7 --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/Registers/ch1_config_reg.bin @@ -0,0 +1,19 @@ +0000000000011000 +0000000000000000 +0000000000000000 +0000000000000000 +0000001100000011 +0000000000000000 +0000000000000000 +0000000000011011 +1100101000010010 +0100101101001010 +0000000000000000 +0000000000110001 +0000000000000000 +0000000000000000 +0000000000000000 +0000001111111111 +0000001111111111 +0000000000000000 +0000000000000000 diff --git a/firmware/hw_layer/mc33816/rusefi/Registers/ch2_config_reg.bin b/firmware/hw_layer/mc33816/rusefi/Registers/ch2_config_reg.bin new file mode 100644 index 0000000000..8549616c30 --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/Registers/ch2_config_reg.bin @@ -0,0 +1,19 @@ +0000000000011000 +0000000000000000 +0000000000000000 +0000000000000000 +0000110000000000 +0000000000000000 +0000000000000000 +0000000000101010 +0000110001111010 +1110111001110001 +0000000000000000 +0000000000010000 +0000000000000000 +0000000000000000 +0000000000000000 +0000001111111111 +0000001111111111 +0000000000000000 +0000000000000000 diff --git a/firmware/hw_layer/mc33816/rusefi/Registers/diag_config_reg.bin b/firmware/hw_layer/mc33816/rusefi/Registers/diag_config_reg.bin new file mode 100644 index 0000000000..a3e2816a55 --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/Registers/diag_config_reg.bin @@ -0,0 +1,44 @@ +0001110111011010 +0000000000001001 +0000000000011110 +0001110111011010 +0000000000001001 +0000000000011110 +0000001010001110 +0000000000001001 +0000000000011110 +0000001010001110 +0000000000001001 +0000000000011110 +0000001010001110 +0000000000001001 +0000000000011110 +0000001010001110 +0000000000001001 +0000000000011110 +0000000000011110 +0001110111011010 +0000000001101001 +0000000000011110 +0001110111011010 +0000000001101001 +0000000000011110 +0000001010001110 +0000000001101001 +0000000000011110 +0000001010001110 +0000000001101001 +0000000000011110 +0000000000000000 +0000000000000000 +0000000000011110 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000001 diff --git a/firmware/hw_layer/mc33816/rusefi/Registers/dram1.bin b/firmware/hw_layer/mc33816/rusefi/Registers/dram1.bin new file mode 100644 index 0000000000..99d37d648d --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/Registers/dram1.bin @@ -0,0 +1,64 @@ +0000000011010100 +0000000001101001 +0000000001000001 +0000000100001110 +0000101110111000 +0000000100001110 +0000000100001110 +1110101001100000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 diff --git a/firmware/hw_layer/mc33816/rusefi/Registers/dram1.hex b/firmware/hw_layer/mc33816/rusefi/Registers/dram1.hex new file mode 100644 index 0000000000..587409d42f --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/Registers/dram1.hex @@ -0,0 +1,72 @@ +// +// Application: +// Asic ID: MC33816 +// Version: +// DRAM +// Date: Thursday, December 26, 2019 +// Author: Andrey +// +0x00D4, +0x0069, +0x0041, +0x010E, +0x0BB8, +0x010E, +0x010E, +0xEA60, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, 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+0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 diff --git a/firmware/hw_layer/mc33816/rusefi/Registers/dram2.hex b/firmware/hw_layer/mc33816/rusefi/Registers/dram2.hex new file mode 100644 index 0000000000..4f7e7b3188 --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/Registers/dram2.hex @@ -0,0 +1,72 @@ +// +// Application: +// Asic ID: MC33816 +// Version: +// DRAM +// Date: Thursday, December 26, 2019 +// Author: Andrey +// +0x00CD, +0x00D0, +0x0025, +0x0037, +0x010E, +0xEA60, +0x0069, +0x0041, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000 diff --git a/firmware/hw_layer/mc33816/rusefi/Registers/io_config_reg.bin b/firmware/hw_layer/mc33816/rusefi/Registers/io_config_reg.bin new file mode 100644 index 0000000000..fcd7655df6 --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/Registers/io_config_reg.bin @@ -0,0 +1,44 @@ +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000001100011 +0000000110001100 +0000100000000000 +0000011000010000 +0000000001000001 +0000000010011000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000010010 +0000000000010010 +0000000000010010 +0000000000000000 +0000000000010101 +0000000000010101 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000010000000 +0000000010000000 +0000000010000000 +0000000000000001 +0000000010000001 +0000000001000001 +0000000000001000 +0000000000000100 +0000000000000001 +0000000010001100 +0000000000000000 +0000000000100000 +0000000000100000 +0000000000101110 +0000000000000000 diff --git a/firmware/hw_layer/mc33816/rusefi/Registers/main_config_reg.bin b/firmware/hw_layer/mc33816/rusefi/Registers/main_config_reg.bin new file mode 100644 index 0000000000..e9a15a99ee --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/Registers/main_config_reg.bin @@ -0,0 +1,29 @@ +0000000000000011 +0001111111000000 +0000000000000000 +0001000000000000 +0000000000010111 +0010000000000000 +0000000000000001 +0000000000000000 +0000000000011111 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +1001110000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 diff --git a/firmware/hw_layer/mc33816/rusefi/Simulator/AutoLoad.xml b/firmware/hw_layer/mc33816/rusefi/Simulator/AutoLoad.xml new file mode 100644 index 0000000000..3a2735e668 --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/Simulator/AutoLoad.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/firmware/hw_layer/mc33816/rusefi/Stimulus/stim.xml b/firmware/hw_layer/mc33816/rusefi/Stimulus/stim.xml new file mode 100644 index 0000000000..69fd5e9267 --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/Stimulus/stim.xml @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/firmware/hw_layer/mc33816/rusefi/labels.xml b/firmware/hw_layer/mc33816/rusefi/labels.xml new file mode 100644 index 0000000000..0fac009540 --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/labels.xml @@ -0,0 +1,23 @@ + + + + init0 + irq_sw + + irq_auto + init1 + + + + + + init0 + + + + init1 + + + + + \ No newline at end of file diff --git a/firmware/hw_layer/mc33816/rusefi/project.xml b/firmware/hw_layer/mc33816/rusefi/project.xml new file mode 100644 index 0000000000..a36057b5b1 --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/project.xml @@ -0,0 +1,473 @@ + + + MC33816 + IDE Project + %APPLICATION% + %DEVICEID% + rusefi + %PREFIX% + + + Registers\main_config_reg.hex + Registers\ch1_config_reg.hex + Registers\ch2_config_reg.hex + Registers\ch3_config_reg.hex + Registers\diag_config_reg.hex + Registers\io_config_reg.hex + MicrocodeCh1\ch1.psc + MicrocodeCh2\ch2.psc + MicrocodeCh3\ch3.psc + Registers\dram1.hex + Registers\dram2.hex + Registers\dram3.hex + Simulator\AutoLoad.xml + + + 1 MHz + + + + + + True + True + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + + + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + + + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + + + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + + + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + + + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + Hex + + + + + + + + + + \ No newline at end of file diff --git a/firmware/hw_layer/mc33816/rusefi/readme.md b/firmware/hw_layer/mc33816/rusefi/readme.md new file mode 100644 index 0000000000..7459e997d6 --- /dev/null +++ b/firmware/hw_layer/mc33816/rusefi/readme.md @@ -0,0 +1 @@ +Completely default project as generated by MC33816 Dev Studio conveniently comes with default source code. \ No newline at end of file