From c0b37d78e43e33ca8c5e0fed0fc3e2612e00c484 Mon Sep 17 00:00:00 2001 From: Matthew Kennedy Date: Tue, 7 Dec 2021 12:12:33 -0800 Subject: [PATCH] testing stm32 stop/standby (#3666) * testing stop/standby * comments * guard * s * we shall figure out f7 later * ok maybe we do worry about f7 * comments and tweaks * f7 * f4 maybe probably --- firmware/hw_layer/ports/stm32/port_mpu_util.h | 5 +++ .../hw_layer/ports/stm32/stm32f4/mpu_util.cpp | 37 ++++++++++++++++++ .../hw_layer/ports/stm32/stm32f7/mpu_util.cpp | 39 +++++++++++++++++++ firmware/rusefi.cpp | 5 +++ 4 files changed, 86 insertions(+) diff --git a/firmware/hw_layer/ports/stm32/port_mpu_util.h b/firmware/hw_layer/ports/stm32/port_mpu_util.h index 18b555e813..6000f1fbc2 100644 --- a/firmware/hw_layer/ports/stm32/port_mpu_util.h +++ b/firmware/hw_layer/ports/stm32/port_mpu_util.h @@ -63,3 +63,8 @@ typedef enum { #ifndef ADC_CR2_SWSTART #define ADC_CR2_SWSTART ((uint32_t)0x40000000) #endif + +#ifdef __cplusplus +void stm32_stop(); +void stm32_standby(); +#endif diff --git a/firmware/hw_layer/ports/stm32/stm32f4/mpu_util.cpp b/firmware/hw_layer/ports/stm32/stm32f4/mpu_util.cpp index bf4dca7a1b..b3b84ef62c 100644 --- a/firmware/hw_layer/ports/stm32/stm32f4/mpu_util.cpp +++ b/firmware/hw_layer/ports/stm32/stm32f4/mpu_util.cpp @@ -30,3 +30,40 @@ uintptr_t getFlashAddrFirstCopy() { uintptr_t getFlashAddrSecondCopy() { return 0x080C0000; } + +void stm32_stop() { + SysTick->CTRL = 0; + __disable_irq(); + RCC->AHB1RSTR = RCC_AHB1RSTR_GPIOERST; + + // configure mode bits + PWR->CR &= ~PWR_CR_PDDS; // cleared PDDS means stop mode (not standby) + PWR->CR |= PWR_CR_FPDS; // turn off flash in stop mode + PWR->CR |= PWR_CR_LPDS; // regulator in low power mode + + // enable Deepsleep mode + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + // Wait for event - this will return when stop mode is done + __WFE(); + + // Lastly, reboot + NVIC_SystemReset(); +} + +void stm32_standby() { + SysTick->CTRL = 0; + __disable_irq(); + + // configure mode bits + PWR->CR |= PWR_CR_PDDS; // PDDS = use standby mode (not stop mode) + + // enable Deepsleep mode + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + // Wait for event - this should never return as it kills the chip until a reset + __WFE(); + + // Lastly, reboot + NVIC_SystemReset(); +} diff --git a/firmware/hw_layer/ports/stm32/stm32f7/mpu_util.cpp b/firmware/hw_layer/ports/stm32/stm32f7/mpu_util.cpp index 831e674f74..97aef38a2f 100644 --- a/firmware/hw_layer/ports/stm32/stm32f7/mpu_util.cpp +++ b/firmware/hw_layer/ports/stm32/stm32f7/mpu_util.cpp @@ -174,3 +174,42 @@ void sys_dual_bank(void) { */ } + +void stm32_stop() { + SysTick->CTRL = 0; + __disable_irq(); + RCC->AHB1RSTR = RCC_AHB1RSTR_GPIOERST; + + // configure mode bits + PWR->CR1 &= ~PWR_CR1_PDDS; // cleared PDDS means stop mode (not standby) + PWR->CR1 |= PWR_CR1_FPDS; // turn off flash in stop mode + PWR->CR1 |= PWR_CR1_UDEN; // regulator underdrive in stop mode + PWR->CR1 |= PWR_CR1_LPUDS; // low power regulator in under drive mode + PWR->CR1 |= PWR_CR1_LPDS; // regulator in low power mode + + // enable Deepsleep mode + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + __WFE(); + + // Lastly, reboot + NVIC_SystemReset(); +} + +void stm32_standby() { + SysTick->CTRL = 0; + __disable_irq(); + RCC->AHB1RSTR = RCC_AHB1RSTR_GPIOERST; + + // configure mode bits + PWR->CR1 |= PWR_CR1_PDDS; // PDDS = use standby mode (not stop mode) + + // enable Deepsleep mode + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + // Wait for event - this should never return as it kills the chip until a reset + __WFE(); + + // Lastly, reboot + NVIC_SystemReset(); +} diff --git a/firmware/rusefi.cpp b/firmware/rusefi.cpp index 43158d368b..82346ae0c9 100644 --- a/firmware/rusefi.cpp +++ b/firmware/rusefi.cpp @@ -176,6 +176,11 @@ void runRusEfi() { addConsoleAction("dual_bank", sys_dual_bank); #endif +#if defined(STM32F4) || defined(STM32F7) + addConsoleAction("stm32_stop", stm32_stop); + addConsoleAction("stm32_standby", stm32_standby); +#endif + addConsoleAction(CMD_REBOOT, scheduleReboot); addConsoleAction(CMD_REBOOT_DFU, jump_to_bootloader);