rusefi
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rusefi-1
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This commit is contained in:
rusEfi 2014-11-08 21:03:27 -06:00
parent 56c01c7951
commit c9cc87cb31
5 changed files with 71 additions and 64 deletions
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4
firmware/chibios/os/kernel/src/chdebug.c
View File

@ -162,8 +162,8 @@ void firmwareError(const char *fmt, ...);
* @notapi
*/
void dbg_check_enter_isr(void) {
if (dbg_isr_cnt > 1)
firmwareError("nesting2");
if (dbg_isr_cnt >= 2)
firmwareError("nesting3");
port_lock_from_isr();
if ((dbg_isr_cnt < 0) || (dbg_lock_cnt != 0))
chDbgPanic("SV#8");

1
firmware/chibios/os/various/chprintf.c
View File

@ -96,6 +96,7 @@ char *ftoa(char *p, double num, unsigned long precision) {
#endif
#include "error_handling.h"
int getRemainingStack(Thread *otp);
/**
* @brief System formatted output function.

2
firmware/config/engines/bmw_e34.cpp
View File

@ -38,6 +38,8 @@ void setBmwE43(engine_configuration_s *engineConfiguration) {
board_configuration_s *bc = &engineConfiguration->bc;
bc->malfunctionIndicatorPin = GPIO_NONE;
// bc->isFastAdcEnabled = true;
bc->ignitionPins[0] = GPIOC_7; // #1
bc->ignitionPins[1] = GPIO_NONE; // #2
bc->ignitionPins[2] = GPIOE_4; // #3

3
firmware/config/system/chconf.h
View File

@ -44,6 +44,9 @@
chDbgPanic3(__QUOTE_THIS(func)"()", __FILE__, __LINE__); \
}
#define COMMON_IRQ_PRIORITY 6
#define CORTEX_PRIORITY_SYSTICK COMMON_IRQ_PRIORITY
#define PORT_IDLE_THREAD_STACK_SIZE 1024

125
firmware/config/system/mcuconf.h
View File

@ -30,6 +30,7 @@
#define STM32F4xx_MCUCONF
#include "chconf.h"
#include "boards.h"
#include "efifeatures.h"
#include "rusefi_enums.h"
@ -89,34 +90,34 @@
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
#define STM32_ADC_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY COMMON_IRQ_PRIORITY
/*
* CAN driver system settings.
*/
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
#define STM32_CAN_CAN1_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_CAN_CAN2_IRQ_PRIORITY COMMON_IRQ_PRIORITY
/*
* EXT driver system settings.
*/
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
#define STM32_EXT_EXTI0_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_EXT_EXTI1_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_EXT_EXTI2_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_EXT_EXTI3_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_EXT_EXTI4_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_EXT_EXTI16_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_EXT_EXTI17_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_EXT_EXTI18_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_EXT_EXTI19_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_EXT_EXTI20_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_EXT_EXTI21_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_EXT_EXTI22_IRQ_PRIORITY COMMON_IRQ_PRIORITY
/*
* GPT driver system settings.
@ -133,18 +134,18 @@
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 3
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
#define STM32_GPT_TIM12_IRQ_PRIORITY 7
#define STM32_GPT_TIM14_IRQ_PRIORITY 7
#define STM32_GPT_TIM1_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_GPT_TIM2_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_GPT_TIM3_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_GPT_TIM4_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_GPT_TIM5_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_GPT_TIM6_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_GPT_TIM7_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_GPT_TIM8_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_GPT_TIM9_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_GPT_TIM11_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_GPT_TIM12_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_GPT_TIM14_IRQ_PRIORITY COMMON_IRQ_PRIORITY
/*
* I2C driver system settings.
@ -156,12 +157,12 @@
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_I2C1_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_I2C_I2C2_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_I2C_I2C3_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_I2C_I2C1_DMA_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_I2C_I2C2_DMA_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_I2C_I2C3_DMA_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt()
#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt()
#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt()
@ -169,13 +170,13 @@
/*
* ICU driver system settings.
*/
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
#define STM32_ICU_TIM1_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_ICU_TIM2_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_ICU_TIM3_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_ICU_TIM4_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_ICU_TIM5_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_ICU_TIM8_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_ICU_TIM9_IRQ_PRIORITY COMMON_IRQ_PRIORITY
/*
* MAC driver system settings.
@ -185,20 +186,20 @@
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_ETH1_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
#define STM32_PWM_TIM1_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_PWM_TIM2_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_PWM_TIM3_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_PWM_TIM4_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_PWM_TIM5_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_PWM_TIM8_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_PWM_TIM9_IRQ_PRIORITY COMMON_IRQ_PRIORITY
/*
* SERIAL driver system settings.
@ -228,9 +229,9 @@
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_SPI1_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_SPI_SPI2_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_SPI_SPI3_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_SPI_DMA_ERROR_HOOK(spip) chDbgCheck(TRUE, "STM32_SPI_DMA_ERROR_HOOK")
/*
@ -248,10 +249,10 @@
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_UART_USART2_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_UART_USART3_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_UART_USART6_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
@ -263,8 +264,8 @@
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_USE_OTG2 FALSE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_USB_OTG2_IRQ_PRIORITY COMMON_IRQ_PRIORITY
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO