mirror of https://github.com/rusefi/rusefi-1.git
auto-sync
This commit is contained in:
rusEfi
parent
e8b6cfd15b
commit
e390c0ebcc
|
|
@ -5,16 +5,16 @@
|
|||
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@ -133,6 +133,7 @@
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|||
<listOptionValue builtIn="false" value=""../chibios/os/kernel/include""/>
|
||||
<listOptionValue builtIn="false" value=""../chibios/boards/ST_STM32F4_DISCOVERY""/>
|
||||
<listOptionValue builtIn="false" value=""../chibios/os/hal/src""/>
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||||
<listOptionValue builtIn="false" value=""../chibios/os/various/devices_lib/accel""/>
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||||
<listOptionValue builtIn="false" value=""../chibios/os/hal/include""/>
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||||
<listOptionValue builtIn="false" value=""../chibios/os/hal/platforms/STM32/TIMv1""/>
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<listOptionValue builtIn="false" value=""../chibios/os/hal/platforms/STM32/I2Cv1""/>
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||||
|
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@ -199,16 +200,16 @@
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<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1741644682" name="Release_broken_original" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release">
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@ -282,16 +283,16 @@
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<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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<configuration artifactName="rusefi" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1034318602.1044213654" name="Debug_EGT2CAN" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
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<configuration artifactName="rusefi" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1034318602.1044213654" name="Debug_EGT2CAN" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
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<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.377175633" name="Cross ARM GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug">
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@ -568,16 +569,16 @@
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<externalSettings/>
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</extensions>
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</storageModule>
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<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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<configuration artifactName="rusefi" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1034318602.160551264" name="Release_EMS" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
|
||||
<configuration artifactName="rusefi" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1034318602.160551264" name="Release_EMS" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
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<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1034318602.160551264." name="/" resourcePath="">
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<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.1412440709" name="Cross ARM GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug">
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<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.871834085" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.none" valueType="enumerated"/>
|
||||
|
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|||
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@ -189,6 +189,7 @@ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
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$(HALINC) $(PLATFORMINC) $(BOARDINC) \
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$(CHCPPINC) \
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$(CHIBIOS)/os/various \
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$(CHIBIOS)/os/various/devices_lib\accel \
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config/stm32f4ems \
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config/engines \
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config \
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@ -717,9 +717,9 @@
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/**
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* @brief I2C1 frequency.
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*/
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#if STM32_I2CSW == STM32_I2C1SW_HSI
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#if STM32_I2C1SW == STM32_I2C1SW_HSI
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#define STM32_I2C1CLK STM32_HSICLK
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#elif STM32_I2CSW == STM32_I2C1SW_SYSCLK
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#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK
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#define STM32_I2C1CLK STM32_SYSCLK
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#else
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#error "invalid source selected for I2C1 clock"
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@ -732,9 +732,9 @@
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#define STM32_USART1CLK STM32_PCLK
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#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
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#define STM32_USART1CLK STM32_SYSCLK
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#elif STM32_USART1SW == STM32_USART1SW_LSECLK
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#elif STM32_USART1SW == STM32_USART1SW_LSE
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#define STM32_USART1CLK STM32_LSECLK
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#elif STM32_USART1SW == STM32_USART1SW_HSICLK
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#elif STM32_USART1SW == STM32_USART1SW_HSI
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#define STM32_USART1CLK STM32_HSICLK
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#else
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#error "invalid source selected for USART1 clock"
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@ -67,11 +67,15 @@
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* instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
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*/
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const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
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{DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
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{DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_3_IRQn},
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{DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel2_3_IRQn},
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{DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_5_IRQn},
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{DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel4_5_IRQn}
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{DMA1_Channel1, &DMA1->IFCR, 0x0001, 0, 0, DMA1_Channel1_IRQn},
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{DMA1_Channel2, &DMA1->IFCR, 0x0006, 4, 1, DMA1_Channel2_3_IRQn},
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{DMA1_Channel3, &DMA1->IFCR, 0x0006, 8, 2, DMA1_Channel2_3_IRQn},
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{DMA1_Channel4, &DMA1->IFCR, 0x0078, 12, 3, DMA1_Channel4_5_IRQn},
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{DMA1_Channel5, &DMA1->IFCR, 0x0078, 16, 4, DMA1_Channel4_5_IRQn},
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#if STM32_DMA_STREAMS > 5
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{DMA1_Channel6, &DMA1->IFCR, 0x0078, 20, 5, DMA1_Channel4_5_6_7_IRQn},
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{DMA1_Channel7, &DMA1->IFCR, 0x0078, 24, 6, DMA1_Channel4_5_6_7_IRQn}
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#endif
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};
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/*===========================================================================*/
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@ -177,6 +181,24 @@ CH_IRQ_HANDLER(Vector6C) {
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dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
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}
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#if STM32_DMA_STREAMS > 5
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/* Check on channel 6.*/
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flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
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if (flags & STM32_DMA_ISR_MASK) {
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DMA1->IFCR = flags << 20;
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if (dma_isr_redir[5].dma_func)
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dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
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}
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/* Check on channel 7.*/
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flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
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if (flags & STM32_DMA_ISR_MASK) {
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DMA1->IFCR = flags << 24;
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if (dma_isr_redir[6].dma_func)
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dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
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}
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#endif
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CH_IRQ_EPILOGUE();
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}
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@ -248,9 +270,8 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
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dmaStreamDisable(dmastp);
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dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
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/* Enables the associated IRQ vector if a callback is defined.*/
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if (func != NULL)
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nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
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/* Enables the associated IRQ vector.*/
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nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
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return FALSE;
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}
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@ -276,12 +297,14 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
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chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
|
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"dmaStreamRelease(), #1", "not allocated");
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|
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/* Disables the associated IRQ vector.*/
|
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nvicDisableVector(dmastp->vector);
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/* Marks the stream as not allocated.*/
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dma_streams_mask &= ~(1 << dmastp->selfindex);
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/* Disables the associated IRQ vector if also the sharing channels are
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also disabled.*/
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if ((dma_streams_mask & dmastp->sharedmask) == 0)
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nvicDisableVector(dmastp->vector);
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/* Shutting down clocks that are no more required, if any.*/
|
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if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
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rccDisableDMA1(FALSE);
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@ -32,12 +32,6 @@
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Total number of DMA streams.
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* @note This is the total number of streams among all the DMA units.
|
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*/
|
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#define STM32_DMA_STREAMS 5
|
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|
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/**
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* @brief Mask of the ISR bits passed to the DMA callback functions.
|
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*/
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@ -113,6 +107,10 @@
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#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2)
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#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3)
|
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#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4)
|
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#if (STM32_DMA_STREAMS > 5) || defined(__DOXYGEN__)
|
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#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5)
|
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#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6)
|
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#endif
|
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/** @} */
|
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|
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/**
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@ -172,6 +170,18 @@
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/* Derived constants and error checks. */
|
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/*===========================================================================*/
|
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|
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#if !defined(STM32_ADVANCED_DMA)
|
||||
#error "missing STM32_ADVANCED_DMA definition in registry"
|
||||
#endif
|
||||
|
||||
#if !defined(STM32_DMA_STREAMS)
|
||||
#error "missing STM32_DMA_STREAMS definition in registry"
|
||||
#endif
|
||||
|
||||
#if STM32_ADVANCED_DMA == TRUE
|
||||
#error "DMAv1 driver does not support STM32_ADVANCED_DMA"
|
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#endif
|
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|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
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|
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@ -182,6 +192,8 @@
|
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typedef struct {
|
||||
DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */
|
||||
volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
|
||||
uint32_t sharedmask; /**< @brief Mask of channels sharing
|
||||
the same ISR. */
|
||||
uint8_t ishift; /**< @brief Bits offset in xIFCR
|
||||
register. */
|
||||
uint8_t selfindex; /**< @brief Index to self in array. */
|
||||
|
|
|
|||
|
|
@ -57,6 +57,7 @@
|
|||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
#define STM32_DMA_STREAMS 5
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
|
@ -186,6 +187,7 @@
|
|||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
#define STM32_DMA_STREAMS 5
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
|
@ -300,6 +302,7 @@
|
|||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
#define STM32_DMA_STREAMS 5
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
|
|
|||
|
|
@ -15,15 +15,15 @@
|
|||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The device used in the target application
|
||||
* - To use or not the peripheral<EFBFBD>s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral<EFBFBD>s registers
|
||||
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral’s registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_STDPERIPH_DRIVER"
|
||||
* - To change few application-specific parameters such as the HSE
|
||||
* crystal frequency
|
||||
* - Data structures and the address mapping for all peripherals
|
||||
* - Peripheral's registers declarations and bits definition
|
||||
* - Macros to access peripheral<EFBFBD>s registers hardware
|
||||
* - Macros to access peripheral’s registers hardware
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -154,6 +154,9 @@
|
|||
/**
|
||||
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
|
||||
*/
|
||||
/* CHIBIOS FIX */
|
||||
#define __CM3_REV 0x0201 /*!< Core revision r2p1, not sure it is right */
|
||||
/* END CHIBIOS FIX */
|
||||
#ifdef STM32F10X_XL
|
||||
#define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -216,7 +216,7 @@ msg_t canReceive(CANDriver *canp,
|
|||
CANRxFrame *crfp,
|
||||
systime_t timeout) {
|
||||
|
||||
chDbgCheck((canp != NULL) && (crfp != NULL) && (mailbox < CAN_RX_MAILBOXES),
|
||||
chDbgCheck((canp != NULL) && (crfp != NULL) && (mailbox <= CAN_RX_MAILBOXES),
|
||||
"canReceive");
|
||||
|
||||
chSysLock();
|
||||
|
|
|
|||
|
|
@ -265,10 +265,11 @@ void rtcGetTimeTm(RTCDriver *rtcp, struct tm *timp) {
|
|||
#if defined __GNUC__
|
||||
localtime_r((time_t *)&(timespec.tv_sec), timp);
|
||||
#else
|
||||
struct tm *t = localtime((time_t *)&(timespec.tv_sec));
|
||||
memcpy(&timp, t, sizeof(struct tm));
|
||||
{
|
||||
struct tm *t = localtime((time_t *)&(timespec.tv_sec));
|
||||
memcpy(&timp, t, sizeof(struct tm));
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -0,0 +1,119 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file lis302dl.c
|
||||
* @brief LIS302DL MEMS interface module through SPI code.
|
||||
*
|
||||
* @addtogroup lis302dl
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
#include "lis302dl.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
static uint8_t txbuf[2];
|
||||
static uint8_t rxbuf[2];
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Reads a register value.
|
||||
* @pre The SPI interface must be initialized and the driver started.
|
||||
*
|
||||
* @param[in] spip pointer to the SPI initerface
|
||||
* @param[in] reg register number
|
||||
* @return The register value.
|
||||
*/
|
||||
uint8_t lis302dlReadRegister(SPIDriver *spip, uint8_t reg) {
|
||||
|
||||
spiSelect(spip);
|
||||
txbuf[0] = 0x80 | reg;
|
||||
txbuf[1] = 0xff;
|
||||
spiExchange(spip, 2, txbuf, rxbuf);
|
||||
spiUnselect(spip);
|
||||
return rxbuf[1];
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes a value into a register.
|
||||
* @pre The SPI interface must be initialized and the driver started.
|
||||
*
|
||||
* @param[in] spip pointer to the SPI initerface
|
||||
* @param[in] reg register number
|
||||
* @param[in] value the value to be written
|
||||
*/
|
||||
void lis302dlWriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value) {
|
||||
|
||||
switch (reg) {
|
||||
default:
|
||||
/* Reserved register must not be written, according to the datasheet
|
||||
this could permanently damage the device.*/
|
||||
chDbgAssert(FALSE, "lis302dlWriteRegister(), #1", "reserved register");
|
||||
case LIS302DL_WHO_AM_I:
|
||||
case LIS302DL_HP_FILTER_RESET:
|
||||
case LIS302DL_STATUS_REG:
|
||||
case LIS302DL_OUTX:
|
||||
case LIS302DL_OUTY:
|
||||
case LIS302DL_OUTZ:
|
||||
case LIS302DL_FF_WU_SRC1:
|
||||
case LIS302DL_FF_WU_SRC2:
|
||||
case LIS302DL_CLICK_SRC:
|
||||
/* Read only registers cannot be written, the command is ignored.*/
|
||||
return;
|
||||
case LIS302DL_CTRL_REG1:
|
||||
case LIS302DL_CTRL_REG2:
|
||||
case LIS302DL_CTRL_REG3:
|
||||
case LIS302DL_FF_WU_CFG1:
|
||||
case LIS302DL_FF_WU_THS1:
|
||||
case LIS302DL_FF_WU_DURATION1:
|
||||
case LIS302DL_FF_WU_CFG2:
|
||||
case LIS302DL_FF_WU_THS2:
|
||||
case LIS302DL_FF_WU_DURATION2:
|
||||
case LIS302DL_CLICK_CFG:
|
||||
case LIS302DL_CLICK_THSY_X:
|
||||
case LIS302DL_CLICK_THSZ:
|
||||
case LIS302DL_CLICK_TIMELIMIT:
|
||||
case LIS302DL_CLICK_LATENCY:
|
||||
case LIS302DL_CLICK_WINDOW:
|
||||
spiSelect(spip);
|
||||
txbuf[0] = reg;
|
||||
txbuf[1] = value;
|
||||
spiSend(spip, 2, txbuf);
|
||||
spiUnselect(spip);
|
||||
}
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file lis302dl.h
|
||||
* @brief LIS302DL MEMS interface module through SPI header.
|
||||
*
|
||||
* @addtogroup lis302dl
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _LIS302DL_H_
|
||||
#define _LIS302DL_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name LIS302DL register names
|
||||
* @{
|
||||
*/
|
||||
#define LIS302DL_WHO_AM_I 0x0F
|
||||
#define LIS302DL_CTRL_REG1 0x20
|
||||
#define LIS302DL_CTRL_REG2 0x21
|
||||
#define LIS302DL_CTRL_REG3 0x22
|
||||
#define LIS302DL_HP_FILTER_RESET 0x23
|
||||
#define LIS302DL_STATUS_REG 0x27
|
||||
#define LIS302DL_OUTX 0x29
|
||||
#define LIS302DL_OUTY 0x2B
|
||||
#define LIS302DL_OUTZ 0x2D
|
||||
#define LIS302DL_FF_WU_CFG1 0x30
|
||||
#define LIS302DL_FF_WU_SRC1 0x31
|
||||
#define LIS302DL_FF_WU_THS1 0x32
|
||||
#define LIS302DL_FF_WU_DURATION1 0x33
|
||||
#define LIS302DL_FF_WU_CFG2 0x34
|
||||
#define LIS302DL_FF_WU_SRC2 0x35
|
||||
#define LIS302DL_FF_WU_THS2 0x36
|
||||
#define LIS302DL_FF_WU_DURATION2 0x37
|
||||
#define LIS302DL_CLICK_CFG 0x38
|
||||
#define LIS302DL_CLICK_SRC 0x39
|
||||
#define LIS302DL_CLICK_THSY_X 0x3B
|
||||
#define LIS302DL_CLICK_THSZ 0x3C
|
||||
#define LIS302DL_CLICK_TIMELIMIT 0x3D
|
||||
#define LIS302DL_CLICK_LATENCY 0x3E
|
||||
#define LIS302DL_CLICK_WINDOW 0x3F
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
uint8_t lis302dlReadRegister(SPIDriver *spip, uint8_t reg);
|
||||
void lis302dlWriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _LIS302DL_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* accelerometer.cpp
|
||||
*
|
||||
* @date May 19, 2016
|
||||
* @author Andrey Belomutskiy, (c) 2012-2016
|
||||
*/
|
||||
|
||||
#include "main.h"
|
||||
#include "lis302dl.h"
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* accelerometer.h
|
||||
*
|
||||
* @date May 19, 2016
|
||||
* @author Andrey Belomutskiy, (c) 2012-2016
|
||||
*/
|
||||
|
||||
#ifndef HW_LAYER_ACCELEROMETER_H_
|
||||
#define HW_LAYER_ACCELEROMETER_H_
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /* HW_LAYER_ACCELEROMETER_H_ */
|
||||
|
|
@ -29,5 +29,6 @@ HW_LAYER_EMS_CPP = $(HW_LAYER_EGT_CPP) \
|
|||
$(PROJECT_DIR)/hw_layer/gpio_helper.cpp \
|
||||
$(PROJECT_DIR)/hw_layer/stm32f4/mpu_util.cpp \
|
||||
$(PROJECT_DIR)/hw_layer/rtc_helper.cpp \
|
||||
$(PROJECT_DIR)/hw_layer/accelerometer.cpp \
|
||||
$(PROJECT_DIR)/hw_layer/wbo.cpp
|
||||
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
// This file was generated by Version2Header
|
||||
// Wed May 18 23:28:56 EDT 2016
|
||||
// Thu May 19 21:51:00 EDT 2016
|
||||
#ifndef VCS_VERSION
|
||||
#define VCS_VERSION "9912"
|
||||
#define VCS_VERSION "9916"
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue