diff --git a/.github/workflows/build-firmware.yaml b/.github/workflows/build-firmware.yaml index c3fff4d5e3..64d0058cc2 100644 --- a/.github/workflows/build-firmware.yaml +++ b/.github/workflows/build-firmware.yaml @@ -45,6 +45,7 @@ jobs: stm32f767_nucleo, stm32h743_nucleo, subaru_eg33_f7, + f429-discovery, atlas, ] @@ -177,6 +178,9 @@ jobs: folder: subaru_eg33 ini-file: rusefi_subaru_eg33_f7.ini + - build-target: f429-discovery + folder: f429-discovery + - build-target: atlas folder: atlas ini-file: rusefi_atlas.ini diff --git a/firmware/config/boards/f429-discovery/board.c b/firmware/config/boards/f429-discovery/board.c new file mode 100644 index 0000000000..933b240dbb --- /dev/null +++ b/firmware/config/boards/f429-discovery/board.c @@ -0,0 +1,422 @@ +/** + * @file boards/f429-discovery/board.c + * + * @date Jan 08, 2022 + * @author Andrey Gusakov, 2022 + */ + +#include "hal.h" +#include "hal_community.h" +#include "hal_sdram_lld.h" +/* for UNUSED() */ +#include "efilib.h" + +#include "board.h" + +/* + * SDRAM driver configuration structure. + */ +static const SDRAMConfig sdram_cfg = { + .sdcr = (uint32_t) (FMC_ColumnBits_Number_8b | + FMC_RowBits_Number_12b | + FMC_SDMemory_Width_16b | + FMC_InternalBank_Number_4 | + FMC_CAS_Latency_3 | + FMC_Write_Protection_Disable | + FMC_SDClock_Period_2 | + FMC_Read_Burst_Disable | + FMC_ReadPipe_Delay_1), + + .sdtr = (uint32_t)( (2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles) + (7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns)) + (4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns)) + (7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns)) + (2 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns)) + (2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns) + (2 << 24)), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns) + + .sdcmr = (uint32_t)(((4 - 1) << 5) | + ((FMC_SDCMR_MRD_BURST_LENGTH_2 | + FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL | + FMC_SDCMR_MRD_CAS_LATENCY_3 | + FMC_SDCMR_MRD_OPERATING_MODE_STANDARD | + FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9)), + + /* if (STM32_SYSCLK == 180000000) -> + 64ms / 4096 = 15.625us + 15.625us * 90MHz = 1406 - 20 = 1386 */ + //.sdrtr = (1386 << 1), + .sdrtr = (uint32_t)(683 << 1), +}; + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +#define SDRAM ((FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE) + +/** + * FMC_Command_Mode + */ +#define FMCCM_NORMAL ((uint32_t)0x00000000) +#define FMCCM_CLK_ENABLED ((uint32_t)0x00000001) +#define FMCCM_PALL ((uint32_t)0x00000002) +#define FMCCM_AUTO_REFRESH ((uint32_t)0x00000003) +#define FMCCM_LOAD_MODE ((uint32_t)0x00000004) +#define FMCCM_SELFREFRESH ((uint32_t)0x00000005) +#define FMCCM_POWER_DOWN ((uint32_t)0x00000006) + +static void __early_sdram_wait_ready(void) { + /* Wait until the SDRAM controller is ready */ + while (SDRAM->SDSR & FMC_SDSR_BUSY); +} + +static void __early_sdram_delay(void) +{ + /* something > 100uS */ + volatile int tmp = 168 * 1000 * 100; + + do { + tmp--; + } while(tmp); +} + +static void __early_sdram_init(const SDRAMConfig *config) +{ + uint32_t command_target = 0; + + #ifdef rccResetFSMC + rccResetFSMC(); + #endif + rccEnableFSMC(FALSE); + + SDRAM->SDCR1 = config->sdcr; + SDRAM->SDTR1 = config->sdtr; + SDRAM->SDCR2 = config->sdcr; + SDRAM->SDTR2 = config->sdtr; + +#if STM32_SDRAM_USE_SDRAM1 + command_target |= FMC_SDCMR_CTB1; +#endif +#if STM32_SDRAM_USE_SDRAM2 + command_target |= FMC_SDCMR_CTB2; +#endif + + /* Step 3: Configure a clock configuration enable command.*/ + __early_sdram_wait_ready(); + SDRAM->SDCMR = FMCCM_CLK_ENABLED | command_target; + + /* Step 4: Insert delay (tipically 100uS).*/ + __early_sdram_delay(); + + /* Step 5: Configure a PALL (precharge all) command.*/ + __early_sdram_wait_ready(); + SDRAM->SDCMR = FMCCM_PALL | command_target; + + /* Step 6.1: Configure a Auto-Refresh command: send the first command.*/ + __early_sdram_wait_ready(); + SDRAM->SDCMR = FMCCM_AUTO_REFRESH | command_target | + (config->sdcmr & FMC_SDCMR_NRFS); + + /* Step 6.2: Send the second command.*/ + __early_sdram_wait_ready(); + SDRAM->SDCMR = FMCCM_AUTO_REFRESH | command_target | + (config->sdcmr & FMC_SDCMR_NRFS); + + /* Step 7: Program the external memory mode register.*/ + __early_sdram_wait_ready(); + SDRAM->SDCMR = FMCCM_LOAD_MODE | command_target | + (config->sdcmr & FMC_SDCMR_MRD); + + /* Step 8: Set clock.*/ + __early_sdram_wait_ready(); + SDRAM->SDRTR = config->sdrtr & FMC_SDRTR_COUNT; + + __early_sdram_wait_ready(); +} + +static int __early_sdram_test(void *base, size_t size) +{ + size_t i; + uint32_t *ptr = base; + + /* test 0 */ + for (i = 0; i < size / sizeof(uint32_t); i++) { + ptr[i] = 0; + } + + for (i = 0; i < size / sizeof(uint32_t); i++) { + if (ptr[i] != 0) + return -1; + } + + /* test 1 */ + for (i = 0; i < size / sizeof(uint32_t); i++) { + ptr[i] = 0xffffffff; + } + + for (i = 0; i < size / sizeof(uint32_t); i++) { + if (ptr[i] != 0xffffffff) + return -1; + } + + /* test 2 */ + for (i = 0; i < size / sizeof(uint32_t); i++) { + ptr[i] = i; + } + + for (i = 0; i < size / sizeof(uint32_t); i++) { + if (ptr[i] != i) + return -1; + } + + return 0; +} + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); + + /* + * Initialise FSMC for SDRAM. + */ +#if 0 + /* clear driver struct */ + memset(&SDRAMD1, 0 sizeof(SDRAMD1)); + sdramInit(); + sdramStart(&SDRAMD1, &sdram_cfg); +#else + __early_sdram_init(&sdram_cfg); +#endif + + if (0) { + /* yes, hardcoded values */ + __early_sdram_test((void *) 0xD0000000, 8 * 1024 * 1024); + } +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) +{ + UNUSED(sdcp); + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) +{ + UNUSED(sdcp); + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) +{ + UNUSED(mmcp); + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) +{ + UNUSED(mmcp); + /* TODO: Fill the implementation.*/ + return false; +} +#endif diff --git a/firmware/config/boards/f429-discovery/board.h b/firmware/config/boards/f429-discovery/board.h new file mode 100644 index 0000000000..8a24867397 --- /dev/null +++ b/firmware/config/boards/f429-discovery/board.h @@ -0,0 +1,1430 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup for STMicroelectronics STM32F429I-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32F429I_DISCOVERY +#define BOARD_NAME "STMicroelectronics STM32F429I-Discovery" + +/* + * USB settings + */ +#define EFI_USB_AF 12U +//#define EFI_USB_SERIAL_ID GPIOA_10 +#define EFI_USB_SERIAL_DM GPIOB_14 +#define EFI_USB_SERIAL_DP GPIOB_15 + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 0U +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000U +#endif + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#ifndef STM32F429xx + #define STM32F429xx +#endif + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0U +#define GPIOA_MEMS_INT1 1U +#define GPIOA_MEMS_INT2 2U +#define GPIOA_LCD_B5 3U +#define GPIOA_LCD_VSYNC 4U +#define GPIOA_PIN5 5U +#define GPIOA_LCD_G2 6U +#define GPIOA_ACP_RST 7U +#define GPIOA_I2C3_SCL 8U +#define GPIOA_UART_TX 9U +#define GPIOA_UART_RX 10U +#define GPIOA_LCD_R4 11U +#define GPIOA_LCD_R5 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_TP_INT 15U + +#define GPIOB_LCD_R3 0U +#define GPIOB_LCD_R6 1U +#define GPIOB_BOOT1 2U +#define GPIOB_SWO 3U +#define GPIOB_PIN4 4U +#define GPIOB_FMC_SDCKE1 5U +#define GPIOB_FMC_SDNE1 6U +#define GPIOB_PIN7 7U +#define GPIOB_LCD_B6 8U +#define GPIOB_LCD_B7 9U +#define GPIOB_LCD_G4 10U +#define GPIOB_LCD_G5 11U +#define GPIOB_OTG_HS_ID 12U +#define GPIOB_OTG_HS_VBUS 13U +#define GPIOB_OTG_HS_DM 14U +#define GPIOB_OTG_HS_DP 15U + +#define GPIOC_FMC_SDNWE 0U +#define GPIOC_SPI5_MEMS_CS 1U +#define GPIOC_SPI5_LCD_CS 2U +#define GPIOC_PIN3 3U +#define GPIOC_OTG_HS_PSO 4U +#define GPIOC_OTG_HS_OC 5U +#define GPIOC_LCD_HSYNC 6U +#define GPIOC_LCD_G6 7U +#define GPIOC_PIN8 8U +#define GPIOC_I2C3_SDA 9U +#define GPIOC_LCD_R2 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_FMC_D2 0U +#define GPIOD_FMC_D3 1U +#define GPIOD_PIN2 2U +#define GPIOD_LCD_G7 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_LCD_B2 6U +#define GPIOD_PIN7 7U +#define GPIOD_FMC_D13 8U +#define GPIOD_FMC_D14 9U +#define GPIOD_FMC_D15 10U +#define GPIOD_LCD_TE 11U +#define GPIOD_LCD_RDX 12U +#define GPIOD_LCD_WRX 13U +#define GPIOD_FMC_D0 14U +#define GPIOD_FMC_D1 15U + +#define GPIOE_FMC_NBL0 0U +#define GPIOE_FMC_NBL1 1U +#define GPIOE_PIN2 2U +#define GPIOE_PIN3 3U +#define GPIOE_PIN4 4U +#define GPIOE_PIN5 5U +#define GPIOE_PIN6 6U +#define GPIOE_FMC_D4 7U +#define GPIOE_FMC_D5 8U +#define GPIOE_FMC_D6 9U +#define GPIOE_FMC_D7 10U +#define GPIOE_FMC_D8 11U +#define GPIOE_FMC_D9 12U +#define GPIOE_FMC_D10 13U +#define GPIOE_FMC_D11 14U +#define GPIOE_FMC_D12 15U + +#define GPIOF_FMC_A0 0U +#define GPIOF_FMC_A1 1U +#define GPIOF_FMC_A2 2U +#define GPIOF_FMC_A3 3U +#define GPIOF_FMC_A4 4U +#define GPIOF_FMC_A5 5U +#define GPIOF_PIN6 6U +#define GPIOF_LCD_DCX 7U +#define GPIOF_SPI5_MISO 8U +#define GPIOF_SPI5_MOSI 9U +#define GPIOF_LCD_DE 10U +#define GPIOF_FMC_SDNRAS 11U +#define GPIOF_FMC_A6 12U +#define GPIOF_FMC_A7 13U +#define GPIOF_FMC_A8 14U +#define GPIOF_FMC_A9 15U + +#define GPIOG_FMC_A10 0U +#define GPIOG_FMC_A11 1U +#define GPIOG_PIN2 2U +#define GPIOG_PIN3 3U +#define GPIOG_FMC_BA0 4U +#define GPIOG_FMC_BA1 5U +#define GPIOG_LCD_R7 6U +#define GPIOG_LCD_CLK 7U +#define GPIOG_FMC_SDCLK 8U +#define GPIOG_PIN9 9U +#define GPIOG_LCD_G3 10U +#define GPIOG_LCD_B3 11U +#define GPIOG_LCD_B4 12U +#define GPIOG_LED3_GREEN 13U +#define GPIOG_LED4_RED 14U +#define GPIOG_FMC_SDNCAS 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +#define GPIOI_PIN0 0U +#define GPIOI_PIN1 1U +#define GPIOI_PIN2 2U +#define GPIOI_PIN3 3U +#define GPIOI_PIN4 4U +#define GPIOI_PIN5 5U +#define GPIOI_PIN6 6U +#define GPIOI_PIN7 7U +#define GPIOI_PIN8 8U +#define GPIOI_PIN9 9U +#define GPIOI_PIN10 10U +#define GPIOI_PIN11 11U +#define GPIOI_PIN12 12U +#define GPIOI_PIN13 13U +#define GPIOI_PIN14 14U +#define GPIOI_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_BUTTON PAL_LINE(GPIOA, 0U) +#define LINE_MEMS_INT1 PAL_LINE(GPIOA, 1U) +#define LINE_MEMS_INT2 PAL_LINE(GPIOA, 2U) +#define LINE_LCD_B5 PAL_LINE(GPIOA, 3U) +#define LINE_LCD_VSYNC PAL_LINE(GPIOA, 4U) +#define LINE_LCD_G2 PAL_LINE(GPIOA, 6U) +#define LINE_ACP_RST PAL_LINE(GPIOA, 7U) +#define LINE_I2C3_SCL PAL_LINE(GPIOA, 8U) +#define LINE_UART_TX PAL_LINE(GPIOA, 9U) +#define LINE_UART_RX PAL_LINE(GPIOA, 10U) +#define LINE_LCD_R4 PAL_LINE(GPIOA, 11U) +#define LINE_LCD_R5 PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_TP_INT PAL_LINE(GPIOA, 15U) +#define LINE_LCD_R3 PAL_LINE(GPIOB, 0U) +#define LINE_LCD_R6 PAL_LINE(GPIOB, 1U) +#define LINE_BOOT1 PAL_LINE(GPIOB, 2U) +#define LINE_SWO PAL_LINE(GPIOB, 3U) +#define LINE_FMC_SDCKE1 PAL_LINE(GPIOB, 5U) +#define LINE_FMC_SDNE1 PAL_LINE(GPIOB, 6U) +#define LINE_LCD_B6 PAL_LINE(GPIOB, 8U) +#define LINE_LCD_B7 PAL_LINE(GPIOB, 9U) +#define LINE_LCD_G4 PAL_LINE(GPIOB, 10U) +#define LINE_LCD_G5 PAL_LINE(GPIOB, 11U) +#define LINE_OTG_HS_ID PAL_LINE(GPIOB, 12U) +#define LINE_OTG_HS_VBUS PAL_LINE(GPIOB, 13U) +#define LINE_OTG_HS_DM PAL_LINE(GPIOB, 14U) +#define LINE_OTG_HS_DP PAL_LINE(GPIOB, 15U) +#define LINE_FMC_SDNWE PAL_LINE(GPIOC, 0U) +#define LINE_SPI5_MEMS_CS PAL_LINE(GPIOC, 1U) +#define LINE_SPI5_LCD_CS PAL_LINE(GPIOC, 2U) +#define LINE_OTG_HS_PSO PAL_LINE(GPIOC, 4U) +#define LINE_OTG_HS_OC PAL_LINE(GPIOC, 5U) +#define LINE_LCD_HSYNC PAL_LINE(GPIOC, 6U) +#define LINE_LCD_G6 PAL_LINE(GPIOC, 7U) +#define LINE_I2C3_SDA PAL_LINE(GPIOC, 9U) +#define LINE_LCD_R2 PAL_LINE(GPIOC, 10U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) +#define LINE_FMC_D2 PAL_LINE(GPIOD, 0U) +#define LINE_FMC_D3 PAL_LINE(GPIOD, 1U) +#define LINE_LCD_G7 PAL_LINE(GPIOD, 3U) +#define LINE_LCD_B2 PAL_LINE(GPIOD, 6U) +#define LINE_FMC_D13 PAL_LINE(GPIOD, 8U) +#define LINE_FMC_D14 PAL_LINE(GPIOD, 9U) +#define LINE_FMC_D15 PAL_LINE(GPIOD, 10U) +#define LINE_LCD_TE PAL_LINE(GPIOD, 11U) +#define LINE_LCD_RDX PAL_LINE(GPIOD, 12U) +#define LINE_LCD_WRX PAL_LINE(GPIOD, 13U) +#define LINE_FMC_D0 PAL_LINE(GPIOD, 14U) +#define LINE_FMC_D1 PAL_LINE(GPIOD, 15U) +#define LINE_FMC_NBL0 PAL_LINE(GPIOE, 0U) +#define LINE_FMC_NBL1 PAL_LINE(GPIOE, 1U) +#define LINE_FMC_D4 PAL_LINE(GPIOE, 7U) +#define LINE_FMC_D5 PAL_LINE(GPIOE, 8U) +#define LINE_FMC_D6 PAL_LINE(GPIOE, 9U) +#define LINE_FMC_D7 PAL_LINE(GPIOE, 10U) +#define LINE_FMC_D8 PAL_LINE(GPIOE, 11U) +#define LINE_FMC_D9 PAL_LINE(GPIOE, 12U) +#define LINE_FMC_D10 PAL_LINE(GPIOE, 13U) +#define LINE_FMC_D11 PAL_LINE(GPIOE, 14U) +#define LINE_FMC_D12 PAL_LINE(GPIOE, 15U) +#define LINE_FMC_A0 PAL_LINE(GPIOF, 0U) +#define LINE_FMC_A1 PAL_LINE(GPIOF, 1U) +#define LINE_FMC_A2 PAL_LINE(GPIOF, 2U) +#define LINE_FMC_A3 PAL_LINE(GPIOF, 3U) +#define LINE_FMC_A4 PAL_LINE(GPIOF, 4U) +#define LINE_FMC_A5 PAL_LINE(GPIOF, 5U) +#define LINE_LCD_DCX PAL_LINE(GPIOF, 7U) +#define LINE_SPI5_MISO PAL_LINE(GPIOF, 8U) +#define LINE_SPI5_MOSI PAL_LINE(GPIOF, 9U) +#define LINE_LCD_DE PAL_LINE(GPIOF, 10U) +#define LINE_FMC_SDNRAS PAL_LINE(GPIOF, 11U) +#define LINE_FMC_A6 PAL_LINE(GPIOF, 12U) +#define LINE_FMC_A7 PAL_LINE(GPIOF, 13U) +#define LINE_FMC_A8 PAL_LINE(GPIOF, 14U) +#define LINE_FMC_A9 PAL_LINE(GPIOF, 15U) +#define LINE_FMC_A10 PAL_LINE(GPIOG, 0U) +#define LINE_FMC_A11 PAL_LINE(GPIOG, 1U) +#define LINE_FMC_BA0 PAL_LINE(GPIOG, 4U) +#define LINE_FMC_BA1 PAL_LINE(GPIOG, 5U) +#define LINE_LCD_R7 PAL_LINE(GPIOG, 6U) +#define LINE_LCD_CLK PAL_LINE(GPIOG, 7U) +#define LINE_FMC_SDCLK PAL_LINE(GPIOG, 8U) +#define LINE_LCD_G3 PAL_LINE(GPIOG, 10U) +#define LINE_LCD_B3 PAL_LINE(GPIOG, 11U) +#define LINE_LCD_B4 PAL_LINE(GPIOG, 12U) +#define LINE_LED3_GREEN PAL_LINE(GPIOG, 13U) +#define LINE_LED4_RED PAL_LINE(GPIOG, 14U) +#define LINE_FMC_SDNCAS PAL_LINE(GPIOG, 15U) +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON (input floating). + * PA1 - MEMS_INT1 (input floating). + * PA2 - MEMS_INT2 (input floating). + * PA3 - LCD_B5 (alternate 14). + * PA4 - LCD_VSYNC (alternate 14). + * PA5 - PIN5 (input pullup). + * PA6 - LCD_G2 (alternate 14). + * PA7 - ACP_RST (input pullup). + * PA8 - I2C3_SCL (alternate 4). + * PA9 - UART_TX (alternate 7). + * PA10 - UART_RX (alternate 7). + * PA11 - LCD_R4 (alternate 14). + * PA12 - LCD_R5 (alternate 14). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - TP_INT (input floating). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ + PIN_MODE_INPUT(GPIOA_MEMS_INT1) | \ + PIN_MODE_INPUT(GPIOA_MEMS_INT2) | \ + PIN_MODE_ALTERNATE(GPIOA_LCD_B5) | \ + PIN_MODE_ALTERNATE(GPIOA_LCD_VSYNC) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOA_LCD_G2) | \ + PIN_MODE_INPUT(GPIOA_ACP_RST) | \ + PIN_MODE_ALTERNATE(GPIOA_I2C3_SCL) | \ + PIN_MODE_ALTERNATE(GPIOA_UART_TX) | \ + PIN_MODE_ALTERNATE(GPIOA_UART_RX) | \ + PIN_MODE_ALTERNATE(GPIOA_LCD_R4) | \ + PIN_MODE_ALTERNATE(GPIOA_LCD_R5) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_TP_INT)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOA_MEMS_INT1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_MEMS_INT2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_B5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_VSYNC) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_G2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ACP_RST) | \ + PIN_OTYPE_OPENDRAIN(GPIOA_I2C3_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOA_UART_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_UART_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_R4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LCD_R5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_TP_INT)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_BUTTON) | \ + PIN_OSPEED_VERYLOW(GPIOA_MEMS_INT1) | \ + PIN_OSPEED_VERYLOW(GPIOA_MEMS_INT2) | \ + PIN_OSPEED_HIGH(GPIOA_LCD_B5) | \ + PIN_OSPEED_HIGH(GPIOA_LCD_VSYNC) | \ + PIN_OSPEED_VERYLOW(GPIOA_PIN5) | \ + PIN_OSPEED_HIGH(GPIOA_LCD_G2) | \ + PIN_OSPEED_VERYLOW(GPIOA_ACP_RST) | \ + PIN_OSPEED_HIGH(GPIOA_I2C3_SCL) | \ + PIN_OSPEED_VERYLOW(GPIOA_UART_TX) | \ + PIN_OSPEED_VERYLOW(GPIOA_UART_RX) | \ + PIN_OSPEED_HIGH(GPIOA_LCD_R4) | \ + PIN_OSPEED_HIGH(GPIOA_LCD_R5) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_VERYLOW(GPIOA_TP_INT)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ + PIN_PUPDR_FLOATING(GPIOA_MEMS_INT1) | \ + PIN_PUPDR_FLOATING(GPIOA_MEMS_INT2) | \ + PIN_PUPDR_FLOATING(GPIOA_LCD_B5) | \ + PIN_PUPDR_FLOATING(GPIOA_LCD_VSYNC) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOA_LCD_G2) | \ + PIN_PUPDR_PULLUP(GPIOA_ACP_RST) | \ + PIN_PUPDR_FLOATING(GPIOA_I2C3_SCL) | \ + PIN_PUPDR_PULLUP(GPIOA_UART_TX) | \ + PIN_PUPDR_PULLUP(GPIOA_UART_RX) | \ + PIN_PUPDR_FLOATING(GPIOA_LCD_R4) | \ + PIN_PUPDR_FLOATING(GPIOA_LCD_R5) | \ + PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ + PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ + PIN_PUPDR_FLOATING(GPIOA_TP_INT)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ + PIN_ODR_HIGH(GPIOA_MEMS_INT1) | \ + PIN_ODR_HIGH(GPIOA_MEMS_INT2) | \ + PIN_ODR_HIGH(GPIOA_LCD_B5) | \ + PIN_ODR_HIGH(GPIOA_LCD_VSYNC) | \ + PIN_ODR_HIGH(GPIOA_PIN5) | \ + PIN_ODR_HIGH(GPIOA_LCD_G2) | \ + PIN_ODR_HIGH(GPIOA_ACP_RST) | \ + PIN_ODR_HIGH(GPIOA_I2C3_SCL) | \ + PIN_ODR_HIGH(GPIOA_UART_TX) | \ + PIN_ODR_HIGH(GPIOA_UART_RX) | \ + PIN_ODR_HIGH(GPIOA_LCD_R4) | \ + PIN_ODR_HIGH(GPIOA_LCD_R5) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_TP_INT)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0U) | \ + PIN_AFIO_AF(GPIOA_MEMS_INT1, 0U) | \ + PIN_AFIO_AF(GPIOA_MEMS_INT2, 0U) | \ + PIN_AFIO_AF(GPIOA_LCD_B5, 14U) | \ + PIN_AFIO_AF(GPIOA_LCD_VSYNC, 14U) | \ + PIN_AFIO_AF(GPIOA_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOA_LCD_G2, 14U) | \ + PIN_AFIO_AF(GPIOA_ACP_RST, 0U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_I2C3_SCL, 4U) | \ + PIN_AFIO_AF(GPIOA_UART_TX, 7U) | \ + PIN_AFIO_AF(GPIOA_UART_RX, 7U) | \ + PIN_AFIO_AF(GPIOA_LCD_R4, 14U) | \ + PIN_AFIO_AF(GPIOA_LCD_R5, 14U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_TP_INT, 0U)) + +/* + * GPIOB setup: + * + * PB0 - LCD_R3 (alternate 14). + * PB1 - LCD_R6 (alternate 14). + * PB2 - BOOT1 (input pullup). + * PB3 - SWO (alternate 0). + * PB4 - PIN4 (input pullup). + * PB5 - FMC_SDCKE1 (alternate 12). + * PB6 - FMC_SDNE1 (alternate 12). + * PB7 - PIN7 (input pullup). + * PB8 - LCD_B6 (alternate 14). + * PB9 - LCD_B7 (alternate 14). + * PB10 - LCD_G4 (alternate 14). + * PB11 - LCD_G5 (alternate 14). + * PB12 - OTG_HS_ID (alternate 12). + * PB13 - OTG_HS_VBUS (input pulldown). + * PB14 - OTG_HS_DM (alternate 12). + * PB15 - OTG_HS_DP (alternate 12). + */ +#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(GPIOB_LCD_R3) | \ + PIN_MODE_ALTERNATE(GPIOB_LCD_R6) | \ + PIN_MODE_INPUT(GPIOB_BOOT1) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_ALTERNATE(GPIOB_FMC_SDCKE1) | \ + PIN_MODE_ALTERNATE(GPIOB_FMC_SDNE1) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_ALTERNATE(GPIOB_LCD_B6) | \ + PIN_MODE_ALTERNATE(GPIOB_LCD_B7) | \ + PIN_MODE_ALTERNATE(GPIOB_LCD_G4) | \ + PIN_MODE_ALTERNATE(GPIOB_LCD_G5) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) | \ + PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_LCD_R3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LCD_R6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_FMC_SDCKE1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_FMC_SDNE1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LCD_B6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LCD_B7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LCD_G4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LCD_G5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_VBUS) |\ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_LCD_R3) | \ + PIN_OSPEED_HIGH(GPIOB_LCD_R6) | \ + PIN_OSPEED_HIGH(GPIOB_BOOT1) | \ + PIN_OSPEED_HIGH(GPIOB_SWO) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \ + PIN_OSPEED_HIGH(GPIOB_FMC_SDCKE1) | \ + PIN_OSPEED_HIGH(GPIOB_FMC_SDNE1) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN7) | \ + PIN_OSPEED_HIGH(GPIOB_LCD_B6) | \ + PIN_OSPEED_HIGH(GPIOB_LCD_B7) | \ + PIN_OSPEED_HIGH(GPIOB_LCD_G4) | \ + PIN_OSPEED_HIGH(GPIOB_LCD_G5) | \ + PIN_OSPEED_HIGH(GPIOB_OTG_HS_ID) | \ + PIN_OSPEED_VERYLOW(GPIOB_OTG_HS_VBUS) |\ + PIN_OSPEED_HIGH(GPIOB_OTG_HS_DM) | \ + PIN_OSPEED_HIGH(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_LCD_R3) | \ + PIN_PUPDR_FLOATING(GPIOB_LCD_R6) | \ + PIN_PUPDR_PULLUP(GPIOB_BOOT1) | \ + PIN_PUPDR_FLOATING(GPIOB_SWO) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOB_FMC_SDCKE1) | \ + PIN_PUPDR_FLOATING(GPIOB_FMC_SDNE1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOB_LCD_B6) | \ + PIN_PUPDR_FLOATING(GPIOB_LCD_B7) | \ + PIN_PUPDR_FLOATING(GPIOB_LCD_G4) | \ + PIN_PUPDR_FLOATING(GPIOB_LCD_G5) | \ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_ID) | \ + PIN_PUPDR_PULLDOWN(GPIOB_OTG_HS_VBUS) |\ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) | \ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_LCD_R3) | \ + PIN_ODR_HIGH(GPIOB_LCD_R6) | \ + PIN_ODR_HIGH(GPIOB_BOOT1) | \ + PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_PIN4) | \ + PIN_ODR_HIGH(GPIOB_FMC_SDCKE1) | \ + PIN_ODR_HIGH(GPIOB_FMC_SDNE1) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_LCD_B6) | \ + PIN_ODR_HIGH(GPIOB_LCD_B7) | \ + PIN_ODR_HIGH(GPIOB_LCD_G4) | \ + PIN_ODR_HIGH(GPIOB_LCD_G5) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_ID) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_VBUS) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_DM) | \ + PIN_ODR_HIGH(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_LCD_R3, 14U) | \ + PIN_AFIO_AF(GPIOB_LCD_R6, 14U) | \ + PIN_AFIO_AF(GPIOB_BOOT1, 0U) | \ + PIN_AFIO_AF(GPIOB_SWO, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOB_FMC_SDCKE1, 12U) | \ + PIN_AFIO_AF(GPIOB_FMC_SDNE1, 12U) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_LCD_B6, 14U) | \ + PIN_AFIO_AF(GPIOB_LCD_B7, 14U) | \ + PIN_AFIO_AF(GPIOB_LCD_G4, 14U) | \ + PIN_AFIO_AF(GPIOB_LCD_G5, 14U) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12U) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_VBUS, 0U) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12U) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12U)) + +/* + * GPIOC setup: + * + * PC0 - FMC_SDNWE (alternate 12). + * PC1 - SPI5_MEMS_CS (output pushpull maximum). + * PC2 - SPI5_LCD_CS (output pushpull maximum). + * PC3 - PIN3 (input pullup). + * PC4 - OTG_HS_PSO (output pushpull maximum). + * PC5 - OTG_HS_OC (input floating). + * PC6 - LCD_HSYNC (alternate 14). + * PC7 - LCD_G6 (alternate 14). + * PC8 - PIN8 (input pullup). + * PC9 - I2C3_SDA (alternate 4). + * PC10 - LCD_R2 (alternate 14). + * PC11 - PIN11 (input pullup). + * PC12 - PIN12 (input pullup). + * PC13 - PIN13 (input pullup). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_ALTERNATE(GPIOC_FMC_SDNWE) | \ + PIN_MODE_OUTPUT(GPIOC_SPI5_MEMS_CS) | \ + PIN_MODE_OUTPUT(GPIOC_SPI5_LCD_CS) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_OUTPUT(GPIOC_OTG_HS_PSO) | \ + PIN_MODE_INPUT(GPIOC_OTG_HS_OC) | \ + PIN_MODE_ALTERNATE(GPIOC_LCD_HSYNC) | \ + PIN_MODE_ALTERNATE(GPIOC_LCD_G6) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_ALTERNATE(GPIOC_I2C3_SDA) | \ + PIN_MODE_ALTERNATE(GPIOC_LCD_R2) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_FMC_SDNWE) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI5_MEMS_CS) |\ + PIN_OTYPE_PUSHPULL(GPIOC_SPI5_LCD_CS) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OTG_HS_PSO) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OTG_HS_OC) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LCD_HSYNC) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LCD_G6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_OPENDRAIN(GPIOC_I2C3_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LCD_R2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_FMC_SDNWE) | \ + PIN_OSPEED_HIGH(GPIOC_SPI5_MEMS_CS) | \ + PIN_OSPEED_HIGH(GPIOC_SPI5_LCD_CS) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN3) | \ + PIN_OSPEED_HIGH(GPIOC_OTG_HS_PSO) | \ + PIN_OSPEED_HIGH(GPIOC_OTG_HS_OC) | \ + PIN_OSPEED_HIGH(GPIOC_LCD_HSYNC) | \ + PIN_OSPEED_HIGH(GPIOC_LCD_G6) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN8) | \ + PIN_OSPEED_HIGH(GPIOC_I2C3_SDA) | \ + PIN_OSPEED_HIGH(GPIOC_LCD_R2) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN13) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_FMC_SDNWE) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI5_MEMS_CS) |\ + PIN_PUPDR_FLOATING(GPIOC_SPI5_LCD_CS) |\ + PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOC_OTG_HS_PSO) | \ + PIN_PUPDR_FLOATING(GPIOC_OTG_HS_OC) | \ + PIN_PUPDR_FLOATING(GPIOC_LCD_HSYNC) | \ + PIN_PUPDR_FLOATING(GPIOC_LCD_G6) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOC_I2C3_SDA) | \ + PIN_PUPDR_FLOATING(GPIOC_LCD_R2) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_FMC_SDNWE) | \ + PIN_ODR_HIGH(GPIOC_SPI5_MEMS_CS) | \ + PIN_ODR_HIGH(GPIOC_SPI5_LCD_CS) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_OTG_HS_PSO) | \ + PIN_ODR_HIGH(GPIOC_OTG_HS_OC) | \ + PIN_ODR_HIGH(GPIOC_LCD_HSYNC) | \ + PIN_ODR_HIGH(GPIOC_LCD_G6) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_I2C3_SDA) | \ + PIN_ODR_HIGH(GPIOC_LCD_R2) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_FMC_SDNWE, 12U) | \ + PIN_AFIO_AF(GPIOC_SPI5_MEMS_CS, 0U) | \ + PIN_AFIO_AF(GPIOC_SPI5_LCD_CS, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOC_OTG_HS_PSO, 0U) | \ + PIN_AFIO_AF(GPIOC_OTG_HS_OC, 0U) | \ + PIN_AFIO_AF(GPIOC_LCD_HSYNC, 14U) | \ + PIN_AFIO_AF(GPIOC_LCD_G6, 14U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOC_I2C3_SDA, 4U) | \ + PIN_AFIO_AF(GPIOC_LCD_R2, 14U) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0 - FMC_D2 (alternate 12). + * PD1 - FMC_D3 (alternate 12). + * PD2 - PIN2 (input pullup). + * PD3 - LCD_G7 (alternate 14). + * PD4 - PIN4 (input pullup). + * PD5 - PIN5 (input pullup). + * PD6 - LCD_B2 (alternate 14). + * PD7 - PIN7 (input pullup). + * PD8 - FMC_D13 (alternate 12). + * PD9 - FMC_D14 (alternate 12). + * PD10 - FMC_D15 (alternate 12). + * PD11 - LCD_TE (input floating). + * PD12 - LCD_RDX (output pushpull maximum). + * PD13 - LCD_WRX (output pushpull maximum). + * PD14 - FMC_D0 (alternate 12). + * PD15 - FMC_D1 (alternate 12). + */ +#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_FMC_D2) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D3) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOD_LCD_G7) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOD_LCD_B2) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D13) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D14) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D15) | \ + PIN_MODE_INPUT(GPIOD_LCD_TE) | \ + PIN_MODE_OUTPUT(GPIOD_LCD_RDX) | \ + PIN_MODE_OUTPUT(GPIOD_LCD_WRX) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D0) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D1)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_FMC_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_G7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_B2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D15) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_TE) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_RDX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_WRX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D1)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_FMC_D2) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D3) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN2) | \ + PIN_OSPEED_HIGH(GPIOD_LCD_G7) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN5) | \ + PIN_OSPEED_HIGH(GPIOD_LCD_B2) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN7) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D13) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D14) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D15) | \ + PIN_OSPEED_HIGH(GPIOD_LCD_TE) | \ + PIN_OSPEED_HIGH(GPIOD_LCD_RDX) | \ + PIN_OSPEED_HIGH(GPIOD_LCD_WRX) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D0) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D1)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_FMC_D2) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D3) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOD_LCD_G7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOD_LCD_B2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D13) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D14) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D15) | \ + PIN_PUPDR_FLOATING(GPIOD_LCD_TE) | \ + PIN_PUPDR_FLOATING(GPIOD_LCD_RDX) | \ + PIN_PUPDR_FLOATING(GPIOD_LCD_WRX) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D0) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D1)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_FMC_D2) | \ + PIN_ODR_HIGH(GPIOD_FMC_D3) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_LCD_G7) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_LCD_B2) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_FMC_D13) | \ + PIN_ODR_HIGH(GPIOD_FMC_D14) | \ + PIN_ODR_HIGH(GPIOD_FMC_D15) | \ + PIN_ODR_HIGH(GPIOD_LCD_TE) | \ + PIN_ODR_HIGH(GPIOD_LCD_RDX) | \ + PIN_ODR_HIGH(GPIOD_LCD_WRX) | \ + PIN_ODR_HIGH(GPIOD_FMC_D0) | \ + PIN_ODR_HIGH(GPIOD_FMC_D1)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_FMC_D2, 12U) | \ + PIN_AFIO_AF(GPIOD_FMC_D3, 12U) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOD_LCD_G7, 14U) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOD_LCD_B2, 14U) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_FMC_D13, 12U) | \ + PIN_AFIO_AF(GPIOD_FMC_D14, 12U) | \ + PIN_AFIO_AF(GPIOD_FMC_D15, 12U) | \ + PIN_AFIO_AF(GPIOD_LCD_TE, 0U) | \ + PIN_AFIO_AF(GPIOD_LCD_RDX, 0U) | \ + PIN_AFIO_AF(GPIOD_LCD_WRX, 0U) | \ + PIN_AFIO_AF(GPIOD_FMC_D0, 12U) | \ + PIN_AFIO_AF(GPIOD_FMC_D1, 12U)) + +/* + * GPIOE setup: + * + * PE0 - FMC_NBL0 (alternate 12). + * PE1 - FMC_NBL1 (alternate 12). + * PE2 - PIN2 (input pullup). + * PE3 - PIN3 (input pullup). + * PE4 - PIN4 (input pullup). + * PE5 - PIN5 (input pullup). + * PE6 - PIN6 (input pullup). + * PE7 - FMC_D4 (alternate 12). + * PE8 - FMC_D5 (alternate 12). + * PE9 - FMC_D6 (alternate 12). + * PE10 - FMC_D7 (alternate 12). + * PE11 - FMC_D8 (alternate 12). + * PE12 - FMC_D9 (alternate 12). + * PE13 - FMC_D10 (alternate 12). + * PE14 - FMC_D11 (alternate 12). + * PE15 - FMC_D12 (alternate 12). + */ +#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(GPIOE_FMC_NBL0) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_NBL1) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D4) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D5) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D6) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D7) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D8) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D9) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D10) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D11) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D12)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D12)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_FMC_NBL0) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_NBL1) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN6) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D4) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D5) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D6) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D7) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D8) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D9) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D10) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D11) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D12)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_FMC_NBL0) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_NBL1) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D4) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D5) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D6) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D7) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D8) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D9) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D10) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D11) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D12)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_FMC_NBL0) | \ + PIN_ODR_HIGH(GPIOE_FMC_NBL1) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_FMC_D4) | \ + PIN_ODR_HIGH(GPIOE_FMC_D5) | \ + PIN_ODR_HIGH(GPIOE_FMC_D6) | \ + PIN_ODR_HIGH(GPIOE_FMC_D7) | \ + PIN_ODR_HIGH(GPIOE_FMC_D8) | \ + PIN_ODR_HIGH(GPIOE_FMC_D9) | \ + PIN_ODR_HIGH(GPIOE_FMC_D10) | \ + PIN_ODR_HIGH(GPIOE_FMC_D11) | \ + PIN_ODR_HIGH(GPIOE_FMC_D12)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_FMC_NBL0, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_NBL1, 12U) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOE_FMC_D4, 12U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_FMC_D5, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D6, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D7, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D8, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D9, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D10, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D11, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D12, 12U)) + +/* + * GPIOF setup: + * + * PF0 - FMC_A0 (alternate 12). + * PF1 - FMC_A1 (alternate 12). + * PF2 - FMC_A2 (alternate 12). + * PF3 - FMC_A3 (alternate 12). + * PF4 - FMC_A4 (alternate 12). + * PF5 - FMC_A5 (alternate 12). + * PF6 - PIN6 (input pullup). + * PF7 - LCD_DCX (alternate 5). + * PF8 - SPI5_MISO (alternate 5). + * PF9 - SPI5_MOSI (alternate 5). + * PF10 - LCD_DE (alternate 14). + * PF11 - FMC_SDNRAS (alternate 12). + * PF12 - FMC_A6 (alternate 12). + * PF13 - FMC_A7 (alternate 12). + * PF14 - FMC_A8 (alternate 12). + * PF15 - FMC_A9 (alternate 12). + */ +#define VAL_GPIOF_MODER (PIN_MODE_ALTERNATE(GPIOF_FMC_A0) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A1) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A2) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A3) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A4) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOF_LCD_DCX) | \ + PIN_MODE_ALTERNATE(GPIOF_SPI5_MISO) | \ + PIN_MODE_ALTERNATE(GPIOF_SPI5_MOSI) | \ + PIN_MODE_ALTERNATE(GPIOF_LCD_DE) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_SDNRAS) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A6) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A7) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A8) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A9)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_FMC_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_LCD_DCX) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SPI5_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SPI5_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOF_LCD_DE) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_SDNRAS) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A9)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_FMC_A0) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A1) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A2) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A3) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A4) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A5) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_LCD_DCX) | \ + PIN_OSPEED_HIGH(GPIOF_SPI5_MISO) | \ + PIN_OSPEED_HIGH(GPIOF_SPI5_MOSI) | \ + PIN_OSPEED_HIGH(GPIOF_LCD_DE) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_SDNRAS) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A6) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A7) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A8) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A9)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_FMC_A0) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A1) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A2) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A3) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A4) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOF_LCD_DCX) | \ + PIN_PUPDR_FLOATING(GPIOF_SPI5_MISO) | \ + PIN_PUPDR_FLOATING(GPIOF_SPI5_MOSI) | \ + PIN_PUPDR_FLOATING(GPIOF_LCD_DE) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_SDNRAS) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A6) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A7) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A8) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A9)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_FMC_A0) | \ + PIN_ODR_HIGH(GPIOF_FMC_A1) | \ + PIN_ODR_HIGH(GPIOF_FMC_A2) | \ + PIN_ODR_HIGH(GPIOF_FMC_A3) | \ + PIN_ODR_HIGH(GPIOF_FMC_A4) | \ + PIN_ODR_HIGH(GPIOF_FMC_A5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_LCD_DCX) | \ + PIN_ODR_HIGH(GPIOF_SPI5_MISO) | \ + PIN_ODR_HIGH(GPIOF_SPI5_MOSI) | \ + PIN_ODR_HIGH(GPIOF_LCD_DE) | \ + PIN_ODR_HIGH(GPIOF_FMC_SDNRAS) | \ + PIN_ODR_HIGH(GPIOF_FMC_A6) | \ + PIN_ODR_HIGH(GPIOF_FMC_A7) | \ + PIN_ODR_HIGH(GPIOF_FMC_A8) | \ + PIN_ODR_HIGH(GPIOF_FMC_A9)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_FMC_A0, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A1, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A2, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A3, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A4, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A5, 12U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_LCD_DCX, 5U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_SPI5_MISO, 5U) | \ + PIN_AFIO_AF(GPIOF_SPI5_MOSI, 5U) | \ + PIN_AFIO_AF(GPIOF_LCD_DE, 14U) | \ + PIN_AFIO_AF(GPIOF_FMC_SDNRAS, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A6, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A7, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A8, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A9, 12U)) + +/* + * GPIOG setup: + * + * PG0 - FMC_A10 (alternate 12). + * PG1 - FMC_A11 (alternate 12). + * PG2 - PIN2 (input pullup). + * PG3 - PIN3 (input pullup). + * PG4 - FMC_BA0 (alternate 12). + * PG5 - FMC_BA1 (alternate 12). + * PG6 - LCD_R7 (alternate 14). + * PG7 - LCD_CLK (alternate 14). + * PG8 - FMC_SDCLK (alternate 12). + * PG9 - PIN9 (input pullup). + * PG10 - LCD_G3 (alternate 14). + * PG11 - LCD_B3 (alternate 14). + * PG12 - LCD_B4 (alternate 14). + * PG13 - LED3_GREEN (output pushpull maximum). + * PG14 - LED4_RED (output pushpull maximum). + * PG15 - FMC_SDNCAS (alternate 12). + */ +#define VAL_GPIOG_MODER (PIN_MODE_ALTERNATE(GPIOG_FMC_A10) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_A11) | \ + PIN_MODE_INPUT(GPIOG_PIN2) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_BA0) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_BA1) | \ + PIN_MODE_ALTERNATE(GPIOG_LCD_R7) | \ + PIN_MODE_ALTERNATE(GPIOG_LCD_CLK) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_SDCLK) | \ + PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_ALTERNATE(GPIOG_LCD_G3) | \ + PIN_MODE_ALTERNATE(GPIOG_LCD_B3) | \ + PIN_MODE_ALTERNATE(GPIOG_LCD_B4) | \ + PIN_MODE_OUTPUT(GPIOG_LED3_GREEN) | \ + PIN_MODE_OUTPUT(GPIOG_LED4_RED) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_FMC_A10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_A11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LCD_R7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LCD_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LCD_G3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LCD_B3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LCD_B4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LED3_GREEN) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LED4_RED) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_FMC_A10) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_A11) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_BA0) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_BA1) | \ + PIN_OSPEED_HIGH(GPIOG_LCD_R7) | \ + PIN_OSPEED_HIGH(GPIOG_LCD_CLK) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_SDCLK) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \ + PIN_OSPEED_HIGH(GPIOG_LCD_G3) | \ + PIN_OSPEED_HIGH(GPIOG_LCD_B3) | \ + PIN_OSPEED_HIGH(GPIOG_LCD_B4) | \ + PIN_OSPEED_HIGH(GPIOG_LED3_GREEN) | \ + PIN_OSPEED_HIGH(GPIOG_LED4_RED) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_FMC_A10) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_A11) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_BA0) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_BA1) | \ + PIN_PUPDR_FLOATING(GPIOG_LCD_R7) | \ + PIN_PUPDR_FLOATING(GPIOG_LCD_CLK) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_SDCLK) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOG_LCD_G3) | \ + PIN_PUPDR_FLOATING(GPIOG_LCD_B3) | \ + PIN_PUPDR_FLOATING(GPIOG_LCD_B4) | \ + PIN_PUPDR_FLOATING(GPIOG_LED3_GREEN) | \ + PIN_PUPDR_FLOATING(GPIOG_LED4_RED) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_FMC_A10) | \ + PIN_ODR_HIGH(GPIOG_FMC_A11) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_FMC_BA0) | \ + PIN_ODR_HIGH(GPIOG_FMC_BA1) | \ + PIN_ODR_HIGH(GPIOG_LCD_R7) | \ + PIN_ODR_HIGH(GPIOG_LCD_CLK) | \ + PIN_ODR_HIGH(GPIOG_FMC_SDCLK) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_LCD_G3) | \ + PIN_ODR_HIGH(GPIOG_LCD_B3) | \ + PIN_ODR_HIGH(GPIOG_LCD_B4) | \ + PIN_ODR_LOW(GPIOG_LED3_GREEN) | \ + PIN_ODR_LOW(GPIOG_LED4_RED) | \ + PIN_ODR_HIGH(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_FMC_A10, 12U) | \ + PIN_AFIO_AF(GPIOG_FMC_A11, 12U) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOG_FMC_BA0, 12U) | \ + PIN_AFIO_AF(GPIOG_FMC_BA1, 12U) | \ + PIN_AFIO_AF(GPIOG_LCD_R7, 14U) | \ + PIN_AFIO_AF(GPIOG_LCD_CLK, 14U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_FMC_SDCLK, 12U) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOG_LCD_G3, 14U) | \ + PIN_AFIO_AF(GPIOG_LCD_B3, 14U) | \ + PIN_AFIO_AF(GPIOG_LCD_B4, 14U) | \ + PIN_AFIO_AF(GPIOG_LED3_GREEN, 0U) | \ + PIN_AFIO_AF(GPIOG_LED4_RED, 0U) | \ + PIN_AFIO_AF(GPIOG_FMC_SDNCAS, 12U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - PIN4 (input pullup). + * PI5 - PIN5 (input pullup). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). + * PI8 - PIN8 (input pullup). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). + * PI12 - PIN12 (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0U)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/firmware/config/boards/f429-discovery/board.mk b/firmware/config/boards/f429-discovery/board.mk index 09acd3ee6d..0a9540beca 100644 --- a/firmware/config/boards/f429-discovery/board.mk +++ b/firmware/config/boards/f429-discovery/board.mk @@ -1,5 +1,24 @@ BOARD_DIR = $(PROJECT_DIR)/config/boards/$(PROJECT_BOARD) -BOARDCPPSRC = $(BOARDS_DIR)/f429-discovery/board_configuration.cpp +HALCONFDIR = $(BOARD_DIR) +# List of all the board related files. +BOARDCPPSRC = $(BOARD_DIR)/board_configuration.cpp + +# Required include directories BOARDINC = $(BOARD_DIR) + +# STM32F429 has FSMC with SDRAM support +IS_STM32F429 = yes +EFI_HAS_EXT_SDRAM = yes + +# avoid any engine setup +DDEFS += -DDEFAULT_ENGINE_TYPE=MINIMAL_PINS + +#LED +DDEFS += -DLED_CRITICAL_ERROR_BRAIN_PIN=GPIOG_14 + +DDEFS += -DSTM32_FSMC_USE_FSMC1=TRUE -DSTM32_SDRAM_USE_SDRAM2=TRUE + +# Shared variables +ALLINC += $(BOARDINC) diff --git a/firmware/config/boards/f429-discovery/board_configuration.cpp b/firmware/config/boards/f429-discovery/board_configuration.cpp index 079d8be00b..99a29bb33e 100644 --- a/firmware/config/boards/f429-discovery/board_configuration.cpp +++ b/firmware/config/boards/f429-discovery/board_configuration.cpp @@ -8,3 +8,22 @@ void setSerialConfigurationOverrides(void) { void setSdCardConfigurationOverrides(void) { } + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) +{ + /* NOP */ +} + +/** + * @brief Board-specific configuration defaults. + * @todo Add your board-specific code, if any. + */ +void setBoardDefaultConfiguration(void) { + engineConfiguration->communicationLedPin = GPIO_UNASSIGNED; + engineConfiguration->runningLedPin = GPIOG_13; /* LD3 - green */ + engineConfiguration->warningLedPin = GPIO_UNASSIGNED; +} \ No newline at end of file diff --git a/firmware/config/boards/f429-discovery/halconf.h b/firmware/config/boards/f429-discovery/halconf.h index 9d1a8e3671..05c6d6e77e 100644 --- a/firmware/config/boards/f429-discovery/halconf.h +++ b/firmware/config/boards/f429-discovery/halconf.h @@ -1,533 +1,22 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - /** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. + * @file boards/f429-discovery/halconf.h * - * @addtogroup HAL_CONF - * @{ + * @brief In this header we can override halconf.h. + * + * @date Jan 08, 2022 + * @author Andrey Gusakov, 2022 */ -#ifndef HALCONF_H -#define HALCONF_H - -#define _CHIBIOS_HAL_CONF_ -#define _CHIBIOS_HAL_CONF_VER_7_1_ +#ifndef _HALCONF_F429_H_ +#define _HALCONF_F429_H_ +/* this file is exist just to include mcuconf.h from THIS directory */ #include "mcuconf.h" -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif +/* you can override some halconf defaults here */ -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN FALSE -#endif - -/** - * @brief Enables the cryptographic subsystem. - */ -#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) -#define HAL_USE_CRY FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EFlash subsystem. - */ -#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) -#define HAL_USE_EFL FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C FALSE -#endif - -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB TRUE -#endif - -/** - * @brief Enables the SIO subsystem. - */ -#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) -#define HAL_USE_SIO FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the TRNG subsystem. - */ -#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) -#define HAL_USE_TRNG FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB TRUE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/** - * @brief Enables the WSPI subsystem. - */ -#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) -#define HAL_USE_WSPI FALSE -#endif - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) -#define PAL_USE_CALLBACKS FALSE -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) -#define PAL_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/** - * @brief Enforces the driver to use direct callbacks rather than OSAL events. - */ -#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE -#endif - -/*===========================================================================*/ -/* CRY driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SW fall-back of the cryptographic driver. - * @details When enabled, this option, activates a fall-back software - * implementation for algorithms not supported by the underlying - * hardware. - * @note Fall-back implementations may not be present for all algorithms. - */ -#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_USE_FALLBACK FALSE -#endif - -/** - * @brief Makes the driver forcibly use the fall-back implementations. - */ -#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) -#define HAL_CRY_ENFORCE_FALLBACK FALSE -#endif - -/*===========================================================================*/ -/* DAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) -#define DAC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DAC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the zero-copy API. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/** - * @brief OCR initialization constant for V20 cards. - */ -#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) -#define SDC_INIT_OCR_V20 0x50FF8000U -#endif - -/** - * @brief OCR initialization constant for non-V20 cards. - */ -#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) -#define SDC_INIT_OCR 0x80100000U -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 38400 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 256 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 2 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables circular transfers APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) -#define SPI_USE_CIRCULAR FALSE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/** - * @brief Handling method for SPI CS line. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) -#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT FALSE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -/*===========================================================================*/ -/* WSPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) -#define WSPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define WSPI_USE_MUTUAL_EXCLUSION TRUE -#endif +#include "../../../hw_layer/ports/stm32/stm32f4/cfg/halconf.h" #include "halconf_community.h" -#endif /* HALCONF_H */ - -/** @} */ +#endif /* _HALCONF_F429_ */ diff --git a/firmware/config/boards/f429-discovery/halconf_community.h b/firmware/config/boards/f429-discovery/halconf_community.h index 8082fce338..fb0e159993 100644 --- a/firmware/config/boards/f429-discovery/halconf_community.h +++ b/firmware/config/boards/f429-discovery/halconf_community.h @@ -1,112 +1,20 @@ -/* - ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef HALCONF_COMMUNITY_H -#define HALCONF_COMMUNITY_H - /** - * @brief Enables the community overlay. + * @file boards/f429-discovery/halconf_community.h + * + * @brief In this header we can override defaults from halconf_community.h. + * + * @date Jan 08, 2022 + * @author Andrey Gusakov, 2022 */ -#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) -#define HAL_USE_COMMUNITY TRUE -#endif -/** - * @brief Enables the FSMC subsystem. - */ -#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#ifndef HALCONF_COMMUNITY_F429_H +#define HALCONF_COMMUNITY_F429_H + +/* Enable SDRAM support */ #define HAL_USE_FSMC TRUE -#endif - -/** - * @brief Enables the SDRAM subsystem. - */ -#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) #define HAL_USE_SDRAM TRUE -#endif -/** - * @brief Enables the SRAM subsystem. - */ -#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) -#define HAL_USE_SRAM FALSE -#endif +/* all other options are default */ +#include "../../../hw_layer/ports/stm32/cfg/halconf_community.h" -/** - * @brief Enables the NAND subsystem. - */ -#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) -#define HAL_USE_NAND FALSE -#endif - -/** - * @brief Enables the 1-wire subsystem. - */ -#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) -#define HAL_USE_ONEWIRE FALSE -#endif - -/** - * @brief Enables the EICU subsystem. - */ -#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) -#define HAL_USE_EICU FALSE -#endif - -/** - * @brief Enables the CRC subsystem. - */ -#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) -#define HAL_USE_CRC FALSE -#endif - -/** - * @brief Enables the RNG subsystem. - */ -#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) -#define HAL_USE_RNG FALSE -#endif - -/*===========================================================================*/ -/* FSMCNAND driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define NAND_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* 1-wire driver related settings. */ -/*===========================================================================*/ -/** - * @brief Enables strong pull up feature. - * @note Disabling this option saves both code and data space. - */ -#define ONEWIRE_USE_STRONG_PULLUP FALSE - -/** - * @brief Enables search ROM feature. - * @note Disabling this option saves both code and data space. - */ -#define ONEWIRE_USE_SEARCH_ROM TRUE - -#endif /* HALCONF_COMMUNITY_H */ - -/** @} */ +#endif /* HALCONF_COMMUNITY_F429_H */ diff --git a/firmware/config/boards/f429-discovery/mcuconf.h b/firmware/config/boards/f429-discovery/mcuconf.h index 5cefe593f9..d4b92b0477 100644 --- a/firmware/config/boards/f429-discovery/mcuconf.h +++ b/firmware/config/boards/f429-discovery/mcuconf.h @@ -1,363 +1,24 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32F4xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. +/** + * @file boards/f429-discovery/mcuconf.h * - * IRQ priorities: - * 15...0 Lowest...Highest. + * @brief In this header we can override mcuconf.h. * - * DMA priorities: - * 0...3 Lowest...Highest. + * @date Jan 08, 2022 + * @author Andrey Gusakov, 2022 */ -#define STM32F4xx_MCUCONF +#ifndef MCUCONF_F429_H +#define MCUCONF_F429_H -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 336 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK -#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 -#define STM32_I2SSRC STM32_I2SSRC_CKIN -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SR_VALUE 5 -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 FALSE -#define STM32_CAN_USE_CAN2 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 3 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 1000 -#define STM32_SDC_READ_TIMEOUT_MS 1000 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 TRUE -#define STM32_SERIAL_USE_USART2 FALSE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 TRUE -#define STM32_SPI_USE_SPI3 TRUE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_USE_SPI5 FALSE -#define STM32_SPI_USE_SPI6 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) -#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI5_DMA_PRIORITY 1 -#define STM32_SPI_SPI6_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_SPI5_IRQ_PRIORITY 10 -#define STM32_SPI_SPI6_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") +#include "../../../hw_layer/ports/stm32/stm32f4/cfg/mcuconf.h" /* * USB driver system settings. */ +#undef STM32_USB_USE_OTG1 #define STM32_USB_USE_OTG1 FALSE + +#undef STM32_USB_USE_OTG2 #define STM32_USB_USE_OTG2 TRUE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#include "mcuconf_community.h" - -#endif /* MCUCONF_H */ +#endif /* MCUCONF_F429_H */ diff --git a/firmware/config/boards/f429-discovery/mcuconf_community.h b/firmware/config/boards/f429-discovery/mcuconf_community.h deleted file mode 100644 index 2528ef4754..0000000000 --- a/firmware/config/boards/f429-discovery/mcuconf_community.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * FSMC driver system settings. - */ -#define STM32_FSMC_USE_FSMC1 TRUE -#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 -#define STM32_FSMC_DMA_CHN 0x03010201 - -/* - * FSMC NAND driver system settings. - */ -#define STM32_NAND_USE_NAND1 FALSE -#define STM32_NAND_USE_NAND2 FALSE -#define STM32_NAND_USE_EXT_INT FALSE -#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_NAND_DMA_PRIORITY 0 -#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") - -/* - * FSMC SRAM driver system settings. - */ -#define STM32_SRAM_USE_SRAM1 FALSE -#define STM32_SRAM_USE_SRAM2 FALSE -#define STM32_SRAM_USE_SRAM3 FALSE -#define STM32_SRAM_USE_SRAM4 FALSE - -/* - * FSMC SDRAM driver system settings. - */ -#define STM32_SDRAM_USE_SDRAM1 FALSE -#define STM32_SDRAM_USE_SDRAM2 TRUE - -/* - * LTDC driver system settings. - */ -#define STM32_LTDC_USE_LTDC TRUE -#define STM32_LTDC_EV_IRQ_PRIORITY 11 -#define STM32_LTDC_ER_IRQ_PRIORITY 11 - -/* - * DMA2D driver system settings. - */ -#define STM32_DMA2D_USE_DMA2D TRUE -#define STM32_DMA2D_IRQ_PRIORITY 11 diff --git a/firmware/hw_layer/ports/stm32/stm32f4/STM32F4.ld b/firmware/hw_layer/ports/stm32/stm32f4/STM32F4.ld index cb5f156188..32d9e26b79 100644 --- a/firmware/hw_layer/ports/stm32/stm32f4/STM32F4.ld +++ b/firmware/hw_layer/ports/stm32/stm32f4/STM32F4.ld @@ -29,9 +29,6 @@ RAM3_SIZE = DEFINED(STM32F4_HAS_SRAM3) ? 64k : 0; /* Only STM32F429I-Discovery has external SDRAM */ SDRAM_SIZE = DEFINED(STM32_HAS_SDRAM) ? 8M : 0; -/* SDRAM */ -SDRAM_SIZE = DEFINED(STM32F4_HAS_SDRAM) ? 8M : 0; - MEMORY { bl : org = 0x08000000, len = 16k /* bootloader section */