[DEFAULT]
projdir = .

[Options]
ExcellonLeadingZeros = 1
PanelWidth = 11.8
PanelHeight = 11.8
XSpacing = 0.1
YSpacing = 0.1
AllowMissingLayers = 0

[MergeOutputFiles]
Prefix = %(projdir)s/merged2layer
*TopLayer=%(prefix)s/Top.gbr
*BottomLayer=%(prefix)s/Bottom.gbr
*TopSilkscreen=%(prefix)s/TopSilk.gbr
*BottomSilkscreen=%(prefix)s/BottomSilk.gbr
*TopSoldermask=%(prefix)s/TopMask.gbr
*BottomSoldermask=%(prefix)s/BottomMask.gbr
Drills=%(prefix)s/Drills.txt
holes=%(prefix)s/Drills-unplated.txt
BoardOutline=%(prefix)s/BoardOutline.gbr
ToolList = %(prefix)s/Tools.drl
Placement = %(prefix)s/Placement.txt


[brain100]
Prefix=%(projdir)s/../brain_board/gerber/brain_board_STM32F407_R0.3/brain_board_STM32F407
*TopLayer=%(prefix)s-F.Cu.gtl
*BottomLayer=%(prefix)s-B.Cu.gbl
*TopSilkscreen=%(prefix)s-F.SilkS.gto
*TopSoldermask=%(prefix)s-F.Mask.gts
*BottomSilkscreen=%(prefix)s-B.SilkS.gbo
*BottomSoldermask=%(prefix)s-B.Mask.gbs
Drills=%(prefix)s_gm.drl
BoardOutline=%(prefix)s-Edge.Cuts.gm1

Repeat = 1

[connector64]
Prefix=%(projdir)s/../176122-6-connector/176122-6-mfg/176122-6-mfg_R0.2/176122-6
*TopLayer=%(prefix)s-Front.gtl
*BottomLayer=%(prefix)s-Back.gbl
*TopSilkscreen=%(prefix)s-F.SilkS.gto
*TopSoldermask=%(prefix)s-F.Mask.gts
*BottomSilkscreen=%(prefix)s-B.SilkS.gbo
*BottomSoldermask=%(prefix)s-B.Mask.gbs
Drills=%(prefix)s_gm.drl
BoardOutline=%(prefix)s-Edge.Cuts.gm1

Repeat = 2