mirror of https://github.com/rusefi/rusefi-1.git
406 lines
10 KiB
C++
406 lines
10 KiB
C++
/**
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* @file mpu_util.cpp
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*
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* @date Jul 27, 2014
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* @author Andrey Belomutskiy, (c) 2012-2018
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*/
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#include "main.h"
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#include "mpu_util.h"
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#include "error_handling.h"
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#include "engine.h"
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#include "pin_repository.h"
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#include "stm32f4xx_hal_flash.h"
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#include "rfiutil.h"
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EXTERN_ENGINE;
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extern "C" {
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void prvGetRegistersFromStack(uint32_t *pulFaultStackAddress);
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}
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extern uint32_t __main_stack_base__;
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#define GET_CFSR() (*((volatile uint32_t *) (0xE000ED28)))
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#if defined __GNUC__
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// GCC version
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typedef struct port_intctx intctx_t;
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int getRemainingStack(thread_t *otp) {
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#if CH_DBG_ENABLE_STACK_CHECK
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// this would dismiss coverity warning - see http://rusefi.com/forum/viewtopic.php?f=5&t=655
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// coverity[uninit_use]
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register intctx_t *r13 asm ("r13");
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otp->activeStack = r13;
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int remainingStack;
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if (ch.dbg.isr_cnt > 0) {
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remainingStack = 9999;
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// ISR context
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// todo remainingStack = (int)(r13 - 1) - (int)&__main_stack_base__;
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} else {
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remainingStack = 9999;
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// todo remainingStack = (int)(r13 - 1) - (int)otp->p_stklimit;
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}
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otp->remainingStack = remainingStack;
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return remainingStack;
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#else
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return 99999;
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#endif /* CH_DBG_ENABLE_STACK_CHECK */
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}
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#else /* __GNUC__ */
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extern uint32_t CSTACK$$Base; /* symbol created by the IAR linker */
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extern uint32_t IRQSTACK$$Base; /* symbol created by the IAR linker */
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int getRemainingStack(thread_t *otp) {
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#if CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
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int remainingStack;
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if (ch.dbg.isr_cnt > 0) {
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remainingStack = (__get_SP() - sizeof(port_intctx)) - (int)&IRQSTACK$$Base;
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} else {
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remainingStack = (__get_SP() - sizeof(port_intctx)) - (int)otp->p_stklimit;
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}
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otp->remainingStack = remainingStack;
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return remainingStack;
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#else
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return 999999;
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#endif
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}
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// IAR version
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#endif /* GNU / IAR */
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void baseHardwareInit(void) {
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// looks like this holds a random value on start? Let's set a nice clean zero
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DWT->CYCCNT = 0;
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BOR_Set(BOR_Level_1); // one step above default value
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}
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void DebugMonitorVector(void) {
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chDbgPanic3("DebugMonitorVector", __FILE__, __LINE__);
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while (TRUE)
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;
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}
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void UsageFaultVector(void) {
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chDbgPanic3("UsageFaultVector", __FILE__, __LINE__);
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while (TRUE)
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;
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}
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void BusFaultVector(void) {
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chDbgPanic3("BusFaultVector", __FILE__, __LINE__);
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while (TRUE) {
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}
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}
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/**
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+ * @brief Register values for postmortem debugging.
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+ */
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volatile uint32_t postmortem_r0;
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volatile uint32_t postmortem_r1;
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volatile uint32_t postmortem_r2;
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volatile uint32_t postmortem_r3;
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volatile uint32_t postmortem_r12;
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volatile uint32_t postmortem_lr; /* Link register. */
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volatile uint32_t postmortem_pc; /* Program counter. */
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volatile uint32_t postmortem_psr;/* Program status register. */
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volatile uint32_t postmortem_CFSR;
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volatile uint32_t postmortem_HFSR;
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volatile uint32_t postmortem_DFSR;
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volatile uint32_t postmortem_AFSR;
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volatile uint32_t postmortem_BFAR;
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volatile uint32_t postmortem_MMAR;
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volatile uint32_t postmortem_SCB_SHCSR;
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/**
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* @brief Evaluates to TRUE if system runs under debugger control.
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* @note This bit resets only by power reset.
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*/
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#define is_under_debugger() (((CoreDebug)->DHCSR) & \
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CoreDebug_DHCSR_C_DEBUGEN_Msk)
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/**
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*
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*/
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void prvGetRegistersFromStack(uint32_t *pulFaultStackAddress) {
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postmortem_r0 = pulFaultStackAddress[0];
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postmortem_r1 = pulFaultStackAddress[1];
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postmortem_r2 = pulFaultStackAddress[2];
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postmortem_r3 = pulFaultStackAddress[3];
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postmortem_r12 = pulFaultStackAddress[4];
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postmortem_lr = pulFaultStackAddress[5];
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postmortem_pc = pulFaultStackAddress[6];
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postmortem_psr = pulFaultStackAddress[7];
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/* Configurable Fault Status Register. Consists of MMSR, BFSR and UFSR */
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postmortem_CFSR = GET_CFSR();
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/* Hard Fault Status Register */
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postmortem_HFSR = (*((volatile uint32_t *) (0xE000ED2C)));
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/* Debug Fault Status Register */
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postmortem_DFSR = (*((volatile uint32_t *) (0xE000ED30)));
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/* Auxiliary Fault Status Register */
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postmortem_AFSR = (*((volatile uint32_t *) (0xE000ED3C)));
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/* Read the Fault Address Registers. These may not contain valid values.
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Check BFARVALID/MMARVALID to see if they are valid values
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MemManage Fault Address Register */
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postmortem_MMAR = (*((volatile uint32_t *) (0xE000ED34)));
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/* Bus Fault Address Register */
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postmortem_BFAR = (*((volatile uint32_t *) (0xE000ED38)));
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postmortem_SCB_SHCSR = SCB->SHCSR;
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if (is_under_debugger()) {
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__asm("BKPT #0\n");
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// Break into the debugger
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}
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/* harmless infinite loop */
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while (1) {
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;
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}
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}
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void HardFaultVector(void) {
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#if 0 && defined __GNUC__
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__asm volatile (
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" tst lr, #4 \n"
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" ite eq \n"
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" mrseq r0, msp \n"
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" mrsne r0, psp \n"
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" ldr r1, [r0, #24] \n"
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" ldr r2, handler2_address_const \n"
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" bx r2 \n"
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" handler2_address_const: .word prvGetRegistersFromStack \n"
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);
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#else
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#endif /* 0 && defined __GNUC__ */
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int cfsr = GET_CFSR();
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if (cfsr & 0x1) {
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chDbgPanic3("H IACCVIOL", __FILE__, __LINE__);
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} else if (cfsr & 0x100) {
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chDbgPanic3("H IBUSERR", __FILE__, __LINE__);
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} else if (cfsr & 0x20000) {
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chDbgPanic3("H INVSTATE", __FILE__, __LINE__);
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} else {
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chDbgPanic3("HardFaultVector", __FILE__, __LINE__);
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}
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while (TRUE) {
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}
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}
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#if HAL_USE_SPI || defined(__DOXYGEN__)
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bool isSpiInitialized[5] = { false, false, false, false, false };
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static int getSpiAf(SPIDriver *driver) {
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#if STM32_SPI_USE_SPI1
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if (driver == &SPID1) {
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return EFI_SPI1_AF;
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}
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#endif
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#if STM32_SPI_USE_SPI2
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if (driver == &SPID2) {
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return EFI_SPI2_AF;
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}
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#endif
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#if STM32_SPI_USE_SPI3
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if (driver == &SPID3) {
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return EFI_SPI3_AF;
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}
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#endif
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return -1;
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}
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brain_pin_e getMisoPin(spi_device_e device) {
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switch(device) {
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case SPI_DEVICE_1:
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return boardConfiguration->spi1misoPin;
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case SPI_DEVICE_2:
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return boardConfiguration->spi2misoPin;
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case SPI_DEVICE_3:
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return boardConfiguration->spi3misoPin;
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default:
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break;
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}
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return GPIO_UNASSIGNED;
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}
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brain_pin_e getMosiPin(spi_device_e device) {
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switch(device) {
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case SPI_DEVICE_1:
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return boardConfiguration->spi1mosiPin;
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case SPI_DEVICE_2:
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return boardConfiguration->spi2mosiPin;
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case SPI_DEVICE_3:
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return boardConfiguration->spi3mosiPin;
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default:
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break;
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}
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return GPIO_UNASSIGNED;
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}
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brain_pin_e getSckPin(spi_device_e device) {
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switch(device) {
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case SPI_DEVICE_1:
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return boardConfiguration->spi1sckPin;
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case SPI_DEVICE_2:
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return boardConfiguration->spi2sckPin;
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case SPI_DEVICE_3:
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return boardConfiguration->spi3sckPin;
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default:
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break;
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}
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return GPIO_UNASSIGNED;
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}
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void turnOnSpi(spi_device_e device) {
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if (isSpiInitialized[device])
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return; // already initialized
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isSpiInitialized[device] = true;
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if (device == SPI_DEVICE_1) {
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// todo: introduce a nice structure with all fields for same SPI
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#if STM32_SPI_USE_SPI1
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// scheduleMsg(&logging, "Turning on SPI1 pins");
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initSpiModule(&SPID1, getSckPin(device),
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getMisoPin(device),
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getMosiPin(device),
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engineConfiguration->spi1SckMode,
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engineConfiguration->spi1MosiMode,
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engineConfiguration->spi1MisoMode);
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#endif /* STM32_SPI_USE_SPI1 */
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}
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if (device == SPI_DEVICE_2) {
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#if STM32_SPI_USE_SPI2
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// scheduleMsg(&logging, "Turning on SPI2 pins");
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initSpiModule(&SPID2, getSckPin(device),
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getMisoPin(device),
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getMosiPin(device),
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engineConfiguration->spi2SckMode,
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engineConfiguration->spi2MosiMode,
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engineConfiguration->spi2MisoMode);
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#endif /* STM32_SPI_USE_SPI2 */
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}
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if (device == SPI_DEVICE_3) {
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#if STM32_SPI_USE_SPI3
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// scheduleMsg(&logging, "Turning on SPI3 pins");
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initSpiModule(&SPID3, getSckPin(device),
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getMisoPin(device),
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getMosiPin(device),
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engineConfiguration->spi3SckMode,
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engineConfiguration->spi3MosiMode,
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engineConfiguration->spi3MisoMode);
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#endif /* STM32_SPI_USE_SPI3 */
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}
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}
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void initSpiModule(SPIDriver *driver, brain_pin_e sck, brain_pin_e miso,
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brain_pin_e mosi,
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int sckMode,
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int mosiMode,
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int misoMode) {
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efiSetPadMode("SPI clock", sck, PAL_MODE_ALTERNATE(getSpiAf(driver)) + sckMode);
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efiSetPadMode("SPI master out", mosi, PAL_MODE_ALTERNATE(getSpiAf(driver)) + mosiMode);
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efiSetPadMode("SPI master in ", miso, PAL_MODE_ALTERNATE(getSpiAf(driver)) + misoMode);
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}
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void initSpiCs(SPIConfig *spiConfig, brain_pin_e csPin) {
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spiConfig->end_cb = NULL;
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ioportid_t port = getHwPort("spi", csPin);
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ioportmask_t pin = getHwPin("spi", csPin);
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spiConfig->ssport = port;
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spiConfig->sspad = pin;
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efiSetPadMode("chip select", csPin, PAL_STM32_MODE_OUTPUT);
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}
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#endif /* HAL_USE_SPI */
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BOR_Level_t BOR_Get(void) {
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FLASH_OBProgramInitTypeDef FLASH_Handle;
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/* Read option bytes */
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HAL_FLASHEx_OBGetConfig(&FLASH_Handle);
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/* Return BOR value */
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return (BOR_Level_t) FLASH_Handle.BORLevel;
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}
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BOR_Result_t BOR_Set(BOR_Level_t BORValue) {
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if (BOR_Get() == BORValue) {
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return BOR_Result_Ok;
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}
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FLASH_OBProgramInitTypeDef FLASH_Handle;
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FLASH_Handle.BORLevel = (uint32_t)BORValue;
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FLASH_Handle.OptionType = OPTIONBYTE_BOR;
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HAL_FLASH_OB_Unlock();
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HAL_FLASHEx_OBProgram(&FLASH_Handle);
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HAL_StatusTypeDef status = HAL_FLASH_OB_Launch();
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HAL_FLASH_OB_Lock();
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if (status != HAL_OK) {
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return BOR_Result_Error;
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}
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return BOR_Result_Ok;
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}
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#if EFI_CAN_SUPPORT || defined(__DOXYGEN__)
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static bool isValidCan1RxPin(brain_pin_e pin) {
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return pin == GPIOA_11 || pin == GPIOB_8 || pin == GPIOD_0;
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}
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static bool isValidCan1TxPin(brain_pin_e pin) {
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return pin == GPIOA_12 || pin == GPIOB_9 || GPIOD_1;
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}
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static bool isValidCan2RxPin(brain_pin_e pin) {
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return pin == GPIOB_5 || pin == GPIOB_12;
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}
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static bool isValidCan2TxPin(brain_pin_e pin) {
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return pin == GPIOB_6 || pin == GPIOB_13;
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}
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bool isValidCanTxPin(brain_pin_e pin) {
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return isValidCan1TxPin(pin) || isValidCan2TxPin(pin);
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}
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bool isValidCanRxPin(brain_pin_e pin) {
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return isValidCan1RxPin(pin) || isValidCan2RxPin(pin);
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}
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CANDriver * detectCanDevice(brain_pin_e pinRx, brain_pin_e pinTx) {
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if (isValidCan1RxPin(pinRx) && isValidCan1TxPin(pinTx))
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return &CAND1;
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if (isValidCan2RxPin(pinRx) && isValidCan2TxPin(pinTx))
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return &CAND2;
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return NULL;
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}
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#endif /* EFI_CAN_SUPPORT */
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