mirror of https://github.com/rusefi/rusefi-1.git
93 lines
2.4 KiB
C
93 lines
2.4 KiB
C
/**
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* @file boards/subarue-eg33/mcuconf.h
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*
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* @brief In this header we can override mcuconf.h.
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*
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* @date Feb 06, 2021
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* @author Andrey Gusakov, 2021
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*/
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#ifndef _MCUCONF_SUBARUEG33_H_
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#define _MCUCONF_SUBARUEG33_H_
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#include "../../../hw_layer/ports/stm32/stm32f7/cfg/mcuconf.h"
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//#undef STM32_LSE_ENABLED
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//#define STM32_LSE_ENABLED FALSE
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#undef STM32_RTCSEL
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#define STM32_RTCSEL STM32_RTCSEL_HSEDIV // STM32_RTCSEL_LSI
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/* serials and uarts */
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#undef STM32_SERIAL_USE_USART1
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#undef STM32_UART_USE_USART1
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#define STM32_SERIAL_USE_USART1 TRUE
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#define STM32_UART_USE_USART1 FALSE
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#undef STM32_SERIAL_USE_USART2
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#undef STM32_UART_USE_USART2
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#define STM32_SERIAL_USE_USART2 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#undef STM32_SERIAL_USE_USART3
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#undef STM32_UART_USE_USART3
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#define STM32_SERIAL_USE_USART3 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#undef STM32_UART_USE_USART3
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#define STM32_UART_USE_USART3 FALSE
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#undef STM32_UART_USE_UART4
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#define STM32_UART_USE_UART4 FALSE
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#undef STM32_USB_USE_OTG1
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#define STM32_USB_USE_OTG1 TRUE
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#undef STM32_USB_USE_USB1
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#define STM32_USB_USE_USB1 TRUE
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#undef STM32_I2C_USE_I2C1
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#define STM32_I2C_USE_I2C1 FALSE
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#undef STM32_SPI_USE_SPI2
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#define STM32_SPI_USE_SPI2 FALSE
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#undef STM32_SPI_USE_SPI4
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#define STM32_SPI_USE_SPI4 TRUE
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#undef STM32_SPI_USE_SPI5
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#define STM32_SPI_USE_SPI5 TRUE
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#undef STM32_ADC_USE_ADC3
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#define STM32_ADC_USE_ADC3 TRUE
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/* default STM32_DMA_STREAM_ID(2, 4) used by ADC1 */
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#undef STM32_SPI_SPI5_TX_DMA_STREAM
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#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
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/* STM32_DMA_STREAM_ID(2, 0) is used by SPI4_RX */
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#undef STM32_SDC_SDMMC2_DMA_STREAM
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#define STM32_SDC_SDMMC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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/* To remove futher possible conflict */
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#undef STM32_SPI_SPI6_RX_DMA_STREAM
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#undef STM32_CAN_USE_CAN2
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#define STM32_CAN_USE_CAN2 FALSE
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//#undef STM32_CAN_CAN1_IRQ_PRIORITY
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//#define STM32_CAN_CAN1_IRQ_PRIORITY 4
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/*
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* WSPI driver system settings.
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*/
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#define STM32_WSPI_USE_QUADSPI1 TRUE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define JEDEC_BUS_MODE JEDEC_BUS_MODE_WSPI4L
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/* QSPI is clocked from AHB clock, which is 216 MHz max
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* Maximum CLK rate for SST26VF is 104/80MHz for Fast Read and
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* Page program
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* 216 / 3 = 72 MHz */
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 3
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#endif /* _MCUCONF_SUBARUEG33_H_ */
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