mirror of https://github.com/rusefi/rusefi-1.git
102 lines
2.1 KiB
Plaintext
102 lines
2.1 KiB
Plaintext
(kicad_pcb (version 3) (host pcbnew "(2013-07-07 BZR 4022)-stable")
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(general
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(links 0)
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(no_connects 0)
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(area 0 0 0 0)
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(thickness 1.6)
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(drawings 0)
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(tracks 0)
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(zones 0)
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(modules 0)
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(nets 1)
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)
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(page A3)
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(layers
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(15 F.Cu signal)
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(0 B.Cu signal)
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(16 B.Adhes user)
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(17 F.Adhes user)
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(18 B.Paste user)
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(19 F.Paste user)
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(20 B.SilkS user)
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(21 F.SilkS user)
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(22 B.Mask user)
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(23 F.Mask user)
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(24 Dwgs.User user)
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(25 Cmts.User user)
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(26 Eco1.User user)
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(27 Eco2.User user)
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(28 Edge.Cuts user)
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)
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(setup
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(last_trace_width 0.254)
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(trace_clearance 0.254)
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(zone_clearance 0.508)
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(zone_45_only no)
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(trace_min 0.254)
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(segment_width 0.2)
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(edge_width 0.15)
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(via_size 0.889)
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(via_drill 0.635)
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(via_min_size 0.889)
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(via_min_drill 0.508)
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(uvia_size 0.508)
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(uvia_drill 0.127)
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(uvias_allowed no)
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(uvia_min_size 0.508)
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(uvia_min_drill 0.127)
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(pcb_text_width 0.3)
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(pcb_text_size 1.5 1.5)
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(mod_edge_width 0.15)
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(mod_text_size 1.5 1.5)
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(mod_text_width 0.15)
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(pad_size 1.4 1.4)
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(pad_drill 0.6)
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(pad_to_mask_clearance 0.2)
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(aux_axis_origin 0 0)
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(visible_elements FFFFFFBF)
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(pcbplotparams
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(layerselection 3178497)
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(usegerberextensions true)
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(excludeedgelayer true)
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(linewidth 0.150000)
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(plotframeref false)
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(viasonmask false)
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(mode 1)
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(useauxorigin false)
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(hpglpennumber 1)
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(hpglpenspeed 20)
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(hpglpendiameter 15)
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(hpglpenoverlay 2)
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(psnegative false)
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(psa4output false)
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(plotreference true)
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(plotvalue true)
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(plotothertext true)
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(plotinvisibletext false)
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(padsonsilk false)
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(subtractmaskfromsilk false)
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(outputformat 1)
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(mirror false)
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(drillshape 1)
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(scaleselection 1)
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(outputdirectory ""))
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)
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(net 0 "")
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(net_class Default "This is the default net class."
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(clearance 0.254)
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(trace_width 0.254)
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(via_dia 0.889)
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(via_drill 0.635)
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(uvia_dia 0.508)
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(uvia_drill 0.127)
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(add_net "")
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)
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)
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