58 lines
1.1 KiB
Prolog
58 lines
1.1 KiB
Prolog
|
update=Чтв 20 Фев 2014 17:40:11
|
||
|
|
version=1
|
||
|
|
last_client=pcbnew
|
||
|
|
[general]
|
||
|
|
version=1
|
||
|
|
[eeschema]
|
||
|
|
version=1
|
||
|
|
LibDir=../rusefi_lib
|
||
|
|
NetFmtName=
|
||
|
|
RptD_X=0
|
||
|
|
RptD_Y=100
|
||
|
|
RptLab=1
|
||
|
|
LabSize=60
|
||
|
|
[eeschema/libraries]
|
||
|
|
LibName1=power
|
||
|
|
LibName2=device
|
||
|
|
LibName3=conn
|
||
|
|
LibName4=logo_flipped
|
||
|
|
LibName5=art-electro-ic
|
||
|
|
LibName6=art-electro-conn
|
||
|
|
[cvpcb]
|
||
|
|
version=1
|
||
|
|
NetIExt=net
|
||
|
|
[cvpcb/libraries]
|
||
|
|
EquName1=devcms
|
||
|
|
[pcbnew]
|
||
|
|
version=1
|
||
|
|
LastNetListRead=
|
||
|
|
UseCmpFile=1
|
||
|
|
PadDrill=" 3,000000"
|
||
|
|
PadDrillOvalY=" 3,000000"
|
||
|
|
PadSizeH=" 3,000000"
|
||
|
|
PadSizeV=" 3,000000"
|
||
|
|
PcbTextSizeV=" 1,000000"
|
||
|
|
PcbTextSizeH=" 1,000000"
|
||
|
|
PcbTextThickness=" 0,300000"
|
||
|
|
ModuleTextSizeV=" 1,000000"
|
||
|
|
ModuleTextSizeH=" 1,000000"
|
||
|
|
ModuleTextSizeThickness=" 0,150000"
|
||
|
|
SolderMaskClearance=" 0,000000"
|
||
|
|
SolderMaskMinWidth=" 0,000000"
|
||
|
|
DrawSegmentWidth=" 0,200000"
|
||
|
|
BoardOutlineThickness=" 0,150000"
|
||
|
|
ModuleOutlineThickness=" 0,150000"
|
||
|
|
[pcbnew/libraries]
|
||
|
|
LibDir=../rusefi_lib
|
||
|
|
LibName1=connect
|
||
|
|
LibName2=pin_array
|
||
|
|
LibName3=divers
|
||
|
|
LibName4=smd_capacitors
|
||
|
|
LibName5=smd_resistors
|
||
|
|
LibName6=smd_dil
|
||
|
|
LibName7=libcms
|
||
|
|
LibName8=led
|
||
|
|
LibName9=art-electro-conn
|
||
|
|
LibName10=logo_flipped
|
||
|
|
LibName11=art-electro-conn_2
|