55 lines
1.1 KiB
Prolog
55 lines
1.1 KiB
Prolog
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update=Пт 28 фев 2014 10:16:27
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last_client=cvpcb
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[common]
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NetDir=
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[general]
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version=1
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[pcbnew]
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version=1
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LastNetListRead=cps_vrs_io_1.net
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UseCmpFile=1
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PadDrill=0.600000000000
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PadDrillOvalY=0.600000000000
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PadSizeH=0.350520000000
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PadSizeV=0.701040000000
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PcbTextSizeV=2.032000000000
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PcbTextSizeH=1.524000000000
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PcbTextThickness=0.431800000000
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ModuleTextSizeV=1.524000000000
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ModuleTextSizeH=1.524000000000
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ModuleTextSizeThickness=0.254000000000
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SolderMaskClearance=0.254000000000
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SolderMaskMinWidth=0.000000000000
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DrawSegmentWidth=0.254000000000
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BoardOutlineThickness=0.254000000000
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ModuleOutlineThickness=0.099060000000
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[pcbnew/libraries]
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LibName1=connect
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LibName2=pin_array
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LibName3=libcms
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LibName4=logo_flipped
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LibName5=art-electro-conn
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LibDir=../rusefi_lib
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[eeschema]
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version=1
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LibDir=../rusefi_lib
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NetFmtName=
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RptD_X=0
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RptD_Y=100
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RptLab=1
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LabSize=60
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[eeschema/libraries]
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LibName1=power
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LibName2=device
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LibName3=conn
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LibName4=linear
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LibName5=interface
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LibName6=sch-libs/project_specific_libs
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LibName7=logo_flipped
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LibName8=art-electro-conn
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[cvpcb]
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version=1
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NetIExt=net
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[cvpcb/libraries]
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EquName1=devcms
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