DRAM SDRAM #2551
This commit is contained in:
Andrey
parent
82439b3ffd
commit
3db0933244
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BOARD_DIR = $(PROJECT_DIR)/config/boards/$(PROJECT_BOARD)
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BOARDINC = $(BOARD_DIR)
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#!/bin/bash
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export PROJECT_BOARD=f429-discovery
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export PROJECT_CPU=ARCH_STM32F4
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export EXTRA_PARAMS=-DSHORT_BOARD_NAME=f429-discovery
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#-DDUMMY -DEFI_ENABLE_ASSERTS=FALSE -DCH_DBG_ENABLE_ASSERTS=FALSE -DCH_DBG_ENABLE_STACK_CHECK=FALSE -DCH_DBG_FILL_THREADS=FALSE -DCH_DBG_THREADS_PROFILING=FALSE"
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bash ../common_make.sh
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file templates/halconf.h
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* @brief HAL configuration header.
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* @details HAL configuration file, this file allows to enable or disable the
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* various device drivers from your application. You may also use
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* this file in order to override the device drivers default settings.
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*
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* @addtogroup HAL_CONF
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* @{
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*/
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#ifndef HALCONF_H
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#define HALCONF_H
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#define _CHIBIOS_HAL_CONF_
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#define _CHIBIOS_HAL_CONF_VER_7_1_
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#include "mcuconf.h"
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/**
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* @brief Enables the PAL subsystem.
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*/
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#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
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#define HAL_USE_PAL TRUE
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#endif
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/**
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* @brief Enables the ADC subsystem.
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*/
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#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
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#define HAL_USE_ADC FALSE
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#endif
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/**
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* @brief Enables the CAN subsystem.
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*/
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#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
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#define HAL_USE_CAN FALSE
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#endif
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/**
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* @brief Enables the cryptographic subsystem.
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*/
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#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
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#define HAL_USE_CRY FALSE
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#endif
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/**
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* @brief Enables the DAC subsystem.
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*/
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#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
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#define HAL_USE_DAC FALSE
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#endif
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/**
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* @brief Enables the EFlash subsystem.
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*/
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#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)
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#define HAL_USE_EFL FALSE
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#endif
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/**
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* @brief Enables the GPT subsystem.
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*/
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#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
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#define HAL_USE_GPT FALSE
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#endif
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/**
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* @brief Enables the I2C subsystem.
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*/
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#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
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#define HAL_USE_I2C FALSE
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#endif
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/**
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* @brief Enables the I2S subsystem.
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*/
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#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
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#define HAL_USE_I2S FALSE
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#endif
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/**
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* @brief Enables the ICU subsystem.
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*/
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#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
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#define HAL_USE_ICU FALSE
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#endif
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/**
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* @brief Enables the MAC subsystem.
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*/
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#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
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#define HAL_USE_MAC FALSE
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#endif
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/**
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* @brief Enables the MMC_SPI subsystem.
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*/
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#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
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#define HAL_USE_MMC_SPI FALSE
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#endif
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/**
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* @brief Enables the PWM subsystem.
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*/
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#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
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#define HAL_USE_PWM FALSE
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#endif
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/**
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* @brief Enables the RTC subsystem.
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*/
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#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
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#define HAL_USE_RTC FALSE
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#endif
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/**
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* @brief Enables the SDC subsystem.
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*/
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#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
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#define HAL_USE_SDC FALSE
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#endif
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/**
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* @brief Enables the SERIAL subsystem.
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*/
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#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
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#define HAL_USE_SERIAL TRUE
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#endif
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/**
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* @brief Enables the SERIAL over USB subsystem.
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*/
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#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
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#define HAL_USE_SERIAL_USB TRUE
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#endif
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/**
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* @brief Enables the SIO subsystem.
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*/
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#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
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#define HAL_USE_SIO FALSE
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#endif
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/**
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* @brief Enables the SPI subsystem.
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*/
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#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
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#define HAL_USE_SPI TRUE
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#endif
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/**
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* @brief Enables the TRNG subsystem.
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*/
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#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
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#define HAL_USE_TRNG FALSE
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#endif
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/**
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* @brief Enables the UART subsystem.
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*/
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#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
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#define HAL_USE_UART FALSE
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#endif
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/**
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* @brief Enables the USB subsystem.
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*/
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#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
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#define HAL_USE_USB TRUE
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#endif
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/**
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* @brief Enables the WDG subsystem.
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*/
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#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
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#define HAL_USE_WDG FALSE
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#endif
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/**
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* @brief Enables the WSPI subsystem.
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*/
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#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
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#define HAL_USE_WSPI FALSE
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#endif
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/*===========================================================================*/
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/* PAL driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Enables synchronous APIs.
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* @note Disabling this option saves both code and data space.
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*/
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#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
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#define PAL_USE_CALLBACKS FALSE
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#endif
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/**
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* @brief Enables synchronous APIs.
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* @note Disabling this option saves both code and data space.
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*/
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#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
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#define PAL_USE_WAIT FALSE
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#endif
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/*===========================================================================*/
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/* ADC driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Enables synchronous APIs.
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* @note Disabling this option saves both code and data space.
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*/
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#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
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#define ADC_USE_WAIT TRUE
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#endif
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/**
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* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
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* @note Disabling this option saves both code and data space.
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*/
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#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
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#define ADC_USE_MUTUAL_EXCLUSION TRUE
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#endif
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/*===========================================================================*/
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/* CAN driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Sleep mode related APIs inclusion switch.
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*/
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#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
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#define CAN_USE_SLEEP_MODE TRUE
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#endif
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/**
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* @brief Enforces the driver to use direct callbacks rather than OSAL events.
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*/
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#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
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#define CAN_ENFORCE_USE_CALLBACKS FALSE
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#endif
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/*===========================================================================*/
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/* CRY driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Enables the SW fall-back of the cryptographic driver.
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* @details When enabled, this option, activates a fall-back software
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* implementation for algorithms not supported by the underlying
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* hardware.
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* @note Fall-back implementations may not be present for all algorithms.
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*/
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#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
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#define HAL_CRY_USE_FALLBACK FALSE
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#endif
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/**
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* @brief Makes the driver forcibly use the fall-back implementations.
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*/
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#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
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#define HAL_CRY_ENFORCE_FALLBACK FALSE
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#endif
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/*===========================================================================*/
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/* DAC driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Enables synchronous APIs.
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* @note Disabling this option saves both code and data space.
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*/
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#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
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#define DAC_USE_WAIT TRUE
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#endif
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/**
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* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
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* @note Disabling this option saves both code and data space.
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*/
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#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
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#define DAC_USE_MUTUAL_EXCLUSION TRUE
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#endif
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/*===========================================================================*/
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/* I2C driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Enables the mutual exclusion APIs on the I2C bus.
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*/
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#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
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#define I2C_USE_MUTUAL_EXCLUSION TRUE
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#endif
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/*===========================================================================*/
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/* MAC driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Enables the zero-copy API.
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*/
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#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
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#define MAC_USE_ZERO_COPY FALSE
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#endif
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/**
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* @brief Enables an event sources for incoming packets.
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*/
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#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
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#define MAC_USE_EVENTS TRUE
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#endif
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/*===========================================================================*/
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/* MMC_SPI driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Delays insertions.
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* @details If enabled this options inserts delays into the MMC waiting
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* routines releasing some extra CPU time for the threads with
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* lower priority, this may slow down the driver a bit however.
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* This option is recommended also if the SPI driver does not
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* use a DMA channel and heavily loads the CPU.
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*/
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#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
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#define MMC_NICE_WAITING TRUE
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#endif
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/*===========================================================================*/
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/* SDC driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Number of initialization attempts before rejecting the card.
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* @note Attempts are performed at 10mS intervals.
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*/
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#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
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#define SDC_INIT_RETRY 100
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#endif
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/**
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* @brief Include support for MMC cards.
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* @note MMC support is not yet implemented so this option must be kept
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* at @p FALSE.
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*/
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#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
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#define SDC_MMC_SUPPORT FALSE
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#endif
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/**
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* @brief Delays insertions.
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* @details If enabled this options inserts delays into the MMC waiting
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* routines releasing some extra CPU time for the threads with
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* lower priority, this may slow down the driver a bit however.
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*/
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#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
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#define SDC_NICE_WAITING TRUE
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#endif
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/**
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* @brief OCR initialization constant for V20 cards.
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*/
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#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
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#define SDC_INIT_OCR_V20 0x50FF8000U
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#endif
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/**
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* @brief OCR initialization constant for non-V20 cards.
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*/
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#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
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#define SDC_INIT_OCR 0x80100000U
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#endif
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/*===========================================================================*/
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/* SERIAL driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Default bit rate.
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* @details Configuration parameter, this is the baud rate selected for the
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* default configuration.
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*/
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#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
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#define SERIAL_DEFAULT_BITRATE 38400
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#endif
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/**
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* @brief Serial buffers size.
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* @details Configuration parameter, you can change the depth of the queue
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* buffers depending on the requirements of your application.
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* @note The default is 16 bytes for both the transmission and receive
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* buffers.
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*/
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#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
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#define SERIAL_BUFFERS_SIZE 16
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#endif
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/*===========================================================================*/
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/* SERIAL_USB driver related setting. */
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/*===========================================================================*/
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/**
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* @brief Serial over USB buffers size.
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* @details Configuration parameter, the buffer size must be a multiple of
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* the USB data endpoint maximum packet size.
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* @note The default is 256 bytes for both the transmission and receive
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* buffers.
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*/
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#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
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#define SERIAL_USB_BUFFERS_SIZE 256
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#endif
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/**
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* @brief Serial over USB number of buffers.
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* @note The default is 2 buffers.
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*/
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#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
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#define SERIAL_USB_BUFFERS_NUMBER 2
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#endif
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/*===========================================================================*/
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/* SPI driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Enables synchronous APIs.
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* @note Disabling this option saves both code and data space.
|
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*/
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#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
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#define SPI_USE_WAIT TRUE
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#endif
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/**
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* @brief Enables circular transfers APIs.
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* @note Disabling this option saves both code and data space.
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*/
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#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
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#define SPI_USE_CIRCULAR FALSE
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#endif
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/**
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* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
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* @note Disabling this option saves both code and data space.
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*/
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#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
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#define SPI_USE_MUTUAL_EXCLUSION TRUE
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#endif
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/**
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* @brief Handling method for SPI CS line.
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* @note Disabling this option saves both code and data space.
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*/
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#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
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#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
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#endif
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/*===========================================================================*/
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/* UART driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
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#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
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#define UART_USE_WAIT FALSE
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#endif
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/**
|
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* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
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* @note Disabling this option saves both code and data space.
|
||||
*/
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#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
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#define UART_USE_MUTUAL_EXCLUSION FALSE
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#endif
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/*===========================================================================*/
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/* USB driver related settings. */
|
||||
/*===========================================================================*/
|
||||
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/**
|
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* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
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#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
|
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#define USB_USE_WAIT FALSE
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#endif
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|
||||
/*===========================================================================*/
|
||||
/* WSPI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define WSPI_USE_WAIT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
#include "halconf_community.h"
|
||||
|
||||
#endif /* HALCONF_H */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef HALCONF_COMMUNITY_H
|
||||
#define HALCONF_COMMUNITY_H
|
||||
|
||||
/**
|
||||
* @brief Enables the community overlay.
|
||||
*/
|
||||
#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_COMMUNITY TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the FSMC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_FSMC TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SDRAM subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SDRAM TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SRAM subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SRAM FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the NAND subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_NAND FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the 1-wire subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_ONEWIRE FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the EICU subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_EICU FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the CRC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_CRC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the RNG subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_RNG FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* FSMCNAND driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define NAND_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* 1-wire driver related settings. */
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @brief Enables strong pull up feature.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#define ONEWIRE_USE_STRONG_PULLUP FALSE
|
||||
|
||||
/**
|
||||
* @brief Enables search ROM feature.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#define ONEWIRE_USE_SEARCH_ROM TRUE
|
||||
|
||||
#endif /* HALCONF_COMMUNITY_H */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,363 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
/*
|
||||
* STM32F4xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32F4xx_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT FALSE
|
||||
#define STM32_HSI_ENABLED TRUE
|
||||
#define STM32_LSI_ENABLED TRUE
|
||||
#define STM32_HSE_ENABLED TRUE
|
||||
#define STM32_LSE_ENABLED FALSE
|
||||
#define STM32_CLOCK48_REQUIRED TRUE
|
||||
#define STM32_SW STM32_SW_PLL
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||
#define STM32_PLLM_VALUE 8
|
||||
#define STM32_PLLN_VALUE 336
|
||||
#define STM32_PLLP_VALUE 2
|
||||
#define STM32_PLLQ_VALUE 7
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV4
|
||||
#define STM32_PPRE2 STM32_PPRE2_DIV2
|
||||
#define STM32_RTCSEL STM32_RTCSEL_LSI
|
||||
#define STM32_RTCPRE_VALUE 8
|
||||
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
|
||||
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
|
||||
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
|
||||
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
|
||||
#define STM32_I2SSRC STM32_I2SSRC_CKIN
|
||||
#define STM32_PLLI2SN_VALUE 192
|
||||
#define STM32_PLLI2SR_VALUE 5
|
||||
#define STM32_PVD_ENABLE FALSE
|
||||
#define STM32_PLS STM32_PLS_LEV0
|
||||
#define STM32_BKPRAM_ENABLE FALSE
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI1_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI2_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI3_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI4_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI16_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI17_PRIORITY 15
|
||||
#define STM32_IRQ_EXTI18_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI19_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI20_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI21_PRIORITY 15
|
||||
#define STM32_IRQ_EXTI22_PRIORITY 15
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#define STM32_ADC_USE_ADC2 FALSE
|
||||
#define STM32_ADC_USE_ADC3 FALSE
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
|
||||
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY 2
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY 2
|
||||
#define STM32_ADC_IRQ_PRIORITY 6
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 FALSE
|
||||
#define STM32_CAN_USE_CAN2 FALSE
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
|
||||
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE FALSE
|
||||
#define STM32_DAC_USE_DAC1_CH1 FALSE
|
||||
#define STM32_DAC_USE_DAC1_CH2 FALSE
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 FALSE
|
||||
#define STM32_GPT_USE_TIM2 FALSE
|
||||
#define STM32_GPT_USE_TIM3 FALSE
|
||||
#define STM32_GPT_USE_TIM4 FALSE
|
||||
#define STM32_GPT_USE_TIM5 FALSE
|
||||
#define STM32_GPT_USE_TIM6 FALSE
|
||||
#define STM32_GPT_USE_TIM7 FALSE
|
||||
#define STM32_GPT_USE_TIM8 FALSE
|
||||
#define STM32_GPT_USE_TIM9 FALSE
|
||||
#define STM32_GPT_USE_TIM11 FALSE
|
||||
#define STM32_GPT_USE_TIM12 FALSE
|
||||
#define STM32_GPT_USE_TIM14 FALSE
|
||||
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM12_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM14_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 FALSE
|
||||
#define STM32_I2C_USE_I2C2 FALSE
|
||||
#define STM32_I2C_USE_I2C3 FALSE
|
||||
#define STM32_I2C_BUSY_TIMEOUT 50
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 3
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 3
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY 3
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* I2S driver system settings.
|
||||
*/
|
||||
#define STM32_I2S_USE_SPI2 FALSE
|
||||
#define STM32_I2S_USE_SPI3 FALSE
|
||||
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
|
||||
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
|
||||
#define STM32_I2S_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_I2S_SPI3_DMA_PRIORITY 1
|
||||
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 FALSE
|
||||
#define STM32_ICU_USE_TIM2 FALSE
|
||||
#define STM32_ICU_USE_TIM3 FALSE
|
||||
#define STM32_ICU_USE_TIM4 FALSE
|
||||
#define STM32_ICU_USE_TIM5 FALSE
|
||||
#define STM32_ICU_USE_TIM8 FALSE
|
||||
#define STM32_ICU_USE_TIM9 FALSE
|
||||
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* MAC driver system settings.
|
||||
*/
|
||||
#define STM32_MAC_TRANSMIT_BUFFERS 2
|
||||
#define STM32_MAC_RECEIVE_BUFFERS 4
|
||||
#define STM32_MAC_BUFFERS_SIZE 1522
|
||||
#define STM32_MAC_PHY_TIMEOUT 100
|
||||
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
|
||||
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
|
||||
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED FALSE
|
||||
#define STM32_PWM_USE_TIM1 FALSE
|
||||
#define STM32_PWM_USE_TIM2 FALSE
|
||||
#define STM32_PWM_USE_TIM3 FALSE
|
||||
#define STM32_PWM_USE_TIM4 FALSE
|
||||
#define STM32_PWM_USE_TIM5 FALSE
|
||||
#define STM32_PWM_USE_TIM8 FALSE
|
||||
#define STM32_PWM_USE_TIM9 FALSE
|
||||
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
*/
|
||||
#define STM32_SDC_SDIO_DMA_PRIORITY 3
|
||||
#define STM32_SDC_SDIO_IRQ_PRIORITY 9
|
||||
#define STM32_SDC_WRITE_TIMEOUT_MS 1000
|
||||
#define STM32_SDC_READ_TIMEOUT_MS 1000
|
||||
#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
|
||||
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
|
||||
#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 TRUE
|
||||
#define STM32_SERIAL_USE_USART2 FALSE
|
||||
#define STM32_SERIAL_USE_USART3 FALSE
|
||||
#define STM32_SERIAL_USE_UART4 FALSE
|
||||
#define STM32_SERIAL_USE_UART5 FALSE
|
||||
#define STM32_SERIAL_USE_USART6 FALSE
|
||||
#define STM32_SERIAL_USE_UART7 FALSE
|
||||
#define STM32_SERIAL_USE_UART8 FALSE
|
||||
#define STM32_SERIAL_USART1_PRIORITY 12
|
||||
#define STM32_SERIAL_USART2_PRIORITY 12
|
||||
#define STM32_SERIAL_USART3_PRIORITY 12
|
||||
#define STM32_SERIAL_UART4_PRIORITY 12
|
||||
#define STM32_SERIAL_UART5_PRIORITY 12
|
||||
#define STM32_SERIAL_USART6_PRIORITY 12
|
||||
#define STM32_SERIAL_UART7_PRIORITY 12
|
||||
#define STM32_SERIAL_UART8_PRIORITY 12
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 FALSE
|
||||
#define STM32_SPI_USE_SPI2 FALSE
|
||||
#define STM32_SPI_USE_SPI3 FALSE
|
||||
#define STM32_SPI_USE_SPI4 FALSE
|
||||
#define STM32_SPI_USE_SPI5 TRUE
|
||||
#define STM32_SPI_USE_SPI6 FALSE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
|
||||
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
||||
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
|
||||
#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
|
||||
#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI4_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI5_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI6_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY 8
|
||||
#define STM32_ST_USE_TIMER 2
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 FALSE
|
||||
#define STM32_UART_USE_USART2 FALSE
|
||||
#define STM32_UART_USE_USART3 FALSE
|
||||
#define STM32_UART_USE_UART4 FALSE
|
||||
#define STM32_UART_USE_UART5 FALSE
|
||||
#define STM32_UART_USE_USART6 FALSE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 FALSE
|
||||
#define STM32_USB_USE_OTG2 TRUE
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY 14
|
||||
#define STM32_USB_OTG2_IRQ_PRIORITY 14
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
|
||||
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
|
||||
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
|
||||
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
|
||||
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG FALSE
|
||||
|
||||
#include "mcuconf_community.h"
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* FSMC driver system settings.
|
||||
*/
|
||||
#define STM32_FSMC_USE_FSMC1 TRUE
|
||||
#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10
|
||||
#define STM32_FSMC_DMA_CHN 0x03010201
|
||||
|
||||
/*
|
||||
* FSMC NAND driver system settings.
|
||||
*/
|
||||
#define STM32_NAND_USE_NAND1 FALSE
|
||||
#define STM32_NAND_USE_NAND2 FALSE
|
||||
#define STM32_NAND_USE_EXT_INT FALSE
|
||||
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_NAND_DMA_PRIORITY 0
|
||||
#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* FSMC SRAM driver system settings.
|
||||
*/
|
||||
#define STM32_SRAM_USE_SRAM1 FALSE
|
||||
#define STM32_SRAM_USE_SRAM2 FALSE
|
||||
#define STM32_SRAM_USE_SRAM3 FALSE
|
||||
#define STM32_SRAM_USE_SRAM4 FALSE
|
||||
|
||||
/*
|
||||
* FSMC SDRAM driver system settings.
|
||||
*/
|
||||
#define STM32_SDRAM_USE_SDRAM1 FALSE
|
||||
#define STM32_SDRAM_USE_SDRAM2 TRUE
|
||||
|
||||
/*
|
||||
* LTDC driver system settings.
|
||||
*/
|
||||
#define STM32_LTDC_USE_LTDC TRUE
|
||||
#define STM32_LTDC_EV_IRQ_PRIORITY 11
|
||||
#define STM32_LTDC_ER_IRQ_PRIORITY 11
|
||||
|
||||
/*
|
||||
* DMA2D driver system settings.
|
||||
*/
|
||||
#define STM32_DMA2D_USE_DMA2D TRUE
|
||||
#define STM32_DMA2D_IRQ_PRIORITY 11
|
||||
|
|
@ -10,3 +10,7 @@ By definition, BOARD_NAME is a folder in firmware\config\boards
|
|||
One BOARD_NAME could be producing a number of artifacts via compile_$BUNDLE_NAME.sh scripts
|
||||
|
||||
Work in progress: SHORT_BOARDNAME becomes BUNDLE_NAME
|
||||
|
||||
New board procedure
|
||||
|
||||
1) manually add four new files to git see gen_config.h comment
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue