This commit is contained in:
rusefi
parent
884da751c3
commit
4582943d4c
|
|
@ -0,0 +1,152 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file crt0.s
|
||||||
|
* @brief Generic ARM startup file.
|
||||||
|
*
|
||||||
|
* @addtogroup ARM_GCC_STARTUP
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
|
||||||
|
.set MODE_USR, 0x10
|
||||||
|
.set MODE_FIQ, 0x11
|
||||||
|
.set MODE_IRQ, 0x12
|
||||||
|
.set MODE_SVC, 0x13
|
||||||
|
.set MODE_ABT, 0x17
|
||||||
|
.set MODE_UND, 0x1B
|
||||||
|
.set MODE_SYS, 0x1F
|
||||||
|
|
||||||
|
.set I_BIT, 0x80
|
||||||
|
.set F_BIT, 0x40
|
||||||
|
|
||||||
|
.text
|
||||||
|
.code 32
|
||||||
|
.balign 4
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Reset handler.
|
||||||
|
*/
|
||||||
|
.global Reset_Handler
|
||||||
|
Reset_Handler:
|
||||||
|
/*
|
||||||
|
* Stack pointers initialization.
|
||||||
|
*/
|
||||||
|
ldr r0, =__stacks_end__
|
||||||
|
/* Undefined */
|
||||||
|
msr CPSR_c, #MODE_UND | I_BIT | F_BIT
|
||||||
|
mov sp, r0
|
||||||
|
ldr r1, =__und_stack_size__
|
||||||
|
sub r0, r0, r1
|
||||||
|
/* Abort */
|
||||||
|
msr CPSR_c, #MODE_ABT | I_BIT | F_BIT
|
||||||
|
mov sp, r0
|
||||||
|
ldr r1, =__abt_stack_size__
|
||||||
|
sub r0, r0, r1
|
||||||
|
/* FIQ */
|
||||||
|
msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT
|
||||||
|
mov sp, r0
|
||||||
|
ldr r1, =__fiq_stack_size__
|
||||||
|
sub r0, r0, r1
|
||||||
|
/* IRQ */
|
||||||
|
msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT
|
||||||
|
mov sp, r0
|
||||||
|
ldr r1, =__irq_stack_size__
|
||||||
|
sub r0, r0, r1
|
||||||
|
/* Supervisor */
|
||||||
|
msr CPSR_c, #MODE_SVC | I_BIT | F_BIT
|
||||||
|
mov sp, r0
|
||||||
|
ldr r1, =__svc_stack_size__
|
||||||
|
sub r0, r0, r1
|
||||||
|
/* System */
|
||||||
|
msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
|
||||||
|
mov sp, r0
|
||||||
|
// ldr r1, =__sys_stack_size__
|
||||||
|
// sub r0, r0, r1
|
||||||
|
/*
|
||||||
|
* Early initialization.
|
||||||
|
*/
|
||||||
|
#if !defined(THUMB_NO_INTERWORKING)
|
||||||
|
bl __early_init
|
||||||
|
#else /* defined(THUMB_NO_INTERWORKING) */
|
||||||
|
add r0, pc, #1
|
||||||
|
bx r0
|
||||||
|
.code 16
|
||||||
|
bl __early_init
|
||||||
|
mov r0, pc
|
||||||
|
bx r0
|
||||||
|
.code 32
|
||||||
|
#endif /* defined(THUMB_NO_INTERWORKING) */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Data initialization.
|
||||||
|
* NOTE: It assumes that the DATA size is a multiple of 4.
|
||||||
|
*/
|
||||||
|
ldr r1, =_textdata
|
||||||
|
ldr r2, =_data
|
||||||
|
ldr r3, =_edata
|
||||||
|
dataloop:
|
||||||
|
cmp r2, r3
|
||||||
|
ldrlo r0, [r1], #4
|
||||||
|
strlo r0, [r2], #4
|
||||||
|
blo dataloop
|
||||||
|
/*
|
||||||
|
* BSS initialization.
|
||||||
|
* NOTE: It assumes that the BSS size is a multiple of 4.
|
||||||
|
*/
|
||||||
|
mov r0, #0
|
||||||
|
ldr r1, =_bss_start
|
||||||
|
ldr r2, =_bss_end
|
||||||
|
bssloop:
|
||||||
|
cmp r1, r2
|
||||||
|
strlo r0, [r1], #4
|
||||||
|
blo bssloop
|
||||||
|
/*
|
||||||
|
* Late initialization.
|
||||||
|
*/
|
||||||
|
#if !defined(THUMB_NO_INTERWORKING)
|
||||||
|
bl __late_init
|
||||||
|
#else /* defined(THUMB_NO_INTERWORKING) */
|
||||||
|
add r0, pc, #1
|
||||||
|
bx r0
|
||||||
|
.code 16
|
||||||
|
bl __late_init
|
||||||
|
mov r0, pc
|
||||||
|
bx r0
|
||||||
|
.code 32
|
||||||
|
#endif /* defined(THUMB_NO_INTERWORKING) */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Main program invocation.
|
||||||
|
*/
|
||||||
|
#if defined(THUMB_NO_INTERWORKING)
|
||||||
|
add r0, pc, #1
|
||||||
|
bx r0
|
||||||
|
.code 16
|
||||||
|
bl main
|
||||||
|
ldr r1, =__default_exit
|
||||||
|
bx r1
|
||||||
|
.code 32
|
||||||
|
#else /* !defined(THUMB_NO_INTERWORKING) */
|
||||||
|
bl main
|
||||||
|
b __default_exit
|
||||||
|
#endif /* !defined(THUMB_NO_INTERWORKING) */
|
||||||
|
|
||||||
|
#endif /* !defined(__DOXYGEN__) */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,72 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file ARMCMx/compilers/GCC/crt1.c
|
||||||
|
* @brief Startup stub functions.
|
||||||
|
*
|
||||||
|
* @addtogroup ARMCMx_GCC_STARTUP
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdbool.h>
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Early initialization.
|
||||||
|
* @details This hook is invoked immediately after the stack initialization
|
||||||
|
* and before the DATA and BSS segments initialization. The
|
||||||
|
* default behavior is to do nothing.
|
||||||
|
* @note This function is a weak symbol.
|
||||||
|
*/
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
__attribute__((weak))
|
||||||
|
#endif
|
||||||
|
/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
|
||||||
|
void __early_init(void) {}
|
||||||
|
/*lint -restore*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Late initialization.
|
||||||
|
* @details This hook is invoked after the DATA and BSS segments
|
||||||
|
* initialization and before any static constructor. The
|
||||||
|
* default behavior is to do nothing.
|
||||||
|
* @note This function is a weak symbol.
|
||||||
|
*/
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
__attribute__((weak))
|
||||||
|
#endif
|
||||||
|
/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
|
||||||
|
void __late_init(void) {}
|
||||||
|
/*lint -restore*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Default @p main() function exit handler.
|
||||||
|
* @details This handler is invoked or the @p main() function exit. The
|
||||||
|
* default behavior is to enter an infinite loop.
|
||||||
|
* @note This function is a weak symbol.
|
||||||
|
*/
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
__attribute__((noreturn, weak))
|
||||||
|
#endif
|
||||||
|
/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
|
||||||
|
void __default_exit(void) {
|
||||||
|
/*lint -restore*/
|
||||||
|
|
||||||
|
while (true) {
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,43 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* LPC2148 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x00000000, len = 512k - 12k
|
||||||
|
ram0 : org = 0x40000200, len = 32k - 0x200 - 288
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for stacks. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("STACKS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,221 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__;
|
||||||
|
|
||||||
|
__ram0_start__ = ORIGIN(ram0);
|
||||||
|
__ram0_size__ = LENGTH(ram0);
|
||||||
|
__ram0_end__ = __ram0_start__ + __ram0_size__;
|
||||||
|
__ram1_start__ = ORIGIN(ram1);
|
||||||
|
__ram1_size__ = LENGTH(ram1);
|
||||||
|
__ram1_end__ = __ram1_start__ + __ram1_size__;
|
||||||
|
__ram2_start__ = ORIGIN(ram2);
|
||||||
|
__ram2_size__ = LENGTH(ram2);
|
||||||
|
__ram2_end__ = __ram2_start__ + __ram2_size__;
|
||||||
|
__ram3_start__ = ORIGIN(ram3);
|
||||||
|
__ram3_size__ = LENGTH(ram3);
|
||||||
|
__ram3_end__ = __ram3_start__ + __ram3_size__;
|
||||||
|
__ram4_start__ = ORIGIN(ram4);
|
||||||
|
__ram4_size__ = LENGTH(ram4);
|
||||||
|
__ram4_end__ = __ram4_start__ + __ram4_size__;
|
||||||
|
__ram5_start__ = ORIGIN(ram5);
|
||||||
|
__ram5_size__ = LENGTH(ram5);
|
||||||
|
__ram5_end__ = __ram5_start__ + __ram5_size__;
|
||||||
|
__ram6_start__ = ORIGIN(ram6);
|
||||||
|
__ram6_size__ = LENGTH(ram6);
|
||||||
|
__ram6_end__ = __ram6_start__ + __ram6_size__;
|
||||||
|
__ram7_start__ = ORIGIN(ram7);
|
||||||
|
__ram7_size__ = LENGTH(ram7);
|
||||||
|
__ram7_end__ = __ram7_start__ + __ram7_size__;
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
. = 0;
|
||||||
|
_text = .;
|
||||||
|
|
||||||
|
startup : ALIGN(16) SUBALIGN(16)
|
||||||
|
{
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
constructors : ALIGN(4) SUBALIGN(4)
|
||||||
|
{
|
||||||
|
PROVIDE(__init_array_start = .);
|
||||||
|
KEEP(*(SORT(.init_array.*)))
|
||||||
|
KEEP(*(.init_array))
|
||||||
|
PROVIDE(__init_array_end = .);
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
destructors : ALIGN(4) SUBALIGN(4)
|
||||||
|
{
|
||||||
|
PROVIDE(__fini_array_start = .);
|
||||||
|
KEEP(*(.fini_array))
|
||||||
|
KEEP(*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE(__fini_array_end = .);
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.text : ALIGN(16) SUBALIGN(16)
|
||||||
|
{
|
||||||
|
*(.text)
|
||||||
|
*(.text.*)
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata.*)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.gcc*)
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.ARM.exidx : {
|
||||||
|
PROVIDE(__exidx_start = .);
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
PROVIDE(__exidx_end = .);
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.eh_frame_hdr :
|
||||||
|
{
|
||||||
|
*(.eh_frame_hdr)
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.eh_frame : ONLY_IF_RO
|
||||||
|
{
|
||||||
|
*(.eh_frame)
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.textalign : ONLY_IF_RO
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .;
|
||||||
|
_textdata = _etext;
|
||||||
|
|
||||||
|
.stacks :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
__stacks_base__ = .;
|
||||||
|
. += __stacks_total_size__;
|
||||||
|
. = ALIGN(8);
|
||||||
|
__stacks_end__ = .;
|
||||||
|
} > STACKS_RAM
|
||||||
|
|
||||||
|
.data : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_data = .);
|
||||||
|
*(.data)
|
||||||
|
*(.data.*)
|
||||||
|
*(.ramtext)
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_edata = .);
|
||||||
|
} > DATA_RAM AT > flash
|
||||||
|
|
||||||
|
.bss : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_bss_start = .);
|
||||||
|
*(.bss)
|
||||||
|
*(.bss.*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_bss_end = .);
|
||||||
|
PROVIDE(end = .);
|
||||||
|
} > BSS_RAM
|
||||||
|
|
||||||
|
.ram0 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.ram0)
|
||||||
|
*(.ram0.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_free__ = .;
|
||||||
|
} > ram0
|
||||||
|
|
||||||
|
.ram1 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.ram1)
|
||||||
|
*(.ram1.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_free__ = .;
|
||||||
|
} > ram1
|
||||||
|
|
||||||
|
.ram2 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.ram2)
|
||||||
|
*(.ram2.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_free__ = .;
|
||||||
|
} > ram2
|
||||||
|
|
||||||
|
.ram3 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.ram3)
|
||||||
|
*(.ram3.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_free__ = .;
|
||||||
|
} > ram3
|
||||||
|
|
||||||
|
.ram4 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.ram4)
|
||||||
|
*(.ram4.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_free__ = .;
|
||||||
|
} > ram4
|
||||||
|
|
||||||
|
.ram5 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.ram5)
|
||||||
|
*(.ram5.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_free__ = .;
|
||||||
|
} > ram5
|
||||||
|
|
||||||
|
.ram6 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.ram6)
|
||||||
|
*(.ram6.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_free__ = .;
|
||||||
|
} > ram6
|
||||||
|
|
||||||
|
.ram7 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.ram7)
|
||||||
|
*(.ram7.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_free__ = .;
|
||||||
|
} > ram7
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Heap default boundaries, it is defaulted to be the non-used part
|
||||||
|
of ram0 region.*/
|
||||||
|
__heap_base__ = __ram0_free__;
|
||||||
|
__heap_end__ = __ram0_end__;
|
||||||
|
|
@ -0,0 +1,312 @@
|
||||||
|
# ARM Cortex-Mx common makefile scripts and rules.
|
||||||
|
|
||||||
|
##############################################################################
|
||||||
|
# Processing options coming from the upper Makefile.
|
||||||
|
#
|
||||||
|
|
||||||
|
# Compiler options
|
||||||
|
OPT = $(USE_OPT)
|
||||||
|
COPT = $(USE_COPT)
|
||||||
|
CPPOPT = $(USE_CPPOPT)
|
||||||
|
|
||||||
|
# Garbage collection
|
||||||
|
ifeq ($(USE_LINK_GC),yes)
|
||||||
|
OPT += -ffunction-sections -fdata-sections -fno-common
|
||||||
|
LDOPT := ,--gc-sections
|
||||||
|
else
|
||||||
|
LDOPT :=
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Linker extra options
|
||||||
|
ifneq ($(USE_LDOPT),)
|
||||||
|
LDOPT := $(LDOPT),$(USE_LDOPT)
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Link time optimizations
|
||||||
|
ifeq ($(USE_LTO),yes)
|
||||||
|
OPT += -flto
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Undefined state stack size
|
||||||
|
ifeq ($(USE_UND_STACKSIZE),)
|
||||||
|
LDOPT := $(LDOPT),--defsym=__und_stack_size__=8
|
||||||
|
else
|
||||||
|
LDOPT := $(LDOPT),--defsym=__und_stack_size__=$(USE_UND_STACKSIZE)
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Abort stack size
|
||||||
|
ifeq ($(USE_ABT_STACKSIZE),)
|
||||||
|
LDOPT := $(LDOPT),--defsym=__abt_stack_size__=8
|
||||||
|
else
|
||||||
|
LDOPT := $(LDOPT),--defsym=__abt_stack_size__=$(USE_ABT_STACKSIZE)
|
||||||
|
endif
|
||||||
|
|
||||||
|
# FIQ stack size
|
||||||
|
ifeq ($(USE_FIQ_STACKSIZE),)
|
||||||
|
LDOPT := $(LDOPT),--defsym=__fiq_stack_size__=64
|
||||||
|
else
|
||||||
|
LDOPT := $(LDOPT),--defsym=__fiq_stack_size__=$(USE_FIQ_STACKSIZE)
|
||||||
|
endif
|
||||||
|
|
||||||
|
# IRQ stack size
|
||||||
|
ifeq ($(USE_IRQ_STACKSIZE),)
|
||||||
|
LDOPT := $(LDOPT),--defsym=__irq_stack_size__=0x400
|
||||||
|
else
|
||||||
|
LDOPT := $(LDOPT),--defsym=__irq_stack_size__=$(USE_IRQ_STACKSIZE)
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Supervisor stack size
|
||||||
|
ifeq ($(USE_SUPERVISOR_STACKSIZE),)
|
||||||
|
LDOPT := $(LDOPT),--defsym=__svc_stack_size__=8
|
||||||
|
else
|
||||||
|
LDOPT := $(LDOPT),--defsym=__svc_stack_size__=$(USE_SUPERVISOR_STACKSIZE)
|
||||||
|
endif
|
||||||
|
|
||||||
|
# System stack size
|
||||||
|
ifeq ($(USE_SYSTEM_STACKSIZE),)
|
||||||
|
LDOPT := $(LDOPT),--defsym=__sys_stack_size__=0x400
|
||||||
|
else
|
||||||
|
LDOPT := $(LDOPT),--defsym=__sys_stack_size__=$(USE_SYSTEM_STACKSIZE)
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Output directory and files
|
||||||
|
ifeq ($(BUILDDIR),)
|
||||||
|
BUILDDIR = build
|
||||||
|
endif
|
||||||
|
ifeq ($(BUILDDIR),.)
|
||||||
|
BUILDDIR = build
|
||||||
|
endif
|
||||||
|
OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \
|
||||||
|
$(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp \
|
||||||
|
$(BUILDDIR)/$(PROJECT).list
|
||||||
|
|
||||||
|
|
||||||
|
# Source files groups and paths
|
||||||
|
ifeq ($(USE_THUMB),yes)
|
||||||
|
TCSRC += $(CSRC)
|
||||||
|
TCPPSRC += $(CPPSRC)
|
||||||
|
else
|
||||||
|
ACSRC += $(CSRC)
|
||||||
|
ACPPSRC += $(CPPSRC)
|
||||||
|
endif
|
||||||
|
ASRC = $(ACSRC) $(ACPPSRC)
|
||||||
|
TSRC = $(TCSRC) $(TCPPSRC)
|
||||||
|
SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)))
|
||||||
|
|
||||||
|
# Various directories
|
||||||
|
OBJDIR = $(BUILDDIR)/obj
|
||||||
|
LSTDIR = $(BUILDDIR)/lst
|
||||||
|
|
||||||
|
# Object files groups
|
||||||
|
ACOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o)))
|
||||||
|
ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o)))
|
||||||
|
TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o)))
|
||||||
|
TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o)))
|
||||||
|
ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
|
||||||
|
ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
|
||||||
|
OBJS = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
|
||||||
|
|
||||||
|
# Paths
|
||||||
|
IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
|
||||||
|
LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
|
||||||
|
|
||||||
|
# Macros
|
||||||
|
DEFS = $(DDEFS) $(UDEFS)
|
||||||
|
ADEFS = $(DADEFS) $(UADEFS)
|
||||||
|
|
||||||
|
# Libs
|
||||||
|
LIBS = $(DLIBS) $(ULIBS)
|
||||||
|
|
||||||
|
# Various settings
|
||||||
|
MCFLAGS = -mcpu=$(MCU)
|
||||||
|
ODFLAGS = -x --syms
|
||||||
|
ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
|
||||||
|
ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
|
||||||
|
CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
|
||||||
|
CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
|
||||||
|
LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),--script=$(LDSCRIPT)$(LDOPT)
|
||||||
|
|
||||||
|
# Thumb interwork enabled only if needed because it kills performance.
|
||||||
|
ifneq ($(strip $(TSRC)),)
|
||||||
|
CFLAGS += -DTHUMB_PRESENT
|
||||||
|
CPPFLAGS += -DTHUMB_PRESENT
|
||||||
|
ASFLAGS += -DTHUMB_PRESENT
|
||||||
|
ASXFLAGS += -DTHUMB_PRESENT
|
||||||
|
ifneq ($(strip $(ASRC)),)
|
||||||
|
# Mixed ARM and THUMB mode.
|
||||||
|
CFLAGS += -mthumb-interwork
|
||||||
|
CPPFLAGS += -mthumb-interwork
|
||||||
|
ASFLAGS += -mthumb-interwork
|
||||||
|
ASXFLAGS += -mthumb-interwork
|
||||||
|
LDFLAGS += -mthumb-interwork
|
||||||
|
else
|
||||||
|
# Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly.
|
||||||
|
CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
|
||||||
|
CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
|
||||||
|
ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb
|
||||||
|
ASXFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb
|
||||||
|
LDFLAGS += -mno-thumb-interwork -mthumb
|
||||||
|
endif
|
||||||
|
else
|
||||||
|
# Pure ARM mode
|
||||||
|
CFLAGS += -mno-thumb-interwork
|
||||||
|
CPPFLAGS += -mno-thumb-interwork
|
||||||
|
ASFLAGS += -mno-thumb-interwork
|
||||||
|
ASXFLAGS += -mno-thumb-interwork
|
||||||
|
LDFLAGS += -mno-thumb-interwork
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Generate dependency information
|
||||||
|
ASFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||||
|
ASXFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||||
|
CFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||||
|
CPPFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||||
|
|
||||||
|
# Paths where to search for sources
|
||||||
|
VPATH = $(SRCPATHS)
|
||||||
|
|
||||||
|
#
|
||||||
|
# Makefile rules
|
||||||
|
#
|
||||||
|
|
||||||
|
all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK
|
||||||
|
|
||||||
|
PRE_MAKE_ALL_RULE_HOOK:
|
||||||
|
|
||||||
|
POST_MAKE_ALL_RULE_HOOK:
|
||||||
|
|
||||||
|
$(OBJS): | $(BUILDDIR) $(OBJDIR) $(LSTDIR)
|
||||||
|
|
||||||
|
$(BUILDDIR):
|
||||||
|
ifneq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
@echo Compiler Options
|
||||||
|
@echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
|
||||||
|
@echo
|
||||||
|
endif
|
||||||
|
@mkdir -p $(BUILDDIR)
|
||||||
|
|
||||||
|
$(OBJDIR):
|
||||||
|
@mkdir -p $(OBJDIR)
|
||||||
|
|
||||||
|
$(LSTDIR):
|
||||||
|
@mkdir -p $(LSTDIR)
|
||||||
|
|
||||||
|
$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
@echo
|
||||||
|
$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
else
|
||||||
|
@echo Compiling $(<F)
|
||||||
|
@$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
@echo
|
||||||
|
$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
else
|
||||||
|
@echo Compiling $(<F)
|
||||||
|
@$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(ACOBJS) : $(OBJDIR)/%.o : %.c Makefile
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
@echo
|
||||||
|
$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
else
|
||||||
|
@echo Compiling $(<F)
|
||||||
|
@$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(TCOBJS) : $(OBJDIR)/%.o : %.c Makefile
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
@echo
|
||||||
|
$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
else
|
||||||
|
@echo Compiling $(<F)
|
||||||
|
@$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
@echo
|
||||||
|
$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
|
||||||
|
else
|
||||||
|
@echo Compiling $(<F)
|
||||||
|
@$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(ASMXOBJS) : $(OBJDIR)/%.o : %.S Makefile
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
@echo
|
||||||
|
$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
else
|
||||||
|
@echo Compiling $(<F)
|
||||||
|
@$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(BUILDDIR)/$(PROJECT).elf: $(OBJS) $(LDSCRIPT)
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
@echo
|
||||||
|
$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
|
||||||
|
else
|
||||||
|
@echo Linking $@
|
||||||
|
@$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
%.hex: %.elf
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
$(HEX) $< $@
|
||||||
|
else
|
||||||
|
@echo Creating $@
|
||||||
|
@$(HEX) $< $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
%.bin: %.elf
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
$(BIN) $< $@
|
||||||
|
else
|
||||||
|
@echo Creating $@
|
||||||
|
@$(BIN) $< $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
%.dmp: %.elf
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
$(OD) $(ODFLAGS) $< > $@
|
||||||
|
$(SZ) $<
|
||||||
|
else
|
||||||
|
@echo Creating $@
|
||||||
|
@$(OD) $(ODFLAGS) $< > $@
|
||||||
|
@echo
|
||||||
|
@$(SZ) $<
|
||||||
|
endif
|
||||||
|
|
||||||
|
%.list: %.elf
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
$(OD) -S $< > $@
|
||||||
|
else
|
||||||
|
@echo Creating $@
|
||||||
|
@$(OD) -S $< > $@
|
||||||
|
@echo
|
||||||
|
@echo Done
|
||||||
|
endif
|
||||||
|
|
||||||
|
lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a
|
||||||
|
|
||||||
|
$(BUILDDIR)/lib$(PROJECT).a: $(OBJS)
|
||||||
|
@$(AR) -r $@ $^
|
||||||
|
@echo
|
||||||
|
@echo Done
|
||||||
|
|
||||||
|
clean:
|
||||||
|
@echo Cleaning
|
||||||
|
-rm -fR .dep $(BUILDDIR)
|
||||||
|
@echo
|
||||||
|
@echo Done
|
||||||
|
|
||||||
|
#
|
||||||
|
# Include the dependency files, should be the last of the makefile
|
||||||
|
#
|
||||||
|
-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
|
||||||
|
|
||||||
|
# *** EOF ***
|
||||||
|
|
@ -0,0 +1,98 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file ARM/compilers/GCC/vectors.s
|
||||||
|
* @brief Interrupt vectors for ARM devices.
|
||||||
|
*
|
||||||
|
* @defgroup ARM_VECTORS ARM Exception Vectors
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(__DOXYGEN__)
|
||||||
|
/**
|
||||||
|
* @brief Unhandled exceptions handler.
|
||||||
|
* @details Any undefined exception vector points to this function by default.
|
||||||
|
* This function simply stops the system into an infinite loop.
|
||||||
|
* @note The default implementation is a weak symbol, the application
|
||||||
|
* can override the default implementation.
|
||||||
|
*
|
||||||
|
* @notapi
|
||||||
|
*/
|
||||||
|
void _unhandled_exception(void) {}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
|
||||||
|
.section .vectors, "ax"
|
||||||
|
.code 32
|
||||||
|
.balign 4
|
||||||
|
|
||||||
|
/*
|
||||||
|
* System entry points.
|
||||||
|
*/
|
||||||
|
.global _start
|
||||||
|
_start:
|
||||||
|
ldr pc, _reset
|
||||||
|
ldr pc, _undefined
|
||||||
|
ldr pc, _swi
|
||||||
|
ldr pc, _prefetch
|
||||||
|
ldr pc, _abort
|
||||||
|
nop
|
||||||
|
ldr pc, _irq
|
||||||
|
ldr pc, _fiq
|
||||||
|
|
||||||
|
_reset:
|
||||||
|
.word Reset_Handler
|
||||||
|
_undefined:
|
||||||
|
.word Und_Handler
|
||||||
|
_swi:
|
||||||
|
.word Swi_Handler
|
||||||
|
_prefetch:
|
||||||
|
.word Prefetch_Handler
|
||||||
|
_abort:
|
||||||
|
.word Abort_Handler
|
||||||
|
_fiq:
|
||||||
|
.word Fiq_Handler
|
||||||
|
_irq:
|
||||||
|
.word Irq_Handler
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Default exceptions handlers. The handlers are declared weak in order to be
|
||||||
|
* replaced by the real handling code. Everything is defaulted to an infinite
|
||||||
|
* loop.
|
||||||
|
*/
|
||||||
|
.weak Reset_Handler
|
||||||
|
Reset_Handler:
|
||||||
|
.weak Und_Handler
|
||||||
|
Und_Handler:
|
||||||
|
.weak Swi_Handler
|
||||||
|
Swi_Handler:
|
||||||
|
.weak Prefetch_Handler
|
||||||
|
Prefetch_Handler:
|
||||||
|
.weak Abort_Handler
|
||||||
|
Abort_Handler:
|
||||||
|
.weak Fiq_Handler
|
||||||
|
Fiq_Handler:
|
||||||
|
.weak Irq_Handler
|
||||||
|
Irq_Handler:
|
||||||
|
.weak _unhandled_exception
|
||||||
|
_unhandled_exception:
|
||||||
|
b _unhandled_exception
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,62 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file armparams.h
|
||||||
|
* @brief ARM parameters for the LPC214x.
|
||||||
|
*
|
||||||
|
* @defgroup ARM_LPC214x LPC214x Specific Parameters
|
||||||
|
* @ingroup ARM_SPECIFIC
|
||||||
|
* @details This file contains the ARM specific parameters for the
|
||||||
|
* LPC214x platform.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _ARMPARAMS_H_
|
||||||
|
#define _ARMPARAMS_H_
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ARM core model.
|
||||||
|
*/
|
||||||
|
#define ARM_CORE ARM_CORE_ARM7TDMI
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Thumb-capable.
|
||||||
|
*/
|
||||||
|
#define ARM_SUPPORTS_THUMB 1
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Thumb2-capable.
|
||||||
|
*/
|
||||||
|
#define ARM_SUPPORTS_THUMB2 0
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Implementation of the wait-for-interrupt state enter.
|
||||||
|
*/
|
||||||
|
#define ARM_WFI_IMPL (PCON = 1)
|
||||||
|
|
||||||
|
#if !defined(_FROM_ASM_) || defined(__DOXYGEN__)
|
||||||
|
/**
|
||||||
|
* @brief Address of the IRQ vector register in the interrupt controller.
|
||||||
|
*/
|
||||||
|
#define ARM_IRQ_VECTOR_REG 0xFFFFF030U
|
||||||
|
#else
|
||||||
|
#define ARM_IRQ_VECTOR_REG 0xFFFFF030
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* _ARMPARAMS_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,523 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file lpc214x.h
|
||||||
|
* @brief LPC214x register definitions.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _LPC214X_H_
|
||||||
|
#define _LPC214X_H_
|
||||||
|
|
||||||
|
typedef volatile uint8_t IOREG8;
|
||||||
|
typedef volatile uint16_t IOREG16;
|
||||||
|
typedef volatile uint32_t IOREG32;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* System.
|
||||||
|
*/
|
||||||
|
#define MEMMAP (*((IOREG32 *)0xE01FC040))
|
||||||
|
#define PCON (*((IOREG32 *)0xE01FC0C0))
|
||||||
|
#define PCONP (*((IOREG32 *)0xE01FC0C4))
|
||||||
|
#define VPBDIV (*((IOREG32 *)0xE01FC100))
|
||||||
|
#define EXTINT (*((IOREG32 *)0xE01FC140))
|
||||||
|
#define INTWAKE (*((IOREG32 *)0xE01FC144))
|
||||||
|
#define EXTMODE (*((IOREG32 *)0xE01FC148))
|
||||||
|
#define EXTPOLAR (*((IOREG32 *)0xE01FC14C))
|
||||||
|
#define RSID (*((IOREG32 *)0xE01FC180))
|
||||||
|
#define CSPR (*((IOREG32 *)0xE01FC184))
|
||||||
|
#define SCS (*((IOREG32 *)0xE01FC1A0))
|
||||||
|
|
||||||
|
#define VPD_D4 0
|
||||||
|
#define VPD_D1 1
|
||||||
|
#define VPD_D2 2
|
||||||
|
#define VPD_RESERVED 3
|
||||||
|
|
||||||
|
#define PCTIM0 (1 << 1)
|
||||||
|
#define PCTIM1 (1 << 2)
|
||||||
|
#define PCUART0 (1 << 3)
|
||||||
|
#define PCUART1 (1 << 4)
|
||||||
|
#define PCPWM0 (1 << 5)
|
||||||
|
#define PCI2C0 (1 << 7)
|
||||||
|
#define PCSPI0 (1 << 8)
|
||||||
|
#define PCRTC (1 << 9)
|
||||||
|
#define PCSPI1 (1 << 10)
|
||||||
|
#define PCAD0 (1 << 12)
|
||||||
|
#define PCI2C1 (1 << 19)
|
||||||
|
#define PCAD1 (1 << 20)
|
||||||
|
#define PCUSB (1 << 31)
|
||||||
|
#define PCALL (PCTIM0 | PCTIM1 | PCUART0 | PCUART1 | \
|
||||||
|
PCPWM0 | PCI2C0 | PCSPI0 | PCRTC | PCSPI1 | \
|
||||||
|
PCAD0 | PCI2C1 | PCAD1 | PCUSB)
|
||||||
|
|
||||||
|
#define EINT0 1
|
||||||
|
#define EINT1 2
|
||||||
|
#define EINT2 4
|
||||||
|
#define EINT3 8
|
||||||
|
|
||||||
|
#define EXTWAKE0 1
|
||||||
|
#define EXTWAKE1 2
|
||||||
|
#define EXTWAKE2 4
|
||||||
|
#define EXTWAKE3 8
|
||||||
|
#define USBWAKE 0x20
|
||||||
|
#define BODWAKE 0x4000
|
||||||
|
#define RTCWAKE 0x8000
|
||||||
|
|
||||||
|
#define EXTMODE0 1
|
||||||
|
#define EXTMODE1 2
|
||||||
|
#define EXTMODE2 4
|
||||||
|
#define EXTMODE3 8
|
||||||
|
|
||||||
|
#define EXTPOLAR0 1
|
||||||
|
#define EXTPOLAR1 2
|
||||||
|
#define EXTPOLAR2 4
|
||||||
|
#define EXTPOLAR3 8
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
IOREG32 PLL_CON;
|
||||||
|
IOREG32 PLL_CFG;
|
||||||
|
IOREG32 PLL_STAT;
|
||||||
|
IOREG32 PLL_FEED;
|
||||||
|
} PLL;
|
||||||
|
|
||||||
|
#define PLL0Base ((PLL *)0xE01FC080)
|
||||||
|
#define PLL1Base ((PLL *)0xE01FC0A0)
|
||||||
|
#define PLL0CON (PLL0Base->PLL_CON)
|
||||||
|
#define PLL0CFG (PLL0Base->PLL_CFG)
|
||||||
|
#define PLL0STAT (PLL0Base->PLL_STAT)
|
||||||
|
#define PLL0FEED (PLL0Base->PLL_FEED)
|
||||||
|
#define PLL1CON (PLL1Base->PLL_CON)
|
||||||
|
#define PLL1CFG (PLL1Base->PLL_CFG)
|
||||||
|
#define PLL1STAT (PLL1Base->PLL_STAT)
|
||||||
|
#define PLL1FEED (PLL1Base->PLL_FEED)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Pins.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
IOREG32 PS_SEL0;
|
||||||
|
IOREG32 PS_SEL1;
|
||||||
|
IOREG32 _dummy[3];
|
||||||
|
IOREG32 PS_SEL2;
|
||||||
|
} PS;
|
||||||
|
|
||||||
|
#define PSBase ((PS *)0xE002C000)
|
||||||
|
#define PINSEL0 (PSBase->PS_SEL0)
|
||||||
|
#define PINSEL1 (PSBase->PS_SEL1)
|
||||||
|
#define PINSEL2 (PSBase->PS_SEL2)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* VIC
|
||||||
|
*/
|
||||||
|
#define SOURCE_WDT 0
|
||||||
|
#define SOURCE_ARMCore0 2
|
||||||
|
#define SOURCE_ARMCore1 3
|
||||||
|
#define SOURCE_Timer0 4
|
||||||
|
#define SOURCE_Timer1 5
|
||||||
|
#define SOURCE_UART0 6
|
||||||
|
#define SOURCE_UART1 7
|
||||||
|
#define SOURCE_PWM0 8
|
||||||
|
#define SOURCE_I2C0 9
|
||||||
|
#define SOURCE_SPI0 10
|
||||||
|
#define SOURCE_SPI1 11
|
||||||
|
#define SOURCE_PLL 12
|
||||||
|
#define SOURCE_RTC 13
|
||||||
|
#define SOURCE_EINT0 14
|
||||||
|
#define SOURCE_EINT1 15
|
||||||
|
#define SOURCE_EINT2 16
|
||||||
|
#define SOURCE_EINT3 17
|
||||||
|
#define SOURCE_ADC0 18
|
||||||
|
#define SOURCE_I2C1 19
|
||||||
|
#define SOURCE_BOD 20
|
||||||
|
#define SOURCE_ADC1 21
|
||||||
|
#define SOURCE_USB 22
|
||||||
|
|
||||||
|
#define INTMASK(n) (1 << (n))
|
||||||
|
#define ALLINTMASK (INTMASK(SOURCE_WDT) | INTMASK(SOURCE_ARMCore0) | \
|
||||||
|
INTMASK(SOURCE_ARMCore1) | INTMASK(SOURCE_Timer0) | \
|
||||||
|
INTMASK(SOURCE_Timer1) | INTMASK(SOURCE_UART0) | \
|
||||||
|
INTMASK(SOURCE_UART1) | INTMASK(SOURCE_PWM0) | \
|
||||||
|
INTMASK(SOURCE_I2C0) | INTMASK(SOURCE_SPI0) | \
|
||||||
|
INTMASK(SOURCE_SPI1) | INTMASK(SOURCE_PLL) | \
|
||||||
|
INTMASK(SOURCE_RTC) | INTMASK(SOURCE_EINT0) | \
|
||||||
|
INTMASK(SOURCE_EINT1) | INTMASK(SOURCE_EINT2) | \
|
||||||
|
INTMASK(SOURCE_EINT3) | INTMASK(SOURCE_ADC0) | \
|
||||||
|
INTMASK(SOURCE_I2C1) | INTMASK(SOURCE_BOD) | \
|
||||||
|
INTMASK(SOURCE_ADC1) | INTMASK(SOURCE_USB))
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
IOREG32 VIC_IRQStatus;
|
||||||
|
IOREG32 VIC_FIQStatus;
|
||||||
|
IOREG32 VIC_RawIntr;
|
||||||
|
IOREG32 VIC_IntSelect;
|
||||||
|
IOREG32 VIC_IntEnable;
|
||||||
|
IOREG32 VIC_IntEnClear;
|
||||||
|
IOREG32 VIC_SoftInt;
|
||||||
|
IOREG32 VIC_SoftIntClear;
|
||||||
|
IOREG32 VIC_Protection;
|
||||||
|
IOREG32 unused1[3];
|
||||||
|
IOREG32 VIC_VectAddr;
|
||||||
|
IOREG32 VIC_DefVectAddr;
|
||||||
|
IOREG32 unused2[50];
|
||||||
|
IOREG32 VIC_VectAddrs[16];
|
||||||
|
IOREG32 unused3[48];
|
||||||
|
IOREG32 VIC_VectCntls[16];
|
||||||
|
} VIC;
|
||||||
|
|
||||||
|
#define VICBase ((VIC *)0xFFFFF000)
|
||||||
|
#define VICVectorsBase ((IOREG32 *)0xFFFFF100)
|
||||||
|
#define VICControlsBase ((IOREG32 *)0xFFFFF200)
|
||||||
|
|
||||||
|
#define VICIRQStatus (VICBase->VIC_IRQStatus)
|
||||||
|
#define VICFIQStatus (VICBase->VIC_FIQStatus)
|
||||||
|
#define VICRawIntr (VICBase->VIC_RawIntr)
|
||||||
|
#define VICIntSelect (VICBase->VIC_IntSelect)
|
||||||
|
#define VICIntEnable (VICBase->VIC_IntEnable)
|
||||||
|
#define VICIntEnClear (VICBase->VIC_IntEnClear)
|
||||||
|
#define VICSoftInt (VICBase->VIC_SoftInt)
|
||||||
|
#define VICSoftIntClear (VICBase->VIC_SoftIntClear)
|
||||||
|
#define VICProtection (VICBase->VIC_Protection)
|
||||||
|
#define VICVectAddr (VICBase->VIC_VectAddr)
|
||||||
|
#define VICDefVectAddr (VICBase->VIC_DefVectAddr)
|
||||||
|
|
||||||
|
#define VICVectAddrs(n) (VICBase->VIC_VectAddrs[n])
|
||||||
|
#define VICVectCntls(n) (VICBase->VIC_VectCntls[n])
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MAM.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
IOREG32 MAM_Control;
|
||||||
|
IOREG32 MAM_Timing;
|
||||||
|
} MAM;
|
||||||
|
|
||||||
|
#define MAMBase ((MAM *)0xE01FC000)
|
||||||
|
#define MAMCR (MAMBase->MAM_Control)
|
||||||
|
#define MAMTIM (MAMBase->MAM_Timing)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GPIO - FIO.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
IOREG32 IO_PIN;
|
||||||
|
IOREG32 IO_SET;
|
||||||
|
IOREG32 IO_DIR;
|
||||||
|
IOREG32 IO_CLR;
|
||||||
|
} GPIO;
|
||||||
|
|
||||||
|
#define GPIO0Base ((GPIO *)0xE0028000)
|
||||||
|
#define IO0PIN (GPIO0Base->IO_PIN)
|
||||||
|
#define IO0SET (GPIO0Base->IO_SET)
|
||||||
|
#define IO0DIR (GPIO0Base->IO_DIR)
|
||||||
|
#define IO0CLR (GPIO0Base->IO_CLR)
|
||||||
|
|
||||||
|
#define GPIO1Base ((GPIO *)0xE0028010)
|
||||||
|
#define IO1PIN (GPIO1Base->IO_PIN)
|
||||||
|
#define IO1SET (GPIO1Base->IO_SET)
|
||||||
|
#define IO1DIR (GPIO1Base->IO_DIR)
|
||||||
|
#define IO1CLR (GPIO1Base->IO_CLR)
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
IOREG32 FIO_DIR;
|
||||||
|
IOREG32 unused1;
|
||||||
|
IOREG32 unused2;
|
||||||
|
IOREG32 unused3;
|
||||||
|
IOREG32 FIO_MASK;
|
||||||
|
IOREG32 FIO_PIN;
|
||||||
|
IOREG32 FIO_SET;
|
||||||
|
IOREG32 FIO_CLR;
|
||||||
|
} FIO;
|
||||||
|
|
||||||
|
#define FIO0Base ((FIO *)0x3FFFC000)
|
||||||
|
#define FIO0DIR (FIO0Base->FIO_DIR)
|
||||||
|
#define FIO0MASK (FIO0Base->FIO_MASK)
|
||||||
|
#define FIO0PIN (FIO0Base->FIO_PIN)
|
||||||
|
#define FIO0SET (FIO0Base->FIO_SET)
|
||||||
|
#define FIO0CLR (FIO0Base->FIO_CLR)
|
||||||
|
|
||||||
|
#define FIO1Base ((FIO *)0x3FFFC020)
|
||||||
|
#define FIO1DIR (FIO1Base->FIO_DIR)
|
||||||
|
#define FIO1MASK (FIO1Base->FIO_MASK)
|
||||||
|
#define FIO1PIN (FIO1Base->FIO_PIN)
|
||||||
|
#define FIO1SET (FIO1Base->FIO_SET)
|
||||||
|
#define FIO1CLR (FIO1Base->FIO_CLR)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* UART.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
union {
|
||||||
|
IOREG32 UART_RBR;
|
||||||
|
IOREG32 UART_THR;
|
||||||
|
IOREG32 UART_DLL;
|
||||||
|
};
|
||||||
|
union {
|
||||||
|
IOREG32 UART_IER;
|
||||||
|
IOREG32 UART_DLM;
|
||||||
|
};
|
||||||
|
union {
|
||||||
|
IOREG32 UART_IIR;
|
||||||
|
IOREG32 UART_FCR;
|
||||||
|
};
|
||||||
|
IOREG32 UART_LCR;
|
||||||
|
IOREG32 UART_MCR;
|
||||||
|
IOREG32 UART_LSR;
|
||||||
|
IOREG32 unused18;
|
||||||
|
IOREG32 UART_SCR;
|
||||||
|
IOREG32 UART_ACR;
|
||||||
|
IOREG32 unused24;
|
||||||
|
IOREG32 UART_FDR;
|
||||||
|
IOREG32 unused2C;
|
||||||
|
IOREG32 UART_TER;
|
||||||
|
} UART;
|
||||||
|
|
||||||
|
#define U0Base ((UART *)0xE000C000)
|
||||||
|
#define U0RBR (U0Base->UART_RBR)
|
||||||
|
#define U0THR (U0Base->UART_THR)
|
||||||
|
#define U0DLL (U0Base->UART_DLL)
|
||||||
|
#define U0IER (U0Base->UART_IER)
|
||||||
|
#define U0DLM (U0Base->UART_DLM)
|
||||||
|
#define U0IIR (U0Base->UART_IIR)
|
||||||
|
#define U0FCR (U0Base->UART_FCR)
|
||||||
|
#define U0LCR (U0Base->UART_LCR)
|
||||||
|
#define U0LSR (U0Base->UART_LSR)
|
||||||
|
#define U0SCR (U0Base->UART_SCR)
|
||||||
|
#define U0ACR (U0Base->UART_ACR)
|
||||||
|
#define U0FDR (U0Base->UART_FDR)
|
||||||
|
#define U0TER (U0Base->UART_TER)
|
||||||
|
|
||||||
|
#define U1Base ((UART *)0xE0010000)
|
||||||
|
#define U1RBR (U1Base->UART_RBR)
|
||||||
|
#define U1THR (U1Base->UART_THR)
|
||||||
|
#define U1DLL (U1Base->UART_DLL)
|
||||||
|
#define U1IER (U1Base->UART_IER)
|
||||||
|
#define U1DLM (U1Base->UART_DLM)
|
||||||
|
#define U1IIR (U1Base->UART_IIR)
|
||||||
|
#define U1FCR (U1Base->UART_FCR)
|
||||||
|
#define U1MCR (U1Base->UART_MCR)
|
||||||
|
#define U1LCR (U1Base->UART_LCR)
|
||||||
|
#define U1LSR (U1Base->UART_LSR)
|
||||||
|
#define U1SCR (U1Base->UART_SCR)
|
||||||
|
#define U1ACR (U1Base->UART_ACR)
|
||||||
|
#define U1FDR (U1Base->UART_FDR)
|
||||||
|
#define U1TER (U1Base->UART_TER)
|
||||||
|
|
||||||
|
#define IIR_SRC_MASK 0x0F
|
||||||
|
#define IIR_SRC_NONE 0x01
|
||||||
|
#define IIR_SRC_TX 0x02
|
||||||
|
#define IIR_SRC_RX 0x04
|
||||||
|
#define IIR_SRC_ERROR 0x06
|
||||||
|
#define IIR_SRC_TIMEOUT 0x0C
|
||||||
|
|
||||||
|
#define IER_RBR 1
|
||||||
|
#define IER_THRE 2
|
||||||
|
#define IER_STATUS 4
|
||||||
|
|
||||||
|
#define IIR_INT_PENDING 1
|
||||||
|
|
||||||
|
#define LCR_WL5 0
|
||||||
|
#define LCR_WL6 1
|
||||||
|
#define LCR_WL7 2
|
||||||
|
#define LCR_WL8 3
|
||||||
|
#define LCR_STOP1 0
|
||||||
|
#define LCR_STOP2 4
|
||||||
|
#define LCR_NOPARITY 0
|
||||||
|
#define LCR_PARITYODD 0x08
|
||||||
|
#define LCR_PARITYEVEN 0x18
|
||||||
|
#define LCR_PARITYONE 0x28
|
||||||
|
#define LCR_PARITYZERO 0x38
|
||||||
|
#define LCR_BREAK_ON 0x40
|
||||||
|
#define LCR_DLAB 0x80
|
||||||
|
|
||||||
|
#define FCR_ENABLE 1
|
||||||
|
#define FCR_RXRESET 2
|
||||||
|
#define FCR_TXRESET 4
|
||||||
|
#define FCR_TRIGGER0 0
|
||||||
|
#define FCR_TRIGGER1 0x40
|
||||||
|
#define FCR_TRIGGER2 0x80
|
||||||
|
#define FCR_TRIGGER3 0xC0
|
||||||
|
|
||||||
|
#define LSR_RBR_FULL 1
|
||||||
|
#define LSR_OVERRUN 2
|
||||||
|
#define LSR_PARITY 4
|
||||||
|
#define LSR_FRAMING 8
|
||||||
|
#define LSR_BREAK 0x10
|
||||||
|
#define LSR_THRE 0x20
|
||||||
|
#define LSR_TEMT 0x40
|
||||||
|
#define LSR_RXFE 0x80
|
||||||
|
|
||||||
|
#define TER_ENABLE 0x80
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SSP.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
IOREG32 SSP_CR0;
|
||||||
|
IOREG32 SSP_CR1;
|
||||||
|
IOREG32 SSP_DR;
|
||||||
|
IOREG32 SSP_SR;
|
||||||
|
IOREG32 SSP_CPSR;
|
||||||
|
IOREG32 SSP_IMSC;
|
||||||
|
IOREG32 SSP_RIS;
|
||||||
|
IOREG32 SSP_MIS;
|
||||||
|
IOREG32 SSP_ICR;
|
||||||
|
} SSP;
|
||||||
|
|
||||||
|
#define SSPBase ((SSP *)0xE0068000)
|
||||||
|
#define SSPCR0 (SSPBase->SSP_CR0)
|
||||||
|
#define SSPCR1 (SSPBase->SSP_CR1)
|
||||||
|
#define SSPDR (SSPBase->SSP_DR)
|
||||||
|
#define SSPSR (SSPBase->SSP_SR)
|
||||||
|
#define SSPCPSR (SSPBase->SSP_CPSR)
|
||||||
|
#define SSPIMSC (SSPBase->SSP_IMSC)
|
||||||
|
#define SSPRIS (SSPBase->SSP_RIS)
|
||||||
|
#define SSPMIS (SSPBase->SSP_MIS)
|
||||||
|
#define SSPICR (SSPBase->SSP_ICR)
|
||||||
|
|
||||||
|
#define CR0_DSSMASK 0x0F
|
||||||
|
#define CR0_DSS4BIT 3
|
||||||
|
#define CR0_DSS5BIT 4
|
||||||
|
#define CR0_DSS6BIT 5
|
||||||
|
#define CR0_DSS7BIT 6
|
||||||
|
#define CR0_DSS8BIT 7
|
||||||
|
#define CR0_DSS9BIT 8
|
||||||
|
#define CR0_DSS10BIT 9
|
||||||
|
#define CR0_DSS11BIT 0xA
|
||||||
|
#define CR0_DSS12BIT 0xB
|
||||||
|
#define CR0_DSS13BIT 0xC
|
||||||
|
#define CR0_DSS14BIT 0xD
|
||||||
|
#define CR0_DSS15BIT 0xE
|
||||||
|
#define CR0_DSS16BIT 0xF
|
||||||
|
#define CR0_FRFSPI 0
|
||||||
|
#define CR0_FRFSSI 0x10
|
||||||
|
#define CR0_FRFMW 0x20
|
||||||
|
#define CR0_CPOL 0x40
|
||||||
|
#define CR0_CPHA 0x80
|
||||||
|
#define CR0_CLOCKRATE(n) ((n) << 8)
|
||||||
|
|
||||||
|
#define CR1_LBM 1
|
||||||
|
#define CR1_SSE 2
|
||||||
|
#define CR1_MS 4
|
||||||
|
#define CR1_SOD 8
|
||||||
|
|
||||||
|
#define SR_TFE 1
|
||||||
|
#define SR_TNF 2
|
||||||
|
#define SR_RNE 4
|
||||||
|
#define SR_RFF 8
|
||||||
|
#define SR_BSY 0x10
|
||||||
|
|
||||||
|
#define IMSC_ROR 1
|
||||||
|
#define IMSC_RT 2
|
||||||
|
#define IMSC_RX 4
|
||||||
|
#define IMSC_TX 8
|
||||||
|
|
||||||
|
#define RIS_ROR 1
|
||||||
|
#define RIS_RT 2
|
||||||
|
#define RIS_RX 4
|
||||||
|
#define RIS_TX 8
|
||||||
|
|
||||||
|
#define MIS_ROR 1
|
||||||
|
#define MIS_RT 2
|
||||||
|
#define MIS_RX 4
|
||||||
|
#define MIS_TX 8
|
||||||
|
|
||||||
|
#define ICR_ROR 1
|
||||||
|
#define ICR_RT 2
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Timers/Counters.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
IOREG32 TC_IR;
|
||||||
|
IOREG32 TC_TCR;
|
||||||
|
IOREG32 TC_TC;
|
||||||
|
IOREG32 TC_PR;
|
||||||
|
IOREG32 TC_PC;
|
||||||
|
IOREG32 TC_MCR;
|
||||||
|
IOREG32 TC_MR0;
|
||||||
|
IOREG32 TC_MR1;
|
||||||
|
IOREG32 TC_MR2;
|
||||||
|
IOREG32 TC_MR3;
|
||||||
|
IOREG32 TC_CCR;
|
||||||
|
IOREG32 TC_CR0;
|
||||||
|
IOREG32 TC_CR1;
|
||||||
|
IOREG32 TC_CR2;
|
||||||
|
IOREG32 TC_CR3;
|
||||||
|
IOREG32 TC_EMR;
|
||||||
|
IOREG32 TC_CTCR;
|
||||||
|
} TC;
|
||||||
|
|
||||||
|
#define T0Base ((TC *)0xE0004000)
|
||||||
|
#define T0IR (T0Base->TC_IR)
|
||||||
|
#define T0TCR (T0Base->TC_TCR)
|
||||||
|
#define T0TC (T0Base->TC_TC)
|
||||||
|
#define T0PR (T0Base->TC_PR)
|
||||||
|
#define T0PC (T0Base->TC_PC)
|
||||||
|
#define T0MCR (T0Base->TC_MCR)
|
||||||
|
#define T0MR0 (T0Base->TC_MR0)
|
||||||
|
#define T0MR1 (T0Base->TC_MR1)
|
||||||
|
#define T0MR2 (T0Base->TC_MR2)
|
||||||
|
#define T0MR3 (T0Base->TC_MR3)
|
||||||
|
#define T0CCR (T0Base->TC_CCR)
|
||||||
|
#define T0CR0 (T0Base->TC_CR0)
|
||||||
|
#define T0CR1 (T0Base->TC_CR1)
|
||||||
|
#define T0CR2 (T0Base->TC_CR2)
|
||||||
|
#define T0CR3 (T0Base->TC_CR3)
|
||||||
|
#define T0EMR (T0Base->TC_EMR)
|
||||||
|
#define T0CTCR (T0Base->TC_CTCR)
|
||||||
|
|
||||||
|
#define T1Base ((TC *)0xE0008000)
|
||||||
|
#define T1IR (T1Base->TC_IR)
|
||||||
|
#define T1TCR (T1Base->TC_TCR)
|
||||||
|
#define T1TC (T1Base->TC_TC)
|
||||||
|
#define T1PR (T1Base->TC_PR)
|
||||||
|
#define T1PC (T1Base->TC_PC)
|
||||||
|
#define T1MCR (T1Base->TC_MCR)
|
||||||
|
#define T1MR0 (T1Base->TC_MR0)
|
||||||
|
#define T1MR1 (T1Base->TC_MR1)
|
||||||
|
#define T1MR2 (T1Base->TC_MR2)
|
||||||
|
#define T1MR3 (T1Base->TC_MR3)
|
||||||
|
#define T1CCR (T1Base->TC_CCR)
|
||||||
|
#define T1CR0 (T1Base->TC_CR0)
|
||||||
|
#define T1CR1 (T1Base->TC_CR1)
|
||||||
|
#define T1CR2 (T1Base->TC_CR2)
|
||||||
|
#define T1CR3 (T1Base->TC_CR3)
|
||||||
|
#define T1EMR (T1Base->TC_EMR)
|
||||||
|
#define T1CTCR (T1Base->TC_CTCR)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Watchdog.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
IOREG32 WD_MOD;
|
||||||
|
IOREG32 WD_TC;
|
||||||
|
IOREG32 WD_FEED;
|
||||||
|
IOREG32 WD_TV;
|
||||||
|
} WD;
|
||||||
|
|
||||||
|
#define WDBase ((WD *)0xE0000000)
|
||||||
|
#define WDMOD (WDBase->WD_MOD)
|
||||||
|
#define WDTC (WDBase->WD_TC)
|
||||||
|
#define WDFEED (WDBase->WD_FEED)
|
||||||
|
#define WDTV (WDBase->WD_TV)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* DAC.
|
||||||
|
*/
|
||||||
|
#define DACR (*((IOREG32 *)0xE006C000))
|
||||||
|
|
||||||
|
#endif /* _LPC214X_H_ */
|
||||||
|
|
||||||
|
|
@ -0,0 +1,256 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file crt0_v6m.s
|
||||||
|
* @brief Generic ARMv6-M (Cortex-M0/M1) startup file for ChibiOS.
|
||||||
|
*
|
||||||
|
* @addtogroup ARMCMx_GCC_STARTUP_V6M
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module constants. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if !defined(FALSE) || defined(__DOXYGEN__)
|
||||||
|
#define FALSE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(TRUE) || defined(__DOXYGEN__)
|
||||||
|
#define TRUE 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONTROL_MODE_PRIVILEGED 0
|
||||||
|
#define CONTROL_MODE_UNPRIVILEGED 1
|
||||||
|
#define CONTROL_USE_MSP 0
|
||||||
|
#define CONTROL_USE_PSP 2
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module pre-compile time settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Control special register initialization value.
|
||||||
|
* @details The system is setup to run in privileged mode using the PSP
|
||||||
|
* stack (dual stack mode).
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_CONTROL_INIT (CONTROL_USE_PSP | \
|
||||||
|
CONTROL_MODE_PRIVILEGED)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Core initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_CORE TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stack segments initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_STACKS_FILL_PATTERN 0x55555555
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stack segments initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_STACKS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DATA segment initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_DATA TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief BSS segment initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_BSS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief RAM areas initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_RAM_AREAS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_RAM_AREAS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Constructors invocation switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_CALL_CONSTRUCTORS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Destructors invocation switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_CALL_DESTRUCTORS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Code section. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
|
||||||
|
.cpu cortex-m0
|
||||||
|
.fpu softvfp
|
||||||
|
|
||||||
|
.thumb
|
||||||
|
.text
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Reset handler.
|
||||||
|
*/
|
||||||
|
.align 2
|
||||||
|
.thumb_func
|
||||||
|
.global Reset_Handler
|
||||||
|
Reset_Handler:
|
||||||
|
/* Interrupts are globally masked initially.*/
|
||||||
|
cpsid i
|
||||||
|
|
||||||
|
/* PSP stack pointers initialization.*/
|
||||||
|
ldr r0, =__process_stack_end__
|
||||||
|
msr PSP, r0
|
||||||
|
|
||||||
|
/* CPU mode initialization as configured.*/
|
||||||
|
movs r0, #CRT0_CONTROL_INIT
|
||||||
|
msr CONTROL, r0
|
||||||
|
isb
|
||||||
|
|
||||||
|
#if CRT0_INIT_CORE == TRUE
|
||||||
|
/* Core initialization.*/
|
||||||
|
bl __core_init
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Early initialization..*/
|
||||||
|
bl __early_init
|
||||||
|
|
||||||
|
#if CRT0_INIT_STACKS == TRUE
|
||||||
|
ldr r0, =CRT0_STACKS_FILL_PATTERN
|
||||||
|
/* Main Stack initialization. Note, it assumes that the
|
||||||
|
stack size is a multiple of 4 so the linker file must
|
||||||
|
ensure this.*/
|
||||||
|
ldr r1, =__main_stack_base__
|
||||||
|
ldr r2, =__main_stack_end__
|
||||||
|
msloop:
|
||||||
|
cmp r1, r2
|
||||||
|
bge endmsloop
|
||||||
|
str r0, [r1]
|
||||||
|
add r1, r1, #4
|
||||||
|
b msloop
|
||||||
|
endmsloop:
|
||||||
|
/* Process Stack initialization. Note, it assumes that the
|
||||||
|
stack size is a multiple of 4 so the linker file must
|
||||||
|
ensure this.*/
|
||||||
|
ldr r1, =__process_stack_base__
|
||||||
|
ldr r2, =__process_stack_end__
|
||||||
|
psloop:
|
||||||
|
cmp r1, r2
|
||||||
|
bge endpsloop
|
||||||
|
str r0, [r1]
|
||||||
|
add r1, r1, #4
|
||||||
|
b psloop
|
||||||
|
endpsloop:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CRT0_INIT_DATA == TRUE
|
||||||
|
/* Data initialization. Note, it assumes that the DATA size
|
||||||
|
is a multiple of 4 so the linker file must ensure this.*/
|
||||||
|
ldr r1, =_textdata
|
||||||
|
ldr r2, =_data
|
||||||
|
ldr r3, =_edata
|
||||||
|
dloop:
|
||||||
|
cmp r2, r3
|
||||||
|
bge enddloop
|
||||||
|
ldr r0, [r1]
|
||||||
|
str r0, [r2]
|
||||||
|
add r1, r1, #4
|
||||||
|
add r2, r2, #4
|
||||||
|
b dloop
|
||||||
|
enddloop:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CRT0_INIT_BSS == TRUE
|
||||||
|
/* BSS initialization. Note, it assumes that the DATA size
|
||||||
|
is a multiple of 4 so the linker file must ensure this.*/
|
||||||
|
movs r0, #0
|
||||||
|
ldr r1, =_bss_start
|
||||||
|
ldr r2, =_bss_end
|
||||||
|
bloop:
|
||||||
|
cmp r1, r2
|
||||||
|
bge endbloop
|
||||||
|
str r0, [r1]
|
||||||
|
add r1, r1, #4
|
||||||
|
b bloop
|
||||||
|
endbloop:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CRT0_INIT_RAM_AREAS == TRUE
|
||||||
|
/* RAM areas initialization.*/
|
||||||
|
bl __init_ram_areas
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Late initialization..*/
|
||||||
|
bl __late_init
|
||||||
|
|
||||||
|
#if CRT0_CALL_CONSTRUCTORS == TRUE
|
||||||
|
/* Constructors invocation.*/
|
||||||
|
ldr r4, =__init_array_start
|
||||||
|
ldr r5, =__init_array_end
|
||||||
|
initloop:
|
||||||
|
cmp r4, r5
|
||||||
|
bge endinitloop
|
||||||
|
ldr r1, [r4]
|
||||||
|
blx r1
|
||||||
|
add r4, r4, #4
|
||||||
|
b initloop
|
||||||
|
endinitloop:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Main program invocation, r0 contains the returned value.*/
|
||||||
|
bl main
|
||||||
|
|
||||||
|
#if CRT0_CALL_DESTRUCTORS == TRUE
|
||||||
|
/* Destructors invocation.*/
|
||||||
|
ldr r4, =__fini_array_start
|
||||||
|
ldr r5, =__fini_array_end
|
||||||
|
finiloop:
|
||||||
|
cmp r4, r5
|
||||||
|
bge endfiniloop
|
||||||
|
ldr r1, [r4]
|
||||||
|
blx r1
|
||||||
|
add r4, r4, #4
|
||||||
|
b finiloop
|
||||||
|
endfiniloop:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Branching to the defined exit handler.*/
|
||||||
|
ldr r1, =__default_exit
|
||||||
|
bx r1
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,319 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file crt0_v7m.s
|
||||||
|
* @brief Generic ARMv7-M (Cortex-M3/M4/M7) startup file for ChibiOS.
|
||||||
|
*
|
||||||
|
* @addtogroup ARMCMx_GCC_STARTUP_V7M
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module constants. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if !defined(FALSE) || defined(__DOXYGEN__)
|
||||||
|
#define FALSE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(TRUE) || defined(__DOXYGEN__)
|
||||||
|
#define TRUE 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONTROL_MODE_PRIVILEGED 0
|
||||||
|
#define CONTROL_MODE_UNPRIVILEGED 1
|
||||||
|
#define CONTROL_USE_MSP 0
|
||||||
|
#define CONTROL_USE_PSP 2
|
||||||
|
#define CONTROL_FPCA 4
|
||||||
|
|
||||||
|
#define FPCCR_ASPEN (1 << 31)
|
||||||
|
#define FPCCR_LSPEN (1 << 30)
|
||||||
|
|
||||||
|
#define SCB_CPACR 0xE000ED88
|
||||||
|
#define SCB_FPCCR 0xE000EF34
|
||||||
|
#define SCB_FPDSCR 0xE000EF3C
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module pre-compile time settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief FPU initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_FPU) || defined(__DOXYGEN__)
|
||||||
|
#if defined(CORTEX_USE_FPU) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_FPU CORTEX_USE_FPU
|
||||||
|
#else
|
||||||
|
#define CRT0_INIT_FPU FALSE
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Control special register initialization value.
|
||||||
|
* @details The system is setup to run in privileged mode using the PSP
|
||||||
|
* stack (dual stack mode).
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_CONTROL_INIT (CONTROL_USE_PSP | \
|
||||||
|
CONTROL_MODE_PRIVILEGED)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Core initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_CORE TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stack segments initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_STACKS_FILL_PATTERN 0x55555555
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stack segments initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_STACKS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DATA segment initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_DATA TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief BSS segment initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_BSS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief RAM areas initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_RAM_AREAS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_RAM_AREAS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Constructors invocation switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_CALL_CONSTRUCTORS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Destructors invocation switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_CALL_DESTRUCTORS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief FPU FPCCR register initialization value.
|
||||||
|
* @note Only used if @p CRT0_INIT_FPU is equal to @p TRUE.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_FPCCR_INIT) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_FPCCR_INIT (FPCCR_ASPEN | FPCCR_LSPEN)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CPACR register initialization value.
|
||||||
|
* @note Only used if @p CRT0_INIT_FPU is equal to @p TRUE.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_CPACR_INIT) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_CPACR_INIT 0x00F00000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Code section. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
#if CRT0_INIT_FPU == TRUE
|
||||||
|
.fpu fpv4-sp-d16
|
||||||
|
#else
|
||||||
|
.fpu softvfp
|
||||||
|
#endif
|
||||||
|
|
||||||
|
.thumb
|
||||||
|
.text
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Reset handler.
|
||||||
|
*/
|
||||||
|
.align 2
|
||||||
|
.thumb_func
|
||||||
|
.global Reset_Handler
|
||||||
|
Reset_Handler:
|
||||||
|
/* Interrupts are globally masked initially.*/
|
||||||
|
cpsid i
|
||||||
|
|
||||||
|
/* PSP stack pointers initialization.*/
|
||||||
|
ldr r0, =__process_stack_end__
|
||||||
|
msr PSP, r0
|
||||||
|
|
||||||
|
#if CRT0_INIT_FPU == TRUE
|
||||||
|
/* FPU FPCCR initialization.*/
|
||||||
|
movw r0, #CRT0_FPCCR_INIT & 0xFFFF
|
||||||
|
movt r0, #CRT0_FPCCR_INIT >> 16
|
||||||
|
movw r1, #SCB_FPCCR & 0xFFFF
|
||||||
|
movt r1, #SCB_FPCCR >> 16
|
||||||
|
str r0, [r1]
|
||||||
|
dsb
|
||||||
|
isb
|
||||||
|
|
||||||
|
/* CPACR initialization.*/
|
||||||
|
movw r0, #CRT0_CPACR_INIT & 0xFFFF
|
||||||
|
movt r0, #CRT0_CPACR_INIT >> 16
|
||||||
|
movw r1, #SCB_CPACR & 0xFFFF
|
||||||
|
movt r1, #SCB_CPACR >> 16
|
||||||
|
str r0, [r1]
|
||||||
|
dsb
|
||||||
|
isb
|
||||||
|
|
||||||
|
/* FPU FPSCR initially cleared.*/
|
||||||
|
mov r0, #0
|
||||||
|
vmsr FPSCR, r0
|
||||||
|
|
||||||
|
/* FPU FPDSCR initially cleared.*/
|
||||||
|
movw r1, #SCB_FPDSCR & 0xFFFF
|
||||||
|
movt r1, #SCB_FPDSCR >> 16
|
||||||
|
str r0, [r1]
|
||||||
|
|
||||||
|
/* Enforcing FPCA bit in the CONTROL register.*/
|
||||||
|
movs r0, #CRT0_CONTROL_INIT | CONTROL_FPCA
|
||||||
|
|
||||||
|
#else
|
||||||
|
movs r0, #CRT0_CONTROL_INIT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CONTROL register initialization as configured.*/
|
||||||
|
msr CONTROL, r0
|
||||||
|
isb
|
||||||
|
|
||||||
|
#if CRT0_INIT_CORE == TRUE
|
||||||
|
/* Core initialization.*/
|
||||||
|
bl __core_init
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Early initialization.*/
|
||||||
|
bl __early_init
|
||||||
|
|
||||||
|
#if CRT0_INIT_STACKS == TRUE
|
||||||
|
ldr r0, =CRT0_STACKS_FILL_PATTERN
|
||||||
|
/* Main Stack initialization. Note, it assumes that the
|
||||||
|
stack size is a multiple of 4 so the linker file must
|
||||||
|
ensure this.*/
|
||||||
|
ldr r1, =__main_stack_base__
|
||||||
|
ldr r2, =__main_stack_end__
|
||||||
|
msloop:
|
||||||
|
cmp r1, r2
|
||||||
|
itt lo
|
||||||
|
strlo r0, [r1], #4
|
||||||
|
blo msloop
|
||||||
|
|
||||||
|
/* Process Stack initialization. Note, it assumes that the
|
||||||
|
stack size is a multiple of 4 so the linker file must
|
||||||
|
ensure this.*/
|
||||||
|
ldr r1, =__process_stack_base__
|
||||||
|
ldr r2, =__process_stack_end__
|
||||||
|
psloop:
|
||||||
|
cmp r1, r2
|
||||||
|
itt lo
|
||||||
|
strlo r0, [r1], #4
|
||||||
|
blo psloop
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CRT0_INIT_DATA == TRUE
|
||||||
|
/* Data initialization. Note, it assumes that the DATA size
|
||||||
|
is a multiple of 4 so the linker file must ensure this.*/
|
||||||
|
ldr r1, =_textdata_start
|
||||||
|
ldr r2, =_data_start
|
||||||
|
ldr r3, =_data_end
|
||||||
|
dloop:
|
||||||
|
cmp r2, r3
|
||||||
|
ittt lo
|
||||||
|
ldrlo r0, [r1], #4
|
||||||
|
strlo r0, [r2], #4
|
||||||
|
blo dloop
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CRT0_INIT_BSS == TRUE
|
||||||
|
/* BSS initialization. Note, it assumes that the DATA size
|
||||||
|
is a multiple of 4 so the linker file must ensure this.*/
|
||||||
|
movs r0, #0
|
||||||
|
ldr r1, =_bss_start
|
||||||
|
ldr r2, =_bss_end
|
||||||
|
bloop:
|
||||||
|
cmp r1, r2
|
||||||
|
itt lo
|
||||||
|
strlo r0, [r1], #4
|
||||||
|
blo bloop
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CRT0_INIT_RAM_AREAS == TRUE
|
||||||
|
/* RAM areas initialization.*/
|
||||||
|
bl __init_ram_areas
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Late initialization..*/
|
||||||
|
bl __late_init
|
||||||
|
|
||||||
|
#if CRT0_CALL_CONSTRUCTORS == TRUE
|
||||||
|
/* Constructors invocation.*/
|
||||||
|
ldr r4, =__init_array_start
|
||||||
|
ldr r5, =__init_array_end
|
||||||
|
initloop:
|
||||||
|
cmp r4, r5
|
||||||
|
bge endinitloop
|
||||||
|
ldr r1, [r4], #4
|
||||||
|
blx r1
|
||||||
|
b initloop
|
||||||
|
endinitloop:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Main program invocation, r0 contains the returned value.*/
|
||||||
|
bl main
|
||||||
|
|
||||||
|
#if CRT0_CALL_DESTRUCTORS == TRUE
|
||||||
|
/* Destructors invocation.*/
|
||||||
|
ldr r4, =__fini_array_start
|
||||||
|
ldr r5, =__fini_array_end
|
||||||
|
finiloop:
|
||||||
|
cmp r4, r5
|
||||||
|
bge endfiniloop
|
||||||
|
ldr r1, [r4], #4
|
||||||
|
blx r1
|
||||||
|
b finiloop
|
||||||
|
endfiniloop:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Branching to the defined exit handler.*/
|
||||||
|
b __default_exit
|
||||||
|
|
||||||
|
#endif /* !defined(__DOXYGEN__) */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,218 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file ARMCMx/compilers/GCC/crt1.c
|
||||||
|
* @brief Startup stub functions.
|
||||||
|
*
|
||||||
|
* @addtogroup ARMCMx_GCC_STARTUP
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdbool.h>
|
||||||
|
|
||||||
|
#include "cmparams.h"
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module local definitions. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if !defined(CRT1_AREAS_NUMBER) || defined(__DOXYGEN__)
|
||||||
|
#define CRT1_AREAS_NUMBER 8
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CRT1_AREAS_NUMBER < 0) || (CRT1_AREAS_NUMBER > 8)
|
||||||
|
#error "CRT1_AREAS_NUMBER must be within 0 and 8"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module exported variables. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module local types. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Type of an area to be initialized.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
uint32_t *init_text_area;
|
||||||
|
uint32_t *init_area;
|
||||||
|
uint32_t *clear_area;
|
||||||
|
uint32_t *no_init_area;
|
||||||
|
} ram_init_area_t;
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module local variables. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if (CRT1_AREAS_NUMBER > 0) || defined(__DOXYGEN__)
|
||||||
|
extern uint32_t __ram0_init_text__, __ram0_init__, __ram0_clear__, __ram0_noinit__;
|
||||||
|
#endif
|
||||||
|
#if (CRT1_AREAS_NUMBER > 1) || defined(__DOXYGEN__)
|
||||||
|
extern uint32_t __ram1_init_text__, __ram1_init__, __ram1_clear__, __ram1_noinit__;
|
||||||
|
#endif
|
||||||
|
#if (CRT1_AREAS_NUMBER > 2) || defined(__DOXYGEN__)
|
||||||
|
extern uint32_t __ram2_init_text__, __ram2_init__, __ram2_clear__, __ram2_noinit__;
|
||||||
|
#endif
|
||||||
|
#if (CRT1_AREAS_NUMBER > 3) || defined(__DOXYGEN__)
|
||||||
|
extern uint32_t __ram3_init_text__, __ram3_init__, __ram3_clear__, __ram3_noinit__;
|
||||||
|
#endif
|
||||||
|
#if (CRT1_AREAS_NUMBER > 4) || defined(__DOXYGEN__)
|
||||||
|
extern uint32_t __ram4_init_text__, __ram4_init__, __ram4_clear__, __ram4_noinit__;
|
||||||
|
#endif
|
||||||
|
#if (CRT1_AREAS_NUMBER > 5) || defined(__DOXYGEN__)
|
||||||
|
extern uint32_t __ram5_init_text__, __ram5_init__, __ram5_clear__, __ram5_noinit__;
|
||||||
|
#endif
|
||||||
|
#if (CRT1_AREAS_NUMBER > 6) || defined(__DOXYGEN__)
|
||||||
|
extern uint32_t __ram6_init_text__, __ram6_init__, __ram6_clear__, __ram6_noinit__;
|
||||||
|
#endif
|
||||||
|
#if (CRT1_AREAS_NUMBER > 7) || defined(__DOXYGEN__)
|
||||||
|
extern uint32_t __ram7_init_text__, __ram7_init__, __ram7_clear__, __ram7_noinit__;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Static table of areas to be initialized.
|
||||||
|
*/
|
||||||
|
#if (CRT1_AREAS_NUMBER > 0) || defined(__DOXYGEN__)
|
||||||
|
static const ram_init_area_t ram_areas[CRT1_AREAS_NUMBER] = {
|
||||||
|
{&__ram0_init_text__, &__ram0_init__, &__ram0_clear__, &__ram0_noinit__},
|
||||||
|
#if (CRT1_AREAS_NUMBER > 1) || defined(__DOXYGEN__)
|
||||||
|
{&__ram1_init_text__, &__ram1_init__, &__ram1_clear__, &__ram1_noinit__},
|
||||||
|
#endif
|
||||||
|
#if (CRT1_AREAS_NUMBER > 2) || defined(__DOXYGEN__)
|
||||||
|
{&__ram2_init_text__, &__ram2_init__, &__ram2_clear__, &__ram2_noinit__},
|
||||||
|
#endif
|
||||||
|
#if (CRT1_AREAS_NUMBER > 3) || defined(__DOXYGEN__)
|
||||||
|
{&__ram3_init_text__, &__ram3_init__, &__ram3_clear__, &__ram3_noinit__},
|
||||||
|
#endif
|
||||||
|
#if (CRT1_AREAS_NUMBER > 4) || defined(__DOXYGEN__)
|
||||||
|
{&__ram4_init_text__, &__ram4_init__, &__ram4_clear__, &__ram4_noinit__},
|
||||||
|
#endif
|
||||||
|
#if (CRT1_AREAS_NUMBER > 5) || defined(__DOXYGEN__)
|
||||||
|
{&__ram5_init_text__, &__ram5_init__, &__ram5_clear__, &__ram5_noinit__},
|
||||||
|
#endif
|
||||||
|
#if (CRT1_AREAS_NUMBER > 6) || defined(__DOXYGEN__)
|
||||||
|
{&__ram6_init_text__, &__ram6_init__, &__ram6_clear__, &__ram6_noinit__},
|
||||||
|
#endif
|
||||||
|
#if (CRT1_AREAS_NUMBER > 7) || defined(__DOXYGEN__)
|
||||||
|
{&__ram7_init_text__, &__ram7_init__, &__ram7_clear__, &__ram7_noinit__},
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module local functions. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module exported functions. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Architecture-dependent core initialization.
|
||||||
|
* @details This hook is invoked immediately after the stack initialization
|
||||||
|
* and before the DATA and BSS segments initialization.
|
||||||
|
* @note This function is a weak symbol.
|
||||||
|
*/
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
__attribute__((weak))
|
||||||
|
#endif
|
||||||
|
/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
|
||||||
|
void __core_init(void) {
|
||||||
|
|
||||||
|
#if __CORTEX_M == 7
|
||||||
|
SCB_EnableICache();
|
||||||
|
SCB_EnableDCache();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Early initialization.
|
||||||
|
* @details This hook is invoked immediately after the stack and core
|
||||||
|
* initialization and before the DATA and BSS segments
|
||||||
|
* initialization.
|
||||||
|
* @note This function is a weak symbol.
|
||||||
|
*/
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
__attribute__((weak))
|
||||||
|
#endif
|
||||||
|
/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
|
||||||
|
void __early_init(void) {}
|
||||||
|
/*lint -restore*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Late initialization.
|
||||||
|
* @details This hook is invoked after the DATA and BSS segments
|
||||||
|
* initialization and before any static constructor. The
|
||||||
|
* default behavior is to do nothing.
|
||||||
|
* @note This function is a weak symbol.
|
||||||
|
*/
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
__attribute__((weak))
|
||||||
|
#endif
|
||||||
|
/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
|
||||||
|
void __late_init(void) {}
|
||||||
|
/*lint -restore*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Default @p main() function exit handler.
|
||||||
|
* @details This handler is invoked or the @p main() function exit. The
|
||||||
|
* default behavior is to enter an infinite loop.
|
||||||
|
* @note This function is a weak symbol.
|
||||||
|
*/
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
__attribute__((noreturn, weak))
|
||||||
|
#endif
|
||||||
|
/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
|
||||||
|
void __default_exit(void) {
|
||||||
|
/*lint -restore*/
|
||||||
|
|
||||||
|
while (true) {
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Performs the initialization of the various RAM areas.
|
||||||
|
*/
|
||||||
|
void __init_ram_areas(void) {
|
||||||
|
#if CRT1_AREAS_NUMBER > 0
|
||||||
|
const ram_init_area_t *rap = ram_areas;
|
||||||
|
|
||||||
|
do {
|
||||||
|
uint32_t *tp = rap->init_text_area;
|
||||||
|
uint32_t *p = rap->init_area;
|
||||||
|
|
||||||
|
/* Copying initialization data.*/
|
||||||
|
while (p < rap->clear_area) {
|
||||||
|
*p = *tp;
|
||||||
|
p++;
|
||||||
|
tp++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Zeroing clear area.*/
|
||||||
|
while (p < rap->no_init_area) {
|
||||||
|
*p = 0;
|
||||||
|
p++;
|
||||||
|
}
|
||||||
|
rap++;
|
||||||
|
}
|
||||||
|
while (rap < &ram_areas[CRT1_AREAS_NUMBER]);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,389 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* KL25Z128 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash0 : org = 0x00000000, len = 0x100
|
||||||
|
flashcfg : org = 0x00000400, len = 0x10
|
||||||
|
flash : org = 0x00000410, len = 128k - 0x410
|
||||||
|
ram0 : org = 0x1FFFF000, len = 16k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
__ram0_start__ = ORIGIN(ram0);
|
||||||
|
__ram0_size__ = LENGTH(ram0);
|
||||||
|
__ram0_end__ = __ram0_start__ + __ram0_size__;
|
||||||
|
__ram1_start__ = ORIGIN(ram1);
|
||||||
|
__ram1_size__ = LENGTH(ram1);
|
||||||
|
__ram1_end__ = __ram1_start__ + __ram1_size__;
|
||||||
|
__ram2_start__ = ORIGIN(ram2);
|
||||||
|
__ram2_size__ = LENGTH(ram2);
|
||||||
|
__ram2_end__ = __ram2_start__ + __ram2_size__;
|
||||||
|
__ram3_start__ = ORIGIN(ram3);
|
||||||
|
__ram3_size__ = LENGTH(ram3);
|
||||||
|
__ram3_end__ = __ram3_start__ + __ram3_size__;
|
||||||
|
__ram4_start__ = ORIGIN(ram4);
|
||||||
|
__ram4_size__ = LENGTH(ram4);
|
||||||
|
__ram4_end__ = __ram4_start__ + __ram4_size__;
|
||||||
|
__ram5_start__ = ORIGIN(ram5);
|
||||||
|
__ram5_size__ = LENGTH(ram5);
|
||||||
|
__ram5_end__ = __ram5_start__ + __ram5_size__;
|
||||||
|
__ram6_start__ = ORIGIN(ram6);
|
||||||
|
__ram6_size__ = LENGTH(ram6);
|
||||||
|
__ram6_end__ = __ram6_start__ + __ram6_size__;
|
||||||
|
__ram7_start__ = ORIGIN(ram7);
|
||||||
|
__ram7_size__ = LENGTH(ram7);
|
||||||
|
__ram7_end__ = __ram7_start__ + __ram7_size__;
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
. = 0;
|
||||||
|
|
||||||
|
startup : ALIGN(16) SUBALIGN(16)
|
||||||
|
{
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
} > flash0
|
||||||
|
|
||||||
|
.cfmprotect : ALIGN(4) SUBALIGN(4)
|
||||||
|
{
|
||||||
|
KEEP(*(.cfmconfig))
|
||||||
|
} > flashcfg
|
||||||
|
|
||||||
|
_text = .;
|
||||||
|
|
||||||
|
constructors : ALIGN(4) SUBALIGN(4)
|
||||||
|
{
|
||||||
|
__init_array_start = .;
|
||||||
|
KEEP(*(SORT(.init_array.*)))
|
||||||
|
KEEP(*(.init_array))
|
||||||
|
__init_array_end = .;
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
destructors : ALIGN(4) SUBALIGN(4)
|
||||||
|
{
|
||||||
|
__fini_array_start = .;
|
||||||
|
KEEP(*(.fini_array))
|
||||||
|
KEEP(*(SORT(.fini_array.*)))
|
||||||
|
__fini_array_end = .;
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.text : ALIGN(16) SUBALIGN(16)
|
||||||
|
{
|
||||||
|
*(.text)
|
||||||
|
*(.text.*)
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata.*)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.gcc*)
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.ARM.exidx : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.eh_frame_hdr :
|
||||||
|
{
|
||||||
|
*(.eh_frame_hdr)
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.eh_frame : ONLY_IF_RO
|
||||||
|
{
|
||||||
|
*(.eh_frame)
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.textalign : ONLY_IF_RO
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
/* Legacy symbol, not used anywhere.*/
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_etext = .);
|
||||||
|
|
||||||
|
/* Special section for exceptions stack.*/
|
||||||
|
.mstack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
__main_stack_base__ = .;
|
||||||
|
. += __main_stack_size__;
|
||||||
|
. = ALIGN(8);
|
||||||
|
__main_stack_end__ = .;
|
||||||
|
} > MAIN_STACK_RAM
|
||||||
|
|
||||||
|
/* Special section for process stack.*/
|
||||||
|
.pstack :
|
||||||
|
{
|
||||||
|
__process_stack_base__ = .;
|
||||||
|
__main_thread_stack_base__ = .;
|
||||||
|
. += __process_stack_size__;
|
||||||
|
. = ALIGN(8);
|
||||||
|
__process_stack_end__ = .;
|
||||||
|
__main_thread_stack_end__ = .;
|
||||||
|
} > PROCESS_STACK_RAM
|
||||||
|
|
||||||
|
.data : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_textdata = LOADADDR(.data));
|
||||||
|
PROVIDE(_data = .);
|
||||||
|
_textdata_start = LOADADDR(.data);
|
||||||
|
_data_start = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data.*)
|
||||||
|
*(.ramtext)
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_edata = .);
|
||||||
|
_data_end = .;
|
||||||
|
} > DATA_RAM AT > flash
|
||||||
|
|
||||||
|
.bss (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_bss_start = .;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss.*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_bss_end = .;
|
||||||
|
PROVIDE(end = .);
|
||||||
|
} > BSS_RAM
|
||||||
|
|
||||||
|
.ram0_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_init_text__ = LOADADDR(.ram0_init);
|
||||||
|
__ram0_init__ = .;
|
||||||
|
*(.ram0_init)
|
||||||
|
*(.ram0_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram0 AT > flash
|
||||||
|
|
||||||
|
.ram0 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_clear__ = .;
|
||||||
|
*(.ram0_clear)
|
||||||
|
*(.ram0_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_noinit__ = .;
|
||||||
|
*(.ram0)
|
||||||
|
*(.ram0.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_free__ = .;
|
||||||
|
} > ram0
|
||||||
|
|
||||||
|
.ram1_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_init_text__ = LOADADDR(.ram1_init);
|
||||||
|
__ram1_init__ = .;
|
||||||
|
*(.ram1_init)
|
||||||
|
*(.ram1_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram1 AT > flash
|
||||||
|
|
||||||
|
.ram1 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_clear__ = .;
|
||||||
|
*(.ram1_clear)
|
||||||
|
*(.ram1_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_noinit__ = .;
|
||||||
|
*(.ram1)
|
||||||
|
*(.ram1.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_free__ = .;
|
||||||
|
} > ram1
|
||||||
|
|
||||||
|
.ram2_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_init_text__ = LOADADDR(.ram2_init);
|
||||||
|
__ram2_init__ = .;
|
||||||
|
*(.ram2_init)
|
||||||
|
*(.ram2_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram2 AT > flash
|
||||||
|
|
||||||
|
.ram2 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_clear__ = .;
|
||||||
|
*(.ram2_clear)
|
||||||
|
*(.ram2_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_noinit__ = .;
|
||||||
|
*(.ram2)
|
||||||
|
*(.ram2.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_free__ = .;
|
||||||
|
} > ram2
|
||||||
|
|
||||||
|
.ram3_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_init_text__ = LOADADDR(.ram3_init);
|
||||||
|
__ram3_init__ = .;
|
||||||
|
*(.ram3_init)
|
||||||
|
*(.ram3_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram3 AT > flash
|
||||||
|
|
||||||
|
.ram3 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_clear__ = .;
|
||||||
|
*(.ram3_clear)
|
||||||
|
*(.ram3_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_noinit__ = .;
|
||||||
|
*(.ram3)
|
||||||
|
*(.ram3.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_free__ = .;
|
||||||
|
} > ram3
|
||||||
|
|
||||||
|
.ram4_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_init_text__ = LOADADDR(.ram4_init);
|
||||||
|
__ram4_init__ = .;
|
||||||
|
*(.ram4_init)
|
||||||
|
*(.ram4_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram4 AT > flash
|
||||||
|
|
||||||
|
.ram4 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_clear__ = .;
|
||||||
|
*(.ram4_clear)
|
||||||
|
*(.ram4_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_noinit__ = .;
|
||||||
|
*(.ram4)
|
||||||
|
*(.ram4.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_free__ = .;
|
||||||
|
} > ram4
|
||||||
|
|
||||||
|
.ram5_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_init_text__ = LOADADDR(.ram5_init);
|
||||||
|
__ram5_init__ = .;
|
||||||
|
*(.ram5_init)
|
||||||
|
*(.ram5_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram5 AT > flash
|
||||||
|
|
||||||
|
.ram5 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_clear__ = .;
|
||||||
|
*(.ram5_clear)
|
||||||
|
*(.ram5_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_noinit__ = .;
|
||||||
|
*(.ram5)
|
||||||
|
*(.ram5.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_free__ = .;
|
||||||
|
} > ram5
|
||||||
|
|
||||||
|
.ram6_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_init_text__ = LOADADDR(.ram6_init);
|
||||||
|
__ram6_init__ = .;
|
||||||
|
*(.ram6_init)
|
||||||
|
*(.ram6_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram6 AT > flash
|
||||||
|
|
||||||
|
.ram6 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_clear__ = .;
|
||||||
|
*(.ram6_clear)
|
||||||
|
*(.ram6_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_noinit__ = .;
|
||||||
|
*(.ram6)
|
||||||
|
*(.ram6.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_free__ = .;
|
||||||
|
} > ram6
|
||||||
|
|
||||||
|
.ram7_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_init_text__ = LOADADDR(.ram7_init);
|
||||||
|
__ram7_init__ = .;
|
||||||
|
*(.ram7_init)
|
||||||
|
*(.ram7_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram7 AT > flash
|
||||||
|
|
||||||
|
.ram7 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_clear__ = .;
|
||||||
|
*(.ram7_clear)
|
||||||
|
*(.ram7_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_noinit__ = .;
|
||||||
|
*(.ram7)
|
||||||
|
*(.ram7.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_free__ = .;
|
||||||
|
} > ram7
|
||||||
|
|
||||||
|
/* The default heap uses the (statically) unused part of a RAM section.*/
|
||||||
|
.heap (NOLOAD) :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
__heap_base__ = .;
|
||||||
|
. = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM);
|
||||||
|
__heap_end__ = .;
|
||||||
|
} > HEAP_RAM
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,389 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MK20DX128 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash0 : org = 0x00000000, len = 0x100
|
||||||
|
flashcfg : org = 0x00000400, len = 0x10
|
||||||
|
flash : org = 0x00000410, len = 128k - 0x410
|
||||||
|
ram0 : org = 0x1fffe000, len = 16k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
__ram0_start__ = ORIGIN(ram0);
|
||||||
|
__ram0_size__ = LENGTH(ram0);
|
||||||
|
__ram0_end__ = __ram0_start__ + __ram0_size__;
|
||||||
|
__ram1_start__ = ORIGIN(ram1);
|
||||||
|
__ram1_size__ = LENGTH(ram1);
|
||||||
|
__ram1_end__ = __ram1_start__ + __ram1_size__;
|
||||||
|
__ram2_start__ = ORIGIN(ram2);
|
||||||
|
__ram2_size__ = LENGTH(ram2);
|
||||||
|
__ram2_end__ = __ram2_start__ + __ram2_size__;
|
||||||
|
__ram3_start__ = ORIGIN(ram3);
|
||||||
|
__ram3_size__ = LENGTH(ram3);
|
||||||
|
__ram3_end__ = __ram3_start__ + __ram3_size__;
|
||||||
|
__ram4_start__ = ORIGIN(ram4);
|
||||||
|
__ram4_size__ = LENGTH(ram4);
|
||||||
|
__ram4_end__ = __ram4_start__ + __ram4_size__;
|
||||||
|
__ram5_start__ = ORIGIN(ram5);
|
||||||
|
__ram5_size__ = LENGTH(ram5);
|
||||||
|
__ram5_end__ = __ram5_start__ + __ram5_size__;
|
||||||
|
__ram6_start__ = ORIGIN(ram6);
|
||||||
|
__ram6_size__ = LENGTH(ram6);
|
||||||
|
__ram6_end__ = __ram6_start__ + __ram6_size__;
|
||||||
|
__ram7_start__ = ORIGIN(ram7);
|
||||||
|
__ram7_size__ = LENGTH(ram7);
|
||||||
|
__ram7_end__ = __ram7_start__ + __ram7_size__;
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
. = 0;
|
||||||
|
|
||||||
|
startup : ALIGN(16) SUBALIGN(16)
|
||||||
|
{
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
} > flash0
|
||||||
|
|
||||||
|
.cfmprotect : ALIGN(4) SUBALIGN(4)
|
||||||
|
{
|
||||||
|
KEEP(*(.cfmconfig))
|
||||||
|
} > flashcfg
|
||||||
|
|
||||||
|
_text = .;
|
||||||
|
|
||||||
|
constructors : ALIGN(4) SUBALIGN(4)
|
||||||
|
{
|
||||||
|
__init_array_start = .;
|
||||||
|
KEEP(*(SORT(.init_array.*)))
|
||||||
|
KEEP(*(.init_array))
|
||||||
|
__init_array_end = .;
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
destructors : ALIGN(4) SUBALIGN(4)
|
||||||
|
{
|
||||||
|
__fini_array_start = .;
|
||||||
|
KEEP(*(.fini_array))
|
||||||
|
KEEP(*(SORT(.fini_array.*)))
|
||||||
|
__fini_array_end = .;
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.text : ALIGN(16) SUBALIGN(16)
|
||||||
|
{
|
||||||
|
*(.text)
|
||||||
|
*(.text.*)
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata.*)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.gcc*)
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.ARM.exidx : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.eh_frame_hdr :
|
||||||
|
{
|
||||||
|
*(.eh_frame_hdr)
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.eh_frame : ONLY_IF_RO
|
||||||
|
{
|
||||||
|
*(.eh_frame)
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.textalign : ONLY_IF_RO
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
/* Legacy symbol, not used anywhere.*/
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_etext = .);
|
||||||
|
|
||||||
|
/* Special section for exceptions stack.*/
|
||||||
|
.mstack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
__main_stack_base__ = .;
|
||||||
|
. += __main_stack_size__;
|
||||||
|
. = ALIGN(8);
|
||||||
|
__main_stack_end__ = .;
|
||||||
|
} > MAIN_STACK_RAM
|
||||||
|
|
||||||
|
/* Special section for process stack.*/
|
||||||
|
.pstack :
|
||||||
|
{
|
||||||
|
__process_stack_base__ = .;
|
||||||
|
__main_thread_stack_base__ = .;
|
||||||
|
. += __process_stack_size__;
|
||||||
|
. = ALIGN(8);
|
||||||
|
__process_stack_end__ = .;
|
||||||
|
__main_thread_stack_end__ = .;
|
||||||
|
} > PROCESS_STACK_RAM
|
||||||
|
|
||||||
|
.data : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_textdata = LOADADDR(.data));
|
||||||
|
PROVIDE(_data = .);
|
||||||
|
_textdata_start = LOADADDR(.data);
|
||||||
|
_data_start = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data.*)
|
||||||
|
*(.ramtext)
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_edata = .);
|
||||||
|
_data_end = .;
|
||||||
|
} > DATA_RAM AT > flash
|
||||||
|
|
||||||
|
.bss (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_bss_start = .;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss.*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_bss_end = .;
|
||||||
|
PROVIDE(end = .);
|
||||||
|
} > BSS_RAM
|
||||||
|
|
||||||
|
.ram0_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_init_text__ = LOADADDR(.ram0_init);
|
||||||
|
__ram0_init__ = .;
|
||||||
|
*(.ram0_init)
|
||||||
|
*(.ram0_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram0 AT > flash
|
||||||
|
|
||||||
|
.ram0 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_clear__ = .;
|
||||||
|
*(.ram0_clear)
|
||||||
|
*(.ram0_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_noinit__ = .;
|
||||||
|
*(.ram0)
|
||||||
|
*(.ram0.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_free__ = .;
|
||||||
|
} > ram0
|
||||||
|
|
||||||
|
.ram1_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_init_text__ = LOADADDR(.ram1_init);
|
||||||
|
__ram1_init__ = .;
|
||||||
|
*(.ram1_init)
|
||||||
|
*(.ram1_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram1 AT > flash
|
||||||
|
|
||||||
|
.ram1 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_clear__ = .;
|
||||||
|
*(.ram1_clear)
|
||||||
|
*(.ram1_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_noinit__ = .;
|
||||||
|
*(.ram1)
|
||||||
|
*(.ram1.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_free__ = .;
|
||||||
|
} > ram1
|
||||||
|
|
||||||
|
.ram2_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_init_text__ = LOADADDR(.ram2_init);
|
||||||
|
__ram2_init__ = .;
|
||||||
|
*(.ram2_init)
|
||||||
|
*(.ram2_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram2 AT > flash
|
||||||
|
|
||||||
|
.ram2 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_clear__ = .;
|
||||||
|
*(.ram2_clear)
|
||||||
|
*(.ram2_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_noinit__ = .;
|
||||||
|
*(.ram2)
|
||||||
|
*(.ram2.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_free__ = .;
|
||||||
|
} > ram2
|
||||||
|
|
||||||
|
.ram3_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_init_text__ = LOADADDR(.ram3_init);
|
||||||
|
__ram3_init__ = .;
|
||||||
|
*(.ram3_init)
|
||||||
|
*(.ram3_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram3 AT > flash
|
||||||
|
|
||||||
|
.ram3 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_clear__ = .;
|
||||||
|
*(.ram3_clear)
|
||||||
|
*(.ram3_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_noinit__ = .;
|
||||||
|
*(.ram3)
|
||||||
|
*(.ram3.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_free__ = .;
|
||||||
|
} > ram3
|
||||||
|
|
||||||
|
.ram4_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_init_text__ = LOADADDR(.ram4_init);
|
||||||
|
__ram4_init__ = .;
|
||||||
|
*(.ram4_init)
|
||||||
|
*(.ram4_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram4 AT > flash
|
||||||
|
|
||||||
|
.ram4 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_clear__ = .;
|
||||||
|
*(.ram4_clear)
|
||||||
|
*(.ram4_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_noinit__ = .;
|
||||||
|
*(.ram4)
|
||||||
|
*(.ram4.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_free__ = .;
|
||||||
|
} > ram4
|
||||||
|
|
||||||
|
.ram5_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_init_text__ = LOADADDR(.ram5_init);
|
||||||
|
__ram5_init__ = .;
|
||||||
|
*(.ram5_init)
|
||||||
|
*(.ram5_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram5 AT > flash
|
||||||
|
|
||||||
|
.ram5 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_clear__ = .;
|
||||||
|
*(.ram5_clear)
|
||||||
|
*(.ram5_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_noinit__ = .;
|
||||||
|
*(.ram5)
|
||||||
|
*(.ram5.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_free__ = .;
|
||||||
|
} > ram5
|
||||||
|
|
||||||
|
.ram6_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_init_text__ = LOADADDR(.ram6_init);
|
||||||
|
__ram6_init__ = .;
|
||||||
|
*(.ram6_init)
|
||||||
|
*(.ram6_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram6 AT > flash
|
||||||
|
|
||||||
|
.ram6 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_clear__ = .;
|
||||||
|
*(.ram6_clear)
|
||||||
|
*(.ram6_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_noinit__ = .;
|
||||||
|
*(.ram6)
|
||||||
|
*(.ram6.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_free__ = .;
|
||||||
|
} > ram6
|
||||||
|
|
||||||
|
.ram7_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_init_text__ = LOADADDR(.ram7_init);
|
||||||
|
__ram7_init__ = .;
|
||||||
|
*(.ram7_init)
|
||||||
|
*(.ram7_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram7 AT > flash
|
||||||
|
|
||||||
|
.ram7 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_clear__ = .;
|
||||||
|
*(.ram7_clear)
|
||||||
|
*(.ram7_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_noinit__ = .;
|
||||||
|
*(.ram7)
|
||||||
|
*(.ram7.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_free__ = .;
|
||||||
|
} > ram7
|
||||||
|
|
||||||
|
/* The default heap uses the (statically) unused part of a RAM section.*/
|
||||||
|
.heap (NOLOAD) :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
__heap_base__ = .;
|
||||||
|
. = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM);
|
||||||
|
__heap_end__ = .;
|
||||||
|
} > HEAP_RAM
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F030x4 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 16k
|
||||||
|
ram0 : org = 0x20000000, len = 4k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F030x6 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 32k
|
||||||
|
ram0 : org = 0x20000000, len = 4k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F030x8 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 64k
|
||||||
|
ram0 : org = 0x20000000, len = 8k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F031x6 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 32k
|
||||||
|
ram0 : org = 0x20000000, len = 4k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F042x6 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 32k
|
||||||
|
ram0 : org = 0x20000000, len = 6k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F051x8 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 64k
|
||||||
|
ram0 : org = 0x20000000, len = 8k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F072xB memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 128k
|
||||||
|
ram0 : org = 0x20000000, len = 16k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F091xC memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 256k
|
||||||
|
ram0 : org = 0x20000000, len = 32k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ST32F103x8 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 64k
|
||||||
|
ram0 : org = 0x20000000, len = 20k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ST32F103xB memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 128k
|
||||||
|
ram0 : org = 0x20000000, len = 20k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ST32F103xE memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 384k
|
||||||
|
ram0 : org = 0x20000000, len = 64k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ST32F103xE memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 512k
|
||||||
|
ram0 : org = 0x20000000, len = 64k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,53 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ST32F103xE memory setup for use with the maplemini bootloader.
|
||||||
|
* You will have to
|
||||||
|
* #define CORTEX_VTOR_INIT 0x5000
|
||||||
|
* in your projects chconf.h
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08005000, len = 512k - 0x5000
|
||||||
|
ram0 : org = 0x20000C00, len = 64k - 0xC00
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ST32F103xG memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 1m
|
||||||
|
ram0 : org = 0x20000000, len = 96k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ST32F107xC memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 256k
|
||||||
|
ram0 : org = 0x20000000, len = 64k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,51 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F207xG memory setup.
|
||||||
|
* Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 1M
|
||||||
|
ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
|
||||||
|
ram1 : org = 0x20000000, len = 112k /* SRAM1 */
|
||||||
|
ram2 : org = 0x2001C000, len = 16k /* SRAM2 */
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
|
||||||
|
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F302x8 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 64k
|
||||||
|
ram0 : org = 0x20000000, len = 16k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F303x8 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 64k
|
||||||
|
ram0 : org = 0x20000000, len = 12k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x10000000, len = 4k
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F303xC memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 256k
|
||||||
|
ram0 : org = 0x20000000, len = 40k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x10000000, len = 8k
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F3334x8 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 64k
|
||||||
|
ram0 : org = 0x20000000, len = 12k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x10000000, len = 4k
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F373xC memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 256k
|
||||||
|
ram0 : org = 0x20000000, len = 32k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F401xC memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 256k
|
||||||
|
ram0 : org = 0x20000000, len = 64k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F401xE memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 512k
|
||||||
|
ram0 : org = 0x20000000, len = 96k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F405xG memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 1M
|
||||||
|
ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
|
||||||
|
ram1 : org = 0x20000000, len = 112k /* SRAM1 */
|
||||||
|
ram2 : org = 0x2001C000, len = 16k /* SRAM2 */
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
|
||||||
|
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,51 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F407xG memory setup.
|
||||||
|
* Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 1M
|
||||||
|
ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
|
||||||
|
ram1 : org = 0x20000000, len = 112k /* SRAM1 */
|
||||||
|
ram2 : org = 0x2001C000, len = 16k /* SRAM2 */
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
|
||||||
|
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F411xC memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 256k
|
||||||
|
ram0 : org = 0x20000000, len = 128k /* SRAM1 */
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F411xE memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 512k
|
||||||
|
ram0 : org = 0x20000000, len = 128k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,51 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ST32F429xI memory setup.
|
||||||
|
* Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 2M
|
||||||
|
ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */
|
||||||
|
ram1 : org = 0x20000000, len = 112k /* SRAM1 */
|
||||||
|
ram2 : org = 0x2001C000, len = 16k /* SRAM2 */
|
||||||
|
ram3 : org = 0x20020000, len = 64k /* SRAM3 */
|
||||||
|
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
|
||||||
|
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,63 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ST32F746xG generic setup.
|
||||||
|
*
|
||||||
|
* RAM0 - Data, Heap.
|
||||||
|
* RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.
|
||||||
|
*
|
||||||
|
* Notes:
|
||||||
|
* BSS is placed in DTCM RAM in order to simplify DMA buffers management.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 1M
|
||||||
|
flash_itcm : org = 0x00200000, len = 1M
|
||||||
|
ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
|
||||||
|
ram1 : org = 0x20010000, len = 240k /* SRAM1 */
|
||||||
|
ram2 : org = 0x2004C000, len = 16k /* SRAM2 */
|
||||||
|
ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */
|
||||||
|
ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
|
||||||
|
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram3);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram3);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram3);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for nocache segment.*/
|
||||||
|
REGION_ALIAS("NOCACHE_RAM", ram3);
|
||||||
|
|
||||||
|
/* RAM region to be used for eth segment.*/
|
||||||
|
REGION_ALIAS("ETH_RAM", ram3);
|
||||||
|
|
||||||
|
INCLUDE ld/rules_STM32F7xx.ld
|
||||||
|
|
@ -0,0 +1,63 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ST32F746xG Ethernet setup.
|
||||||
|
*
|
||||||
|
* RAM1 - Data, Heap.
|
||||||
|
* RAM2 - ETH.
|
||||||
|
* RAM3 - Main Stack, Process Stack, BSS, NOCACHE.
|
||||||
|
*
|
||||||
|
* Notes:
|
||||||
|
* BSS is placed in DTCM RAM in order to simplify DMA buffers management.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 1M
|
||||||
|
ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
|
||||||
|
ram1 : org = 0x20010000, len = 240k /* SRAM1 */
|
||||||
|
ram2 : org = 0x2004C000, len = 16k /* SRAM2 */
|
||||||
|
ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */
|
||||||
|
ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
|
||||||
|
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram3);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram3);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram1);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram3);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram1);
|
||||||
|
|
||||||
|
/* RAM region to be used for nocache segment.*/
|
||||||
|
REGION_ALIAS("NOCACHE_RAM", ram3);
|
||||||
|
|
||||||
|
/* RAM region to be used for eth segment.*/
|
||||||
|
REGION_ALIAS("ETH_RAM", ram2);
|
||||||
|
|
||||||
|
INCLUDE rules_dma.ld
|
||||||
|
|
@ -0,0 +1,65 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ST32F746xG maximum RAM setup.
|
||||||
|
*
|
||||||
|
* RAM0 - Data, BSS, Heap.
|
||||||
|
* RAM3 - Main Stack, Process Stack, NOCACHE, ETH.
|
||||||
|
*
|
||||||
|
* Notes:
|
||||||
|
* BSS is placed in cached RAM, DMA buffers management is delegated to the
|
||||||
|
* application code. This setup maximizes the linear RAM available to BSS and
|
||||||
|
* Heap.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 1M
|
||||||
|
flash_itcm : org = 0x00200000, len = 1M
|
||||||
|
ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
|
||||||
|
ram1 : org = 0x20010000, len = 240k /* SRAM1 */
|
||||||
|
ram2 : org = 0x2004C000, len = 16k /* SRAM2 */
|
||||||
|
ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */
|
||||||
|
ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
|
||||||
|
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram3);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram3);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for nocache segment.*/
|
||||||
|
REGION_ALIAS("NOCACHE_RAM", ram3);
|
||||||
|
|
||||||
|
/* RAM region to be used for eth segment.*/
|
||||||
|
REGION_ALIAS("ETH_RAM", ram3);
|
||||||
|
|
||||||
|
INCLUDE ld/rules_STM32F7xx.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32L052x8 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 16k
|
||||||
|
ram0 : org = 0x20000000, len = 8k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32L052x8 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 64k
|
||||||
|
ram0 : org = 0x20000000, len = 8k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32L053x8 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 64k
|
||||||
|
ram0 : org = 0x20000000, len = 8k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32L151x6 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 32k
|
||||||
|
ram0 : org = 0x20000000, len = 10k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32L152xB memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 128k
|
||||||
|
ram0 : org = 0x20000000, len = 16k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32L152xB memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 512k
|
||||||
|
ram0 : org = 0x20000000, len = 80k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x00000000, len = 0
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F303xC memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x08000000, len = 1M
|
||||||
|
ram0 : org = 0x20000000, len = 96k
|
||||||
|
ram1 : org = 0x00000000, len = 0
|
||||||
|
ram2 : org = 0x00000000, len = 0
|
||||||
|
ram3 : org = 0x00000000, len = 0
|
||||||
|
ram4 : org = 0x10000000, len = 32k
|
||||||
|
ram5 : org = 0x00000000, len = 0
|
||||||
|
ram6 : org = 0x00000000, len = 0
|
||||||
|
ram7 : org = 0x00000000, len = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||||
|
of all exceptions and interrupts*/
|
||||||
|
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the process stack. This is the stack used by
|
||||||
|
the main() function.*/
|
||||||
|
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for data segment.*/
|
||||||
|
REGION_ALIAS("DATA_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for BSS segment.*/
|
||||||
|
REGION_ALIAS("BSS_RAM", ram0);
|
||||||
|
|
||||||
|
/* RAM region to be used for the default heap.*/
|
||||||
|
REGION_ALIAS("HEAP_RAM", ram0);
|
||||||
|
|
||||||
|
INCLUDE rules.ld
|
||||||
|
|
@ -0,0 +1,391 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
__ram0_start__ = ORIGIN(ram0);
|
||||||
|
__ram0_size__ = LENGTH(ram0);
|
||||||
|
__ram0_end__ = __ram0_start__ + __ram0_size__;
|
||||||
|
__ram1_start__ = ORIGIN(ram1);
|
||||||
|
__ram1_size__ = LENGTH(ram1);
|
||||||
|
__ram1_end__ = __ram1_start__ + __ram1_size__;
|
||||||
|
__ram2_start__ = ORIGIN(ram2);
|
||||||
|
__ram2_size__ = LENGTH(ram2);
|
||||||
|
__ram2_end__ = __ram2_start__ + __ram2_size__;
|
||||||
|
__ram3_start__ = ORIGIN(ram3);
|
||||||
|
__ram3_size__ = LENGTH(ram3);
|
||||||
|
__ram3_end__ = __ram3_start__ + __ram3_size__;
|
||||||
|
__ram4_start__ = ORIGIN(ram4);
|
||||||
|
__ram4_size__ = LENGTH(ram4);
|
||||||
|
__ram4_end__ = __ram4_start__ + __ram4_size__;
|
||||||
|
__ram5_start__ = ORIGIN(ram5);
|
||||||
|
__ram5_size__ = LENGTH(ram5);
|
||||||
|
__ram5_end__ = __ram5_start__ + __ram5_size__;
|
||||||
|
__ram6_start__ = ORIGIN(ram6);
|
||||||
|
__ram6_size__ = LENGTH(ram6);
|
||||||
|
__ram6_end__ = __ram6_start__ + __ram6_size__;
|
||||||
|
__ram7_start__ = ORIGIN(ram7);
|
||||||
|
__ram7_size__ = LENGTH(ram7);
|
||||||
|
__ram7_end__ = __ram7_start__ + __ram7_size__;
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
. = 0;
|
||||||
|
_text = .;
|
||||||
|
|
||||||
|
startup : ALIGN(16) SUBALIGN(16)
|
||||||
|
{
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
} > flash_itcm AT > flash
|
||||||
|
|
||||||
|
constructors : ALIGN(4) SUBALIGN(4)
|
||||||
|
{
|
||||||
|
__init_array_start = .;
|
||||||
|
KEEP(*(SORT(.init_array.*)))
|
||||||
|
KEEP(*(.init_array))
|
||||||
|
__init_array_end = .;
|
||||||
|
} > flash_itcm AT > flash
|
||||||
|
|
||||||
|
destructors : ALIGN(4) SUBALIGN(4)
|
||||||
|
{
|
||||||
|
__fini_array_start = .;
|
||||||
|
KEEP(*(.fini_array))
|
||||||
|
KEEP(*(SORT(.fini_array.*)))
|
||||||
|
__fini_array_end = .;
|
||||||
|
} > flash_itcm AT > flash
|
||||||
|
|
||||||
|
.text : ALIGN(16) SUBALIGN(16)
|
||||||
|
{
|
||||||
|
*(.text)
|
||||||
|
*(.text.*)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.gcc*)
|
||||||
|
} > flash_itcm AT > flash
|
||||||
|
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} > flash_itcm AT > flash
|
||||||
|
|
||||||
|
.ARM.exidx : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} > flash_itcm AT > flash
|
||||||
|
|
||||||
|
.eh_frame_hdr :
|
||||||
|
{
|
||||||
|
*(.eh_frame_hdr)
|
||||||
|
} > flash_itcm AT > flash
|
||||||
|
|
||||||
|
.eh_frame : ONLY_IF_RO
|
||||||
|
{
|
||||||
|
*(.eh_frame)
|
||||||
|
} > flash_itcm AT > flash
|
||||||
|
|
||||||
|
.textalign : ONLY_IF_RO
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > flash_itcm AT > flash
|
||||||
|
|
||||||
|
/* Constants are placed in the normal flash (non-ITCM) region because it
|
||||||
|
is desirable to make them DMA-accessible.*/
|
||||||
|
.rodata : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__rodata_base__ = .;
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__rodata_end__ = .;
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
/* Legacy symbol, not used anywhere.*/
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_etext = .);
|
||||||
|
|
||||||
|
/* Special section for exceptions stack.*/
|
||||||
|
.mstack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
__main_stack_base__ = .;
|
||||||
|
. += __main_stack_size__;
|
||||||
|
. = ALIGN(8);
|
||||||
|
__main_stack_end__ = .;
|
||||||
|
} > MAIN_STACK_RAM
|
||||||
|
|
||||||
|
/* Special section for process stack.*/
|
||||||
|
.pstack :
|
||||||
|
{
|
||||||
|
__process_stack_base__ = .;
|
||||||
|
__main_thread_stack_base__ = .;
|
||||||
|
. += __process_stack_size__;
|
||||||
|
. = ALIGN(8);
|
||||||
|
__process_stack_end__ = .;
|
||||||
|
__main_thread_stack_end__ = .;
|
||||||
|
} > PROCESS_STACK_RAM
|
||||||
|
|
||||||
|
/* Special section for non cache-able areas.*/
|
||||||
|
.nocache (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
__nocache_base__ = .;
|
||||||
|
*(.nocache)
|
||||||
|
*(.nocache.*)
|
||||||
|
*(.bss.__nocache_*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__nocache_end__ = .;
|
||||||
|
} > NOCACHE_RAM
|
||||||
|
|
||||||
|
/* Special section for Ethernet DMA non cache-able areas.*/
|
||||||
|
.eth (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
__eth_base__ = .;
|
||||||
|
*(.eth)
|
||||||
|
*(.eth.*)
|
||||||
|
*(.bss.__eth_*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__eth_end__ = .;
|
||||||
|
} > ETH_RAM
|
||||||
|
|
||||||
|
.data : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_textdata = LOADADDR(.data));
|
||||||
|
PROVIDE(_data = .);
|
||||||
|
_textdata_start = LOADADDR(.data);
|
||||||
|
_data_start = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data.*)
|
||||||
|
*(.ramtext)
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_edata = .);
|
||||||
|
_data_end = .;
|
||||||
|
} > DATA_RAM AT > flash
|
||||||
|
|
||||||
|
.bss (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_bss_start = .;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss.*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_bss_end = .;
|
||||||
|
PROVIDE(end = .);
|
||||||
|
} > BSS_RAM
|
||||||
|
|
||||||
|
.ram0_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_init_text__ = LOADADDR(.ram0_init);
|
||||||
|
__ram0_init__ = .;
|
||||||
|
*(.ram0_init)
|
||||||
|
*(.ram0_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram0 AT > flash
|
||||||
|
|
||||||
|
.ram0 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_clear__ = .;
|
||||||
|
*(.ram0_clear)
|
||||||
|
*(.ram0_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_noinit__ = .;
|
||||||
|
*(.ram0)
|
||||||
|
*(.ram0.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_free__ = .;
|
||||||
|
} > ram0
|
||||||
|
|
||||||
|
.ram1_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_init_text__ = LOADADDR(.ram1_init);
|
||||||
|
__ram1_init__ = .;
|
||||||
|
*(.ram1_init)
|
||||||
|
*(.ram1_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram1 AT > flash
|
||||||
|
|
||||||
|
.ram1 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_clear__ = .;
|
||||||
|
*(.ram1_clear)
|
||||||
|
*(.ram1_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_noinit__ = .;
|
||||||
|
*(.ram1)
|
||||||
|
*(.ram1.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_free__ = .;
|
||||||
|
} > ram1
|
||||||
|
|
||||||
|
.ram2_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_init_text__ = LOADADDR(.ram2_init);
|
||||||
|
__ram2_init__ = .;
|
||||||
|
*(.ram2_init)
|
||||||
|
*(.ram2_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram2 AT > flash
|
||||||
|
|
||||||
|
.ram2 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_clear__ = .;
|
||||||
|
*(.ram2_clear)
|
||||||
|
*(.ram2_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_noinit__ = .;
|
||||||
|
*(.ram2)
|
||||||
|
*(.ram2.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_free__ = .;
|
||||||
|
} > ram2
|
||||||
|
|
||||||
|
.ram3_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_init_text__ = LOADADDR(.ram3_init);
|
||||||
|
__ram3_init__ = .;
|
||||||
|
*(.ram3_init)
|
||||||
|
*(.ram3_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram3 AT > flash
|
||||||
|
|
||||||
|
.ram3 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_clear__ = .;
|
||||||
|
*(.ram3_clear)
|
||||||
|
*(.ram3_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_noinit__ = .;
|
||||||
|
*(.ram3)
|
||||||
|
*(.ram3.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_free__ = .;
|
||||||
|
} > ram3
|
||||||
|
|
||||||
|
.ram4_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_init_text__ = LOADADDR(.ram4_init);
|
||||||
|
__ram4_init__ = .;
|
||||||
|
*(.ram4_init)
|
||||||
|
*(.ram4_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram4 AT > flash
|
||||||
|
|
||||||
|
.ram4 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_clear__ = .;
|
||||||
|
*(.ram4_clear)
|
||||||
|
*(.ram4_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_noinit__ = .;
|
||||||
|
*(.ram4)
|
||||||
|
*(.ram4.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_free__ = .;
|
||||||
|
} > ram4
|
||||||
|
|
||||||
|
.ram5_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_init_text__ = LOADADDR(.ram5_init);
|
||||||
|
__ram5_init__ = .;
|
||||||
|
*(.ram5_init)
|
||||||
|
*(.ram5_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram5 AT > flash
|
||||||
|
|
||||||
|
.ram5 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_clear__ = .;
|
||||||
|
*(.ram5_clear)
|
||||||
|
*(.ram5_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_noinit__ = .;
|
||||||
|
*(.ram5)
|
||||||
|
*(.ram5.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_free__ = .;
|
||||||
|
} > ram5
|
||||||
|
|
||||||
|
.ram6_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_init_text__ = LOADADDR(.ram6_init);
|
||||||
|
__ram6_init__ = .;
|
||||||
|
*(.ram6_init)
|
||||||
|
*(.ram6_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram6 AT > flash
|
||||||
|
|
||||||
|
.ram6 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_clear__ = .;
|
||||||
|
*(.ram6_clear)
|
||||||
|
*(.ram6_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_noinit__ = .;
|
||||||
|
*(.ram6)
|
||||||
|
*(.ram6.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_free__ = .;
|
||||||
|
} > ram6
|
||||||
|
|
||||||
|
.ram7_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_init_text__ = LOADADDR(.ram7_init);
|
||||||
|
__ram7_init__ = .;
|
||||||
|
*(.ram7_init)
|
||||||
|
*(.ram7_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram7 AT > flash
|
||||||
|
|
||||||
|
.ram7 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_clear__ = .;
|
||||||
|
*(.ram7_clear)
|
||||||
|
*(.ram7_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_noinit__ = .;
|
||||||
|
*(.ram7)
|
||||||
|
*(.ram7.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_free__ = .;
|
||||||
|
} > ram7
|
||||||
|
|
||||||
|
/* The default heap uses the (statically) unused part of a RAM section.*/
|
||||||
|
.heap (NOLOAD) :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
__heap_base__ = .;
|
||||||
|
. = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM);
|
||||||
|
__heap_end__ = .;
|
||||||
|
} > HEAP_RAM
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
# List of the ChibiOS generic K20x startup and CMSIS files.
|
||||||
|
STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c
|
||||||
|
|
||||||
|
STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s
|
||||||
|
|
||||||
|
STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/devices/K20x \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/include \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/KINETIS
|
||||||
|
|
||||||
|
STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
# List of the ChibiOS generic KL2x startup and CMSIS files.
|
||||||
|
STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c
|
||||||
|
|
||||||
|
STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v6m.s
|
||||||
|
|
||||||
|
STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/devices/KL2x \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/include \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/KINETIS
|
||||||
|
|
||||||
|
STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
# List of the ChibiOS generic STM32F0xx startup and CMSIS files.
|
||||||
|
STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c
|
||||||
|
|
||||||
|
STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v6m.s
|
||||||
|
|
||||||
|
STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32F0xx \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/include \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/ST/STM32F0xx
|
||||||
|
|
||||||
|
STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
# List of the ChibiOS generic STM32F1xx startup and CMSIS files.
|
||||||
|
STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c
|
||||||
|
|
||||||
|
STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s
|
||||||
|
|
||||||
|
STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32F1xx \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/include \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/ST/STM32F1xx
|
||||||
|
|
||||||
|
STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
# List of the ChibiOS generic STM32F2xx startup and CMSIS files.
|
||||||
|
STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c
|
||||||
|
|
||||||
|
STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s
|
||||||
|
|
||||||
|
STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32F2xx \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/include \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/ST/STM32F2xx
|
||||||
|
|
||||||
|
STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
# List of the ChibiOS generic STM32F3xx startup and CMSIS files.
|
||||||
|
STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c
|
||||||
|
|
||||||
|
STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s
|
||||||
|
|
||||||
|
STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32F3xx \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/include \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/ST/STM32F3xx
|
||||||
|
|
||||||
|
STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
# List of the ChibiOS generic STM32F4xx startup and CMSIS files.
|
||||||
|
STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c
|
||||||
|
|
||||||
|
STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s
|
||||||
|
|
||||||
|
STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32F4xx \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/include \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/ST/STM32F4xx
|
||||||
|
|
||||||
|
STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
# List of the ChibiOS generic STM32F7xx startup and CMSIS files.
|
||||||
|
STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c
|
||||||
|
|
||||||
|
STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s
|
||||||
|
|
||||||
|
STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32F7xx \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/include \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/ST/STM32F7xx
|
||||||
|
|
||||||
|
STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
# List of the ChibiOS generic STM32L0xx startup and CMSIS files.
|
||||||
|
STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c
|
||||||
|
|
||||||
|
STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v6m.s
|
||||||
|
|
||||||
|
STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32L0xx \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/include \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/ST/STM32L0xx
|
||||||
|
|
||||||
|
STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
# List of the ChibiOS generic STM32L1xx startup and CMSIS files.
|
||||||
|
STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c
|
||||||
|
|
||||||
|
STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s
|
||||||
|
|
||||||
|
STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32L1xx \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/include \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/ST/STM32L1xx
|
||||||
|
|
||||||
|
STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
# List of the ChibiOS generic STM32L4xx startup and CMSIS files.
|
||||||
|
STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c
|
||||||
|
|
||||||
|
STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s
|
||||||
|
|
||||||
|
STARTUPINC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC \
|
||||||
|
$(CHIBIOS)/os/common/ports/ARMCMx/devices/STM32L4xx \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/include \
|
||||||
|
$(CHIBIOS)/os/ext/CMSIS/ST/STM32L4xx
|
||||||
|
|
||||||
|
STARTUPLD = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld
|
||||||
|
|
@ -0,0 +1,359 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
__ram0_start__ = ORIGIN(ram0);
|
||||||
|
__ram0_size__ = LENGTH(ram0);
|
||||||
|
__ram0_end__ = __ram0_start__ + __ram0_size__;
|
||||||
|
__ram1_start__ = ORIGIN(ram1);
|
||||||
|
__ram1_size__ = LENGTH(ram1);
|
||||||
|
__ram1_end__ = __ram1_start__ + __ram1_size__;
|
||||||
|
__ram2_start__ = ORIGIN(ram2);
|
||||||
|
__ram2_size__ = LENGTH(ram2);
|
||||||
|
__ram2_end__ = __ram2_start__ + __ram2_size__;
|
||||||
|
__ram3_start__ = ORIGIN(ram3);
|
||||||
|
__ram3_size__ = LENGTH(ram3);
|
||||||
|
__ram3_end__ = __ram3_start__ + __ram3_size__;
|
||||||
|
__ram4_start__ = ORIGIN(ram4);
|
||||||
|
__ram4_size__ = LENGTH(ram4);
|
||||||
|
__ram4_end__ = __ram4_start__ + __ram4_size__;
|
||||||
|
__ram5_start__ = ORIGIN(ram5);
|
||||||
|
__ram5_size__ = LENGTH(ram5);
|
||||||
|
__ram5_end__ = __ram5_start__ + __ram5_size__;
|
||||||
|
__ram6_start__ = ORIGIN(ram6);
|
||||||
|
__ram6_size__ = LENGTH(ram6);
|
||||||
|
__ram6_end__ = __ram6_start__ + __ram6_size__;
|
||||||
|
__ram7_start__ = ORIGIN(ram7);
|
||||||
|
__ram7_size__ = LENGTH(ram7);
|
||||||
|
__ram7_end__ = __ram7_start__ + __ram7_size__;
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
. = 0;
|
||||||
|
_text = .;
|
||||||
|
|
||||||
|
startup : ALIGN(16) SUBALIGN(16)
|
||||||
|
{
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
constructors : ALIGN(4) SUBALIGN(4)
|
||||||
|
{
|
||||||
|
__init_array_start = .;
|
||||||
|
KEEP(*(SORT(.init_array.*)))
|
||||||
|
KEEP(*(.init_array))
|
||||||
|
__init_array_end = .;
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
destructors : ALIGN(4) SUBALIGN(4)
|
||||||
|
{
|
||||||
|
__fini_array_start = .;
|
||||||
|
KEEP(*(.fini_array))
|
||||||
|
KEEP(*(SORT(.fini_array.*)))
|
||||||
|
__fini_array_end = .;
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.text : ALIGN(16) SUBALIGN(16)
|
||||||
|
{
|
||||||
|
*(.text)
|
||||||
|
*(.text.*)
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata.*)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.gcc*)
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.ARM.exidx : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.eh_frame_hdr :
|
||||||
|
{
|
||||||
|
*(.eh_frame_hdr)
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.eh_frame : ONLY_IF_RO
|
||||||
|
{
|
||||||
|
*(.eh_frame)
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
.textalign : ONLY_IF_RO
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > flash
|
||||||
|
|
||||||
|
/* Legacy symbol, not used anywhere.*/
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_etext = .);
|
||||||
|
|
||||||
|
/* Special section for exceptions stack.*/
|
||||||
|
.mstack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
__main_stack_base__ = .;
|
||||||
|
. += __main_stack_size__;
|
||||||
|
. = ALIGN(8);
|
||||||
|
__main_stack_end__ = .;
|
||||||
|
} > MAIN_STACK_RAM
|
||||||
|
|
||||||
|
/* Special section for process stack.*/
|
||||||
|
.pstack :
|
||||||
|
{
|
||||||
|
__process_stack_base__ = .;
|
||||||
|
__main_thread_stack_base__ = .;
|
||||||
|
. += __process_stack_size__;
|
||||||
|
. = ALIGN(8);
|
||||||
|
__process_stack_end__ = .;
|
||||||
|
__main_thread_stack_end__ = .;
|
||||||
|
} > PROCESS_STACK_RAM
|
||||||
|
|
||||||
|
.data : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_textdata = LOADADDR(.data));
|
||||||
|
PROVIDE(_data = .);
|
||||||
|
_textdata_start = LOADADDR(.data);
|
||||||
|
_data_start = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data.*)
|
||||||
|
*(.ramtext)
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_edata = .);
|
||||||
|
_data_end = .;
|
||||||
|
} > DATA_RAM AT > flash
|
||||||
|
|
||||||
|
.bss (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_bss_start = .;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss.*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_bss_end = .;
|
||||||
|
PROVIDE(end = .);
|
||||||
|
} > BSS_RAM
|
||||||
|
|
||||||
|
.ram0_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_init_text__ = LOADADDR(.ram0_init);
|
||||||
|
__ram0_init__ = .;
|
||||||
|
*(.ram0_init)
|
||||||
|
*(.ram0_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram0 AT > flash
|
||||||
|
|
||||||
|
.ram0 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_clear__ = .;
|
||||||
|
*(.ram0_clear)
|
||||||
|
*(.ram0_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_noinit__ = .;
|
||||||
|
*(.ram0)
|
||||||
|
*(.ram0.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram0_free__ = .;
|
||||||
|
} > ram0
|
||||||
|
|
||||||
|
.ram1_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_init_text__ = LOADADDR(.ram1_init);
|
||||||
|
__ram1_init__ = .;
|
||||||
|
*(.ram1_init)
|
||||||
|
*(.ram1_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram1 AT > flash
|
||||||
|
|
||||||
|
.ram1 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_clear__ = .;
|
||||||
|
*(.ram1_clear)
|
||||||
|
*(.ram1_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_noinit__ = .;
|
||||||
|
*(.ram1)
|
||||||
|
*(.ram1.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram1_free__ = .;
|
||||||
|
} > ram1
|
||||||
|
|
||||||
|
.ram2_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_init_text__ = LOADADDR(.ram2_init);
|
||||||
|
__ram2_init__ = .;
|
||||||
|
*(.ram2_init)
|
||||||
|
*(.ram2_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram2 AT > flash
|
||||||
|
|
||||||
|
.ram2 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_clear__ = .;
|
||||||
|
*(.ram2_clear)
|
||||||
|
*(.ram2_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_noinit__ = .;
|
||||||
|
*(.ram2)
|
||||||
|
*(.ram2.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram2_free__ = .;
|
||||||
|
} > ram2
|
||||||
|
|
||||||
|
.ram3_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_init_text__ = LOADADDR(.ram3_init);
|
||||||
|
__ram3_init__ = .;
|
||||||
|
*(.ram3_init)
|
||||||
|
*(.ram3_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram3 AT > flash
|
||||||
|
|
||||||
|
.ram3 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_clear__ = .;
|
||||||
|
*(.ram3_clear)
|
||||||
|
*(.ram3_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_noinit__ = .;
|
||||||
|
*(.ram3)
|
||||||
|
*(.ram3.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram3_free__ = .;
|
||||||
|
} > ram3
|
||||||
|
|
||||||
|
.ram4_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_init_text__ = LOADADDR(.ram4_init);
|
||||||
|
__ram4_init__ = .;
|
||||||
|
*(.ram4_init)
|
||||||
|
*(.ram4_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram4 AT > flash
|
||||||
|
|
||||||
|
.ram4 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_clear__ = .;
|
||||||
|
*(.ram4_clear)
|
||||||
|
*(.ram4_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_noinit__ = .;
|
||||||
|
*(.ram4)
|
||||||
|
*(.ram4.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram4_free__ = .;
|
||||||
|
} > ram4
|
||||||
|
|
||||||
|
.ram5_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_init_text__ = LOADADDR(.ram5_init);
|
||||||
|
__ram5_init__ = .;
|
||||||
|
*(.ram5_init)
|
||||||
|
*(.ram5_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram5 AT > flash
|
||||||
|
|
||||||
|
.ram5 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_clear__ = .;
|
||||||
|
*(.ram5_clear)
|
||||||
|
*(.ram5_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_noinit__ = .;
|
||||||
|
*(.ram5)
|
||||||
|
*(.ram5.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram5_free__ = .;
|
||||||
|
} > ram5
|
||||||
|
|
||||||
|
.ram6_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_init_text__ = LOADADDR(.ram6_init);
|
||||||
|
__ram6_init__ = .;
|
||||||
|
*(.ram6_init)
|
||||||
|
*(.ram6_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram6 AT > flash
|
||||||
|
|
||||||
|
.ram6 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_clear__ = .;
|
||||||
|
*(.ram6_clear)
|
||||||
|
*(.ram6_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_noinit__ = .;
|
||||||
|
*(.ram6)
|
||||||
|
*(.ram6.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram6_free__ = .;
|
||||||
|
} > ram6
|
||||||
|
|
||||||
|
.ram7_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_init_text__ = LOADADDR(.ram7_init);
|
||||||
|
__ram7_init__ = .;
|
||||||
|
*(.ram7_init)
|
||||||
|
*(.ram7_init.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > ram7 AT > flash
|
||||||
|
|
||||||
|
.ram7 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_clear__ = .;
|
||||||
|
*(.ram7_clear)
|
||||||
|
*(.ram7_clear.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_noinit__ = .;
|
||||||
|
*(.ram7)
|
||||||
|
*(.ram7.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ram7_free__ = .;
|
||||||
|
} > ram7
|
||||||
|
|
||||||
|
/* The default heap uses the (statically) unused part of a RAM section.*/
|
||||||
|
.heap (NOLOAD) :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
__heap_base__ = .;
|
||||||
|
. = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM);
|
||||||
|
__heap_end__ = .;
|
||||||
|
} > HEAP_RAM
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,312 @@
|
||||||
|
# ARM Cortex-Mx common makefile scripts and rules.
|
||||||
|
|
||||||
|
##############################################################################
|
||||||
|
# Processing options coming from the upper Makefile.
|
||||||
|
#
|
||||||
|
|
||||||
|
# Compiler options
|
||||||
|
OPT := $(USE_OPT)
|
||||||
|
COPT := $(USE_COPT)
|
||||||
|
CPPOPT := $(USE_CPPOPT)
|
||||||
|
|
||||||
|
# Garbage collection
|
||||||
|
ifeq ($(USE_LINK_GC),yes)
|
||||||
|
OPT += -ffunction-sections -fdata-sections -fno-common
|
||||||
|
LDOPT := ,--gc-sections
|
||||||
|
else
|
||||||
|
LDOPT :=
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Linker extra options
|
||||||
|
ifneq ($(USE_LDOPT),)
|
||||||
|
LDOPT := $(LDOPT),$(USE_LDOPT)
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Link time optimizations
|
||||||
|
ifeq ($(USE_LTO),yes)
|
||||||
|
OPT += -flto
|
||||||
|
endif
|
||||||
|
|
||||||
|
# FPU-related options
|
||||||
|
ifeq ($(USE_FPU),)
|
||||||
|
USE_FPU = no
|
||||||
|
endif
|
||||||
|
ifneq ($(USE_FPU),no)
|
||||||
|
OPT += -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -fsingle-precision-constant
|
||||||
|
DDEFS += -DCORTEX_USE_FPU=TRUE
|
||||||
|
DADEFS += -DCORTEX_USE_FPU=TRUE
|
||||||
|
else
|
||||||
|
DDEFS += -DCORTEX_USE_FPU=FALSE
|
||||||
|
DADEFS += -DCORTEX_USE_FPU=FALSE
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Process stack size
|
||||||
|
ifeq ($(USE_PROCESS_STACKSIZE),)
|
||||||
|
LDOPT := $(LDOPT),--defsym=__process_stack_size__=0x400
|
||||||
|
else
|
||||||
|
LDOPT := $(LDOPT),--defsym=__process_stack_size__=$(USE_PROCESS_STACKSIZE)
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Exceptions stack size
|
||||||
|
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
|
||||||
|
LDOPT := $(LDOPT),--defsym=__main_stack_size__=0x400
|
||||||
|
else
|
||||||
|
LDOPT := $(LDOPT),--defsym=__main_stack_size__=$(USE_EXCEPTIONS_STACKSIZE)
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Output directory and files
|
||||||
|
ifeq ($(BUILDDIR),)
|
||||||
|
BUILDDIR = build
|
||||||
|
endif
|
||||||
|
ifeq ($(BUILDDIR),.)
|
||||||
|
BUILDDIR = build
|
||||||
|
endif
|
||||||
|
OUTFILES := $(BUILDDIR)/$(PROJECT).elf \
|
||||||
|
$(BUILDDIR)/$(PROJECT).hex \
|
||||||
|
$(BUILDDIR)/$(PROJECT).bin \
|
||||||
|
$(BUILDDIR)/$(PROJECT).dmp \
|
||||||
|
$(BUILDDIR)/$(PROJECT).list
|
||||||
|
|
||||||
|
ifdef SREC
|
||||||
|
OUTFILES += $(BUILDDIR)/$(PROJECT).srec
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Source files groups and paths
|
||||||
|
ifeq ($(USE_THUMB),yes)
|
||||||
|
TCSRC += $(CSRC)
|
||||||
|
TCPPSRC += $(CPPSRC)
|
||||||
|
else
|
||||||
|
ACSRC += $(CSRC)
|
||||||
|
ACPPSRC += $(CPPSRC)
|
||||||
|
endif
|
||||||
|
ASRC := $(ACSRC) $(ACPPSRC)
|
||||||
|
TSRC := $(TCSRC) $(TCPPSRC)
|
||||||
|
SRCPATHS := $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)))
|
||||||
|
|
||||||
|
# Various directories
|
||||||
|
OBJDIR := $(BUILDDIR)/obj
|
||||||
|
LSTDIR := $(BUILDDIR)/lst
|
||||||
|
|
||||||
|
# Object files groups
|
||||||
|
ACOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o)))
|
||||||
|
ACPPOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o)))
|
||||||
|
TCOBJS := $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o)))
|
||||||
|
TCPPOBJS := $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o)))
|
||||||
|
ASMOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
|
||||||
|
ASMXOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
|
||||||
|
OBJS := $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
|
||||||
|
|
||||||
|
# Paths
|
||||||
|
IINCDIR := $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
|
||||||
|
LLIBDIR := $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
|
||||||
|
|
||||||
|
# Macros
|
||||||
|
DEFS := $(DDEFS) $(UDEFS)
|
||||||
|
ADEFS := $(DADEFS) $(UADEFS)
|
||||||
|
|
||||||
|
# Libs
|
||||||
|
LIBS := $(DLIBS) $(ULIBS)
|
||||||
|
|
||||||
|
# Various settings
|
||||||
|
MCFLAGS := -mcpu=$(MCU)
|
||||||
|
ODFLAGS = -x --syms
|
||||||
|
ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
|
||||||
|
ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
|
||||||
|
CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
|
||||||
|
CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
|
||||||
|
LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),--script=$(LDSCRIPT)$(LDOPT)
|
||||||
|
|
||||||
|
# Thumb interwork enabled only if needed because it kills performance.
|
||||||
|
ifneq ($(strip $(TSRC)),)
|
||||||
|
CFLAGS += -DTHUMB_PRESENT
|
||||||
|
CPPFLAGS += -DTHUMB_PRESENT
|
||||||
|
ASFLAGS += -DTHUMB_PRESENT
|
||||||
|
ASXFLAGS += -DTHUMB_PRESENT
|
||||||
|
ifneq ($(strip $(ASRC)),)
|
||||||
|
# Mixed ARM and THUMB mode.
|
||||||
|
CFLAGS += -mthumb-interwork
|
||||||
|
CPPFLAGS += -mthumb-interwork
|
||||||
|
ASFLAGS += -mthumb-interwork
|
||||||
|
ASXFLAGS += -mthumb-interwork
|
||||||
|
LDFLAGS += -mthumb-interwork
|
||||||
|
else
|
||||||
|
# Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly.
|
||||||
|
CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
|
||||||
|
CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
|
||||||
|
ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb
|
||||||
|
ASXFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb
|
||||||
|
LDFLAGS += -mno-thumb-interwork -mthumb
|
||||||
|
endif
|
||||||
|
else
|
||||||
|
# Pure ARM mode
|
||||||
|
CFLAGS += -mno-thumb-interwork
|
||||||
|
CPPFLAGS += -mno-thumb-interwork
|
||||||
|
ASFLAGS += -mno-thumb-interwork
|
||||||
|
ASXFLAGS += -mno-thumb-interwork
|
||||||
|
LDFLAGS += -mno-thumb-interwork
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Generate dependency information
|
||||||
|
ASFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||||
|
ASXFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||||
|
CFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||||
|
CPPFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||||
|
|
||||||
|
# Paths where to search for sources
|
||||||
|
VPATH = $(SRCPATHS)
|
||||||
|
|
||||||
|
#
|
||||||
|
# Makefile rules
|
||||||
|
#
|
||||||
|
|
||||||
|
all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK
|
||||||
|
|
||||||
|
PRE_MAKE_ALL_RULE_HOOK:
|
||||||
|
|
||||||
|
POST_MAKE_ALL_RULE_HOOK:
|
||||||
|
|
||||||
|
$(OBJS): | $(BUILDDIR) $(OBJDIR) $(LSTDIR)
|
||||||
|
|
||||||
|
$(BUILDDIR):
|
||||||
|
ifneq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
@echo Compiler Options
|
||||||
|
@echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
|
||||||
|
@echo
|
||||||
|
endif
|
||||||
|
@mkdir -p $(BUILDDIR)
|
||||||
|
|
||||||
|
$(OBJDIR):
|
||||||
|
@mkdir -p $(OBJDIR)
|
||||||
|
|
||||||
|
$(LSTDIR):
|
||||||
|
@mkdir -p $(LSTDIR)
|
||||||
|
|
||||||
|
$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
@echo
|
||||||
|
$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
else
|
||||||
|
@echo Compiling $(<F)
|
||||||
|
@$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
@echo
|
||||||
|
$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
else
|
||||||
|
@echo Compiling $(<F)
|
||||||
|
@$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(ACOBJS) : $(OBJDIR)/%.o : %.c Makefile
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
@echo
|
||||||
|
$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
else
|
||||||
|
@echo Compiling $(<F)
|
||||||
|
@$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(TCOBJS) : $(OBJDIR)/%.o : %.c Makefile
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
@echo
|
||||||
|
$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
else
|
||||||
|
@echo Compiling $(<F)
|
||||||
|
@$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
@echo
|
||||||
|
$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
|
||||||
|
else
|
||||||
|
@echo Compiling $(<F)
|
||||||
|
@$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(ASMXOBJS) : $(OBJDIR)/%.o : %.S Makefile
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
@echo
|
||||||
|
$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
else
|
||||||
|
@echo Compiling $(<F)
|
||||||
|
@$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(BUILDDIR)/$(PROJECT).elf: $(OBJS) $(LDSCRIPT)
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
@echo
|
||||||
|
$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
|
||||||
|
else
|
||||||
|
@echo Linking $@
|
||||||
|
@$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
%.hex: %.elf
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
$(HEX) $< $@
|
||||||
|
else
|
||||||
|
@echo Creating $@
|
||||||
|
@$(HEX) $< $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
%.bin: %.elf
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
$(BIN) $< $@
|
||||||
|
else
|
||||||
|
@echo Creating $@
|
||||||
|
@$(BIN) $< $@
|
||||||
|
endif
|
||||||
|
|
||||||
|
%.srec: %.elf
|
||||||
|
ifdef SREC
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
$(SREC) $< $@
|
||||||
|
else
|
||||||
|
@echo Creating $@
|
||||||
|
@$(SREC) $< $@
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
|
||||||
|
%.dmp: %.elf
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
$(OD) $(ODFLAGS) $< > $@
|
||||||
|
$(SZ) $<
|
||||||
|
else
|
||||||
|
@echo Creating $@
|
||||||
|
@$(OD) $(ODFLAGS) $< > $@
|
||||||
|
@echo
|
||||||
|
@$(SZ) $<
|
||||||
|
endif
|
||||||
|
|
||||||
|
%.list: %.elf
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),yes)
|
||||||
|
$(OD) -S $< > $@
|
||||||
|
else
|
||||||
|
@echo Creating $@
|
||||||
|
@$(OD) -S $< > $@
|
||||||
|
@echo
|
||||||
|
@echo Done
|
||||||
|
endif
|
||||||
|
|
||||||
|
lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a
|
||||||
|
|
||||||
|
$(BUILDDIR)/lib$(PROJECT).a: $(OBJS)
|
||||||
|
@$(AR) -r $@ $^
|
||||||
|
@echo
|
||||||
|
@echo Done
|
||||||
|
|
||||||
|
clean:
|
||||||
|
@echo Cleaning
|
||||||
|
-rm -fR .dep $(BUILDDIR)
|
||||||
|
@echo
|
||||||
|
@echo Done
|
||||||
|
|
||||||
|
#
|
||||||
|
# Include the dependency files, should be the last of the makefile
|
||||||
|
#
|
||||||
|
-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
|
||||||
|
|
||||||
|
# *** EOF ***
|
||||||
|
|
@ -0,0 +1,629 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file ARMCMx/compilers/GCC/vectors.c
|
||||||
|
* @brief Interrupt vectors for Cortex-Mx devices.
|
||||||
|
*
|
||||||
|
* @defgroup ARMCMx_VECTORS Cortex-Mx Interrupt Vectors
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdbool.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include "vectors.h"
|
||||||
|
|
||||||
|
#if (CORTEX_NUM_VECTORS % 8) != 0
|
||||||
|
#error "the constant CORTEX_NUM_VECTORS must be a multiple of 8"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CORTEX_NUM_VECTORS < 8) || (CORTEX_NUM_VECTORS > 240)
|
||||||
|
#error "the constant CORTEX_NUM_VECTORS must be between 8 and 240 inclusive"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Unhandled exceptions handler.
|
||||||
|
* @details Any undefined exception vector points to this function by default.
|
||||||
|
* This function simply stops the system into an infinite loop.
|
||||||
|
*
|
||||||
|
* @notapi
|
||||||
|
*/
|
||||||
|
/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
|
||||||
|
void _unhandled_exception(void) {
|
||||||
|
/*lint -restore*/
|
||||||
|
|
||||||
|
while (true) {
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
extern uint32_t __main_stack_end__;
|
||||||
|
void Reset_Handler(void);
|
||||||
|
void NMI_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void HardFault_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void MemManage_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void BusFault_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void UsageFault_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void SVC_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void DebugMon_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void PendSV_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void SysTick_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#if CORTEX_NUM_VECTORS > 4
|
||||||
|
void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 8
|
||||||
|
void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 12
|
||||||
|
void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 16
|
||||||
|
void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 20
|
||||||
|
void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 24
|
||||||
|
void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 28
|
||||||
|
void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 32
|
||||||
|
void VectorC0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorC4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorC8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorCC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 36
|
||||||
|
void VectorD0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorD4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorD8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorDC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 40
|
||||||
|
void VectorE0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorE4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorE8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorEC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 44
|
||||||
|
void VectorF0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorF4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorF8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void VectorFC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 48
|
||||||
|
void Vector100(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector104(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector108(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector10C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 52
|
||||||
|
void Vector110(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector114(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector118(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector11C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 56
|
||||||
|
void Vector120(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector124(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector128(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector12C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 60
|
||||||
|
void Vector130(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector134(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector138(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector13C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 64
|
||||||
|
void Vector140(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector144(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector148(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector14C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 68
|
||||||
|
void Vector150(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector154(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector158(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector15C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 72
|
||||||
|
void Vector160(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector164(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector168(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector16C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 76
|
||||||
|
void Vector170(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector174(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector178(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector17C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 80
|
||||||
|
void Vector180(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector184(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector188(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector18C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 84
|
||||||
|
void Vector190(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector194(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector198(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector19C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 88
|
||||||
|
void Vector1A0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1A4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1A8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1AC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 92
|
||||||
|
void Vector1B0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1B4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1B8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1BC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 96
|
||||||
|
void Vector1C0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1C4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1C8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1CC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 100
|
||||||
|
void Vector1D0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1D4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1D8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1DC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 104
|
||||||
|
void Vector1E0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1E4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1E8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1EC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 108
|
||||||
|
void Vector1F0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1F4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1F8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector1FC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 112
|
||||||
|
void Vector200(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector204(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector208(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector20C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 116
|
||||||
|
void Vector210(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector214(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector218(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector21C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 120
|
||||||
|
void Vector220(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector224(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector228(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector22C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 124
|
||||||
|
void Vector230(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector234(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector238(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector23C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 128
|
||||||
|
void Vector240(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector244(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector248(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector24C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 132
|
||||||
|
void Vector250(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector254(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector258(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector25C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 136
|
||||||
|
void Vector260(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector264(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector268(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector26C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 140
|
||||||
|
void Vector270(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector274(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector278(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector27C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 144
|
||||||
|
void Vector280(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector284(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector288(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector28C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 148
|
||||||
|
void Vector290(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector294(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector298(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector29C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 152
|
||||||
|
void Vector2A0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2A4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2A8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2AC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 156
|
||||||
|
void Vector2B0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2B4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2B8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2BC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 160
|
||||||
|
void Vector2C0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2C4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2C8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2CC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 164
|
||||||
|
void Vector2D0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2D4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2D8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2DC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 168
|
||||||
|
void Vector2E0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2E4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2E8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2EC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 172
|
||||||
|
void Vector2F0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2F4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2F8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector2FC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 176
|
||||||
|
void Vector300(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector304(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector308(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector30C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 180
|
||||||
|
void Vector310(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector314(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector318(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector31C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 184
|
||||||
|
void Vector320(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector324(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector328(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector32C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 188
|
||||||
|
void Vector330(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector334(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector338(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector33C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 192
|
||||||
|
void Vector340(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector344(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector348(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector34C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 196
|
||||||
|
void Vector350(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector354(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector358(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector35C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 200
|
||||||
|
void Vector360(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector364(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector368(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector36C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 204
|
||||||
|
void Vector370(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector374(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector378(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector37C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 208
|
||||||
|
void Vector380(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector384(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector388(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector38C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 212
|
||||||
|
void Vector390(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector394(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector398(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector39C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 216
|
||||||
|
void Vector3A0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3A4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3A8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3AC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 220
|
||||||
|
void Vector3B0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3B4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3B8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3BC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 224
|
||||||
|
void Vector3C0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3C4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3C8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3CC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 228
|
||||||
|
void Vector3D0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3D4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3D8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3DC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 232
|
||||||
|
void Vector3E0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3E4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3E8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3EC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 236
|
||||||
|
void Vector3F0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3F4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3F8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
void Vector3FC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||||
|
#endif
|
||||||
|
#endif /* !defined(__DOXYGEN__) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STM32 vectors table.
|
||||||
|
*/
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
#if !defined(VECTORS_SECTION)
|
||||||
|
__attribute__ ((used, aligned(128), section(".vectors")))
|
||||||
|
#else
|
||||||
|
__attribute__ ((used, aligned(128), section(VECTORS_SECTION)))
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
|
||||||
|
vectors_t _vectors = {
|
||||||
|
/*lint -restore*/
|
||||||
|
&__main_stack_end__,Reset_Handler, NMI_Handler, HardFault_Handler,
|
||||||
|
MemManage_Handler, BusFault_Handler, UsageFault_Handler, Vector1C,
|
||||||
|
Vector20, Vector24, Vector28, SVC_Handler,
|
||||||
|
DebugMon_Handler, Vector34, PendSV_Handler, SysTick_Handler,
|
||||||
|
{
|
||||||
|
Vector40, Vector44, Vector48, Vector4C,
|
||||||
|
#if CORTEX_NUM_VECTORS > 4
|
||||||
|
Vector50, Vector54, Vector58, Vector5C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 8
|
||||||
|
Vector60, Vector64, Vector68, Vector6C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 12
|
||||||
|
Vector70, Vector74, Vector78, Vector7C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 16
|
||||||
|
Vector80, Vector84, Vector88, Vector8C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 20
|
||||||
|
Vector90, Vector94, Vector98, Vector9C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 24
|
||||||
|
VectorA0, VectorA4, VectorA8, VectorAC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 28
|
||||||
|
VectorB0, VectorB4, VectorB8, VectorBC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 32
|
||||||
|
VectorC0, VectorC4, VectorC8, VectorCC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 36
|
||||||
|
VectorD0, VectorD4, VectorD8, VectorDC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 40
|
||||||
|
VectorE0, VectorE4, VectorE8, VectorEC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 44
|
||||||
|
VectorF0, VectorF4, VectorF8, VectorFC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 48
|
||||||
|
Vector100, Vector104, Vector108, Vector10C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 52
|
||||||
|
Vector110, Vector114, Vector118, Vector11C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 56
|
||||||
|
Vector120, Vector124, Vector128, Vector12C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 60
|
||||||
|
Vector130, Vector134, Vector138, Vector13C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 64
|
||||||
|
Vector140, Vector144, Vector148, Vector14C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 68
|
||||||
|
Vector150, Vector154, Vector158, Vector15C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 72
|
||||||
|
Vector160, Vector164, Vector168, Vector16C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 76
|
||||||
|
Vector170, Vector174, Vector178, Vector17C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 80
|
||||||
|
Vector180, Vector184, Vector188, Vector18C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 84
|
||||||
|
Vector190, Vector194, Vector198, Vector19C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 88
|
||||||
|
Vector1A0, Vector1A4, Vector1A8, Vector1AC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 92
|
||||||
|
Vector1B0, Vector1B4, Vector1B8, Vector1BC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 96
|
||||||
|
Vector1C0, Vector1C4, Vector1C8, Vector1CC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 100
|
||||||
|
Vector1D0, Vector1D4, Vector1D8, Vector1DC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 104
|
||||||
|
Vector1E0, Vector1E4, Vector1E8, Vector1EC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 108
|
||||||
|
Vector1F0, Vector1F4, Vector1F8, Vector1FC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 112
|
||||||
|
Vector200, Vector204, Vector208, Vector20C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 116
|
||||||
|
Vector210, Vector214, Vector218, Vector21C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 120
|
||||||
|
Vector220, Vector224, Vector228, Vector22C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 124
|
||||||
|
Vector230, Vector234, Vector238, Vector23C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 128
|
||||||
|
Vector240, Vector244, Vector248, Vector24C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 132
|
||||||
|
Vector250, Vector254, Vector258, Vector25C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 136
|
||||||
|
Vector260, Vector264, Vector268, Vector26C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 140
|
||||||
|
Vector270, Vector274, Vector278, Vector27C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 144
|
||||||
|
Vector280, Vector284, Vector288, Vector28C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 148
|
||||||
|
Vector290, Vector294, Vector298, Vector29C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 152
|
||||||
|
Vector2A0, Vector2A4, Vector2A8, Vector2AC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 156
|
||||||
|
Vector2B0, Vector2B4, Vector2B8, Vector2BC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 160
|
||||||
|
Vector2C0, Vector2C4, Vector2C8, Vector2CC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 164
|
||||||
|
Vector2D0, Vector2D4, Vector2D8, Vector2DC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 168
|
||||||
|
Vector2E0, Vector2E4, Vector2E8, Vector2EC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 172
|
||||||
|
Vector2F0, Vector2F4, Vector2F8, Vector2FC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 176
|
||||||
|
Vector300, Vector304, Vector308, Vector30C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 180
|
||||||
|
Vector310, Vector314, Vector318, Vector31C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 184
|
||||||
|
Vector320, Vector324, Vector328, Vector32C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 188
|
||||||
|
Vector330, Vector334, Vector338, Vector33C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 192
|
||||||
|
Vector340, Vector344, Vector348, Vector34C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 196
|
||||||
|
Vector350, Vector354, Vector358, Vector35C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 200
|
||||||
|
Vector360, Vector364, Vector368, Vector36C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 204
|
||||||
|
Vector370, Vector374, Vector378, Vector37C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 208
|
||||||
|
Vector380, Vector384, Vector388, Vector38C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 212
|
||||||
|
Vector390, Vector394, Vector398, Vector39C,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 216
|
||||||
|
Vector3A0, Vector3A4, Vector3A8, Vector3AC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 220
|
||||||
|
Vector3B0, Vector3B4, Vector3B8, Vector3BC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 224
|
||||||
|
Vector3C0, Vector3C4, Vector3C8, Vector3CC,
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 228
|
||||||
|
Vector3D0, Vector3D4, Vector3D8, Vector3DC
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 232
|
||||||
|
Vector3E0, Vector3E4, Vector3E8, Vector3EC
|
||||||
|
#endif
|
||||||
|
#if CORTEX_NUM_VECTORS > 236
|
||||||
|
Vector3F0, Vector3F4, Vector3F8, Vector3FC
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,112 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file ARMCMx/compilers/GCC/vectors.h
|
||||||
|
* @brief Interrupt vectors for Cortex-Mx devices.
|
||||||
|
*
|
||||||
|
* @defgroup ARMCMx_VECTORS Cortex-Mx Interrupt Vectors
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _VECTORS_H_
|
||||||
|
#define _VECTORS_H_
|
||||||
|
|
||||||
|
#include "cmparams.h"
|
||||||
|
|
||||||
|
/* This inclusion can be used to remap vectors using different names.
|
||||||
|
* Example:
|
||||||
|
* #define Vector7C UartRX_Handler
|
||||||
|
* This can be useful when using 3rd part libraries that assume specific
|
||||||
|
* vector names.
|
||||||
|
*/
|
||||||
|
#if defined(VECTORS_USE_CONF)
|
||||||
|
#include "vectorsconf.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module constants. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module pre-compile time settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Derived constants and error checks. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module data structures and types. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if !defined(_FROM_ASM_)
|
||||||
|
/**
|
||||||
|
* @brief Type of an IRQ vector.
|
||||||
|
*/
|
||||||
|
typedef void (*irq_vector_t)(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Type of a structure representing the whole vectors table.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
uint32_t *init_stack;
|
||||||
|
irq_vector_t reset_handler;
|
||||||
|
irq_vector_t nmi_handler;
|
||||||
|
irq_vector_t hardfault_handler;
|
||||||
|
irq_vector_t memmanage_handler;
|
||||||
|
irq_vector_t busfault_handler;
|
||||||
|
irq_vector_t usagefault_handler;
|
||||||
|
irq_vector_t vector1c;
|
||||||
|
irq_vector_t vector20;
|
||||||
|
irq_vector_t vector24;
|
||||||
|
irq_vector_t vector28;
|
||||||
|
irq_vector_t svc_handler;
|
||||||
|
irq_vector_t debugmonitor_handler;
|
||||||
|
irq_vector_t vector34;
|
||||||
|
irq_vector_t pendsv_handler;
|
||||||
|
irq_vector_t systick_handler;
|
||||||
|
irq_vector_t vectors[CORTEX_NUM_VECTORS];
|
||||||
|
} vectors_t;
|
||||||
|
#endif /* !defined(_FROM_ASM_) */
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module macros. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* External declarations. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if !defined(_FROM_ASM_)
|
||||||
|
extern vectors_t _vectors;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module inline functions. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#endif /* _VECTORS_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,79 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file ARMCMx/IAR/cstartup.s
|
||||||
|
* @brief Generic IAR Cortex-Mx startup file.
|
||||||
|
*
|
||||||
|
* @addtogroup ARMCMx_IAR_STARTUP
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
|
||||||
|
MODULE ?cstartup
|
||||||
|
|
||||||
|
CONTROL_MODE_PRIVILEGED SET 0
|
||||||
|
CONTROL_MODE_UNPRIVILEGED SET 1
|
||||||
|
CONTROL_USE_MSP SET 0
|
||||||
|
CONTROL_USE_PSP SET 2
|
||||||
|
|
||||||
|
AAPCS INTERWORK, VFP_COMPATIBLE, ROPI
|
||||||
|
PRESERVE8
|
||||||
|
|
||||||
|
SECTION .intvec:CODE:NOROOT(3)
|
||||||
|
|
||||||
|
SECTION CSTACK:DATA:NOROOT(3)
|
||||||
|
PUBLIC __main_thread_stack_base__
|
||||||
|
__main_thread_stack_base__:
|
||||||
|
PUBLIC __heap_end__
|
||||||
|
__heap_end__:
|
||||||
|
|
||||||
|
SECTION SYSHEAP:DATA:NOROOT(3)
|
||||||
|
PUBLIC __heap_base__
|
||||||
|
__heap_base__:
|
||||||
|
|
||||||
|
PUBLIC __iar_program_start
|
||||||
|
EXTERN __vector_table
|
||||||
|
EXTWEAK __iar_init_core
|
||||||
|
EXTWEAK __iar_init_vfp
|
||||||
|
EXTERN __cmain
|
||||||
|
|
||||||
|
SECTION .text:CODE:REORDER(2)
|
||||||
|
REQUIRE __vector_table
|
||||||
|
THUMB
|
||||||
|
__iar_program_start:
|
||||||
|
cpsid i
|
||||||
|
ldr r0, =SFE(CSTACK)
|
||||||
|
msr PSP, r0
|
||||||
|
movs r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP
|
||||||
|
msr CONTROL, r0
|
||||||
|
isb
|
||||||
|
bl __early_init
|
||||||
|
bl __iar_init_core
|
||||||
|
bl __iar_init_vfp
|
||||||
|
b __cmain
|
||||||
|
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||||
|
PUBWEAK __early_init
|
||||||
|
__early_init:
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
#endif /* !defined(__DOXYGEN__) */
|
||||||
|
|
||||||
|
/**< @} */
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,131 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file ARMCMx/RVCT/cstartup.s
|
||||||
|
* @brief Generic RVCT Cortex-Mx startup file.
|
||||||
|
*
|
||||||
|
* @addtogroup ARMCMx_RVCT_STARTUP
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
|
||||||
|
;/* <<< Use Configuration Wizard in Context Menu >>> */
|
||||||
|
|
||||||
|
;// <h> Main Stack Configuration (IRQ Stack)
|
||||||
|
;// <o> Main Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
;// </h>
|
||||||
|
main_stack_size EQU 0x00000400
|
||||||
|
|
||||||
|
;// <h> Process Stack Configuration
|
||||||
|
;// <o> Process Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
;// </h>
|
||||||
|
proc_stack_size EQU 0x00000400
|
||||||
|
|
||||||
|
;// <h> C-runtime heap size
|
||||||
|
;// <o> C-runtime heap size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
;// </h>
|
||||||
|
heap_size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA MSTACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
main_stack_mem SPACE main_stack_size
|
||||||
|
EXPORT __initial_msp
|
||||||
|
__initial_msp
|
||||||
|
|
||||||
|
AREA CSTACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__main_thread_stack_base__
|
||||||
|
EXPORT __main_thread_stack_base__
|
||||||
|
proc_stack_mem SPACE proc_stack_size
|
||||||
|
EXPORT __initial_sp
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE heap_size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
CONTROL_MODE_PRIVILEGED EQU 0
|
||||||
|
CONTROL_MODE_UNPRIVILEGED EQU 1
|
||||||
|
CONTROL_USE_MSP EQU 0
|
||||||
|
CONTROL_USE_PSP EQU 2
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Reset handler.
|
||||||
|
*/
|
||||||
|
IMPORT __main
|
||||||
|
EXPORT Reset_Handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
cpsid i
|
||||||
|
ldr r0, =__initial_sp
|
||||||
|
msr PSP, r0
|
||||||
|
movs r0, #CONTROL_MODE_PRIVILEGED :OR: CONTROL_USE_PSP
|
||||||
|
msr CONTROL, r0
|
||||||
|
isb
|
||||||
|
bl __early_init
|
||||||
|
|
||||||
|
IF {CPU} = "Cortex-M4.fp"
|
||||||
|
LDR R0, =0xE000ED88 ; Enable CP10,CP11
|
||||||
|
LDR R1, [R0]
|
||||||
|
ORR R1, R1, #(0xF << 20)
|
||||||
|
STR R1, [R0]
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
ldr r0, =__main
|
||||||
|
bx r0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
__early_init PROC
|
||||||
|
EXPORT __early_init [WEAK]
|
||||||
|
bx lr
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
/*
|
||||||
|
* User Initial Stack & Heap.
|
||||||
|
*/
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
__user_initial_stackheap
|
||||||
|
ldr r0, =Heap_Mem
|
||||||
|
ldr r1, =(proc_stack_mem + proc_stack_size)
|
||||||
|
ldr r2, =(Heap_Mem + heap_size)
|
||||||
|
ldr r3, =proc_stack_mem
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
#endif /* !defined(__DOXYGEN__) */
|
||||||
|
|
||||||
|
/**< @} */
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,79 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file GCC/ARMCMx/MK20Dx/cmparams.h
|
||||||
|
* @brief ARM Cortex-M4 parameters for the Kinetis MK20Dx.
|
||||||
|
*
|
||||||
|
* @defgroup ARMCMx_MK20Dx Kinetis MK20Dx Specific Parameters
|
||||||
|
* @ingroup ARMCMx_SPECIFIC
|
||||||
|
* @details This file contains the Cortex-M4 specific parameters for the
|
||||||
|
* Kinetis MK20Dx platform.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _CMPARAMS_H_
|
||||||
|
#define _CMPARAMS_H_
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Cortex core model.
|
||||||
|
*/
|
||||||
|
#define CORTEX_MODEL 4
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Systick unit presence.
|
||||||
|
*/
|
||||||
|
#define CORTEX_HAS_ST TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Floating Point unit presence.
|
||||||
|
*/
|
||||||
|
#define CORTEX_HAS_FPU FALSE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of bits in priority masks.
|
||||||
|
*/
|
||||||
|
#define CORTEX_PRIORITY_BITS 4
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of interrupt vectors.
|
||||||
|
* @note This number does not include the 16 system vectors and must be
|
||||||
|
* rounded to a multiple of 8.
|
||||||
|
*/
|
||||||
|
#define CORTEX_NUM_VECTORS 48
|
||||||
|
|
||||||
|
/* The following code is not processed when the file is included from an
|
||||||
|
asm module.*/
|
||||||
|
#if !defined(_FROM_ASM_)
|
||||||
|
|
||||||
|
/* Including the device CMSIS header. Note, we are not using the definitions
|
||||||
|
from this header because we need this file to be usable also from
|
||||||
|
assembler source files. We verify that the info matches instead.*/
|
||||||
|
#include "mk20d5.h"
|
||||||
|
|
||||||
|
#if CORTEX_MODEL != __CORTEX_M
|
||||||
|
#error "CMSIS __CORTEX_M mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
|
||||||
|
#error "CMSIS __NVIC_PRIO_BITS mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* !defined(_FROM_ASM_) */
|
||||||
|
|
||||||
|
#endif /* _CMPARAMS_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,79 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file KL2x/cmparams.h
|
||||||
|
* @brief ARM Cortex-M0+ parameters for the Kinetis KL2x family.
|
||||||
|
*
|
||||||
|
* @defgroup ARMCMx_KL2x Kinetis KL2x Specific Parameters
|
||||||
|
* @ingroup ARMCMx_SPECIFIC
|
||||||
|
* @details This file contains the Cortex-M0+ specific parameters for the
|
||||||
|
* Kinetis KL2x platform.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _CMPARAMS_H_
|
||||||
|
#define _CMPARAMS_H_
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Cortex core model.
|
||||||
|
*/
|
||||||
|
#define CORTEX_MODEL 0
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Systick unit presence.
|
||||||
|
*/
|
||||||
|
#define CORTEX_HAS_ST TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Floating Point unit presence.
|
||||||
|
*/
|
||||||
|
#define CORTEX_HAS_FPU FALSE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of bits in priority masks.
|
||||||
|
*/
|
||||||
|
#define CORTEX_PRIORITY_BITS 2
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of interrupt vectors.
|
||||||
|
* @note This number does not include the 16 system vectors and must be
|
||||||
|
* rounded to a multiple of 8.
|
||||||
|
*/
|
||||||
|
#define CORTEX_NUM_VECTORS 32
|
||||||
|
|
||||||
|
/* The following code is not processed when the file is included from an
|
||||||
|
asm module.*/
|
||||||
|
#if !defined(_FROM_ASM_)
|
||||||
|
|
||||||
|
/* Including the device CMSIS header. Note, we are not using the definitions
|
||||||
|
from this header because we need this file to be usable also from
|
||||||
|
assembler source files. We verify that the info matches instead.*/
|
||||||
|
#include "kl25z.h"
|
||||||
|
|
||||||
|
#if CORTEX_MODEL != __CORTEX_M
|
||||||
|
#error "CMSIS __CORTEX_M mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
|
||||||
|
#error "CMSIS __NVIC_PRIO_BITS mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* !defined(_FROM_ASM_) */
|
||||||
|
|
||||||
|
#endif /* _CMPARAMS_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,86 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file STM32F0xx/cmparams.h
|
||||||
|
* @brief ARM Cortex-M0 parameters for the STM32F0xx.
|
||||||
|
*
|
||||||
|
* @defgroup ARMCMx_STM32F0xx STM32F0xx Specific Parameters
|
||||||
|
* @ingroup ARMCMx_SPECIFIC
|
||||||
|
* @details This file contains the Cortex-M0 specific parameters for the
|
||||||
|
* STM32F0xx platform.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _CMPARAMS_H_
|
||||||
|
#define _CMPARAMS_H_
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Cortex core model.
|
||||||
|
*/
|
||||||
|
#define CORTEX_MODEL 0
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Floating Point unit presence.
|
||||||
|
*/
|
||||||
|
#define CORTEX_HAS_FPU 0
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of bits in priority masks.
|
||||||
|
*/
|
||||||
|
#define CORTEX_PRIORITY_BITS 2
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of interrupt vectors.
|
||||||
|
* @note This number does not include the 16 system vectors and must be
|
||||||
|
* rounded to a multiple of 8.
|
||||||
|
*/
|
||||||
|
#define CORTEX_NUM_VECTORS 32
|
||||||
|
|
||||||
|
/* The following code is not processed when the file is included from an
|
||||||
|
asm module.*/
|
||||||
|
#if !defined(_FROM_ASM_)
|
||||||
|
|
||||||
|
/* If the device type is not externally defined, for example from the Makefile,
|
||||||
|
then a file named board.h is included. This file must contain a device
|
||||||
|
definition compatible with the vendor include file.*/
|
||||||
|
#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
|
||||||
|
!defined (STM32F031x6) && !defined (STM32F038xx) && \
|
||||||
|
!defined (STM32F042x6) && !defined (STM32F048xx) && \
|
||||||
|
!defined (STM32F051x8) && !defined (STM32F058xx) && \
|
||||||
|
!defined (STM32F071xB) && !defined (STM32F072xB) && \
|
||||||
|
!defined (STM32F078xx)
|
||||||
|
#include "board.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Including the device CMSIS header. Note, we are not using the definitions
|
||||||
|
from this header because we need this file to be usable also from
|
||||||
|
assembler source files. We verify that the info matches instead.*/
|
||||||
|
#include "stm32f0xx.h"
|
||||||
|
|
||||||
|
#if CORTEX_MODEL != __CORTEX_M
|
||||||
|
#error "CMSIS __CORTEX_M mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
|
||||||
|
#error "CMSIS __NVIC_PRIO_BITS mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* !defined(_FROM_ASM_) */
|
||||||
|
|
||||||
|
#endif /* _CMPARAMS_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,87 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file STM32F1xx/cmparams.h
|
||||||
|
* @brief ARM Cortex-M3 parameters for the STM32F1xx.
|
||||||
|
*
|
||||||
|
* @defgroup ARMCMx_STM32F1xx STM32F1xx Specific Parameters
|
||||||
|
* @ingroup ARMCMx_SPECIFIC
|
||||||
|
* @details This file contains the Cortex-M4 specific parameters for the
|
||||||
|
* STM32F1xx platform.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _CMPARAMS_H_
|
||||||
|
#define _CMPARAMS_H_
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Cortex core model.
|
||||||
|
*/
|
||||||
|
#define CORTEX_MODEL 3
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Floating Point unit presence.
|
||||||
|
*/
|
||||||
|
#define CORTEX_HAS_FPU 0
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of bits in priority masks.
|
||||||
|
*/
|
||||||
|
#define CORTEX_PRIORITY_BITS 4
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of interrupt vectors.
|
||||||
|
* @note This number does not include the 16 system vectors and must be
|
||||||
|
* rounded to a multiple of 8.
|
||||||
|
*/
|
||||||
|
#define CORTEX_NUM_VECTORS 72
|
||||||
|
|
||||||
|
/* The following code is not processed when the file is included from an
|
||||||
|
asm module.*/
|
||||||
|
#if !defined(_FROM_ASM_)
|
||||||
|
|
||||||
|
/* If the device type is not externally defined, for example from the Makefile,
|
||||||
|
then a file named board.h is included. This file must contain a device
|
||||||
|
definition compatible with the vendor include file.*/
|
||||||
|
#if !defined(STM32F100xB) && !defined(STM32F100xE) && \
|
||||||
|
!defined(STM32F101x6) && !defined(STM32F101xB) && \
|
||||||
|
!defined(STM32F101xE) && !defined(STM32F101xG) && \
|
||||||
|
!defined(STM32F102x6) && !defined(STM32F102xB) && \
|
||||||
|
!defined(STM32F103x6) && !defined(STM32F103xB) && \
|
||||||
|
!defined(STM32F103xE) && !defined(STM32F103xG) && \
|
||||||
|
!defined(STM32F105xC) && !defined(STM32F107xC)
|
||||||
|
#include "board.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Including the device CMSIS header. Note, we are not using the definitions
|
||||||
|
from this header because we need this file to be usable also from
|
||||||
|
assembler source files. We verify that the info matches instead.*/
|
||||||
|
#include "stm32f1xx.h"
|
||||||
|
|
||||||
|
#if CORTEX_MODEL != __CORTEX_M
|
||||||
|
#error "CMSIS __CORTEX_M mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
|
||||||
|
#error "CMSIS __NVIC_PRIO_BITS mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* !defined(_FROM_ASM_) */
|
||||||
|
|
||||||
|
#endif /* _CMPARAMS_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,81 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file STM32F2xx/cmparams.h
|
||||||
|
* @brief ARM Cortex-M3 parameters for the STM32F2xx.
|
||||||
|
*
|
||||||
|
* @defgroup ARMCMx_STM32F2xx STM32F2xx Specific Parameters
|
||||||
|
* @ingroup ARMCMx_SPECIFIC
|
||||||
|
* @details This file contains the Cortex-M3 specific parameters for the
|
||||||
|
* STM32F2xx platform.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _CMPARAMS_H_
|
||||||
|
#define _CMPARAMS_H_
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Cortex core model.
|
||||||
|
*/
|
||||||
|
#define CORTEX_MODEL 3
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Floating Point unit presence.
|
||||||
|
*/
|
||||||
|
#define CORTEX_HAS_FPU 0
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of bits in priority masks.
|
||||||
|
*/
|
||||||
|
#define CORTEX_PRIORITY_BITS 4
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of interrupt vectors.
|
||||||
|
* @note This number does not include the 16 system vectors and must be
|
||||||
|
* rounded to a multiple of 8.
|
||||||
|
*/
|
||||||
|
#define CORTEX_NUM_VECTORS 96
|
||||||
|
|
||||||
|
/* The following code is not processed when the file is included from an
|
||||||
|
asm module.*/
|
||||||
|
#if !defined(_FROM_ASM_)
|
||||||
|
|
||||||
|
/* If the device type is not externally defined, for example from the Makefile,
|
||||||
|
then a file named board.h is included. This file must contain a device
|
||||||
|
definition compatible with the vendor include file.*/
|
||||||
|
#if !defined(STM32F2XX)
|
||||||
|
#include "board.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Including the device CMSIS header. Note, we are not using the definitions
|
||||||
|
from this header because we need this file to be usable also from
|
||||||
|
assembler source files. We verify that the info matches instead.*/
|
||||||
|
#include "stm32f2xx.h"
|
||||||
|
|
||||||
|
#if CORTEX_MODEL != __CORTEX_M
|
||||||
|
#error "CMSIS __CORTEX_M mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
|
||||||
|
#error "CMSIS __NVIC_PRIO_BITS mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* !defined(_FROM_ASM_) */
|
||||||
|
|
||||||
|
#endif /* _CMPARAMS_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,90 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file STM32F3xx/cmparams.h
|
||||||
|
* @brief ARM Cortex-M4 parameters for the STM32F3xx.
|
||||||
|
*
|
||||||
|
* @defgroup ARMCMx_STM32F3xx STM32F3xx Specific Parameters
|
||||||
|
* @ingroup ARMCMx_SPECIFIC
|
||||||
|
* @details This file contains the Cortex-M4 specific parameters for the
|
||||||
|
* STM32F3xx platform.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _CMPARAMS_H_
|
||||||
|
#define _CMPARAMS_H_
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Cortex core model.
|
||||||
|
*/
|
||||||
|
#define CORTEX_MODEL 4
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Floating Point unit presence.
|
||||||
|
*/
|
||||||
|
#define CORTEX_HAS_FPU 1
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of bits in priority masks.
|
||||||
|
*/
|
||||||
|
#define CORTEX_PRIORITY_BITS 4
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of interrupt vectors.
|
||||||
|
* @note This number does not include the 16 system vectors and must be
|
||||||
|
* rounded to a multiple of 8.
|
||||||
|
*/
|
||||||
|
#define CORTEX_NUM_VECTORS 88
|
||||||
|
|
||||||
|
/* The following code is not processed when the file is included from an
|
||||||
|
asm module.*/
|
||||||
|
#if !defined(_FROM_ASM_)
|
||||||
|
|
||||||
|
/* If the device type is not externally defined, for example from the Makefile,
|
||||||
|
then a file named board.h is included. This file must contain a device
|
||||||
|
definition compatible with the vendor include file.*/
|
||||||
|
#if !defined (STM32F301x8) && !defined (STM32F318xx) && \
|
||||||
|
!defined (STM32F302x8) && !defined (STM32F302xC) && \
|
||||||
|
!defined (STM32F303x8) && !defined (STM32F303xC) && \
|
||||||
|
!defined (STM32F358xx) && !defined (STM32F334x8) && \
|
||||||
|
!defined (STM32F328xx) && \
|
||||||
|
!defined (STM32F373xC) && !defined (STM32F378xx)
|
||||||
|
#include "board.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Including the device CMSIS header. Note, we are not using the definitions
|
||||||
|
from this header because we need this file to be usable also from
|
||||||
|
assembler source files. We verify that the info matches instead.*/
|
||||||
|
#include "stm32f3xx.h"
|
||||||
|
|
||||||
|
#if CORTEX_MODEL != __CORTEX_M
|
||||||
|
#error "CMSIS __CORTEX_M mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CORTEX_HAS_FPU != __FPU_PRESENT
|
||||||
|
#error "CMSIS __FPU_PRESENT mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
|
||||||
|
#error "CMSIS __NVIC_PRIO_BITS mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* !defined(_FROM_ASM_) */
|
||||||
|
|
||||||
|
#endif /* _CMPARAMS_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,90 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file STM32F4xx/cmparams.h
|
||||||
|
* @brief ARM Cortex-M4 parameters for the STM32F4xx.
|
||||||
|
*
|
||||||
|
* @defgroup ARMCMx_STM32F4xx STM32F4xx Specific Parameters
|
||||||
|
* @ingroup ARMCMx_SPECIFIC
|
||||||
|
* @details This file contains the Cortex-M4 specific parameters for the
|
||||||
|
* STM32F4xx platform.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _CMPARAMS_H_
|
||||||
|
#define _CMPARAMS_H_
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Cortex core model.
|
||||||
|
*/
|
||||||
|
#define CORTEX_MODEL 4
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Floating Point unit presence.
|
||||||
|
*/
|
||||||
|
#define CORTEX_HAS_FPU 1
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of bits in priority masks.
|
||||||
|
*/
|
||||||
|
#define CORTEX_PRIORITY_BITS 4
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of interrupt vectors.
|
||||||
|
* @note This number does not include the 16 system vectors and must be
|
||||||
|
* rounded to a multiple of 8.
|
||||||
|
*/
|
||||||
|
#define CORTEX_NUM_VECTORS 96
|
||||||
|
|
||||||
|
/* The following code is not processed when the file is included from an
|
||||||
|
asm module.*/
|
||||||
|
#if !defined(_FROM_ASM_)
|
||||||
|
|
||||||
|
/* If the device type is not externally defined, for example from the Makefile,
|
||||||
|
then a file named board.h is included. This file must contain a device
|
||||||
|
definition compatible with the vendor include file.*/
|
||||||
|
#if !defined(STM32F405xx) && !defined(STM32F415xx) && \
|
||||||
|
!defined(STM32F407xx) && !defined(STM32F417xx) && \
|
||||||
|
!defined(STM32F427xx) && !defined(STM32F437xx) && \
|
||||||
|
!defined(STM32F429xx) && !defined(STM32F439xx) && \
|
||||||
|
!defined(STM32F401xC) && !defined(STM32F401xE) && \
|
||||||
|
!defined(STM32F411xE)
|
||||||
|
#include "board.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Including the device CMSIS header. Note, we are not using the definitions
|
||||||
|
from this header because we need this file to be usable also from
|
||||||
|
assembler source files. We verify that the info matches instead.*/
|
||||||
|
#include "stm32f4xx.h"
|
||||||
|
|
||||||
|
#if CORTEX_MODEL != __CORTEX_M
|
||||||
|
#error "CMSIS __CORTEX_M mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CORTEX_HAS_FPU != __FPU_PRESENT
|
||||||
|
#error "CMSIS __FPU_PRESENT mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
|
||||||
|
#error "CMSIS __NVIC_PRIO_BITS mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* !defined(_FROM_ASM_) */
|
||||||
|
|
||||||
|
#endif /* _CMPARAMS_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,85 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file STM32F7xx/cmparams.h
|
||||||
|
* @brief ARM Cortex-M7 parameters for the STM32F4xx.
|
||||||
|
*
|
||||||
|
* @defgroup ARMCMx_STM32F7xx STM32F7xx Specific Parameters
|
||||||
|
* @ingroup ARMCMx_SPECIFIC
|
||||||
|
* @details This file contains the Cortex-M7 specific parameters for the
|
||||||
|
* STM32F7xx platform.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _CMPARAMS_H_
|
||||||
|
#define _CMPARAMS_H_
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Cortex core model.
|
||||||
|
*/
|
||||||
|
#define CORTEX_MODEL 7
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Floating Point unit presence.
|
||||||
|
*/
|
||||||
|
#define CORTEX_HAS_FPU 1
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of bits in priority masks.
|
||||||
|
*/
|
||||||
|
#define CORTEX_PRIORITY_BITS 4
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of interrupt vectors.
|
||||||
|
* @note This number does not include the 16 system vectors and must be
|
||||||
|
* rounded to a multiple of 8.
|
||||||
|
*/
|
||||||
|
#define CORTEX_NUM_VECTORS 112
|
||||||
|
|
||||||
|
/* The following code is not processed when the file is included from an
|
||||||
|
asm module.*/
|
||||||
|
#if !defined(_FROM_ASM_)
|
||||||
|
|
||||||
|
/* If the device type is not externally defined, for example from the Makefile,
|
||||||
|
then a file named board.h is included. This file must contain a device
|
||||||
|
definition compatible with the vendor include file.*/
|
||||||
|
#if !defined(STM32F745xx) && !defined(STM32F746xx) && !defined(STM32F756xx)
|
||||||
|
#include "board.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Including the device CMSIS header. Note, we are not using the definitions
|
||||||
|
from this header because we need this file to be usable also from
|
||||||
|
assembler source files. We verify that the info matches instead.*/
|
||||||
|
#include "stm32f7xx.h"
|
||||||
|
|
||||||
|
#if CORTEX_MODEL != __CORTEX_M
|
||||||
|
#error "CMSIS __CORTEX_M mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CORTEX_HAS_FPU != __FPU_PRESENT
|
||||||
|
#error "CMSIS __FPU_PRESENT mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
|
||||||
|
#error "CMSIS __NVIC_PRIO_BITS mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* !defined(_FROM_ASM_) */
|
||||||
|
|
||||||
|
#endif /* _CMPARAMS_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,83 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file STM32L0xx/cmparams.h
|
||||||
|
* @brief ARM Cortex-M0+ parameters for the STM32L0xx.
|
||||||
|
*
|
||||||
|
* @defgroup ARMCMx_STM32L0xx STM32L0xx Specific Parameters
|
||||||
|
* @ingroup ARMCMx_SPECIFIC
|
||||||
|
* @details This file contains the Cortex-M0 specific parameters for the
|
||||||
|
* STM32L0xx platform.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _CMPARAMS_H_
|
||||||
|
#define _CMPARAMS_H_
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Cortex core model.
|
||||||
|
*/
|
||||||
|
#define CORTEX_MODEL 0
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Floating Point unit presence.
|
||||||
|
*/
|
||||||
|
#define CORTEX_HAS_FPU 0
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of bits in priority masks.
|
||||||
|
*/
|
||||||
|
#define CORTEX_PRIORITY_BITS 2
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of interrupt vectors.
|
||||||
|
* @note This number does not include the 16 system vectors and must be
|
||||||
|
* rounded to a multiple of 8.
|
||||||
|
*/
|
||||||
|
#define CORTEX_NUM_VECTORS 32
|
||||||
|
|
||||||
|
/* The following code is not processed when the file is included from an
|
||||||
|
asm module.*/
|
||||||
|
#if !defined(_FROM_ASM_)
|
||||||
|
|
||||||
|
/* If the device type is not externally defined, for example from the Makefile,
|
||||||
|
then a file named board.h is included. This file must contain a device
|
||||||
|
definition compatible with the vendor include file.*/
|
||||||
|
#if !defined(STM32L051xx) && !defined(STM32L052xx) && \
|
||||||
|
!defined(STM32L053xx) && !defined(STM32L062xx) && \
|
||||||
|
!defined(STM32L063xx) && !defined(STM32L061xx)
|
||||||
|
#include "board.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Including the device CMSIS header. Note, we are not using the definitions
|
||||||
|
from this header because we need this file to be usable also from
|
||||||
|
assembler source files. We verify that the info matches instead.*/
|
||||||
|
#include "stm32l0xx.h"
|
||||||
|
|
||||||
|
#if CORTEX_MODEL != __CORTEX_M
|
||||||
|
#error "CMSIS __CORTEX_M mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
|
||||||
|
#error "CMSIS __NVIC_PRIO_BITS mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* !defined(_FROM_ASM_) */
|
||||||
|
|
||||||
|
#endif /* _CMPARAMS_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,94 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file STM32L1xx/cmparams.h
|
||||||
|
* @brief ARM Cortex-M3 parameters for the STM32L1xx.
|
||||||
|
*
|
||||||
|
* @defgroup ARMCMx_STM32L1xx STM32L1xx Specific Parameters
|
||||||
|
* @ingroup ARMCMx_SPECIFIC
|
||||||
|
* @details This file contains the Cortex-M3 specific parameters for the
|
||||||
|
* STM32L1xx platform.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _CMPARAMS_H_
|
||||||
|
#define _CMPARAMS_H_
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Cortex core model.
|
||||||
|
*/
|
||||||
|
#define CORTEX_MODEL 3
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Floating Point unit presence.
|
||||||
|
*/
|
||||||
|
#define CORTEX_HAS_FPU 0
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of bits in priority masks.
|
||||||
|
*/
|
||||||
|
#define CORTEX_PRIORITY_BITS 4
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of interrupt vectors.
|
||||||
|
* @note This number does not include the 16 system vectors and must be
|
||||||
|
* rounded to a multiple of 8.
|
||||||
|
*/
|
||||||
|
#define CORTEX_NUM_VECTORS 64
|
||||||
|
|
||||||
|
/* The following code is not processed when the file is included from an
|
||||||
|
asm module.*/
|
||||||
|
#if !defined(_FROM_ASM_)
|
||||||
|
|
||||||
|
/* If the device type is not externally defined, for example from the Makefile,
|
||||||
|
then a file named board.h is included. This file must contain a device
|
||||||
|
definition compatible with the vendor include file.*/
|
||||||
|
#if !defined(STM32L100xB) && !defined(STM32L100xBA) && \
|
||||||
|
!defined(STM32L100xC) && !defined(STM32L151xB) && \
|
||||||
|
!defined(STM32L151xBA) && !defined(STM32L151xC) && \
|
||||||
|
!defined(STM32L151xCA) && !defined(STM32L151xD) && \
|
||||||
|
!defined(STM32L151xDX) && !defined(STM32L151xE) && \
|
||||||
|
!defined(STM32L152xB) && !defined(STM32L152xBA) && \
|
||||||
|
!defined(STM32L152xC) && !defined(STM32L152xCA) && \
|
||||||
|
!defined(STM32L152xD) && !defined(STM32L152xDX) && \
|
||||||
|
!defined(STM32L152xE) && !defined(STM32L162xC) && \
|
||||||
|
!defined(STM32L162xCA) && !defined(STM32L162xD) && \
|
||||||
|
!defined(STM32L162xDX) && !defined(STM32L162xE)
|
||||||
|
#include "board.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Including the device CMSIS header. Note, we are not using the definitions
|
||||||
|
from this header because we need this file to be usable also from
|
||||||
|
assembler source files. We verify that the info matches instead.*/
|
||||||
|
#include "stm32l1xx.h"
|
||||||
|
|
||||||
|
#if CORTEX_MODEL != __CORTEX_M
|
||||||
|
#error "CMSIS __CORTEX_M mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
|
||||||
|
#error "CMSIS __NVIC_PRIO_BITS mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Fix for yet another consistency error in ST headers.*/
|
||||||
|
#define SVCall_IRQn SVC_IRQn
|
||||||
|
|
||||||
|
#endif /* !defined(_FROM_ASM_) */
|
||||||
|
|
||||||
|
#endif /* _CMPARAMS_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,87 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file STM32F4xx/cmparams.h
|
||||||
|
* @brief ARM Cortex-M4 parameters for the STM32F4xx.
|
||||||
|
*
|
||||||
|
* @defgroup ARMCMx_STM32L$xx STM32L4xx Specific Parameters
|
||||||
|
* @ingroup ARMCMx_SPECIFIC
|
||||||
|
* @details This file contains the Cortex-M4 specific parameters for the
|
||||||
|
* STM32L4xx platform.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _CMPARAMS_H_
|
||||||
|
#define _CMPARAMS_H_
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Cortex core model.
|
||||||
|
*/
|
||||||
|
#define CORTEX_MODEL 4
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Floating Point unit presence.
|
||||||
|
*/
|
||||||
|
#define CORTEX_HAS_FPU 1
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of bits in priority masks.
|
||||||
|
*/
|
||||||
|
#define CORTEX_PRIORITY_BITS 4
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of interrupt vectors.
|
||||||
|
* @note This number does not include the 16 system vectors and must be
|
||||||
|
* rounded to a multiple of 8.
|
||||||
|
*/
|
||||||
|
#define CORTEX_NUM_VECTORS 88
|
||||||
|
|
||||||
|
/* The following code is not processed when the file is included from an
|
||||||
|
asm module.*/
|
||||||
|
#if !defined(_FROM_ASM_)
|
||||||
|
|
||||||
|
/* If the device type is not externally defined, for example from the Makefile,
|
||||||
|
then a file named board.h is included. This file must contain a device
|
||||||
|
definition compatible with the vendor include file.*/
|
||||||
|
#if !defined(STM32L471xx) && !defined(STM32L475xx) && \
|
||||||
|
!defined(STM32L476xx) && !defined(STM32L485xx) && \
|
||||||
|
!defined (STM32L486xx)
|
||||||
|
#include "board.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Including the device CMSIS header. Note, we are not using the definitions
|
||||||
|
from this header because we need this file to be usable also from
|
||||||
|
assembler source files. We verify that the info matches instead.*/
|
||||||
|
#include "stm32l4xx.h"
|
||||||
|
|
||||||
|
#if CORTEX_MODEL != __CORTEX_M
|
||||||
|
#error "CMSIS __CORTEX_M mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CORTEX_HAS_FPU != __FPU_PRESENT
|
||||||
|
#error "CMSIS __FPU_PRESENT mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
|
||||||
|
#error "CMSIS __NVIC_PRIO_BITS mismatch"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* !defined(_FROM_ASM_) */
|
||||||
|
|
||||||
|
#endif /* _CMPARAMS_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,258 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file CW/crt0.s
|
||||||
|
* @brief Generic PowerPC startup file for CodeWarrior.
|
||||||
|
*
|
||||||
|
* @addtogroup PPC_CW_CORE
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module constants. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if !defined(FALSE) || defined(__DOXYGEN__)
|
||||||
|
#define FALSE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(TRUE) || defined(__DOXYGEN__)
|
||||||
|
#define TRUE 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module pre-compile time settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stack segments initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_STACKS_FILL_PATTERN 0x55555555
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stack segments initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_STACKS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DATA segment initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_DATA TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief BSS segment initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_BSS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Constructors invocation switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_CALL_CONSTRUCTORS FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Destructors invocation switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_CALL_DESTRUCTORS FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Code section. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
.extern __sdata2_start__
|
||||||
|
.extern __sdata_start__
|
||||||
|
.extern __bss_start__
|
||||||
|
.extern __bss_end__
|
||||||
|
.extern __irq_stack_base__
|
||||||
|
.extern __irq_stack_end__
|
||||||
|
.extern __process_stack_end__
|
||||||
|
.extern __process_stack_base__
|
||||||
|
.extern __romdata_start__
|
||||||
|
.extern __data_start__
|
||||||
|
.extern __data_end__
|
||||||
|
.extern __init_array_start
|
||||||
|
.extern __init_array_end
|
||||||
|
.extern __fini_array_start
|
||||||
|
.extern __fini_array_end
|
||||||
|
|
||||||
|
.extern main
|
||||||
|
|
||||||
|
.section .crt0, text_vle
|
||||||
|
.align 16
|
||||||
|
.globl _boot_address
|
||||||
|
.type _boot_address, @function
|
||||||
|
_boot_address:
|
||||||
|
/* Stack setup.*/
|
||||||
|
e_lis r1, __process_stack_end__@h
|
||||||
|
e_or2i r1, __process_stack_end__@l
|
||||||
|
se_li r0, 0
|
||||||
|
e_stwu r0, -8(r1)
|
||||||
|
|
||||||
|
/* Small sections registers initialization.*/
|
||||||
|
e_lis r2, __sdata2_start__@h
|
||||||
|
e_or2i r2, __sdata2_start__@l
|
||||||
|
e_lis r13, __sdata_start__@h
|
||||||
|
e_or2i r13, __sdata_start__@l
|
||||||
|
|
||||||
|
/* Early initialization.*/
|
||||||
|
e_bl __early_init
|
||||||
|
|
||||||
|
#if CRT0_INIT_STACKS == TRUE
|
||||||
|
/* Stacks fill pattern.*/
|
||||||
|
e_lis r7, CRT0_STACKS_FILL_PATTERN@h
|
||||||
|
e_or2i r7, CRT0_STACKS_FILL_PATTERN@l
|
||||||
|
|
||||||
|
/* IRQ Stack initialization. Note, the architecture does not use this
|
||||||
|
stack, the size is usually zero. An OS can have special SW handling
|
||||||
|
and require this. A 4 bytes alignment is assumed and required.*/
|
||||||
|
e_lis r4, __irq_stack_base__@h
|
||||||
|
e_or2i r4, __irq_stack_base__@l
|
||||||
|
e_lis r5, __irq_stack_end__@h
|
||||||
|
e_or2i r5, __irq_stack_end__@l
|
||||||
|
.irqsloop:
|
||||||
|
se_cmpl r4, r5
|
||||||
|
se_bge .irqsend
|
||||||
|
se_stw r7, 0(r4)
|
||||||
|
se_addi r4, 4
|
||||||
|
se_b .irqsloop
|
||||||
|
.irqsend:
|
||||||
|
|
||||||
|
/* Process Stack initialization. Note, does not overwrite the already
|
||||||
|
written EABI frame. A 4 bytes alignment is assumed and required.*/
|
||||||
|
e_lis r4, __process_stack_base__@h
|
||||||
|
e_or2i r4, __process_stack_base__@l
|
||||||
|
e_lis r5, (__process_stack_end__ - 8)@h
|
||||||
|
e_or2i r5, (__process_stack_end__ - 8)@l
|
||||||
|
.prcsloop:
|
||||||
|
se_cmpl r4, r5
|
||||||
|
se_bge .prcsend
|
||||||
|
se_stw r7, 0(r4)
|
||||||
|
se_addi r4, 4
|
||||||
|
se_b .prcsloop
|
||||||
|
.prcsend:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CRT0_INIT_BSS == TRUE
|
||||||
|
/* BSS clearing.*/
|
||||||
|
e_lis r4, __bss_start__@h
|
||||||
|
e_or2i r4, __bss_start__@l
|
||||||
|
e_lis r5, __bss_end__@h
|
||||||
|
e_or2i r5, __bss_end__@l
|
||||||
|
se_li r7, 0
|
||||||
|
.bssloop:
|
||||||
|
se_cmpl r4, r5
|
||||||
|
se_bge .bssend
|
||||||
|
se_stw r7, 0(r4)
|
||||||
|
se_addi r4, 4
|
||||||
|
se_b .bssloop
|
||||||
|
.bssend:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CRT0_INIT_DATA == TRUE
|
||||||
|
/* DATA initialization.*/
|
||||||
|
e_lis r4, __romdata_start__@h
|
||||||
|
e_or2i r4, __romdata_start__@l
|
||||||
|
e_lis r5, __data_start__@h
|
||||||
|
e_or2i r5, __data_start__@l
|
||||||
|
e_lis r6, __data_end__@h
|
||||||
|
e_or2i r6, __data_end__@l
|
||||||
|
.dataloop:
|
||||||
|
se_cmpl r5, r6
|
||||||
|
se_bge .dataend
|
||||||
|
se_lwz r7, 0(r4)
|
||||||
|
se_addi r4, 4
|
||||||
|
se_stw r7, 0(r5)
|
||||||
|
se_addi r5, 4
|
||||||
|
se_b .dataloop
|
||||||
|
.dataend:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Late initialization.*/
|
||||||
|
e_bl __late_init
|
||||||
|
|
||||||
|
#if CRT0_CALL_CONSTRUCTORS == TRUE
|
||||||
|
/* Constructors invocation.*/
|
||||||
|
e_lis r4, __init_array_start@h
|
||||||
|
e_or2i r4, __init_array_start@l
|
||||||
|
e_lis r5, __init_array_end@h
|
||||||
|
e_or2i r5, __init_array_end@l
|
||||||
|
.iniloop:
|
||||||
|
se_cmpl r4, r5
|
||||||
|
se_bge .iniend
|
||||||
|
se_lwz r6, 0(r4)
|
||||||
|
se_mtctr r6
|
||||||
|
se_addi r4, 4
|
||||||
|
se_bctrl
|
||||||
|
se_b .iniloop
|
||||||
|
.iniend:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Main program invocation.*/
|
||||||
|
e_bl main
|
||||||
|
|
||||||
|
#if CRT0_CALL_DESTRUCTORS == TRUE
|
||||||
|
/* Destructors invocation.*/
|
||||||
|
e_lis r4, __fini_array_start@h
|
||||||
|
e_or2i r4, __fini_array_start@l
|
||||||
|
e_lis r5, __fini_array_end@h
|
||||||
|
e_or2i r5, __fini_array_end@l
|
||||||
|
.finiloop:
|
||||||
|
se_cmpl r4, r5
|
||||||
|
se_bge .finiend
|
||||||
|
se_lwz r6, 0(r4)
|
||||||
|
se_mtctr r6
|
||||||
|
se_addi r4, 4
|
||||||
|
se_bctrl
|
||||||
|
se_b .finiloop
|
||||||
|
.finiend:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Branching to the defined exit handler.*/
|
||||||
|
e_b __default_exit
|
||||||
|
|
||||||
|
#endif /* !defined(__DOXYGEN__) */
|
||||||
|
|
||||||
|
.section .text_vle
|
||||||
|
.align 4
|
||||||
|
|
||||||
|
/* Default main exit code, infinite loop.*/
|
||||||
|
.weak __default_exit
|
||||||
|
__default_exit:
|
||||||
|
e_b __default_exit
|
||||||
|
|
||||||
|
/* Default early initialization code, none.*/
|
||||||
|
.weak __early_init
|
||||||
|
se_blr
|
||||||
|
|
||||||
|
/* Default late initialization code, none.*/
|
||||||
|
.weak __late_init
|
||||||
|
__late_init:
|
||||||
|
se_blr
|
||||||
|
|
||||||
|
/** @} */
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,242 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file GCC/crt0.s
|
||||||
|
* @brief Generic PowerPC startup file for GCC.
|
||||||
|
*
|
||||||
|
* @addtogroup PPC_GCC_CORE
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module constants. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if !defined(FALSE) || defined(__DOXYGEN__)
|
||||||
|
#define FALSE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(TRUE) || defined(__DOXYGEN__)
|
||||||
|
#define TRUE 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module pre-compile time settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stack segments initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_STACKS_FILL_PATTERN 0x55555555
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stack segments initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_STACKS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DATA segment initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_DATA TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief BSS segment initialization switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_INIT_BSS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Constructors invocation switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_CALL_CONSTRUCTORS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Destructors invocation switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
|
||||||
|
#define CRT0_CALL_DESTRUCTORS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Code section. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
|
||||||
|
.section .crt0, "ax"
|
||||||
|
.align 2
|
||||||
|
.globl _boot_address
|
||||||
|
.type _boot_address, @function
|
||||||
|
_boot_address:
|
||||||
|
/* Stack setup.*/
|
||||||
|
lis %r1, __process_stack_end__@h
|
||||||
|
ori %r1, %r1, __process_stack_end__@l
|
||||||
|
li %r0, 0
|
||||||
|
stwu %r0, -8(%r1)
|
||||||
|
|
||||||
|
/* Small sections registers initialization.*/
|
||||||
|
lis %r2, __sdata2_start__@h
|
||||||
|
ori %r2, %r2, __sdata2_start__@l
|
||||||
|
lis %r13, __sdata_start__@h
|
||||||
|
ori %r13, %r13, __sdata_start__@l
|
||||||
|
|
||||||
|
/* Early initialization.*/
|
||||||
|
bl __early_init
|
||||||
|
|
||||||
|
#if CRT0_INIT_STACKS == TRUE
|
||||||
|
/* Stacks fill pattern.*/
|
||||||
|
lis %r7, CRT0_STACKS_FILL_PATTERN@h
|
||||||
|
ori %r7, %r7, CRT0_STACKS_FILL_PATTERN@l
|
||||||
|
|
||||||
|
/* IRQ Stack initialization. Note, the architecture does not use this
|
||||||
|
stack, the size is usually zero. An OS can have special SW handling
|
||||||
|
and require this. A 4 bytes alignment is assmend and required.*/
|
||||||
|
lis %r4, __irq_stack_base__@h
|
||||||
|
ori %r4, %r4, __irq_stack_base__@l
|
||||||
|
lis %r5, __irq_stack_end__@h
|
||||||
|
ori %r5, %r5, __irq_stack_end__@l
|
||||||
|
.irqsloop:
|
||||||
|
cmpl cr0, %r4, %r5
|
||||||
|
bge cr0, .irqsend
|
||||||
|
stw %r7, 0(%r4)
|
||||||
|
addi %r4, %r4, 4
|
||||||
|
b .irqsloop
|
||||||
|
.irqsend:
|
||||||
|
|
||||||
|
/* Process Stack initialization. Note, does not overwrite the already
|
||||||
|
written EABI frame. A 4 bytes alignment is assmend and required.*/
|
||||||
|
lis %r4, __process_stack_base__@h
|
||||||
|
ori %r4, %r4, __process_stack_base__@l
|
||||||
|
lis %r5, (__process_stack_end__ - 8)@h
|
||||||
|
ori %r5, %r5, (__process_stack_end__ - 8)@l
|
||||||
|
.prcsloop:
|
||||||
|
cmpl cr0, %r4, %r5
|
||||||
|
bge cr0, .prcsend
|
||||||
|
stw %r7, 0(%r4)
|
||||||
|
addi %r4, %r4, 4
|
||||||
|
b .prcsloop
|
||||||
|
.prcsend:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CRT0_INIT_BSS == TRUE
|
||||||
|
/* BSS clearing.*/
|
||||||
|
lis %r4, __bss_start__@h
|
||||||
|
ori %r4, %r4, __bss_start__@l
|
||||||
|
lis %r5, __bss_end__@h
|
||||||
|
ori %r5, %r5, __bss_end__@l
|
||||||
|
li %r7, 0
|
||||||
|
.bssloop:
|
||||||
|
cmpl cr0, %r4, %r5
|
||||||
|
bge cr0, .bssend
|
||||||
|
stw %r7, 0(%r4)
|
||||||
|
addi %r4, %r4, 4
|
||||||
|
b .bssloop
|
||||||
|
.bssend:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CRT0_INIT_DATA == TRUE
|
||||||
|
/* DATA initialization.*/
|
||||||
|
lis %r4, __romdata_start__@h
|
||||||
|
ori %r4, %r4, __romdata_start__@l
|
||||||
|
lis %r5, __data_start__@h
|
||||||
|
ori %r5, %r5, __data_start__@l
|
||||||
|
lis %r6, __data_end__@h
|
||||||
|
ori %r6, %r6, __data_end__@l
|
||||||
|
.dataloop:
|
||||||
|
cmpl cr0, %r5, %r6
|
||||||
|
bge cr0, .dataend
|
||||||
|
lwz %r7, 0(%r4)
|
||||||
|
addi %r4, %r4, 4
|
||||||
|
stw %r7, 0(%r5)
|
||||||
|
addi %r5, %r5, 4
|
||||||
|
b .dataloop
|
||||||
|
.dataend:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Late initialization.*/
|
||||||
|
bl __late_init
|
||||||
|
|
||||||
|
#if CRT0_CALL_CONSTRUCTORS == TRUE
|
||||||
|
/* Constructors invocation.*/
|
||||||
|
lis %r4, __init_array_start@h
|
||||||
|
ori %r4, %r4, __init_array_start@l
|
||||||
|
lis %r5, __init_array_end@h
|
||||||
|
ori %r5, %r5, __init_array_end@l
|
||||||
|
.iniloop:
|
||||||
|
cmplw %cr0, %r4, %r5
|
||||||
|
bge %cr0, .iniend
|
||||||
|
lwz %r6, 0(%r4)
|
||||||
|
mtctr %r6
|
||||||
|
addi %r4, %r4, 4
|
||||||
|
bctrl
|
||||||
|
b .iniloop
|
||||||
|
.iniend:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Main program invocation.*/
|
||||||
|
bl main
|
||||||
|
|
||||||
|
#if CRT0_CALL_DESTRUCTORS == TRUE
|
||||||
|
/* Destructors invocation.*/
|
||||||
|
lis %r4, __fini_array_start@h
|
||||||
|
ori %r4, %r4, __fini_array_start@l
|
||||||
|
lis %r5, __fini_array_end@h
|
||||||
|
ori %r5, %r5, __fini_array_end@l
|
||||||
|
.finiloop:
|
||||||
|
cmplw %cr0, %r4, %r5
|
||||||
|
bge %cr0, .finiend
|
||||||
|
lwz %r6, 0(%r4)
|
||||||
|
mtctr %r6
|
||||||
|
addi %r4, %r4, 4
|
||||||
|
bctrl
|
||||||
|
b .finiloop
|
||||||
|
.finiend:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Branching to the defined exit handler.*/
|
||||||
|
b __default_exit
|
||||||
|
|
||||||
|
/* Default main exit code, infinite loop.*/
|
||||||
|
.weak __default_exit
|
||||||
|
.type __default_exit, @function
|
||||||
|
__default_exit:
|
||||||
|
b __default_exit
|
||||||
|
|
||||||
|
/* Default early initialization code, none.*/
|
||||||
|
.weak __early_init
|
||||||
|
.type __early_init, @function
|
||||||
|
__early_init:
|
||||||
|
blr
|
||||||
|
|
||||||
|
/* Default late initialization code, none.*/
|
||||||
|
.weak __late_init
|
||||||
|
.type __late_init, @function
|
||||||
|
__late_init:
|
||||||
|
blr
|
||||||
|
|
||||||
|
#endif /* !defined(__DOXYGEN__) */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPC560B50 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x00000000, len = 512k
|
||||||
|
dataflash : org = 0x00800000, len = 64k
|
||||||
|
ram : org = 0x40000000, len = 32k
|
||||||
|
}
|
||||||
|
|
||||||
|
INCLUDE rules_z0.ld
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPC560B60 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x00000000, len = 1024k
|
||||||
|
dataflash : org = 0x00800000, len = 64k
|
||||||
|
ram : org = 0x40000000, len = 80k
|
||||||
|
}
|
||||||
|
|
||||||
|
INCLUDE rules_z0.ld
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPC560B64 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x00000000, len = 1536k
|
||||||
|
dataflash : org = 0x00800000, len = 64k
|
||||||
|
ram : org = 0x40000000, len = 96k
|
||||||
|
}
|
||||||
|
|
||||||
|
INCLUDE rules_z0.ld
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPC560D40 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x00000000, len = 256k
|
||||||
|
dataflash : org = 0x00800000, len = 64k
|
||||||
|
ram : org = 0x40000000, len = 16k
|
||||||
|
}
|
||||||
|
|
||||||
|
INCLUDE rules_z0.ld
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPC560P50 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x00000000, len = 512k
|
||||||
|
dataflash : org = 0x00800000, len = 64k
|
||||||
|
ram : org = 0x40000000, len = 40k
|
||||||
|
}
|
||||||
|
|
||||||
|
INCLUDE rules_z0.ld
|
||||||
|
|
@ -0,0 +1,26 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPC563M64 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x00000000, len = 1536k
|
||||||
|
ram : org = 0x40000000, len = 94k
|
||||||
|
}
|
||||||
|
|
||||||
|
INCLUDE rules_z3.ld
|
||||||
|
|
@ -0,0 +1,26 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPC563A70 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x00000000, len = 2M
|
||||||
|
ram : org = 0x40000000, len = 128k
|
||||||
|
}
|
||||||
|
|
||||||
|
INCLUDE rules_z4.ld
|
||||||
|
|
@ -0,0 +1,26 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPC563A80 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x00000000, len = 4M
|
||||||
|
ram : org = 0x40000000, len = 192k
|
||||||
|
}
|
||||||
|
|
||||||
|
INCLUDE rules_z4.ld
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPC56EC74 memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x00000000, len = 3M
|
||||||
|
dataflash : org = 0x00800000, len = 64k
|
||||||
|
ram : org = 0x40000000, len = 256k
|
||||||
|
}
|
||||||
|
|
||||||
|
INCLUDE rules_z4.ld
|
||||||
|
|
@ -0,0 +1,26 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPC56EL54 memory setup in LSM mode.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x00000000, len = 768k
|
||||||
|
ram : org = 0x40000000, len = 128k
|
||||||
|
}
|
||||||
|
|
||||||
|
INCLUDE rules_z4.ld
|
||||||
|
|
@ -0,0 +1,26 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPC56EL60 memory setup in LSM mode.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x00000000, len = 1M
|
||||||
|
ram : org = 0x40000000, len = 128k
|
||||||
|
}
|
||||||
|
|
||||||
|
INCLUDE rules_z4.ld
|
||||||
|
|
@ -0,0 +1,26 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPC56EL70 memory setup in LSM mode.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x00000000, len = 2M
|
||||||
|
ram : org = 0x40000000, len = 192k
|
||||||
|
}
|
||||||
|
|
||||||
|
INCLUDE rules_z4.ld
|
||||||
|
|
@ -0,0 +1,28 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPC57EM80-HSM memory setup.
|
||||||
|
*/
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash : org = 0x0060C000, len = 144k
|
||||||
|
dflash0 : org = 0x00680000, len = 16k
|
||||||
|
dflash1 : org = 0x00684000, len = 16k
|
||||||
|
ram : org = 0xA0000000, len = 40k
|
||||||
|
}
|
||||||
|
|
||||||
|
INCLUDE rules_z0.ld
|
||||||
|
|
@ -0,0 +1,11 @@
|
||||||
|
# List of the ChibiOS e200z0 SPC560BCxx startup files.
|
||||||
|
STARTUPSRC =
|
||||||
|
|
||||||
|
STARTUPASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560BCxx/boot.s \
|
||||||
|
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
|
||||||
|
$(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s
|
||||||
|
|
||||||
|
STARTUPINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
|
||||||
|
${CHIBIOS}/os/common/ports/e200/devices/SPC560BCxx
|
||||||
|
|
||||||
|
STARTUPLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue