diff --git a/firmware/config/stm32f0egt/efifeatures.h b/firmware/config/stm32f0egt/efifeatures.h
index 68d2c6929e..0666abf013 100644
--- a/firmware/config/stm32f0egt/efifeatures.h
+++ b/firmware/config/stm32f0egt/efifeatures.h
@@ -1,7 +1,7 @@
/**
* @file efifeatures.h
*
- * @brief In this header we can configure which firmware modules are used.
+ * @brief In this header we can configure which modules are used for EGT2CAN firmware.
*
* @date Dec 23, 2014
* @author Andrey Belomutskiy, (c) 2012-2014
diff --git a/firmware/config/stm32f0egt/global.h b/firmware/config/stm32f0egt/global.h
new file mode 100644
index 0000000000..ed5ab093ba
--- /dev/null
+++ b/firmware/config/stm32f0egt/global.h
@@ -0,0 +1,9 @@
+
+#define EXTERN_ENGINE
+
+// this stuff is about ChibiOS 2.6 > Migration
+typedef VirtualTimer virtual_timer_t;
+typedef EventListener event_listener_t;
+typedef Thread thread_t;
+
+#define THD_WORKING_AREA WORKING_AREA
diff --git a/firmware/config/stm32f0egt/halconf.h b/firmware/config/stm32f0egt/halconf.h
index 012ec4aa14..aa407e3b46 100644
--- a/firmware/config/stm32f0egt/halconf.h
+++ b/firmware/config/stm32f0egt/halconf.h
@@ -139,7 +139,7 @@
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
-#define HAL_USE_SPI FALSE
+#define HAL_USE_SPI TRUE
#endif
/**
diff --git a/firmware/config/stm32f0egt/mcuconf.h b/firmware/config/stm32f0egt/mcuconf.h
index 3d3b94c983..9064f94e23 100644
--- a/firmware/config/stm32f0egt/mcuconf.h
+++ b/firmware/config/stm32f0egt/mcuconf.h
@@ -129,7 +129,7 @@
/*
* SPI driver system settings.
*/
-#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI1 TRUE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
diff --git a/firmware/config/stm32f0egt/mpu_util.h b/firmware/config/stm32f0egt/mpu_util.h
new file mode 100644
index 0000000000..878eb44b0e
--- /dev/null
+++ b/firmware/config/stm32f0egt/mpu_util.h
@@ -0,0 +1,3 @@
+
+
+#define baseHardwareInit() {}
\ No newline at end of file
diff --git a/firmware/egt2can.cpp b/firmware/egt2can.cpp
index 0aa19db106..b5b2344df7 100644
--- a/firmware/egt2can.cpp
+++ b/firmware/egt2can.cpp
@@ -1,13 +1,14 @@
#include "main.h"
+#include "engine_configuration.h"
+#include "max31855.h"
+
+egt_cs_array_t max31855_cs;
int main_loop_started;
void firmwareError(const char *fmt, ...) {
-}
-
-
/*
* Blue LED blinker thread, times are in milliseconds.
*/
@@ -43,6 +44,16 @@ static msg_t Thread2(void *arg) {
}
+void initSpiCs(SPIConfig *spiConfig, brain_pin_e csPin) {
+ spiConfig->end_cb = NULL;
+// ioportid_t port = getHwPort(csPin);
+// ioportmask_t pin = getHwPin(csPin);
+// spiConfig->ssport = port;
+// spiConfig->sspad = pin;
+// mySetPadMode("chip select", port, pin, PAL_STM32_MODE_OUTPUT);
+}
+
+
void runRusEfi(void) {
@@ -60,16 +71,20 @@ void runRusEfi(void) {
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL);
+ initMax31855(NULL, max31855_cs);
+
/*
* Normal main() thread activity, in this demo it does nothing except
* sleeping in a loop and check the button state, when the button is
* pressed the test procedure is launched with output on the serial
* driver 1.
*/
- while (TRUE) {
+ while (true) {
// if (palReadPad(GPIOA, GPIOA_BUTTON))
// TestThread(&SD1);
- chThdSleepMilliseconds(500);
+ chThdSleepMilliseconds(50);
+
+ printPending();
}
diff --git a/firmware/hw_layer/hardware.h b/firmware/hw_layer/hardware.h
index 773a8aaa20..7e2ea23b7d 100644
--- a/firmware/hw_layer/hardware.h
+++ b/firmware/hw_layer/hardware.h
@@ -52,8 +52,12 @@ void unlockSpi(void);
#define GET_BOARD_TEST_MODE_VALUE() (!palReadPad(getHwPort(boardConfiguration->boardTestModeJumperPin), getHwPin(boardConfiguration->boardTestModeJumperPin)))
#ifdef __cplusplus
+
+#if EFI_PROD_CODE
#include "engine.h"
void initHardware(Logging *logging, Engine *engine);
+#endif /* EFI_PROD_CODE */
+
#endif /* __cplusplus */
#endif /* HARDWARE_H_ */
diff --git a/firmware/hw_layer/max31855.cpp b/firmware/hw_layer/max31855.cpp
index d1c6901cc8..ffd9ec717a 100644
--- a/firmware/hw_layer/max31855.cpp
+++ b/firmware/hw_layer/max31855.cpp
@@ -14,8 +14,9 @@
#include "max31855.h"
-#if EFI_PROD_CODE
#include "hardware.h"
+
+#if EFI_PROD_CODE
#include "settings.h"
#include "pin_repository.h"
#endif /* EFI_PROD_CODE */
@@ -147,7 +148,9 @@ void initMax31855(SPIDriver *drv, egt_cs_array_t max31855_cs) {
addConsoleAction("egtread", (Void) egtRead);
+#if EFI_PROD_CODE
turnOnSpi(SPI_DEVICE_3);
+#endif /* EFI_PROD_CODE */
for (int i = 0; i < MAX31855_CS_COUNT; i++) {
if (max31855_cs[i] != GPIO_UNASSIGNED) {
diff --git a/firmware/iar_egt/build.bat b/firmware/iar_egt/build.bat
new file mode 100644
index 0000000000..943829d8eb
--- /dev/null
+++ b/firmware/iar_egt/build.bat
@@ -0,0 +1,5 @@
+cd ..
+call update_version.bat
+cd iar
+iarbuild ch.ewp -clean Debug
+iarbuild ch.ewp -build Debug
diff --git a/firmware/iar_egt/ch.ewd b/firmware/iar_egt/ch.ewd
new file mode 100644
index 0000000000..c01694ea3e
--- /dev/null
+++ b/firmware/iar_egt/ch.ewd
@@ -0,0 +1,2601 @@
+
+
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+ THIRDPARTY_ID
+ 2
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+ 0
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+ XDS100_ID
+ 2
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+ 2
+ 1
+ 1
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+
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+
+
+
+
+ $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+ 0
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+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+ 0
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+
+ $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+ 1
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+
+ $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin
+ 1
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+ $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
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+ 0
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+ $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin
+ 0
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+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+ 0
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+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+ 0
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+ $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+ 0
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+ $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin
+ 0
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+ 0
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+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+ 1
+
+
+ $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin
+ 1
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+
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+ 0
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+
diff --git a/firmware/iar_egt/ch.ewp b/firmware/iar_egt/ch.ewp
new file mode 100644
index 0000000000..aa6cf27155
--- /dev/null
+++ b/firmware/iar_egt/ch.ewp
@@ -0,0 +1,3282 @@
+
+
+
+ 2
+
+ Debug
+
+ ARM
+
+ 1
+
+ General
+ 3
+
+ 21
+ 1
+ 1
+
+
+
+
+
+
+
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+ ICCARM
+ 2
+
+ 28
+ 1
+ 1
+
+
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+ OBJCOPY
+ 0
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+ 1
+ 1
+ 1
+
+
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+ CUSTOM
+ 3
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+ 0
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+ 1
+
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+ IARCHIVE
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+ 0
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+
+
+ BILINK
+ 0
+
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+
+ Release
+
+ ARM
+
+ 0
+
+ General
+ 3
+
+ 21
+ 1
+ 0
+
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+ AARM
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+
+ 8
+ 1
+ 0
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+
+
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+
+
+ OBJCOPY
+ 0
+
+ 1
+ 1
+ 0
+
+
+
+
+
+
+
+
+ CUSTOM
+ 3
+
+
+
+
+
+
+ BICOMP
+ 0
+
+
+
+ BUILDACTION
+ 1
+
+
+
+
+
+
+ ILINK
+ 0
+
+ 15
+ 1
+ 0
+
+
+
+
+
+
+
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+
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+ config
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+ engines
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+ algo
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+
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+
+ $PROJ_DIR$\..\controllers\core\table_helper.cpp
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+
+ $PROJ_DIR$\..\controllers\core\table_helper.h
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+
+
+ math
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+ $PROJ_DIR$\..\controllers\math\efitime.h
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+
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+
+ $PROJ_DIR$\..\controllers\math\engine_math.h
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+
+ $PROJ_DIR$\..\controllers\math\speed_density.cpp
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+ $PROJ_DIR$\..\controllers\math\speed_density.h
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+
+
+ sensors
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+
+ $PROJ_DIR$\..\controllers\sensors\allsensors.h
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+
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+
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+
+
+ system
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+ trigger
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+
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+
+ $PROJ_DIR$\..\controllers\settings.h
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+
+
+ emulation
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+ hw_layer
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
+ $PROJ_DIR$\..\hw_layer\stepper.h
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+
+ $PROJ_DIR$\..\hw_layer\stm32f4xx_specific.h
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+
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+
+ $PROJ_DIR$\..\hw_layer\trigger_input.h
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+
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+
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+
+ $PROJ_DIR$\..\hw_layer\wave_analyzer_hw.c
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+
+ $PROJ_DIR$\..\hw_layer\wave_analyzer_hw.h
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+
+
+ os
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+ board
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+
+ $PROJ_DIR$\..\chibios\boards\ST_STM32F4_DISCOVERY\board.h
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+
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+ hal
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+ include
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+
+ $PROJ_DIR$\..\chibios\os\hal\include\can.h
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+
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+
+ $PROJ_DIR$\..\chibios\os\hal\include\mac.h
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+
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+ $PROJ_DIR$\..\chibios\os\hal\include\serial_usb.h
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+ $PROJ_DIR$\..\chibios\os\hal\include\spi.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\include\uart.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\include\usb.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\include\usb_cdc.h
+
+
+
+ src
+
+ $PROJ_DIR$\..\chibios\os\hal\src\adc.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\can.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\ext.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\ext_lld.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32F4xx\ext_lld_isr.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\gpt.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\hal.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\i2c.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\icu.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\mac.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\mmc_spi.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\mmcsd.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\pal.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\pwm.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\rtc.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\sdc.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\serial.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\serial_usb.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\spi.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\uart.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\src\usb.c
+
+
+
+
+ kernel
+
+ include
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\ch.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chcond.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chdebug.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chdynamic.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chevents.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chheap.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chinline.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chioch.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chlists.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chmboxes.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chmemcore.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chmempools.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chmsg.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chmtx.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chqueues.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chregistry.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chschd.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chsem.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chstreams.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chsys.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chthreads.h
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\include\chvt.h
+
+
+
+ src
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chcond.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chdebug.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chdynamic.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chevents.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chheap.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chlists.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chmboxes.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chmemcore.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chmempools.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chmsg.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chmtx.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chqueues.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chregistry.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chschd.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chsem.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chsys.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chthreads.c
+
+
+ $PROJ_DIR$\..\chibios\os\kernel\src\chvt.c
+
+
+
+
+ platform
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32F4xx\adc_lld.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32F4xx\adc_lld.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\can_lld.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\can_lld.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\TIMv1\gpt_lld.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\TIMv1\gpt_lld.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32F4xx\hal_lld.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32F4xx\hal_lld.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\I2Cv1\i2c_lld.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\I2Cv1\i2c_lld.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\TIMv1\icu_lld.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\TIMv1\icu_lld.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\GPIOv2\pal_lld.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\GPIOv2\pal_lld.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\TIMv1\pwm_lld.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\TIMv1\pwm_lld.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\RTCv2\rtc_lld.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\RTCv2\rtc_lld.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\USARTv1\serial_lld.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\USARTv1\serial_lld.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\SPIv1\spi_lld.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\SPIv1\spi_lld.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32F4xx\stm32_dma.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32F4xx\stm32_dma.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\OTGv1\stm32_otg.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32F4xx\stm32_rcc.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\TIMv1\stm32_tim.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32F4xx\stm32f4xx.h
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\OTGv1\usb_lld.c
+
+
+ $PROJ_DIR$\..\chibios\os\hal\platforms\STM32\OTGv1\usb_lld.h
+
+
+
+ port
+
+ STM32F4xx
+
+ $PROJ_DIR$\..\chibios\os\ports\IAR\ARMCMx\STM32F4xx\cmparams.h
+
+
+ $PROJ_DIR$\..\chibios\os\ports\IAR\ARMCMx\STM32F4xx\vectors.s
+
+
+
+ $PROJ_DIR$\..\chibios\os\ports\IAR\ARMCMx\chcore.c
+
+
+ $PROJ_DIR$\..\chibios\os\ports\IAR\ARMCMx\chcore.h
+
+
+ $PROJ_DIR$\..\chibios\os\ports\IAR\ARMCMx\chcore_v7m.c
+
+
+ $PROJ_DIR$\..\chibios\os\ports\IAR\ARMCMx\chcore_v7m.h
+
+
+ $PROJ_DIR$\..\chibios\os\ports\IAR\ARMCMx\chcoreasm_v7m.s
+
+
+ $PROJ_DIR$\..\chibios\os\ports\IAR\ARMCMx\chtypes.h
+
+
+ $PROJ_DIR$\..\chibios\os\ports\IAR\ARMCMx\cstartup.s
+
+
+ $PROJ_DIR$\..\chibios\os\ports\common\ARMCMx\nvic.c
+
+
+ $PROJ_DIR$\..\chibios\os\ports\common\ARMCMx\nvic.h
+
+
+
+ various
+
+ $PROJ_DIR$\..\chibios\os\various\chprintf.c
+
+
+ $PROJ_DIR$\..\chibios\os\various\chprintf.h
+
+
+ $PROJ_DIR$\..\chibios\os\various\fatfs_bindings\fatfs_diskio.c
+
+
+ $PROJ_DIR$\..\chibios\os\various\fatfs_bindings\fatfs_syscall.c
+
+
+ $PROJ_DIR$\..\chibios\os\various\memstreams.c
+
+
+ $PROJ_DIR$\..\chibios\os\various\memstreams.h
+
+
+
+
+ util
+
+ $PROJ_DIR$\..\util\cli_registry.c
+
+
+ $PROJ_DIR$\..\util\cli_registry.h
+
+
+ $PROJ_DIR$\..\util\crc.c
+
+
+ $PROJ_DIR$\..\util\crc.h
+
+
+ $PROJ_DIR$\..\util\cyclic_buffer.cpp
+
+
+ $PROJ_DIR$\..\util\cyclic_buffer.h
+
+
+ $PROJ_DIR$\..\util\data_buffer.c
+
+
+ $PROJ_DIR$\..\util\data_buffer.h
+
+
+ $PROJ_DIR$\..\util\efilib.cpp
+
+
+ $PROJ_DIR$\..\util\efilib.h
+
+
+ $PROJ_DIR$\..\util\efilib2.cpp
+
+
+ $PROJ_DIR$\..\util\efilib2.h
+
+
+ $PROJ_DIR$\..\util\histogram.c
+
+
+ $PROJ_DIR$\..\util\histogram.h
+
+
+ $PROJ_DIR$\..\util\listener_array.cpp
+
+
+ $PROJ_DIR$\..\util\listener_array.h
+
+
+ $PROJ_DIR$\..\util\LocalVersionHolder.cpp
+
+
+ $PROJ_DIR$\..\util\LocalVersionHolder.h
+
+
+
+ $PROJ_DIR$\..\chconf.h
+
+
+ $PROJ_DIR$\..\global.h
+
+
+ $PROJ_DIR$\..\halconf.h
+
+
+ $PROJ_DIR$\..\main.cpp
+
+
+ $PROJ_DIR$\..\main.h
+
+
+ $PROJ_DIR$\..\mcuconf.h
+
+
+ $PROJ_DIR$\..\rusefi.cpp
+
+
+ $PROJ_DIR$\..\rusefi.h
+
+
+ $PROJ_DIR$\..\svnversion.h
+
+
+
+
diff --git a/firmware/iar_egt/ch.eww b/firmware/iar_egt/ch.eww
new file mode 100644
index 0000000000..7eb2089077
--- /dev/null
+++ b/firmware/iar_egt/ch.eww
@@ -0,0 +1,10 @@
+
+
+
+
+ $WS_DIR$\ch.ewp
+
+
+
+
+
diff --git a/firmware/iar_egt/ch.icf b/firmware/iar_egt/ch.icf
new file mode 100644
index 0000000000..63f48eb13f
--- /dev/null
+++ b/firmware/iar_egt/ch.icf
@@ -0,0 +1,44 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+/* Size of the IRQ Stack (Main Stack).*/
+define symbol __ICFEDIT_size_irqstack__ = 0x1000;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK};
+define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {};
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {};
+define block SYSHEAP with alignment = 8 {section SYSHEAP};
+define block DATABSS with alignment = 8 {readwrite, zeroinit};
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+keep { section .intvec };
+
+place at address mem:__ICFEDIT_intvec_start__ {section .intvec};
+place in ROM_region {readonly};
+place at start of RAM_region {block IRQSTACK};
+place in RAM_region {block DATABSS, block HEAP};
+place in RAM_region {block SYSHEAP};
+/* todo place in RAM_region {section .ram}; */
+place at end of RAM_region {block CSTACK};
+place in CCMRAM_region {section .ccm};
diff --git a/firmware/iar_egt/flash.bat b/firmware/iar_egt/flash.bat
new file mode 100644
index 0000000000..06a5b394cd
--- /dev/null
+++ b/firmware/iar_egt/flash.bat
@@ -0,0 +1 @@
+st-link_cli -c SWD ur -P Debug\Exe\iar.hex -Rst -Run