fresh openocd
This commit is contained in:
rusefi
parent
e673290e43
commit
76cc993aca
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@ -34,7 +34,7 @@ add_help_text mrb "Returns value of byte in memory."
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# $reg <== ((value & ~$clearbits) | $setbits)
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proc mmw {reg setbits clearbits} {
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set old [mrw $reg]
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set new [expr ($old & ~$clearbits) | $setbits]
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set new [expr {($old & ~$clearbits) | $setbits}]
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mww $reg $new
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}
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Binary file not shown.
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@ -3,10 +3,10 @@
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# debugger/programmer
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#
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interface hla
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adapter driver hla
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hla_layout stlink
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hla_device_desc "ST-LINK"
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hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753
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hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754
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# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2
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# devices seem to have serial numbers with unreadable characters. ST-LINK/V2
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@ -14,4 +14,3 @@ hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374
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# number reset issues.
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# eg.
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#hla_serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
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@ -38,6 +38,8 @@ if { [info exists CPUTAPID] } {
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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@ -52,15 +54,21 @@ flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
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if { [info exists QUADSPI] && $QUADSPI } {
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set a [llength [flash list]]
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set _QSPINAME $_CHIPNAME.qspi
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flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
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}
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# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
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#
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# Since we may be running of an RC oscilator, we crank down the speed a
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# bit more to be on the safe side. Perhaps superstition, but if are
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# running off a crystal, we can run closer to the limit. Note
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# that there can be a pretty wide band where things are more or less stable.
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adapter_khz 2000
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adapter speed 2000
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adapter_nsrst_delay 100
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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@ -83,13 +91,37 @@ $_TARGETNAME configure -event examine-end {
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mmw 0xE0042008 0x00001800 0
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}
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$_TARGETNAME configure -event trace-config {
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# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
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# change this value accordingly to configure trace pins
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# assignment
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mmw 0xE0042004 0x00000020 0
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proc proc_post_enable {_chipname} {
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targets $_chipname.cpu
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if { [$_chipname.tpiu cget -protocol] eq "sync" } {
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switch [$_chipname.tpiu cget -port-width] {
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1 {
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mmw 0xE0042004 0x00000060 0x000000c0
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mmw 0x40021020 0x00000000 0x0000ff00
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mmw 0x40021000 0x000000a0 0x000000f0
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mmw 0x40021008 0x000000f0 0x00000000
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}
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2 {
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mmw 0xE0042004 0x000000a0 0x000000c0
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mmw 0x40021020 0x00000000 0x000fff00
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mmw 0x40021000 0x000002a0 0x000003f0
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mmw 0x40021008 0x000003f0 0x00000000
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}
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4 {
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mmw 0xE0042004 0x000000e0 0x000000c0
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mmw 0x40021020 0x00000000 0x0fffff00
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mmw 0x40021000 0x00002aa0 0x00003ff0
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mmw 0x40021008 0x00003ff0 0x00000000
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}
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}
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} else {
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mmw 0xE0042004 0x00000020 0x000000c0
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}
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}
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$_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME"
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$_TARGETNAME configure -event reset-init {
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# Configure PLL to boost clock to HSI x 4 (64 MHz)
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mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
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@ -100,10 +132,10 @@ $_TARGETNAME configure -event reset-init {
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mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
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# Boost JTAG frequency
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adapter_khz 8000
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adapter speed 8000
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}
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$_TARGETNAME configure -event reset-start {
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# Reduce speed since CPU speed will slow down to 16MHz with the reset
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adapter_khz 2000
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adapter speed 2000
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}
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@ -12,7 +12,7 @@ if { [info exists CHIPNAME] } {
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set _CHIPNAME stm32f7x
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}
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set _ENDIAN little
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 128kB
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@ -64,10 +64,16 @@ flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME
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# the Flash via ITCM alias as virtual
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flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME
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# adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
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adapter_khz 2000
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if { [info exists QUADSPI] && $QUADSPI } {
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set a [llength [flash list]]
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set _QSPINAME $_CHIPNAME.qspi
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flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
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}
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adapter_nsrst_delay 100
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# adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
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adapter speed 2000
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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@ -76,7 +82,7 @@ if {[using_jtag]} {
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#
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# This target is compatible with connect_assert_srst, which may be set in a
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# board file.
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reset_config srst_only srst_nogate
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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@ -162,12 +168,11 @@ $_TARGETNAME configure -event reset-init {
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if {[using_jtag]} {
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[[target current] cget -dap] memaccess 16
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} {
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adapter_khz 8000
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adapter speed 8000
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}
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}
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$_TARGETNAME configure -event reset-start {
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# Reduce speed since CPU speed will slow down to 16MHz with the reset
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adapter_khz 2000
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adapter speed 2000
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}
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@ -12,6 +12,39 @@ if { [info exists CHIPNAME] } {
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set _CHIPNAME stm32h7x
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}
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if { [info exists DUAL_BANK] } {
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set $_CHIPNAME.DUAL_BANK $DUAL_BANK
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unset DUAL_BANK
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} else {
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set $_CHIPNAME.DUAL_BANK 0
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}
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if { [info exists DUAL_CORE] } {
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set $_CHIPNAME.DUAL_CORE $DUAL_CORE
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unset DUAL_CORE
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} else {
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set $_CHIPNAME.DUAL_CORE 0
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}
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# Issue a warning when hla is used, and fallback to single core configuration
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if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
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echo "Warning : hla does not support multicore debugging"
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set $_CHIPNAME.DUAL_CORE 0
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}
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if { [info exists USE_CTI] } {
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set $_CHIPNAME.USE_CTI $USE_CTI
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unset USE_CTI
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} else {
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set $_CHIPNAME.USE_CTI 0
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}
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# Issue a warning when DUAL_CORE=0 and USE_CTI=1, and fallback to USE_CTI=0
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if { ![set $_CHIPNAME.DUAL_CORE] && [set $_CHIPNAME.USE_CTI] } {
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echo "Warning : could not use CTI with a single core device, CTI is disabled"
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set $_CHIPNAME.USE_CTI 0
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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@ -37,21 +70,63 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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swj_newdap $_CHIPNAME bs -irlen 5
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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if {![using_hla]} {
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# STM32H7 provides an APB-AP at access port 2, which allows the access to
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# the debug and trace features on the system APB System Debug Bus (APB-D).
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target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
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swo create $_CHIPNAME.swo -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00E3000
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tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00F5000
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}
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME
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$_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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flash bank $_CHIPNAME.bank1.cpu0 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0
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if {[set $_CHIPNAME.DUAL_BANK]} {
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flash bank $_CHIPNAME.bank2.cpu0 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu0
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}
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if {[set $_CHIPNAME.DUAL_CORE]} {
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target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3
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$_CHIPNAME.cpu1 configure -work-area-phys 0x38000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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flash bank $_CHIPNAME.bank1.cpu1 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu1
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if {[set $_CHIPNAME.DUAL_BANK]} {
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flash bank $_CHIPNAME.bank2.cpu1 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu1
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}
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}
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# Make sure that cpu0 is selected
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targets $_CHIPNAME.cpu0
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if { [info exists QUADSPI] && $QUADSPI } {
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set a [llength [flash list]]
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set _QSPINAME $_CHIPNAME.qspi
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flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
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} else {
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if { [info exists OCTOSPI1] && $OCTOSPI1 } {
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set a [llength [flash list]]
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set _OCTOSPINAME1 $_CHIPNAME.octospi1
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flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
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}
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if { [info exists OCTOSPI2] && $OCTOSPI2 } {
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set b [llength [flash list]]
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set _OCTOSPINAME2 $_CHIPNAME.octospi2
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flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_CHIPNAME.cpu0 0x5200A000
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}
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}
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# Clock after reset is HSI at 64 MHz, no need of PLL
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adapter_khz 1800
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adapter speed 1800
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adapter_nsrst_delay 100
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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@ -67,12 +142,16 @@ if {[using_jtag]} {
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# usage does not work with HLA, so is not done by default. That change could be
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# made in a local configuration file if connect_assert_srst mode is needed for
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# a specific application and a non-HLA adapter is in use.
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reset_config srst_only srst_nogate
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
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if {[set $_CHIPNAME.DUAL_CORE]} {
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$_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
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}
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# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
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# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
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@ -83,31 +162,147 @@ if {![using_hla]} {
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$_CHIPNAME.dap apcsw 0x08000000 0x08000000
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}
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$_TARGETNAME configure -event examine-end {
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$_CHIPNAME.cpu0 configure -event examine-end {
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# Enable D3 and D1 DBG clocks
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# DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
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mmw 0x5C001004 0x00600000 0
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stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
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# Enable debug during low power modes (uses more power)
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains
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mmw 0x5C001004 0x00000187 0
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D1 Domain
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stm32h7x_dbgmcu_mmw 0x004 0x00000007 0
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D2 Domain
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stm32h7x_dbgmcu_mmw 0x004 0x00000038 0
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# Stop watchdog counters during halt
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# DBGMCU_APB3FZ1 |= WWDG1
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mmw 0x5C001034 0x00000040 0
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# DBGMCU_APB4FZ1 |= WDGLSD1
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mmw 0x5C001054 0x00040000 0
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stm32h7x_dbgmcu_mmw 0x034 0x00000040 0
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# DBGMCU_APB1LFZ1 |= WWDG2
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stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
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# DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
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stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
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# Enable clock for tracing
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# DBGMCU_CR |= TRACECLKEN
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stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
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# RM0399 (id 0x450) M7+M4 with SWO Funnel
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# RM0433 (id 0x450) M7 with SWO Funnel
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# RM0455 (id 0x480) M7 without SWO Funnel
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# RM0468 (id 0x483) M7 without SWO Funnel
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# Enable CM7 and CM4 slave ports in SWO trace Funnel
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# Works ok also on devices single core and without SWO funnel
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# Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF
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# SWTF_CTRL |= ENS0 | ENS1
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stm32h7x_dbgmcu_mmw 0x3000 0x00000003 0
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}
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$_TARGETNAME configure -event trace-config {
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# Set TRACECLKEN; TRACE_MODE is set to async; when using sync
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# change this value accordingly to configure trace pins
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# assignment
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mmw 0x5C001004 0x00100000 0
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}
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$_TARGETNAME configure -event reset-init {
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$_CHIPNAME.cpu0 configure -event reset-init {
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# Clock after reset is HSI at 64 MHz, no need of PLL
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adapter_khz 4000
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adapter speed 4000
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}
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# get _CHIPNAME from current target
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proc stm32h7x_get_chipname {} {
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set t [target current]
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set sep [string last "." $t]
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if {$sep == -1} {
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return $t
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}
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return [string range $t 0 [expr {$sep - 1}]]
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}
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if {[set $_CHIPNAME.DUAL_CORE]} {
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$_CHIPNAME.cpu1 configure -event examine-end {
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set _CHIPNAME [stm32h7x_get_chipname]
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global $_CHIPNAME.USE_CTI
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# Stop watchdog counters during halt
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# DBGMCU_APB3FZ2 |= WWDG1
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stm32h7x_dbgmcu_mmw 0x038 0x00000040 0
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# DBGMCU_APB1LFZ2 |= WWDG2
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stm32h7x_dbgmcu_mmw 0x040 0x00000800 0
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# DBGMCU_APB4FZ2 |= WDGLSD1 | WDGLSD2
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stm32h7x_dbgmcu_mmw 0x058 0x000C0000 0
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if {[set $_CHIPNAME.USE_CTI]} {
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stm32h7x_cti_start
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}
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}
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}
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# like mrw, but with target selection
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proc stm32h7x_mrw {used_target reg} {
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set value ""
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$used_target mem2array value 32 $reg 1
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return $value(0)
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}
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# like mmw, but with target selection
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proc stm32h7x_mmw {used_target reg setbits clearbits} {
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set old [stm32h7x_mrw $used_target $reg]
|
||||
set new [expr {($old & ~$clearbits) | $setbits}]
|
||||
$used_target mww $reg $new
|
||||
}
|
||||
|
||||
# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base
|
||||
# this procedure will use the mem_ap on AP2 whenever possible
|
||||
proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
|
||||
# use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
|
||||
if {![using_hla]} {
|
||||
set _CHIPNAME [stm32h7x_get_chipname]
|
||||
set used_target $_CHIPNAME.ap2
|
||||
set reg_addr [expr {0xE00E1000 + $reg_offset}]
|
||||
} {
|
||||
set used_target [target current]
|
||||
set reg_addr [expr {0x5C001000 + $reg_offset}]
|
||||
}
|
||||
|
||||
stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
|
||||
}
|
||||
|
||||
if {[set $_CHIPNAME.USE_CTI]} {
|
||||
# create CTI instances for both cores
|
||||
cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0043000
|
||||
cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xE0043000
|
||||
|
||||
$_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
|
||||
$_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
|
||||
|
||||
$_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
|
||||
$_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
|
||||
|
||||
proc stm32h7x_cti_start {} {
|
||||
set _CHIPNAME [stm32h7x_get_chipname]
|
||||
|
||||
# Configure Cores' CTIs to halt each other
|
||||
# TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
|
||||
$_CHIPNAME.cti0 write INEN0 0x1
|
||||
$_CHIPNAME.cti0 write OUTEN0 0x1
|
||||
$_CHIPNAME.cti1 write INEN0 0x1
|
||||
$_CHIPNAME.cti1 write OUTEN0 0x1
|
||||
|
||||
# enable CTIs
|
||||
$_CHIPNAME.cti0 enable on
|
||||
$_CHIPNAME.cti1 enable on
|
||||
}
|
||||
|
||||
proc stm32h7x_cti_stop {} {
|
||||
set _CHIPNAME [stm32h7x_get_chipname]
|
||||
|
||||
$_CHIPNAME.cti0 enable off
|
||||
$_CHIPNAME.cti1 enable off
|
||||
}
|
||||
|
||||
proc stm32h7x_cti_prepare_restart_all {} {
|
||||
stm32h7x_cti_prepare_restart cti0
|
||||
stm32h7x_cti_prepare_restart cti1
|
||||
}
|
||||
|
||||
proc stm32h7x_cti_prepare_restart {cti} {
|
||||
set _CHIPNAME [stm32h7x_get_chipname]
|
||||
|
||||
# Acknowlodge EDBGRQ at TRIGOUT0
|
||||
$_CHIPNAME.$cti write INACK 0x01
|
||||
$_CHIPNAME.$cti write INACK 0x00
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,11 +24,12 @@ if [catch {transport select}] {
|
|||
}
|
||||
|
||||
proc swj_newdap {chip tag args} {
|
||||
if [using_hla] {
|
||||
eval hla newtap $chip $tag $args
|
||||
} elseif [using_jtag] {
|
||||
if [using_jtag] {
|
||||
eval jtag newtap $chip $tag $args
|
||||
} elseif [using_swd] {
|
||||
eval swd newdap $chip $tag $args
|
||||
} else {
|
||||
echo "Error: transport '[ transport select ]' not supported by swj_newdap"
|
||||
shutdown
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue