tle8888: fix spi confog for STM32F4 (#735)
* tle8888: fix spi confog for STM32F4 * TLE8888: fix array out of bounds access due to incorrect define used in loop
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@ -163,12 +163,10 @@ int tle8888_chip_init(void * data)
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// ret = markUsed(cfg->spi_config.ssport, cfg->spi_config.sspad, DRIVER_NAME " CS");
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// ret = markUsed(cfg->spi_config.ssport, cfg->spi_config.sspad, DRIVER_NAME " CS");
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if (cfg->reset.port != NULL)
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if (cfg->reset.port != NULL)
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ret |= markUsed(cfg->reset.port, cfg->reset.pad, DRIVER_NAME " RST");
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ret |= markUsed(cfg->reset.port, cfg->reset.pad, DRIVER_NAME " RST");
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/*
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for (i = 0; i < TLE8888_DIRECT_MISC; i++)
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error: iteration 4 invokes undefined behavior [-Werror=aggressive-loop-optimizations]
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for (i = 0; i < TLE8888_DIRECT_OUTPUTS; i++)
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if (cfg->direct_io[i].port)
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if (cfg->direct_io[i].port)
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ret |= markUsed(cfg->direct_io[i].port, cfg->direct_io[i].pad, DRIVER_NAME " DIRECT IO");
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ret |= markUsed(cfg->direct_io[i].port, cfg->direct_io[i].pad, DRIVER_NAME " DIRECT IO");
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*/
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if (ret) {
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if (ret) {
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ret = -1;
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ret = -1;
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goto err_gpios;
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goto err_gpios;
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@ -228,15 +226,13 @@ int tle8888_chip_init(void * data)
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err_gpios:
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err_gpios:
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/* unmark pins */
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/* unmark pins */
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markUnused(cfg->spi_config.ssport, cfg->spi_config.sspad);
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//markUnused(cfg->spi_config.ssport, cfg->spi_config.sspad);
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if (cfg->reset.port != NULL)
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if (cfg->reset.port != NULL)
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markUnused(cfg->reset.port, cfg->reset.pad);
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markUnused(cfg->reset.port, cfg->reset.pad);
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/*
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for (i = 0; i < TLE8888_DIRECT_MISC; i++)
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error: iteration 4 invokes undefined behavior [-Werror=aggressive-loop-optimizations]
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for (i = 0; i < TLE8888_DIRECT_OUTPUTS; i++)
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if (cfg->direct_io[i].port)
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if (cfg->direct_io[i].port)
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markUnused(cfg->direct_io[i].port, cfg->direct_io[i].pad);
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markUnused(cfg->direct_io[i].port, cfg->direct_io[i].pad);
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*/
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return ret;
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return ret;
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}
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}
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@ -290,12 +286,15 @@ static struct tle8888_config tle8888_cfg = {
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.ssport = GPIOF,
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.ssport = GPIOF,
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.sspad = 0U,
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.sspad = 0U,
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.cr1 =
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.cr1 =
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/* TODO: set LSB first mode !!!! */
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SPI_CR1_DFF | // 16-bit transfer
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/* SPI_CR1_CPOL | */ // = 0
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SPI_CR1_SSM |
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SPI_CR1_CPHA | // = 1
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SPI_CR1_SSI |
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(((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) |
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SPI_CR1_LSBFIRST | //LSB first
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SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR),
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((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) | // div = 16
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/* 16-bit transfer */
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SPI_CR1_MSTR |
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// SPI_CR1_CPOL | // = 0 CHECK!
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SPI_CR1_CPHA | // = 1 CHECK!
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0,
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.cr2 = 0/* not for F4? SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0*/
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.cr2 = 0/* not for F4? SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0*/
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},
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},
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/* not implemented yet, use STM32 gpios directly */
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/* not implemented yet, use STM32 gpios directly */
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