diff --git a/firmware/config/engines/mazda_miata_vvt.cpp b/firmware/config/engines/mazda_miata_vvt.cpp index 2e68b08ffe..c4ed4294fa 100644 --- a/firmware/config/engines/mazda_miata_vvt.cpp +++ b/firmware/config/engines/mazda_miata_vvt.cpp @@ -118,6 +118,7 @@ void setMazdaMiata2003EngineConfiguration(DECLARE_ENGINE_PARAMETER_F) { // set vvt_mode 3 engineConfiguration->vvtMode = MIATA_NB2; boardConfiguration->vvtCamSensorUseRise = true; + engineConfiguration->vvtDisplayInverted = true; engineConfiguration->vvtOffset = 83; engineConfiguration->activateAuxPid1 = true; // todo: remove this field? diff --git a/firmware/console/status_loop.cpp b/firmware/console/status_loop.cpp index b4cf0e7b41..c8c4695a68 100644 --- a/firmware/console/status_loop.cpp +++ b/firmware/console/status_loop.cpp @@ -226,6 +226,7 @@ static void printSensors(Logging *log, bool fileFormat) { if (fileFormat) { reportSensorF(log, fileFormat, "tCharge", "K", engine->engineState.tChargeK, 2); // log column #8 reportSensorF(log, fileFormat, "curVE", "%", veMap.getValue(rpm, getMap()), 2); + reportSensorF(log, fileFormat, "VVT", "deg", engine->triggerCentral.vvtPosition, 1); } float engineLoad = getEngineLoadT(PASS_ENGINE_PARAMETER_F); diff --git a/firmware/tunerstudio/rusefi.ini b/firmware/tunerstudio/rusefi.ini index 977a929188..262b98e46f 100644 --- a/firmware/tunerstudio/rusefi.ini +++ b/firmware/tunerstudio/rusefi.ini @@ -42,7 +42,7 @@ enable2ndByteCanID = false ; see PAGE_0_SIZE in C source code ; CONFIG_DEFINITION_START -; this section was generated automatically by ConfigDefinition.jar based on rusefi_config.txt Sun Jan 22 11:23:24 EST 2017 +; this section was generated automatically by ConfigDefinition.jar based on rusefi_config.txt Sun Jan 22 11:59:04 EST 2017 pageSize = 16376 page = 1 @@ -1301,6 +1301,7 @@ fileVersion = { 20161225 } entry = cltCorrection, "cltCorrection", float,"%.3f" entry = sparkDwellValue, "dwell", float,"%.3f" + entry = vvtPosition, "VVT", float,"%.2f" ; is there a way to log parameter? entry = debugMode, "debugMode",int,"%d" ; Alternator_PID: alternator duty cycle diff --git a/firmware/tunerstudio/rusefi.input b/firmware/tunerstudio/rusefi.input index e6696dc573..f06f11cbf0 100644 --- a/firmware/tunerstudio/rusefi.input +++ b/firmware/tunerstudio/rusefi.input @@ -1246,6 +1246,7 @@ fileVersion = { 20161225 } entry = cltCorrection, "cltCorrection", float,"%.3f" entry = sparkDwellValue, "dwell", float,"%.3f" + entry = vvtPosition, "VVT", float,"%.2f" ; is there a way to log parameter? entry = debugMode, "debugMode",int,"%d" ; Alternator_PID: alternator duty cycle diff --git a/hardware/brain_board_STM32F407_SD_wing-it/brain_board_STM32F407_SD_wing-it.kicad_pcb b/hardware/brain_board_STM32F407_SD_wing-it/brain_board_STM32F407_SD_wing-it.kicad_pcb new file mode 100644 index 0000000000..390d8e1bec --- /dev/null +++ b/hardware/brain_board_STM32F407_SD_wing-it/brain_board_STM32F407_SD_wing-it.kicad_pcb @@ -0,0 +1,808 @@ +(kicad_pcb (version 4) (host pcbnew 4.0.5) + + (general + (links 6) + (no_connects 0) + (area 141.021999 116.383999 149.078001 155.650001) + (thickness 1.6) + (drawings 75) + (tracks 41) + (zones 0) + (modules 8) + (nets 7) + ) + + (page A) + (title_block + (title brain_board_STM32F407_SD_wing-it) + (date 2017-01-22) + (rev R0.1) + (company "rusEFI by DAECU") + ) + + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + ) + + (setup + (last_trace_width 0.254) + (trace_clearance 0.2032) + (zone_clearance 0.2286) + (zone_45_only no) + (trace_min 0.254) + (segment_width 0.2) + (edge_width 0.15) + (via_size 0.889) + (via_drill 0.635) + (via_min_size 0.889) + (via_min_drill 0.508) + (uvia_size 0.508) + (uvia_drill 0.127) + (uvias_allowed no) + (uvia_min_size 0.508) + (uvia_min_drill 0.127) + (pcb_text_width 0.3) + (pcb_text_size 1 1) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.7 1.7) + (pad_drill 1) + (pad_to_mask_clearance 0.0762) + (aux_axis_origin 0 0) + (visible_elements 7FFFFF7F) + (pcbplotparams + (layerselection 0x010f0_80000001) + (usegerberextensions true) + (excludeedgelayer true) + (linewidth 0.150000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15) + (hpglpenoverlay 2) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 0) + (scaleselection 1) + (outputdirectory gerber/)) + ) + + (net 0 "") + (net 1 /PB3) + (net 2 /PB4) + (net 3 /PB5) + (net 4 /PD4) + (net 5 /VDD) + (net 6 GND) + + (net_class Default "Это класс цепей по умолчанию." + (clearance 0.2032) + (trace_width 0.254) + (via_dia 0.889) + (via_drill 0.635) + (uvia_dia 0.508) + (uvia_drill 0.127) + (add_net /PB3) + (add_net /PB4) + (add_net /PB5) + (add_net /PD4) + (add_net /VDD) + (add_net GND) + ) + + (module Pin_Headers:Pin_Header_Straight_2x03_Pitch2.54mm (layer F.Cu) (tedit 5885015B) (tstamp 588500AE) + (at 142.24 144.272) + (descr "Through hole straight pin header, 2x03, 2.54mm pitch, double rows") + (tags "Through hole pin header THT 2x03 2.54mm double row") + (path /58850D8E) + (fp_text reference P2 (at 1.27 -2.39) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value CONN_02X03 (at 1.27 7.47) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.27 -1.27) (end -1.27 6.35) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 6.35) (end 3.81 6.35) (layer F.Fab) (width 0.1)) + (fp_line (start 3.81 6.35) (end 3.81 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 3.81 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -1.6) (end -1.6 6.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.6 6.6) (end 4.1 6.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.1 6.6) (end 4.1 -1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.1 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole circle (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 2 thru_hole oval (at 2.54 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 3 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 4 thru_hole oval (at 2.54 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 5 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 6 thru_hole oval (at 2.54 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (model Pin_Headers.3dshapes/Pin_Header_Straight_2x03_Pitch2.54mm.wrl + (at (xyz 0.05 -0.1 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 90)) + ) + ) + + (module Pin_Headers:Pin_Header_Straight_2x04_Pitch2.54mm (layer F.Cu) (tedit 588500E8) (tstamp 58850094) + (at 142.24 118.872) + (descr "Through hole straight pin header, 2x04, 2.54mm pitch, double rows") + (tags "Through hole pin header THT 2x04 2.54mm double row") + (path /58850F4A) + (fp_text reference P1 (at 1.27 -2.39) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value CONN_02X04 (at 1.27 10.01) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.27 -1.27) (end -1.27 8.89) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 8.89) (end 3.81 8.89) (layer F.Fab) (width 0.1)) + (fp_line (start 3.81 8.89) (end 3.81 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 3.81 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -1.6) (end -1.6 9.2) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.6 9.2) (end 4.1 9.2) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.1 9.2) (end 4.1 -1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.1 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole circle (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 2 thru_hole oval (at 2.54 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 5 /VDD)) + (pad 3 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 4 thru_hole oval (at 2.54 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 5 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 2 /PB4)) + (pad 6 thru_hole oval (at 2.54 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 3 /PB5)) + (pad 7 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 8 thru_hole oval (at 2.54 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 1 /PB3)) + (model Pin_Headers.3dshapes/Pin_Header_Straight_2x04_Pitch2.54mm.wrl + (at (xyz 0.05 -0.15 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 90)) + ) + ) + + (module Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm (layer F.Cu) (tedit 5884F641) (tstamp 5884F659) + (at 142.24 131.572) + (descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x01 2.54mm single row") + (path /5884F69A) + (fp_text reference P11 (at 0 -2.39) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value CONN_01X01 (at 0 2.39) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -1.6) (end -1.6 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.6 1.6) (end 1.6 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.6 1.6) (end 1.6 -1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.6 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole circle (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (model Pin_Headers.3dshapes/Pin_Header_Straight_1x01_Pitch2.54mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 90)) + ) + ) + + (module Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm (layer F.Cu) (tedit 5884F6CF) (tstamp 5884F66C) + (at 141.859 154.432) + (descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x01 2.54mm single row") + (path /5884F6E2) + (fp_text reference P12 (at 0 -2.39) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value CONN_01X01 (at 0 2.39) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -1.6) (end -1.6 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.6 1.6) (end 1.6 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.6 1.6) (end 1.6 -1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.6 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole circle (at 0.381 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (model Pin_Headers.3dshapes/Pin_Header_Straight_1x01_Pitch2.54mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 90)) + ) + ) + + (module Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm (layer F.Cu) (tedit 5884DCD6) (tstamp 5884DBE5) + (at 144.78 154.432) + (descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x01 2.54mm single row") + (path /5884E591) + (fp_text reference P8 (at 0 -2.39) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value CONN_01X01 (at 0 2.39) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -1.6) (end -1.6 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.6 1.6) (end 1.6 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.6 1.6) (end 1.6 -1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.6 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole circle (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 6 GND)) + (model Pin_Headers.3dshapes/Pin_Header_Straight_1x01_Pitch2.54mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 90)) + ) + ) + + (module Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm (layer F.Cu) (tedit 5884DC4B) (tstamp 5884DBD2) + (at 144.78 131.572) + (descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x01 2.54mm single row") + (path /5884E491) + (fp_text reference P7 (at 0 -2.39) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value CONN_01X01 (at 0 2.39) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -1.6) (end -1.6 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.6 1.6) (end 1.6 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.6 1.6) (end 1.6 -1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.6 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole circle (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 4 /PD4)) + (model Pin_Headers.3dshapes/Pin_Header_Straight_1x01_Pitch2.54mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 90)) + ) + ) + + (module Pin_Headers:Pin_Header_Angled_1x03 (layer B.Cu) (tedit 58616A15) (tstamp 5861092D) + (at 147.066 122.682) + (descr "Through hole pin header") + (tags "pin header") + (path /58618F13) + (fp_text reference P5 (at 0.127 2.54) (layer B.SilkS) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_text value CONN_01X03 (at 0 3.1) (layer B.Fab) hide + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_line (start -1.5 1.75) (end -1.5 -6.85) (layer B.CrtYd) (width 0.05)) + (fp_line (start 10.65 1.75) (end 10.65 -6.85) (layer B.CrtYd) (width 0.05)) + (fp_line (start -1.5 1.75) (end 10.65 1.75) (layer B.CrtYd) (width 0.05)) + (fp_line (start -1.5 -6.85) (end 10.65 -6.85) (layer B.CrtYd) (width 0.05)) + (fp_line (start -1.3 1.55) (end -1.3 0) (layer B.SilkS) (width 0.15)) + (fp_line (start 0 1.55) (end -1.3 1.55) (layer B.SilkS) (width 0.15)) + (fp_line (start 4.191 0.127) (end 10.033 0.127) (layer B.SilkS) (width 0.15)) + (fp_line (start 10.033 0.127) (end 10.033 -0.127) (layer B.SilkS) (width 0.15)) + (fp_line (start 10.033 -0.127) (end 4.191 -0.127) (layer B.SilkS) (width 0.15)) + (fp_line (start 4.191 -0.127) (end 4.191 0) (layer B.SilkS) (width 0.15)) + (fp_line (start 4.191 0) (end 10.033 0) (layer B.SilkS) (width 0.15)) + (fp_line (start 1.524 0.254) (end 1.143 0.254) (layer B.SilkS) (width 0.15)) + (fp_line (start 1.524 -0.254) (end 1.143 -0.254) (layer B.SilkS) (width 0.15)) + (fp_line (start 1.524 -2.286) (end 1.143 -2.286) (layer B.SilkS) (width 0.15)) + (fp_line (start 1.524 -2.794) (end 1.143 -2.794) (layer B.SilkS) (width 0.15)) + (fp_line (start 1.524 -4.826) (end 1.143 -4.826) (layer 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b/hardware/brain_board_STM32F407_SD_wing-it/brain_board_STM32F407_SD_wing-it.net @@ -0,0 +1,174 @@ +(export (version D) + (design + (source C:/Users/Vista_64_D630/Desktop/Jared/code/Hardware/trunk/rusefi.com/brain_board_STM32F407_SD_wing-it/brain_board_STM32F407_SD_wing-it.sch) + (date "1/22/2017 1:54:05 PM") + (tool "Eeschema 4.0.5") + (sheet (number 1) (name /) (tstamps /) + (title_block + (title brain_board_STM32F407_SD_wing-it) + (company "rusEFI by DAECU") + (rev R0.1) + (date 2017-01-22) + (source brain_board_STM32F407_SD_wing-it.sch) + (comment (number 1) (value "")) + (comment (number 2) (value "")) + (comment (number 3) (value "")) + (comment (number 4) (value ""))))) + (components + (comp (ref P5) + (value CONN_01X03) + (footprint Pin_Headers:Pin_Header_Angled_1x03) + (libsource (lib conn) (part CONN_01X03)) + (sheetpath (names /) (tstamps /)) + (tstamp 58618F13)) + (comp (ref P6) + (value CONN_01X03) + (footprint Pin_Headers:Pin_Header_Angled_1x03) + (libsource (lib conn) (part CONN_01X03)) + (sheetpath (names /) (tstamps /)) + (tstamp 58619400)) + (comp (ref P7) + (value CONN_01X01) + (footprint Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm) + (libsource (lib conn) (part CONN_01X01)) + (sheetpath (names /) (tstamps /)) + (tstamp 5884E491)) + (comp (ref P8) + (value CONN_01X01) + (footprint Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm) + (libsource (lib conn) (part CONN_01X01)) + (sheetpath (names /) (tstamps /)) + (tstamp 5884E591)) + (comp (ref P11) + (value CONN_01X01) + (footprint Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm) + (libsource (lib conn) (part CONN_01X01)) + (sheetpath (names /) (tstamps /)) + (tstamp 5884F69A)) + (comp (ref P12) + (value CONN_01X01) + (footprint Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm) + (libsource (lib conn) (part CONN_01X01)) + (sheetpath (names /) (tstamps /)) + (tstamp 5884F6E2)) + (comp (ref P2) + (value CONN_02X03) + (footprint Pin_Headers:Pin_Header_Straight_2x03_Pitch2.54mm) + (libsource (lib conn) (part CONN_02X03)) + (sheetpath (names /) (tstamps /)) + (tstamp 58850D8E)) + (comp (ref P1) + (value CONN_02X04) + (footprint Pin_Headers:Pin_Header_Straight_2x04_Pitch2.54mm) + (libsource (lib conn) (part CONN_02X04)) + (sheetpath (names /) (tstamps /)) + (tstamp 58850F4A))) + (libparts + (libpart (lib conn) (part CONN_01X01) + (description "Connector, single row, 01x01") + (footprints + (fp Pin_Header_Straight_1X01) + (fp Pin_Header_Angled_1X01) + (fp Socket_Strip_Straight_1X01) + (fp Socket_Strip_Angled_1X01)) + (fields + (field (name Reference) P) + (field (name Value) CONN_01X01)) + (pins + (pin (num 1) (name P1) (type passive)))) + (libpart (lib conn) (part CONN_01X03) + (description "Connector, single row, 01x03") + (footprints + (fp Pin_Header_Straight_1X03) + (fp Pin_Header_Angled_1X03) + (fp Socket_Strip_Straight_1X03) + (fp Socket_Strip_Angled_1X03)) + (fields + (field (name Reference) P) + (field (name Value) CONN_01X03)) + (pins + (pin (num 1) (name P1) (type passive)) + (pin (num 2) (name P2) (type passive)) + (pin (num 3) (name P3) (type passive)))) + (libpart (lib conn) (part CONN_02X03) + (description "Connector, double row, 02x03") + (footprints + (fp Pin_Header_Straight_2X03) + (fp Pin_Header_Angled_2X03) + (fp Socket_Strip_Straight_2X03) + (fp Socket_Strip_Angled_2X03)) + (fields + (field (name Reference) P) + (field (name Value) CONN_02X03)) + (pins + (pin (num 1) (name P1) (type passive)) + (pin (num 2) (name P2) (type passive)) + (pin (num 3) (name P3) (type passive)) + (pin (num 4) (name P4) (type passive)) + (pin (num 5) (name P5) (type passive)) + (pin (num 6) (name P6) (type passive)))) + (libpart (lib conn) (part CONN_02X04) + (description "Connector, double row, 02x04") + (footprints + (fp Pin_Header_Straight_2X04) + (fp Pin_Header_Angled_2X04) + (fp Socket_Strip_Straight_2X04) + (fp Socket_Strip_Angled_2X04)) + (fields + (field (name Reference) P) + (field (name Value) CONN_02X04)) + (pins + (pin (num 1) (name P1) (type passive)) + (pin (num 2) (name P2) (type passive)) + (pin (num 3) (name P3) (type passive)) + (pin (num 4) (name P4) (type passive)) + (pin (num 5) (name P5) (type passive)) + (pin (num 6) (name P6) (type passive)) + (pin (num 7) (name P7) (type passive)) + (pin (num 8) (name P8) (type passive))))) + (libraries + (library (logical conn) + (uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\conn.lib"))) + (nets + (net (code 1) (name "Net-(P2-Pad1)") + (node (ref P2) (pin 1))) + (net (code 2) (name "Net-(P11-Pad1)") + (node (ref P11) (pin 1))) + (net (code 3) (name "Net-(P12-Pad1)") + (node (ref P12) (pin 1))) + (net (code 4) (name "Net-(P1-Pad1)") + (node (ref P1) (pin 1))) + (net (code 5) (name "Net-(P1-Pad7)") + (node (ref P1) (pin 7))) + (net (code 6) (name "Net-(P1-Pad3)") + (node (ref P1) (pin 3))) + (net (code 7) (name "Net-(P1-Pad4)") + (node (ref P1) (pin 4))) + (net (code 8) (name "Net-(P2-Pad3)") + (node (ref P2) (pin 3))) + (net (code 9) (name "Net-(P2-Pad5)") + (node (ref P2) (pin 5))) + (net (code 10) (name "Net-(P2-Pad6)") + (node (ref P2) (pin 6))) + (net (code 11) (name "Net-(P2-Pad4)") + (node (ref P2) (pin 4))) + (net (code 12) (name "Net-(P2-Pad2)") + (node (ref P2) (pin 2))) + (net (code 13) (name GND) + (node (ref P6) (pin 1)) + (node (ref P8) (pin 1))) + (net (code 14) (name /VDD) + (node (ref P5) (pin 3)) + (node (ref P1) (pin 2))) + (net (code 15) (name /PB3) + (node (ref P1) (pin 8)) + (node (ref P6) (pin 3))) + (net (code 16) (name /PD4) + (node (ref P7) (pin 1)) + (node (ref P6) (pin 2))) + (net (code 18) (name /PB4) + (node (ref P5) (pin 1)) + (node (ref P1) (pin 5))) + (net (code 19) (name /PB5) + (node (ref P5) (pin 2)) + (node (ref P1) (pin 6))))) \ No newline at end of file diff --git a/hardware/brain_board_STM32F407_SD_wing-it/brain_board_STM32F407_SD_wing-it.pro b/hardware/brain_board_STM32F407_SD_wing-it/brain_board_STM32F407_SD_wing-it.pro new file mode 100644 index 0000000000..076605cbe4 --- /dev/null +++ b/hardware/brain_board_STM32F407_SD_wing-it/brain_board_STM32F407_SD_wing-it.pro @@ -0,0 +1,55 @@ +update=1/20/2017 5:28:03 PM +version=1 +last_client=kicad +[general] +version=1 +[cvpcb] +version=1 +NetIExt=net +[cvpcb/libraries] +EquName1=devcms +[eeschema] +version=1 +LibDir=../rusefi_lib +[eeschema/libraries] +LibName1=KICAD_Older_Version +LibName2=power +LibName3=device +LibName4=conn +LibName5=linear +LibName6=analog_switches +LibName7=stm32 +LibName8=../rusefi_misc/lib/art-electro-conn +LibName9=../rusefi_misc/lib/art-electro-ic +LibName10=../rusefi_misc/lib/art-electro-conn_2 +LibName11=../rusefi_misc/lib/logo_flipped +LibName12=crystal(mc306) +[pcbnew] +version=1 +PageLayoutDescrFile=../rusefi_lib/Border.kicad_wks +LastNetListRead=stm32f407_board.net +PadDrill=0 +PadDrillOvalY=0 +PadSizeH=1.3 +PadSizeV=1.9 +PcbTextSizeV=1 +PcbTextSizeH=1 +PcbTextThickness=0.3 +ModuleTextSizeV=1 +ModuleTextSizeH=1 +ModuleTextSizeThickness=0.15 +SolderMaskClearance=0 +SolderMaskMinWidth=0 +DrawSegmentWidth=0.2 +BoardOutlineThickness=0.15 +ModuleOutlineThickness=0.15 +[schematic_editor] +version=1 +PageLayoutDescrFile=../rusefi_lib/Border.kicad_wks +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName=Pcbnew +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/hardware/brain_board_STM32F407_SD_wing-it/brain_board_STM32F407_SD_wing-it.sch b/hardware/brain_board_STM32F407_SD_wing-it/brain_board_STM32F407_SD_wing-it.sch new file mode 100644 index 0000000000..da83020623 --- /dev/null +++ b/hardware/brain_board_STM32F407_SD_wing-it/brain_board_STM32F407_SD_wing-it.sch @@ -0,0 +1,188 @@ +EESchema Schematic File Version 2 +LIBS:KICAD_Older_Version +LIBS:power +LIBS:device +LIBS:conn +LIBS:linear +LIBS:analog_switches +LIBS:stm32 +LIBS:art-electro-conn +LIBS:art-electro-ic +LIBS:art-electro-conn_2 +LIBS:logo_flipped +LIBS:crystal(mc306) +LIBS:brain_board_STM32F407_SD_wing-it-cache +EELAYER 25 0 +EELAYER END +$Descr A 11000 8500 +encoding utf-8 +Sheet 1 1 +Title "brain_board_STM32F407_SD_wing-it" +Date "2017-01-22" +Rev "R0.1" +Comp "rusEFI by DAECU" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 8125 5400 0 60 ~ 0 +Right conn +$Comp +L GND #PWR01 +U 1 1 52CFAC0C +P 8700 7000 +F 0 "#PWR01" H 8700 7000 30 0001 C CNN +F 1 "GND" H 8700 6930 30 0001 C CNN +F 2 "" H 8700 7000 60 0000 C CNN +F 3 "" H 8700 7000 60 0000 C CNN + 1 8700 7000 + 0 -1 -1 0 +$EndComp +Text Label 8750 5600 0 60 ~ 0 +VDD +Text Label 8750 5800 0 60 ~ 0 +PB5 +Text Label 8750 5900 0 60 ~ 0 +PB3 +Text Label 8750 6100 0 60 ~ 0 +PD4 +Wire Wire Line + 8600 7000 8700 7000 +Wire Wire Line + 8750 5600 8600 5600 +Wire Wire Line + 8750 5800 8600 5800 +Wire Wire Line + 8750 5900 8600 5900 +Wire Wire Line + 8750 6100 8600 6100 +Connection ~ -4675 3450 +Text Label 7950 5800 2 60 ~ 0 +PB4 +Wire Wire Line + 8100 5800 7950 5800 +Text Label 9625 6125 2 60 ~ 0 +PB5 +Text Label 9625 6650 2 60 ~ 0 +PB3 +Text Label 9625 6550 2 60 ~ 0 +PD4 +Text Label 9625 6225 2 60 ~ 0 +VDD +Text Label 9625 6025 2 60 ~ 0 +PB4 +$Comp +L GND #PWR02 +U 1 1 5861744D +P 9625 6450 +F 0 "#PWR02" H 9625 6450 30 0001 C CNN +F 1 "GND" H 9625 6380 30 0001 C CNN +F 2 "" H 9625 6450 60 0000 C CNN +F 3 "" H 9625 6450 60 0000 C CNN + 1 9625 6450 + 0 1 1 0 +$EndComp +Text Notes 9975 6350 0 60 ~ 0 +SD Card +$Comp +L CONN_01X03 P5 +U 1 1 58618F13 +P 9825 6125 +F 0 "P5" H 9825 6325 50 0000 C CNN +F 1 "CONN_01X03" V 9925 6125 50 0001 C CNN +F 2 "Pin_Headers:Pin_Header_Angled_1x03" H 9825 6125 50 0001 C CNN +F 3 "" H 9825 6125 50 0000 C CNN + 1 9825 6125 + 1 0 0 -1 +$EndComp +$Comp +L CONN_01X03 P6 +U 1 1 58619400 +P 9825 6550 +F 0 "P6" H 9825 6750 50 0000 C CNN +F 1 "CONN_01X03" V 9925 6550 50 0001 C CNN +F 2 "Pin_Headers:Pin_Header_Angled_1x03" H 9825 6550 50 0001 C CNN +F 3 "" H 9825 6550 50 0000 C CNN + 1 9825 6550 + 1 0 0 -1 +$EndComp +$Comp +L CONN_01X01 P7 +U 1 1 5884E491 +P 8400 6100 +F 0 "P7" H 8525 6100 50 0000 C CNN +F 1 "CONN_01X01" V 8500 6100 50 0001 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm" H 8400 6100 50 0001 C CNN +F 3 "" H 8400 6100 50 0000 C CNN + 1 8400 6100 + -1 0 0 1 +$EndComp +$Comp +L CONN_01X01 P8 +U 1 1 5884E591 +P 8400 7000 +F 0 "P8" H 8525 7000 50 0000 C CNN +F 1 "CONN_01X01" V 8500 7000 50 0001 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm" H 8400 7000 50 0001 C CNN +F 3 "" H 8400 7000 50 0000 C CNN + 1 8400 7000 + -1 0 0 1 +$EndComp +$Comp +L CONN_01X01 P11 +U 1 1 5884F69A +P 7925 6100 +F 0 "P11" H 8050 6100 50 0000 C CNN +F 1 "CONN_01X01" V 8025 6100 50 0001 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm" H 7925 6100 50 0001 C CNN +F 3 "" H 7925 6100 50 0000 C CNN + 1 7925 6100 + 1 0 0 -1 +$EndComp +$Comp +L CONN_01X01 P12 +U 1 1 5884F6E2 +P 7950 7000 +F 0 "P12" H 8075 7000 50 0000 C CNN +F 1 "CONN_01X01" V 8050 7000 50 0001 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm" H 7950 7000 50 0001 C CNN +F 3 "" H 7950 7000 50 0000 C CNN + 1 7950 7000 + 1 0 0 -1 +$EndComp +NoConn ~ 8100 5600 +NoConn ~ 8100 5900 +NoConn ~ 7725 6100 +NoConn ~ 7750 7000 +NoConn ~ 8100 5700 +NoConn ~ 8600 5700 +NoConn ~ 8725 6450 +NoConn ~ 8725 6550 +NoConn ~ 8725 6650 +NoConn ~ 9225 6650 +NoConn ~ 9225 6550 +NoConn ~ 9225 6450 +$Comp +L CONN_02X03 P2 +U 1 1 58850D8E +P 8975 6550 +F 0 "P2" H 8975 6750 50 0000 C CNN +F 1 "CONN_02X03" H 8975 6350 50 0001 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_2x03_Pitch2.54mm" H 8975 5350 50 0000 C CNN +F 3 "" H 8975 5350 50 0000 C CNN + 1 8975 6550 + 1 0 0 -1 +$EndComp +$Comp +L CONN_02X04 P1 +U 1 1 58850F4A +P 8350 5750 +F 0 "P1" H 8350 6000 50 0000 C CNN +F 1 "CONN_02X04" H 8350 5500 50 0001 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_2x04_Pitch2.54mm" H 8350 4550 50 0001 C CNN +F 3 "" H 8350 4550 50 0000 C CNN + 1 8350 5750 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/hardware/brain_board_STM32F407_SD_wing-it/gerber/brain_board_STM32F407_SD_wing-it_R0.1_PCB_MFG.zip b/hardware/brain_board_STM32F407_SD_wing-it/gerber/brain_board_STM32F407_SD_wing-it_R0.1_PCB_MFG.zip new file mode 100644 index 0000000000..4fa0fcbfa5 Binary files /dev/null and b/hardware/brain_board_STM32F407_SD_wing-it/gerber/brain_board_STM32F407_SD_wing-it_R0.1_PCB_MFG.zip differ