diff --git a/firmware/config/boards/proteus/prepend.txt b/firmware/config/boards/proteus/prepend.txt
index 5da692cdab..1caf775e5c 100644
--- a/firmware/config/boards/proteus/prepend.txt
+++ b/firmware/config/boards/proteus/prepend.txt
@@ -18,3 +18,4 @@
 #define show_Frankenso_presets false
 #define show_microRusEFI_presets false
 #define show_Proteus_presets true
+#define show_f7_presets true
diff --git a/firmware/controllers/bench_test.cpp b/firmware/controllers/bench_test.cpp
index 510e91e5fb..79fc737c5c 100644
--- a/firmware/controllers/bench_test.cpp
+++ b/firmware/controllers/bench_test.cpp
@@ -386,6 +386,15 @@ static void handleCommandX14(uint16_t index) {
 	case 0x12:
 		widebandUpdatePending = true;
 		return;
+	case 0x14:
+#ifdef STM32F7
+		void sys_dual_bank(void);
+		sys_dual_bank();
+		//rebootNow();
+#else
+		firmwareError(OBD_PCM_Processor_Fault, "Unexpected dbank command", index);
+#endif
+		return;
 	default:
 		firmwareError(OBD_PCM_Processor_Fault, "Unexpected bench x14 %d", index);
 	}
diff --git a/firmware/hw_layer/ports/stm32/stm32f7/mpu_util.cpp b/firmware/hw_layer/ports/stm32/stm32f7/mpu_util.cpp
index d22497f725..3d2ab1cc59 100644
--- a/firmware/hw_layer/ports/stm32/stm32f7/mpu_util.cpp
+++ b/firmware/hw_layer/ports/stm32/stm32f7/mpu_util.cpp
@@ -120,3 +120,32 @@ uintptr_t getFlashAddrSecondCopy() {
 			return 0;
 	}
 }
+
+#define FLASH_ACR           (*(volatile uint32_t *)(FLASH_BASE + 0x00))
+#define FLASH_KEYR          (*(volatile uint32_t *)(FLASH_BASE + 0x04))
+#define FLASH_OPTKEYR       (*(volatile uint32_t *)(FLASH_BASE + 0x08))
+#define FLASH_SR            (*(volatile uint32_t *)(FLASH_BASE + 0x0C))
+#define FLASH_CR            (*(volatile uint32_t *)(FLASH_BASE + 0x10))
+#define FLASH_OPTCR         (*(volatile uint32_t *)(FLASH_BASE + 0x14))
+
+#define FLASH_OPTCR_STRT                       (1 << 1)
+
+#define FLASH_OPTKEY1                         (0x08192A3B)
+#define FLASH_OPTKEY2                         (0x4C5D6E7F)
+
+void sys_dual_bank(void) {
+    uint32_t reg;
+
+    /* Unlock OPTCR */
+    FLASH_OPTKEYR = FLASH_OPTKEY1;
+    FLASH_OPTKEYR = FLASH_OPTKEY2;
+
+    /* Disable protection + Switch to dual bank */
+    reg = FLASH_OPTCR;
+    reg &= ~0x000FF00;
+    reg |= 0x0000AA00;
+    reg &= ~(FLASH_OPTCR_nDBANK);
+    FLASH_OPTCR = reg;
+    FLASH_OPTCR |= FLASH_OPTCR_STRT;
+}
+
diff --git a/firmware/tunerstudio/rusefi.input b/firmware/tunerstudio/rusefi.input
index f9ad5cf0bf..b36352bd29 100644
--- a/firmware/tunerstudio/rusefi.input
+++ b/firmware/tunerstudio/rusefi.input
@@ -1714,6 +1714,7 @@ cmd_etb_autotune_stop        = "@@TS_IO_TEST_COMMAND_char@@@@CMD_TS_X14_16_hex@@
 cmb_etb_auto_calibrate_2     = "@@TS_IO_TEST_COMMAND_char@@@@CMD_TS_X14_16_hex@@\x00\x11"
 cmd_wideband_firmare_update  = "@@TS_IO_TEST_COMMAND_char@@@@CMD_TS_X14_16_hex@@\x00\x12"
 cmd_enable_ext_stim          = "@@TS_IO_TEST_COMMAND_char@@@@CMD_TS_X14_16_hex@@\x00\x13"
+cmd_nDBANK                   = "@@TS_IO_TEST_COMMAND_char@@@@CMD_TS_X14_16_hex@@\x00\x14"@@if_ts_show_f7_presets
 
 cmd_set_wideband_idx_0       = "@@TS_IO_TEST_COMMAND_char@@\x00\x15\x00\x00"
 cmd_set_wideband_idx_1       = "@@TS_IO_TEST_COMMAND_char@@\x00\x15\x00\x01"
@@ -3476,6 +3477,7 @@ cmd_set_engine_type_default					= "@@TS_IO_TEST_COMMAND_char@@\x00\x31\x00\x00"
 		commandButton = "Write Config", cmd_write_config          
 		commandButton = "Reset ECU", cmd_reset_controller
 		commandButton = "Reset to DFU", cmd_dfu
+		commandButton = "F7 nDBANK fix", cmd_nDBANK@@if_ts_show_f7_presets
 
 	; bench test	
 	dialog = ioTest, "Bench Test & Commands", xAxis