auto-sync
This commit is contained in:
rusEfi
parent
b99fe9345e
commit
d1ac9add2e
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@ -0,0 +1,24 @@
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Cmp-Mod V01 Created by CvPcb (2013-07-07 BZR 4022)-stable date = 06/12/2014 09:24:36
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BeginCmp
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TimeStamp = /54830CC1;
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Reference = P1;
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ValeurCmp = CONN_4;
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IdModule = SIL-4;
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EndCmp
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BeginCmp
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TimeStamp = /54830CCE;
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Reference = P2;
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ValeurCmp = CONN_4;
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IdModule = SIL-4;
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EndCmp
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BeginCmp
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TimeStamp = /54830CB2;
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Reference = U1;
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ValeurCmp = XTR116U;
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IdModule = so-8;
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EndCmp
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EndListe
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@ -0,0 +1,236 @@
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(kicad_pcb (version 3) (host pcbnew "(2013-07-07 BZR 4022)-stable")
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||||
|
||||
(general
|
||||
(links 4)
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||||
(no_connects 4)
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||||
(area 94.907099 69.40169 106.641901 111.467901)
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||||
(thickness 1.6)
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||||
(drawings 0)
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||||
(tracks 0)
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||||
(zones 0)
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||||
(modules 3)
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||||
(nets 5)
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)
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(page A3)
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(layers
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(15 F.Cu signal)
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(0 B.Cu signal)
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||||
(16 B.Adhes user)
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||||
(17 F.Adhes user)
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||||
(18 B.Paste user)
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||||
(19 F.Paste user)
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||||
(20 B.SilkS user)
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||||
(21 F.SilkS user)
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||||
(22 B.Mask user)
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||||
(23 F.Mask user)
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||||
(24 Dwgs.User user)
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||||
(25 Cmts.User user)
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||||
(26 Eco1.User user)
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||||
(27 Eco2.User user)
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||||
(28 Edge.Cuts user)
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||||
)
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||||
|
||||
(setup
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||||
(last_trace_width 0.254)
|
||||
(trace_clearance 0.254)
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||||
(zone_clearance 0.508)
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||||
(zone_45_only no)
|
||||
(trace_min 0.254)
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||||
(segment_width 0.2)
|
||||
(edge_width 0.1)
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||||
(via_size 0.889)
|
||||
(via_drill 0.635)
|
||||
(via_min_size 0.889)
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||||
(via_min_drill 0.508)
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||||
(uvia_size 0.508)
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||||
(uvia_drill 0.127)
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||||
(uvias_allowed no)
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||||
(uvia_min_size 0.508)
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||||
(uvia_min_drill 0.127)
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||||
(pcb_text_width 0.3)
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||||
(pcb_text_size 1.5 1.5)
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||||
(mod_edge_width 0.15)
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||||
(mod_text_size 1 1)
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||||
(mod_text_width 0.15)
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||||
(pad_size 1.5 1.5)
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||||
(pad_drill 0.6)
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||||
(pad_to_mask_clearance 0)
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||||
(aux_axis_origin 0 0)
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||||
(visible_elements FFFFFBBF)
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||||
(pcbplotparams
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||||
(layerselection 3178497)
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||||
(usegerberextensions true)
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||||
(excludeedgelayer true)
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||||
(linewidth 0.150000)
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||||
(plotframeref false)
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||||
(viasonmask false)
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||||
(mode 1)
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||||
(useauxorigin false)
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||||
(hpglpennumber 1)
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||||
(hpglpenspeed 20)
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||||
(hpglpendiameter 15)
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||||
(hpglpenoverlay 2)
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||||
(psnegative false)
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||||
(psa4output false)
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||||
(plotreference true)
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||||
(plotvalue true)
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||||
(plotothertext true)
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||||
(plotinvisibletext false)
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||||
(padsonsilk false)
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||||
(subtractmaskfromsilk false)
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||||
(outputformat 1)
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||||
(mirror false)
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||||
(drillshape 1)
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||||
(scaleselection 1)
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||||
(outputdirectory ""))
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)
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||||
(net 0 "")
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||||
(net 1 N-000003)
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||||
(net 2 N-000006)
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||||
(net 3 N-000007)
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||||
(net 4 N-000008)
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||||
|
||||
(net_class Default "This is the default net class."
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||||
(clearance 0.254)
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||||
(trace_width 0.254)
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||||
(via_dia 0.889)
|
||||
(via_drill 0.635)
|
||||
(uvia_dia 0.508)
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||||
(uvia_drill 0.127)
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||||
(add_net "")
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(add_net N-000003)
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(add_net N-000006)
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(add_net N-000007)
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||||
(add_net N-000008)
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||||
)
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|
||||
(module so-8 (layer F.Cu) (tedit 48A6C16E) (tstamp 548311C3)
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(at 100.5205 87.884 180)
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(descr SO-8)
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(path /54830CB2)
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(attr smd)
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(fp_text reference U1 (at 0 -1.016 180) (layer F.SilkS)
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||||
(effects (font (size 0.7493 0.7493) (thickness 0.14986)))
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)
|
||||
(fp_text value XTR116U (at 0 1.016 180) (layer F.SilkS)
|
||||
(effects (font (size 0.7493 0.7493) (thickness 0.14986)))
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||||
)
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||||
(fp_line (start -2.413 -1.9812) (end -2.413 1.9812) (layer F.SilkS) (width 0.127))
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||||
(fp_line (start -2.413 1.9812) (end 2.413 1.9812) (layer F.SilkS) (width 0.127))
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||||
(fp_line (start 2.413 1.9812) (end 2.413 -1.9812) (layer F.SilkS) (width 0.127))
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||||
(fp_line (start 2.413 -1.9812) (end -2.413 -1.9812) (layer F.SilkS) (width 0.127))
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||||
(fp_line (start -1.905 -1.9812) (end -1.905 -3.0734) (layer F.SilkS) (width 0.127))
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||||
(fp_line (start -0.635 -1.9812) (end -0.635 -3.0734) (layer F.SilkS) (width 0.127))
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||||
(fp_line (start 0.635 -1.9812) (end 0.635 -3.0734) (layer F.SilkS) (width 0.127))
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||||
(fp_line (start 1.905 -3.0734) (end 1.905 -1.9812) (layer F.SilkS) (width 0.127))
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||||
(fp_line (start 1.905 1.9812) (end 1.905 3.0734) (layer F.SilkS) (width 0.127))
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||||
(fp_line (start 0.635 3.0734) (end 0.635 1.9812) (layer F.SilkS) (width 0.127))
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||||
(fp_line (start -0.635 3.0734) (end -0.635 1.9812) (layer F.SilkS) (width 0.127))
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||||
(fp_line (start -1.905 3.0734) (end -1.905 1.9812) (layer F.SilkS) (width 0.127))
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||||
(fp_circle (center -1.6764 1.2446) (end -1.9558 1.6256) (layer F.SilkS) (width 0.127))
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||||
(pad 1 smd rect (at -1.905 2.794 180) (size 0.635 1.27)
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||||
(layers F.Cu F.Paste F.Mask)
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||||
(net 4 N-000008)
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)
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||||
(pad 2 smd rect (at -0.635 2.794 180) (size 0.635 1.27)
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||||
(layers F.Cu F.Paste F.Mask)
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||||
(net 3 N-000007)
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||||
)
|
||||
(pad 3 smd rect (at 0.635 2.794 180) (size 0.635 1.27)
|
||||
(layers F.Cu F.Paste F.Mask)
|
||||
(net 2 N-000006)
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||||
)
|
||||
(pad 4 smd rect (at 1.905 2.794 180) (size 0.635 1.27)
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||||
(layers F.Cu F.Paste F.Mask)
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||||
)
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||||
(pad 5 smd rect (at 1.905 -2.794 180) (size 0.635 1.27)
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||||
(layers F.Cu F.Paste F.Mask)
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||||
)
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||||
(pad 6 smd rect (at 0.635 -2.794 180) (size 0.635 1.27)
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||||
(layers F.Cu F.Paste F.Mask)
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||||
(net 1 N-000003)
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||||
)
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||||
(pad 7 smd rect (at -0.635 -2.794 180) (size 0.635 1.27)
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||||
(layers F.Cu F.Paste F.Mask)
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||||
)
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||||
(pad 8 smd rect (at -1.905 -2.794 180) (size 0.635 1.27)
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||||
(layers F.Cu F.Paste F.Mask)
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||||
)
|
||||
(model smd/smd_dil/so-8.wrl
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||||
(at (xyz 0 0 0))
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||||
(scale (xyz 1 1 1))
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||||
(rotate (xyz 0 0 0))
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||||
)
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||||
)
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||||
|
||||
(module SIL-4 (layer F.Cu) (tedit 200000) (tstamp 548311D2)
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(at 100.33 75.565 180)
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||||
(descr "Connecteur 4 pibs")
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||||
(tags "CONN DEV")
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||||
(path /54830CC1)
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(fp_text reference P1 (at 0 -2.54 180) (layer F.SilkS)
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||||
(effects (font (size 1.73482 1.08712) (thickness 0.3048)))
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||||
)
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||||
(fp_text value CONN_4 (at 0 -2.54 180) (layer F.SilkS) hide
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||||
(effects (font (size 1.524 1.016) (thickness 0.3048)))
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||||
)
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||||
(fp_line (start -5.08 -1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.3048))
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||||
(fp_line (start -5.08 1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.3048))
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||||
(fp_line (start -5.08 -1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.3048))
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||||
(fp_line (start -5.08 -1.27) (end 5.08 -1.27) (layer F.SilkS) (width 0.3048))
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||||
(fp_line (start 5.08 -1.27) (end 5.08 1.27) (layer F.SilkS) (width 0.3048))
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||||
(fp_line (start 5.08 1.27) (end -5.08 1.27) (layer F.SilkS) (width 0.3048))
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||||
(fp_line (start -2.54 1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.3048))
|
||||
(pad 1 thru_hole rect (at -3.81 0 180) (size 1.397 1.397) (drill 0.8128)
|
||||
(layers *.Cu *.Mask F.SilkS)
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||||
(net 4 N-000008)
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||||
)
|
||||
(pad 2 thru_hole circle (at -1.27 0 180) (size 1.397 1.397) (drill 0.8128)
|
||||
(layers *.Cu *.Mask F.SilkS)
|
||||
(net 3 N-000007)
|
||||
)
|
||||
(pad 3 thru_hole circle (at 1.27 0 180) (size 1.397 1.397) (drill 0.8128)
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||||
(layers *.Cu *.Mask F.SilkS)
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||||
(net 2 N-000006)
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||||
)
|
||||
(pad 4 thru_hole circle (at 3.81 0 180) (size 1.397 1.397) (drill 0.8128)
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||||
(layers *.Cu *.Mask F.SilkS)
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||||
)
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||||
)
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||||
|
||||
(module SIL-4 (layer F.Cu) (tedit 200000) (tstamp 548311E1)
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||||
(at 100.838 98.6155)
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||||
(descr "Connecteur 4 pibs")
|
||||
(tags "CONN DEV")
|
||||
(path /54830CCE)
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||||
(fp_text reference P2 (at 0 -2.54) (layer F.SilkS)
|
||||
(effects (font (size 1.73482 1.08712) (thickness 0.3048)))
|
||||
)
|
||||
(fp_text value CONN_4 (at 0 -2.54) (layer F.SilkS) hide
|
||||
(effects (font (size 1.524 1.016) (thickness 0.3048)))
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||||
)
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||||
(fp_line (start -5.08 -1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.3048))
|
||||
(fp_line (start -5.08 1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.3048))
|
||||
(fp_line (start -5.08 -1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.3048))
|
||||
(fp_line (start -5.08 -1.27) (end 5.08 -1.27) (layer F.SilkS) (width 0.3048))
|
||||
(fp_line (start 5.08 -1.27) (end 5.08 1.27) (layer F.SilkS) (width 0.3048))
|
||||
(fp_line (start 5.08 1.27) (end -5.08 1.27) (layer F.SilkS) (width 0.3048))
|
||||
(fp_line (start -2.54 1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.3048))
|
||||
(pad 1 thru_hole rect (at -3.81 0) (size 1.397 1.397) (drill 0.8128)
|
||||
(layers *.Cu *.Mask F.SilkS)
|
||||
)
|
||||
(pad 2 thru_hole circle (at -1.27 0) (size 1.397 1.397) (drill 0.8128)
|
||||
(layers *.Cu *.Mask F.SilkS)
|
||||
(net 1 N-000003)
|
||||
)
|
||||
(pad 3 thru_hole circle (at 1.27 0) (size 1.397 1.397) (drill 0.8128)
|
||||
(layers *.Cu *.Mask F.SilkS)
|
||||
)
|
||||
(pad 4 thru_hole circle (at 3.81 0) (size 1.397 1.397) (drill 0.8128)
|
||||
(layers *.Cu *.Mask F.SilkS)
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||||
)
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||||
)
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||||
|
||||
)
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@ -0,0 +1,81 @@
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(export (version D)
|
||||
(design
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||||
(source F:/stuff/rusefi_sourceforge/hardware/soic8_breakout/soic8_breakout.sch)
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||||
(date "06/12/2014 09:06:30")
|
||||
(tool "eeschema (2013-07-07 BZR 4022)-stable"))
|
||||
(components
|
||||
(comp (ref P1)
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||||
(value CONN_4)
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(libsource (lib conn) (part CONN_4))
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(sheetpath (names /) (tstamps /))
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||||
(tstamp 54830CC1))
|
||||
(comp (ref P2)
|
||||
(value CONN_4)
|
||||
(libsource (lib conn) (part CONN_4))
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||||
(sheetpath (names /) (tstamps /))
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||||
(tstamp 54830CCE))
|
||||
(comp (ref U1)
|
||||
(value XTR116U)
|
||||
(libsource (lib interface) (part XTR116U))
|
||||
(sheetpath (names /) (tstamps /))
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||||
(tstamp 54830CB2)))
|
||||
(libparts
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||||
(libpart (lib conn) (part CONN_4)
|
||||
(description "Symbole general de connecteur")
|
||||
(fields
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||||
(field (name Reference) P)
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||||
(field (name Value) CONN_4))
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||||
(pins
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||||
(pin (num 1) (name P1) (type passive))
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||||
(pin (num 2) (name P2) (type passive))
|
||||
(pin (num 3) (name P3) (type passive))
|
||||
(pin (num 4) (name P4) (type passive))))
|
||||
(libpart (lib interface) (part XTR115U)
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||||
(description "XTR115U, 4-20mA Current Loop Transmitter, SO8")
|
||||
(docs http://www.ti.com/lit/ds/symlink/xtr115.pdf)
|
||||
(fields
|
||||
(field (name Reference) U)
|
||||
(field (name Value) XTR115U))
|
||||
(pins
|
||||
(pin (num 1) (name Vref) (type output))
|
||||
(pin (num 2) (name Iin) (type input))
|
||||
(pin (num 3) (name Iret) (type input))
|
||||
(pin (num 4) (name Io) (type output))
|
||||
(pin (num 5) (name E) (type passive))
|
||||
(pin (num 6) (name B) (type passive))
|
||||
(pin (num 7) (name V+) (type input))
|
||||
(pin (num 8) (name Vreg) (type output)))))
|
||||
(libraries
|
||||
(library (logical conn)
|
||||
(uri "C:\\Program Files (x86)\\KiCad\\share\\library\\conn.lib"))
|
||||
(library (logical interface)
|
||||
(uri "C:\\Program Files (x86)\\KiCad\\share\\library\\interface.lib")))
|
||||
(nets
|
||||
(net (code 1) (name "")
|
||||
(node (ref U1) (pin 8)))
|
||||
(net (code 2) (name "")
|
||||
(node (ref U1) (pin 7)))
|
||||
(net (code 3) (name "")
|
||||
(node (ref U1) (pin 6))
|
||||
(node (ref P2) (pin 2)))
|
||||
(net (code 4) (name "")
|
||||
(node (ref U1) (pin 5)))
|
||||
(net (code 5) (name "")
|
||||
(node (ref U1) (pin 4)))
|
||||
(net (code 6) (name "")
|
||||
(node (ref U1) (pin 3))
|
||||
(node (ref P1) (pin 3)))
|
||||
(net (code 7) (name "")
|
||||
(node (ref P1) (pin 2))
|
||||
(node (ref U1) (pin 2)))
|
||||
(net (code 8) (name "")
|
||||
(node (ref P1) (pin 1))
|
||||
(node (ref U1) (pin 1)))
|
||||
(net (code 9) (name "")
|
||||
(node (ref P2) (pin 1)))
|
||||
(net (code 10) (name "")
|
||||
(node (ref P2) (pin 4)))
|
||||
(net (code 11) (name "")
|
||||
(node (ref P2) (pin 3)))
|
||||
(net (code 12) (name "")
|
||||
(node (ref P1) (pin 4)))))
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
update=06/12/2014 09:01:53
|
||||
version=1
|
||||
last_client=kicad
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[cvpcb/libraries]
|
||||
EquName1=devcms
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
NetFmtName=
|
||||
RptD_X=0
|
||||
RptD_Y=100
|
||||
RptLab=1
|
||||
LabSize=60
|
||||
[eeschema/libraries]
|
||||
LibName1=power
|
||||
LibName2=device
|
||||
LibName3=transistors
|
||||
LibName4=conn
|
||||
LibName5=linear
|
||||
LibName6=regul
|
||||
LibName7=74xx
|
||||
LibName8=cmos4000
|
||||
LibName9=adc-dac
|
||||
LibName10=memory
|
||||
LibName11=xilinx
|
||||
LibName12=special
|
||||
LibName13=microcontrollers
|
||||
LibName14=dsp
|
||||
LibName15=microchip
|
||||
LibName16=analog_switches
|
||||
LibName17=motorola
|
||||
LibName18=texas
|
||||
LibName19=intel
|
||||
LibName20=audio
|
||||
LibName21=interface
|
||||
LibName22=digital-audio
|
||||
LibName23=philips
|
||||
LibName24=display
|
||||
LibName25=cypress
|
||||
LibName26=siliconi
|
||||
LibName27=opto
|
||||
LibName28=atmel
|
||||
LibName29=contrib
|
||||
LibName30=valves
|
||||
[pcbnew]
|
||||
version=1
|
||||
LastNetListRead=
|
||||
UseCmpFile=1
|
||||
PadDrill=0.600000000000
|
||||
PadDrillOvalY=0.600000000000
|
||||
PadSizeH=1.500000000000
|
||||
PadSizeV=1.500000000000
|
||||
PcbTextSizeV=1.500000000000
|
||||
PcbTextSizeH=1.500000000000
|
||||
PcbTextThickness=0.300000000000
|
||||
ModuleTextSizeV=1.000000000000
|
||||
ModuleTextSizeH=1.000000000000
|
||||
ModuleTextSizeThickness=0.150000000000
|
||||
SolderMaskClearance=0.000000000000
|
||||
SolderMaskMinWidth=0.000000000000
|
||||
DrawSegmentWidth=0.200000000000
|
||||
BoardOutlineThickness=0.100000000000
|
||||
ModuleOutlineThickness=0.150000000000
|
||||
[pcbnew/libraries]
|
||||
LibDir=
|
||||
LibName1=sockets
|
||||
LibName2=connect
|
||||
LibName3=discret
|
||||
LibName4=pin_array
|
||||
LibName5=divers
|
||||
LibName6=smd_capacitors
|
||||
LibName7=smd_resistors
|
||||
LibName8=smd_crystal&oscillator
|
||||
LibName9=smd_dil
|
||||
LibName10=smd_transistors
|
||||
LibName11=libcms
|
||||
LibName12=display
|
||||
LibName13=led
|
||||
LibName14=dip_sockets
|
||||
LibName15=pga_sockets
|
||||
LibName16=valves
|
||||
[general]
|
||||
version=1
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
EESchema Schematic File Version 2
|
||||
LIBS:power
|
||||
LIBS:device
|
||||
LIBS:transistors
|
||||
LIBS:conn
|
||||
LIBS:linear
|
||||
LIBS:regul
|
||||
LIBS:74xx
|
||||
LIBS:cmos4000
|
||||
LIBS:adc-dac
|
||||
LIBS:memory
|
||||
LIBS:xilinx
|
||||
LIBS:special
|
||||
LIBS:microcontrollers
|
||||
LIBS:dsp
|
||||
LIBS:microchip
|
||||
LIBS:analog_switches
|
||||
LIBS:motorola
|
||||
LIBS:texas
|
||||
LIBS:intel
|
||||
LIBS:audio
|
||||
LIBS:interface
|
||||
LIBS:digital-audio
|
||||
LIBS:philips
|
||||
LIBS:display
|
||||
LIBS:cypress
|
||||
LIBS:siliconi
|
||||
LIBS:opto
|
||||
LIBS:atmel
|
||||
LIBS:contrib
|
||||
LIBS:valves
|
||||
EELAYER 27 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 1 1
|
||||
Title ""
|
||||
Date "6 dec 2014"
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Comp
|
||||
L CONN_4 P1
|
||||
U 1 1 54830CC1
|
||||
P 3500 3450
|
||||
F 0 "P1" V 3450 3450 50 0000 C CNN
|
||||
F 1 "CONN_4" V 3550 3450 50 0000 C CNN
|
||||
F 2 "" H 3500 3450 60 0000 C CNN
|
||||
F 3 "" H 3500 3450 60 0000 C CNN
|
||||
1 3500 3450
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L CONN_4 P2
|
||||
U 1 1 54830CCE
|
||||
P 6000 3200
|
||||
F 0 "P2" V 5950 3200 50 0000 C CNN
|
||||
F 1 "CONN_4" V 6050 3200 50 0000 C CNN
|
||||
F 2 "" H 6000 3200 60 0000 C CNN
|
||||
F 3 "" H 6000 3200 60 0000 C CNN
|
||||
1 6000 3200
|
||||
1 0 0 1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5250 3400 5650 3400
|
||||
Wire Wire Line
|
||||
5650 3400 5650 3350
|
||||
Wire Wire Line
|
||||
5650 3250 5200 3250
|
||||
Wire Wire Line
|
||||
5200 3250 5200 3200
|
||||
Wire Wire Line
|
||||
3850 3400 4400 3400
|
||||
Wire Wire Line
|
||||
3850 3300 4400 3300
|
||||
Wire Wire Line
|
||||
4400 3300 4400 3150
|
||||
Wire Wire Line
|
||||
3850 3500 4150 3500
|
||||
Wire Wire Line
|
||||
4150 3500 4150 3700
|
||||
Wire Wire Line
|
||||
4150 3700 4400 3700
|
||||
$Comp
|
||||
L XTR116U U1
|
||||
U 1 1 54830CB2
|
||||
P 4800 3350
|
||||
F 0 "U1" H 4600 3800 50 0000 C CNN
|
||||
F 1 "XTR116U" H 4700 2900 50 0000 C CNN
|
||||
F 2 "" H 4800 3350 60 0000 C CNN
|
||||
F 3 "" H 4800 3350 60 0000 C CNN
|
||||
1 4800 3350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$EndSCHEMATC
|
||||
Loading…
Reference in New Issue