1427 lines
92 KiB
Plaintext
1427 lines
92 KiB
Plaintext
(kicad_pcb (version 3) (host pcbnew "(2013-07-07 BZR 4022)-stable")
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(general
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(links 37)
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(no_connects 0)
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(area 206.959287 137.16 256.540001 162.941423)
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(thickness 1.6)
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(drawings 15)
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(tracks 210)
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(zones 0)
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(modules 18)
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(nets 13)
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)
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(page A)
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(title_block
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(title "PowerSSO-24 breakout")
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(rev R0.1)
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(company rusEFI)
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)
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(layers
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(15 F.Cu signal)
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(0 B.Cu signal)
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(16 B.Adhes user)
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(17 F.Adhes user)
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(18 B.Paste user)
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(19 F.Paste user)
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(20 B.SilkS user)
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(21 F.SilkS user)
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(22 B.Mask user)
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(23 F.Mask user)
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(24 Dwgs.User user)
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(25 Cmts.User user)
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(26 Eco1.User user)
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(27 Eco2.User user)
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(28 Edge.Cuts user)
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)
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(setup
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(last_trace_width 0.3048)
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(trace_clearance 0.24892)
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(zone_clearance 0.254)
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(zone_45_only no)
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(trace_min 0.254)
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(segment_width 0.2)
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(edge_width 0.1)
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(via_size 0.889)
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(via_drill 0.635)
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(via_min_size 0.889)
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(via_min_drill 0.508)
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(user_via 0.889 0.635)
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(user_via 1.54178 1.18618)
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(uvia_size 0.508)
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(uvia_drill 0.127)
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(uvias_allowed no)
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(uvia_min_size 0.508)
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(uvia_min_drill 0.127)
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(pcb_text_width 0.3)
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(pcb_text_size 1.5 1.5)
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(mod_edge_width 0.15)
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(mod_text_size 1 1)
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(mod_text_width 0.15)
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(pad_size 1.524 1.524)
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(pad_drill 1.016)
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(pad_to_mask_clearance 0)
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(aux_axis_origin 0 0)
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(visible_elements 7FFFFB3F)
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(pcbplotparams
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(layerselection 3178497)
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(usegerberextensions true)
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(excludeedgelayer true)
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(linewidth 0.150000)
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(plotframeref false)
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(viasonmask false)
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(mode 1)
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(useauxorigin false)
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(hpglpennumber 1)
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(hpglpenspeed 20)
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(hpglpendiameter 15)
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(hpglpenoverlay 2)
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(psnegative false)
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(psa4output false)
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(plotreference true)
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(plotvalue true)
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(plotothertext true)
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(plotinvisibletext false)
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(padsonsilk false)
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(subtractmaskfromsilk false)
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(outputformat 1)
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(mirror false)
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(drillshape 0)
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(scaleselection 1)
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(outputdirectory ""))
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)
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(net 0 "")
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(net 1 /CS_DIS)
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(net 2 /I1)
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(net 3 /I2)
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(net 4 /IN1)
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(net 5 /IN2)
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(net 6 /O1)
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(net 7 /O2)
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(net 8 /VCC)
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(net 9 GND)
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(net 10 N-000001)
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(net 11 N-000004)
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(net 12 N-000005)
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(net_class Default "This is the default net class."
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(clearance 0.24892)
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(via_drill 0.635)
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(uvia_dia 0.508)
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(uvia_drill 0.127)
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(add_net "")
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(add_net /CS_DIS)
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(add_net /I1)
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(add_net /I2)
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(add_net /IN1)
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(add_net /IN2)
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(add_net /O1)
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(add_net /O2)
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(add_net /VCC)
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(add_net GND)
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(add_net N-000001)
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(add_net N-000004)
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(add_net N-000005)
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)
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(net_class FAT ""
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(clearance 1.7526)
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(trace_width 2.54)
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(via_dia 0.889)
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(via_drill 0.635)
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(uvia_dia 0.508)
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(uvia_drill 0.127)
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)
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(net_class MIN ""
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(clearance 2.54)
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(trace_width 0.3048)
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(via_dia 0.889)
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(via_drill 0.635)
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(uvia_dia 0.508)
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(uvia_drill 0.127)
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)
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(module SIL-1 (layer B.Cu) (tedit 54A88DBF) (tstamp 54A84B00)
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(at 217.17 151.13)
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(descr "Connecteurs 1 pin")
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(tags "CONN DEV")
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(path /54A83628)
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(fp_text value CONN_1 (at 0 2.54) (layer B.SilkS) hide
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(pad 1 thru_hole rect (at 0 0) (size 1.524 1.524) (drill 1.016)
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(layers *.Cu *.Mask B.SilkS)
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(net 11 N-000004)
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)
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)
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(module SIL-1 (layer B.Cu) (tedit 54A88DB3) (tstamp 54A84B12)
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(at 217.17 156.21)
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(descr "Connecteurs 1 pin")
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(tags "CONN DEV")
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(path /54A83634)
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(fp_text reference P106 (at 2.921 0) (layer B.SilkS)
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(effects (font (size 0.762 0.762) (thickness 0.127)) (justify mirror))
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(fp_text value CONN_1 (at 0 2.54) (layer B.SilkS) hide
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(effects (font (size 1.524 1.016) (thickness 0.254)) (justify mirror))
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(fp_line (start -1.27 -1.27) (end 1.27 -1.27) (layer B.SilkS) (width 0.3175))
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(fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer B.SilkS) (width 0.3048))
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(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer B.SilkS) (width 0.3048))
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(pad 1 thru_hole rect (at 0 0) (size 1.524 1.524) (drill 1.016)
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(layers *.Cu *.Mask B.SilkS)
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(net 1 /CS_DIS)
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)
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)
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(module SIL-1 (layer B.Cu) (tedit 54A88DD5) (tstamp 54A84B24)
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(at 217.17 143.51)
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(descr "Connecteurs 1 pin")
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(tags "CONN DEV")
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(path /544A1CD8)
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(pad 1 thru_hole rect (at 0 0) (size 1.524 1.524) (drill 1.016)
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(layers *.Cu *.Mask B.SilkS)
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(net 10 N-000001)
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)
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)
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(module SIL-1 (layer B.Cu) (tedit 54A88DCA) (tstamp 54A84B2D)
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(at 217.17 146.05)
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(descr "Connecteurs 1 pin")
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(tags "CONN DEV")
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(path /544A1CBF)
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(fp_text reference P102 (at 2.921 0) (layer B.SilkS)
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(effects (font (size 0.762 0.762) (thickness 0.127)) (justify mirror))
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(fp_text value CONN_1 (at 0 2.54) (layer B.SilkS) hide
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(fp_line (start -1.27 -1.27) (end 1.27 -1.27) (layer B.SilkS) (width 0.3175))
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(fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer B.SilkS) (width 0.3048))
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(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer B.SilkS) (width 0.3048))
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(pad 1 thru_hole rect (at 0 0) (size 1.524 1.524) (drill 1.016)
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(layers *.Cu *.Mask B.SilkS)
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(net 12 N-000005)
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)
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)
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(module "DO-214AA(SMB)" (layer F.Cu) (tedit 54A88491) (tstamp 54A8B128)
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(at 238.76 146.812 270)
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(descr "DO-214AA (SMB) PACKAGE.")
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(tags "DO-214AA SMB")
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(path /54A84930)
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(attr smd)
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(fp_text reference D102 (at 3.429 -1.143 360) (layer F.SilkS)
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(net 9 GND)
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)
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(pad 2 smd rect (at 2.0066 0 270) (size 1.80086 2.19964)
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(layers F.Cu F.Paste F.Mask)
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(net 7 /O2)
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(model smd/do214.wrl
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(at (xyz 0 0 0))
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(scale (xyz 1 1 1))
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(rotate (xyz 0 0 0))
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(module "DO-214AA(SMB)" (layer F.Cu) (tedit 54A8848B) (tstamp 54A8B140)
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(at 238.76 153.67 90)
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(descr "DO-214AA (SMB) PACKAGE.")
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(tags "DO-214AA SMB")
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(path /54A84995)
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(attr smd)
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(layers F.Cu F.Paste F.Mask)
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(net 9 GND)
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(pad 2 smd rect (at 2.0066 0 90) (size 1.80086 2.19964)
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(layers F.Cu F.Paste F.Mask)
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(net 6 /O1)
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(model smd/do214.wrl
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(module "DO-214AA(SMB)" (layer F.Cu) (tedit 54A880EB) (tstamp 54A8B158)
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(at 229.362 142.367)
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(descr "DO-214AA (SMB) PACKAGE.")
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(tags "DO-214AA SMB")
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(module SM0805 (layer F.Cu) (tedit 54A87E7A) (tstamp 54A84A4D)
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(at 219.71 143.51)
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(module SM0805 (layer F.Cu) (tedit 54A87E82) (tstamp 54A84A91)
|
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(module SM0805 (layer F.Cu) (tedit 54A87E8E) (tstamp 54A84AB3)
|
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|
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(model smd/chip_cms.wrl
|
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(module SM0805 (layer F.Cu) (tedit 54A87E8B) (tstamp 54A84AC4)
|
|
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|
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(path /54A835C6)
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|
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(model smd/chip_cms.wrl
|
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(module SM0805 (layer F.Cu) (tedit 54A87E88) (tstamp 54A84AD5)
|
|
(at 222.885 151.13 270)
|
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(path /54A835C0)
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(module SM0805 (layer F.Cu) (tedit 54A87E7F) (tstamp 54A84AE6)
|
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