50 lines
1.2 KiB
C
50 lines
1.2 KiB
C
/*
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* @file smart_gpio.h
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*
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* @date Apr 13, 2019
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* @author Andrey Belomutskiy, (c) 2012-2019
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*/
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#ifndef HW_LAYER_SMART_GPIO_H_
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#define HW_LAYER_SMART_GPIO_H_
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/* TLE6240 pins go right after on chips */
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#define TLE6240_PIN(n) ((brain_pin_e)((int)BRAIN_PIN_LAST_ONCHIP + 1 + (n)))
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/* MC33972 pins go right after TLE6240 */
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#define MC33972_PIN(n) ((brain_pin_e)((int)BRAIN_PIN_LAST_ONCHIP + 1 + 16 + (n)))
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void initSmartGpio(void);
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#if (defined(STM32F405xx) || defined(STM32F407xx) || defined (STM32F469xx))
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#define STM_F4_FAMILY
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#elif (defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F746xx))
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#define STM_F7_FAMILY
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#else
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unexpected platform
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#endif
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#if (BOARD_EXT_GPIOCHIPS > 0)
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#if defined(STM_F4_FAMILY)
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#define SPI_CR1_16BIT_MODE SPI_CR1_DFF
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#define SPI_CR2_16BIT_MODE 0
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// TODO
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#define SPI_CR1_24BIT_MODE 0
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#define SPI_CR2_24BIT_MODE 0
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#elif defined(STM_F7_FAMILY)
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#define SPI_CR1_16BIT_MODE 0
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#define SPI_CR2_16BIT_MODE SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
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#define SPI_CR1_24BIT_MODE 0
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/* 3 x 8-bit transfer */
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#define SPI_CR2_24BIT_MODE SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
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#else
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unexpected platform
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#endif
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#endif /* (BOARD_EXT_GPIOCHIPS > 0) */
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#endif /* HW_LAYER_SMART_GPIO_H_ */
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