648 lines
15 KiB
Plaintext
648 lines
15 KiB
Plaintext
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{
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"board": {
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.127,
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"copper_line_width": 0.127,
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"copper_text_italic": false,
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"copper_text_size_h": 1.016,
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"copper_text_size_v": 1.016,
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"copper_text_thickness": 0.127,
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"copper_text_upright": false,
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"courtyard_line_width": 0.049999999999999996,
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"dimension_precision": 4,
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"dimension_units": 3,
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"dimensions": {
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"arrow_length": 1270000,
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"extension_offset": 500000,
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"keep_text_aligned": true,
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"suppress_zeroes": false,
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"text_position": 0,
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"units_format": 1
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},
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"fab_line_width": 0.09999999999999999,
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"fab_text_italic": false,
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"fab_text_size_h": 1.0,
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"fab_text_size_v": 1.0,
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"fab_text_thickness": 0.15,
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"fab_text_upright": false,
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"other_line_width": 0.09999999999999999,
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"other_text_italic": false,
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"other_text_size_h": 1.0,
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"other_text_size_v": 1.0,
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"other_text_thickness": 0.15,
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"other_text_upright": false,
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"pads": {
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"drill": 1.27,
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"height": 1.99898,
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"width": 1.99898
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},
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"silk_line_width": 0.254,
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"silk_text_italic": false,
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"silk_text_size_h": 0.508,
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"silk_text_size_v": 0.508,
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"silk_text_thickness": 0.127,
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"silk_text_upright": false,
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"zones": {
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"45_degree_only": false,
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"min_clearance": 0.17779999999999999
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}
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},
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"diff_pair_dimensions": [],
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"drc_exclusions": [],
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"meta": {
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"filename": "board_design_settings.json",
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"version": 2
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},
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"rule_severities": {
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"annular_width": "error",
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"clearance": "error",
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"copper_edge_clearance": "error",
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"courtyards_overlap": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"footprint_type_mismatch": "error",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"invalid_outline": "error",
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"item_on_disabled_layer": "error",
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"items_not_allowed": "error",
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"length_out_of_range": "error",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"net_conflict": "warning",
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"npth_inside_courtyard": "ignore",
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"padstack": "error",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"silk_over_copper": "warning",
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"silk_overlap": "warning",
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"skew_out_of_range": "error",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"track_dangling": "warning",
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"track_width": "error",
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"tracks_crossing": "error",
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"unconnected_items": "error",
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"unresolved_variable": "error",
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"via_dangling": "warning",
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"zone_has_empty_net": "error",
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"zones_intersect": "error"
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},
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"rule_severitieslegacy_courtyards_overlap": true,
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"rule_severitieslegacy_no_courtyard_defined": false,
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"rules": {
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"allow_blind_buried_vias": false,
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"allow_microvias": false,
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"max_error": 0.005,
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"min_clearance": 0.0,
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"min_copper_edge_clearance": 0.0635,
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"min_hole_clearance": 0.25,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.508,
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"min_microvia_drill": 0.127,
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"min_silk_clearance": 0.0,
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"min_through_hole_diameter": 0.3302,
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"min_track_width": 0.15239999999999998,
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"min_via_annular_width": 0.049999999999999996,
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"min_via_diameter": 0.39999999999999997,
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"use_height_for_length_calcs": true
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},
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"track_widths": [
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0.0,
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0.1524,
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0.2159,
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0.3048,
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1.0668,
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1.651,
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1.6764,
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2.7178
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],
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"via_dimensions": [
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{
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"diameter": 0.0,
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"drill": 0.0
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},
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{
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"diameter": 0.6858,
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"drill": 0.3302
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},
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{
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"diameter": 0.78994,
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"drill": 0.43434
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},
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{
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"diameter": 1.54178,
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"drill": 1.18618
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}
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],
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"zones_allow_external_fillets": false,
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"zones_use_no_outline": true
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},
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"layer_presets": []
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},
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"boards": [],
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"cvpcb": {
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"equivalence_files": []
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},
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"erc": {
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"erc_exclusions": [],
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"meta": {
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"version": 0
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},
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"pin_map": [
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],
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"rule_severities": {
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"bus_definition_conflict": "error",
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"bus_entry_needed": "error",
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"bus_label_syntax": "error",
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"bus_to_bus_conflict": "error",
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"bus_to_net_conflict": "error",
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"different_unit_footprint": "error",
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"different_unit_net": "error",
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"duplicate_reference": "error",
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"duplicate_sheet_names": "error",
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"extra_units": "error",
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"global_label_dangling": "warning",
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"hier_label_mismatch": "error",
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"label_dangling": "error",
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"lib_symbol_issues": "warning",
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"multiple_net_names": "warning",
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"net_not_bus_member": "warning",
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"no_connect_connected": "warning",
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"no_connect_dangling": "warning",
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"pin_not_connected": "error",
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"pin_not_driven": "error",
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"pin_to_pin": "warning",
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"power_pin_not_driven": "error",
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"similar_labels": "warning",
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"unannotated": "error",
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"unit_value_mismatch": "error",
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"unresolved_variable": "error",
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"wire_dangling": "error"
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}
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},
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"libraries": {
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"pinned_footprint_libs": [],
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||
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"pinned_symbol_libs": []
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},
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"meta": {
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||
|
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"filename": "GDI-4ch.kicad_pro",
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|
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"version": 1
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},
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"net_settings": {
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||
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"classes": [
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{
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"bus_width": 12.0,
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"clearance": 0.1524,
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||
|
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"diff_pair_gap": 0.25,
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||
|
|
"diff_pair_via_gap": 0.25,
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||
|
|
"diff_pair_width": 0.2,
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||
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"line_style": 0,
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||
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"microvia_diameter": 0.508,
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||
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"microvia_drill": 0.127,
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||
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"name": "Default",
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||
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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||
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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||
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|
"track_width": 0.1524,
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||
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|
"via_diameter": 0.6858,
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||
|
|
"via_drill": 0.3302,
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||
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|
"wire_width": 6.0
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||
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},
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||
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{
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||
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"bus_width": 12.0,
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||
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"clearance": 0.1778,
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||
|
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"diff_pair_gap": 0.25,
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||
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"diff_pair_via_gap": 0.25,
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||
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"diff_pair_width": 0.2,
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||
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"line_style": 0,
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||
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"microvia_diameter": 0.508,
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||
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"microvia_drill": 0.127,
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||
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"name": "1A_external",
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"nets": [
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"/3.3V",
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"/5V",
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"/CLK",
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||
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"/CSB",
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"/DBG_EXT1",
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||
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"/DBG_EXT2",
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||
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"/DRVEN",
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||
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"/EXT_CLK",
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||
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"/FLAG_0",
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||
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"/FLAG_1",
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||
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"/FLAG_2",
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||
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"/IRQB",
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||
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"/MISO",
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||
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"/MOSI",
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||
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"/OA_1",
|
||
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"/OA_2",
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||
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"/RESETB",
|
||
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"/SCLK",
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||
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|
"/START1",
|
||
|
|
"/START2",
|
||
|
|
"/START3",
|
||
|
|
"/START4",
|
||
|
|
"/START5",
|
||
|
|
"/START6",
|
||
|
|
"/VBAT_EXT",
|
||
|
|
"/VCCP",
|
||
|
|
"/Vbat",
|
||
|
|
"GND",
|
||
|
|
"Net-(C23-Pad1)",
|
||
|
|
"Net-(C24-Pad1)",
|
||
|
|
"Net-(C26-Pad2)",
|
||
|
|
"Net-(C39-Pad1)",
|
||
|
|
"Net-(C55-Pad2)",
|
||
|
|
"Net-(C63-Pad1)",
|
||
|
|
"Net-(C64-Pad2)",
|
||
|
|
"Net-(C71-Pad2)",
|
||
|
|
"Net-(D1-Pad2)",
|
||
|
|
"Net-(D18-Pad2)",
|
||
|
|
"Net-(D19-Pad2)",
|
||
|
|
"Net-(D2-Pad2)",
|
||
|
|
"Net-(D20-Pad2)",
|
||
|
|
"Net-(D21-Pad2)",
|
||
|
|
"Net-(D22-Pad2)",
|
||
|
|
"Net-(D23-Pad2)",
|
||
|
|
"Net-(D24-Pad2)",
|
||
|
|
"Net-(D25-Pad2)",
|
||
|
|
"Net-(D26-Pad2)",
|
||
|
|
"Net-(D27-Pad2)",
|
||
|
|
"Net-(D29-Pad2)",
|
||
|
|
"Net-(D3-Pad2)",
|
||
|
|
"Net-(D4-Pad2)",
|
||
|
|
"Net-(D5-Pad2)",
|
||
|
|
"Net-(D6-Pad2)",
|
||
|
|
"Net-(D7-Pad2)",
|
||
|
|
"Net-(D8-Pad2)"
|
||
|
|
],
|
||
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||
|
|
"track_width": 0.3048,
|
||
|
|
"via_diameter": 0.6858,
|
||
|
|
"via_drill": 0.3302,
|
||
|
|
"wire_width": 6.0
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"bus_width": 12.0,
|
||
|
|
"clearance": 0.2159,
|
||
|
|
"diff_pair_gap": 0.25,
|
||
|
|
"diff_pair_via_gap": 0.25,
|
||
|
|
"diff_pair_width": 0.2,
|
||
|
|
"line_style": 0,
|
||
|
|
"microvia_diameter": 0.508,
|
||
|
|
"microvia_drill": 0.127,
|
||
|
|
"name": "2.5A_external",
|
||
|
|
"nets": [],
|
||
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||
|
|
"track_width": 1.0668,
|
||
|
|
"via_diameter": 0.6858,
|
||
|
|
"via_drill": 0.3302,
|
||
|
|
"wire_width": 6.0
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"bus_width": 12.0,
|
||
|
|
"clearance": 0.2159,
|
||
|
|
"diff_pair_gap": 0.25,
|
||
|
|
"diff_pair_via_gap": 0.25,
|
||
|
|
"diff_pair_width": 0.2,
|
||
|
|
"line_style": 0,
|
||
|
|
"microvia_diameter": 0.508,
|
||
|
|
"microvia_drill": 0.127,
|
||
|
|
"name": "3.5A_external",
|
||
|
|
"nets": [],
|
||
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||
|
|
"track_width": 1.651,
|
||
|
|
"via_diameter": 1.0922,
|
||
|
|
"via_drill": 0.6858,
|
||
|
|
"wire_width": 6.0
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"bus_width": 12.0,
|
||
|
|
"clearance": 1.016,
|
||
|
|
"diff_pair_gap": 0.25,
|
||
|
|
"diff_pair_via_gap": 0.25,
|
||
|
|
"diff_pair_width": 0.2,
|
||
|
|
"line_style": 0,
|
||
|
|
"microvia_diameter": 0.508,
|
||
|
|
"microvia_drill": 0.127,
|
||
|
|
"name": "3.5A_external_high_voltage",
|
||
|
|
"nets": [],
|
||
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||
|
|
"track_width": 1.6764,
|
||
|
|
"via_diameter": 0.6858,
|
||
|
|
"via_drill": 0.3302,
|
||
|
|
"wire_width": 6.0
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"bus_width": 12.0,
|
||
|
|
"clearance": 0.2159,
|
||
|
|
"diff_pair_gap": 0.25,
|
||
|
|
"diff_pair_via_gap": 0.25,
|
||
|
|
"diff_pair_width": 0.2,
|
||
|
|
"line_style": 0,
|
||
|
|
"microvia_diameter": 0.508,
|
||
|
|
"microvia_drill": 0.127,
|
||
|
|
"name": "5A_external",
|
||
|
|
"nets": [],
|
||
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||
|
|
"track_width": 2.7178,
|
||
|
|
"via_diameter": 1.54178,
|
||
|
|
"via_drill": 1.18618,
|
||
|
|
"wire_width": 6.0
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"bus_width": 12.0,
|
||
|
|
"clearance": 0.1778,
|
||
|
|
"diff_pair_gap": 0.25,
|
||
|
|
"diff_pair_via_gap": 0.25,
|
||
|
|
"diff_pair_width": 0.2,
|
||
|
|
"line_style": 0,
|
||
|
|
"microvia_diameter": 0.508,
|
||
|
|
"microvia_drill": 0.127,
|
||
|
|
"name": "Supply_200V",
|
||
|
|
"nets": [],
|
||
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||
|
|
"track_width": 0.3048,
|
||
|
|
"via_diameter": 0.6858,
|
||
|
|
"via_drill": 0.3302,
|
||
|
|
"wire_width": 6.0
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"bus_width": 12.0,
|
||
|
|
"clearance": 0.1524,
|
||
|
|
"diff_pair_gap": 0.25,
|
||
|
|
"diff_pair_via_gap": 0.25,
|
||
|
|
"diff_pair_width": 0.2,
|
||
|
|
"line_style": 0,
|
||
|
|
"microvia_diameter": 0.508,
|
||
|
|
"microvia_drill": 0.127,
|
||
|
|
"name": "min2_extern_.188A",
|
||
|
|
"nets": [],
|
||
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||
|
|
"track_width": 0.1524,
|
||
|
|
"via_diameter": 0.6858,
|
||
|
|
"via_drill": 0.3302,
|
||
|
|
"wire_width": 6.0
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"bus_width": 12.0,
|
||
|
|
"clearance": 0.2159,
|
||
|
|
"diff_pair_gap": 0.25,
|
||
|
|
"diff_pair_via_gap": 0.25,
|
||
|
|
"diff_pair_width": 0.2,
|
||
|
|
"line_style": 0,
|
||
|
|
"microvia_diameter": 0.508,
|
||
|
|
"microvia_drill": 0.127,
|
||
|
|
"name": "min_extern_.241A",
|
||
|
|
"nets": [],
|
||
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||
|
|
"track_width": 0.2159,
|
||
|
|
"via_diameter": 0.6858,
|
||
|
|
"via_drill": 0.3302,
|
||
|
|
"wire_width": 6.0
|
||
|
|
}
|
||
|
|
],
|
||
|
|
"meta": {
|
||
|
|
"version": 2
|
||
|
|
},
|
||
|
|
"net_colors": null
|
||
|
|
},
|
||
|
|
"pcbnew": {
|
||
|
|
"last_paths": {
|
||
|
|
"gencad": "",
|
||
|
|
"idf": "",
|
||
|
|
"netlist": "frankenso.net",
|
||
|
|
"specctra_dsn": "",
|
||
|
|
"step": "",
|
||
|
|
"vrml": ""
|
||
|
|
},
|
||
|
|
"page_layout_descr_file": ""
|
||
|
|
},
|
||
|
|
"schematic": {
|
||
|
|
"annotate_start_num": 0,
|
||
|
|
"drawing": {
|
||
|
|
"default_line_thickness": 6.0,
|
||
|
|
"default_text_size": 60.0,
|
||
|
|
"field_names": [],
|
||
|
|
"intersheets_ref_own_page": false,
|
||
|
|
"intersheets_ref_prefix": "",
|
||
|
|
"intersheets_ref_short": false,
|
||
|
|
"intersheets_ref_show": false,
|
||
|
|
"intersheets_ref_suffix": "",
|
||
|
|
"junction_size_choice": 3,
|
||
|
|
"label_size_ratio": 0.25,
|
||
|
|
"pin_symbol_size": 25.0,
|
||
|
|
"text_offset_ratio": 0.08
|
||
|
|
},
|
||
|
|
"legacy_lib_dir": "",
|
||
|
|
"legacy_lib_list": [],
|
||
|
|
"meta": {
|
||
|
|
"version": 1
|
||
|
|
},
|
||
|
|
"net_format_name": "Pcbnew",
|
||
|
|
"ngspice": {
|
||
|
|
"fix_include_paths": true,
|
||
|
|
"fix_passive_vals": false,
|
||
|
|
"meta": {
|
||
|
|
"version": 0
|
||
|
|
},
|
||
|
|
"model_mode": 0,
|
||
|
|
"workbook_filename": ""
|
||
|
|
},
|
||
|
|
"page_layout_descr_file": "",
|
||
|
|
"plot_directory": "./",
|
||
|
|
"spice_adjust_passive_values": false,
|
||
|
|
"spice_external_command": "spice \"%I\"",
|
||
|
|
"subpart_first_id": 65,
|
||
|
|
"subpart_id_separator": 0
|
||
|
|
},
|
||
|
|
"sheets": [
|
||
|
|
[
|
||
|
|
"03caada9-9e22-4e2d-9035-b15433dfbb17",
|
||
|
|
""
|
||
|
|
]
|
||
|
|
],
|
||
|
|
"text_variables": {}
|
||
|
|
}
|