rusefi
/
rusefi-hardware
mirror of https://github.com/rusefi/rusefi-hardware.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

VR-Hall

This commit is contained in:
Vladimir Vinogradov 2023-06-02 23:16:39 +03:00
parent faaf75cf4d
commit 2c5e5934af
16 changed files with 110251 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
ChibiOS

@ -1 +1 @@
Subproject commit d46398838ea9e0c5a85d2437cab4ccc6ad85bef9
Subproject commit a5930d1c1f912e194e14ad9cd7366ab668dbdade

13396
VR-Hall/VR-Hall.kicad_pcb Normal file
View File

File diff suppressed because it is too large Load Diff

559
VR-Hall/VR-Hall.kicad_pro Normal file
View File

@ -0,0 +1,559 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.127,
"copper_line_width": 0.127,
"copper_text_italic": false,
"copper_text_size_h": 1.016,
"copper_text_size_v": 1.016,
"copper_text_thickness": 0.127,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 1.5,
"height": 2.5,
"width": 2.5
},
"silk_line_width": 0.254,
"silk_text_italic": false,
"silk_text_size_h": 0.508,
"silk_text_size_v": 0.508,
"silk_text_thickness": 0.127,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.19999999999999998
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "ignore",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rule_severitieslegacy_courtyards_overlap": true,
"rule_severitieslegacy_no_courtyard_defined": false,
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.25,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.508,
"min_microvia_drill": 0.127,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.76,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.15,
"min_via_annular_width": 0.125,
"min_via_diameter": 0.19999999999999998,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.15,
0.2,
0.25,
0.4,
0.5,
0.7,
0.8,
1.0,
1.5,
2.0,
2.5,
3.0
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.45,
"drill": 0.2
},
{
"diameter": 0.6,
"drill": 0.3
},
{
"diameter": 2.0,
"drill": 0.8
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [
"lib_symbol_issues|1358900|1257300|f1f8aa13-11f2-4068-98c4-31a61f2caaa0|00000000-0000-0000-0000-000000000000|||",
"lib_symbol_issues|1358900|1371600|9f955963-9704-4dd3-9585-928a8578e201|00000000-0000-0000-0000-000000000000|||",
"lib_symbol_issues|1524000|1308100|6c9ad223-eaba-4f0b-b95d-79c3a0d9a77e|00000000-0000-0000-0000-000000000000|||",
"lib_symbol_issues|1524000|1422400|2f122c58-a546-4674-b081-a41ae2d5cb5a|00000000-0000-0000-0000-000000000000|||",
"lib_symbol_issues|1828800|1727200|2ba443fe-6d3d-4bb5-879f-72a61a91fe57|00000000-0000-0000-0000-000000000000|||",
"multiple_net_names|1524000|1282700|3ed20a49-49f2-4e8e-bebb-ab69a150badc|1b0c8909-3f68-4470-bb11-eb85ca29b6b2|||",
"multiple_net_names|1524000|1397000|4d8200bb-fc3a-41f3-b196-fb06f2966fe5|faee3873-89ca-4c17-bb07-5db38419bbf9|||"
],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "ignore",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "VR-Hall.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.508,
"microvia_drill": 0.127,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.4,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.508,
"microvia_drill": 0.127,
"name": "HV",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "HV",
"pattern": "/IN_VR*"
}
]
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "frankenso.net",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 60.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.25,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.08
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "Pcbnew",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "/production/",
"spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"03caada9-9e22-4e2d-9035-b15433dfbb17",
""
]
],
"text_variables": {}
}

5426
VR-Hall/VR-Hall.kicad_sch Normal file
View File

File diff suppressed because it is too large Load Diff

90322
VR-Hall/fp-info-cache Normal file
View File

File diff suppressed because it is too large Load Diff

4
VR-Hall/fp-lib-table Normal file
View File

@ -0,0 +1,4 @@
(fp_lib_table
(lib (name "kicad6-libraries")(type "KiCad")(uri "${KIPRJMOD}/../ext/kicad6-libraries")(options "")(descr ""))
(lib (name "hellen-one-common")(type "KiCad")(uri "${KIPRJMOD}/../ext/hellen-one/kicad/footprints")(options "")(descr "Hellen-One common library"))
)

BIN
VR-Hall/production/VR-Hall.pdf Normal file
View File

Binary file not shown.

17
VR-Hall/production/bom.csv Normal file
View File

@ -0,0 +1,17 @@
Designator,Footprint,Quantity,Value,LCSC Part #
"C1, C2, C3, C4, C7, C8",C0603,6,1n,C1588
"C10, C9",C0603,2,22u,C59461
"C11, C12, C5, C6",C0603,4,100n,C14663
"D1, D2",SOT-23,2,BAT54S,C408389
"D3, D4, D5, D6, D7, D8",0603,6,GREEN,C72043
G1,rusefi_logo,1,RUSEFI_LOGO,
"H1, H2, H3, H4",MountingHole_3.2mm_M3_Pad_Via,4,MountingHole_Pad,
J1,TerminalBlock_MetzConnect_Type055_RT01504HDWU_1x04_P5.00mm_Horizontal,1,DNP,
P1,33311-24AW-2,1,33311-24AW-2,
"R1, R13, R14, R2",R0603,4,4.7k,C23162
"R10, R3, R4, R5, R6, R7, R8, R9",R1206,8,4.7k,C17936
"R11, R12, R23, R24, R25, R26",R0603,6,DNP,
"R15, R16, R17, R18, R19, R20, R21, R22",R0603,8,10k,C25804
"U1, U2",MSOP-10_3x3mm_P0.5mm,2,MAX9924UAUB+,C143633
U3,SOT-363,1,74HC2G17GW,C94189
U4,MSOP-8_3x3mm_P0.65mm,1,74LVC2G86,C130023
1 Designator Footprint Quantity Value LCSC Part #
2 C1, C2, C3, C4, C7, C8 C0603 6 1n C1588
3 C10, C9 C0603 2 22u C59461
4 C11, C12, C5, C6 C0603 4 100n C14663
5 D1, D2 SOT-23 2 BAT54S C408389
6 D3, D4, D5, D6, D7, D8 0603 6 GREEN C72043
7 G1 rusefi_logo 1 RUSEFI_LOGO
8 H1, H2, H3, H4 MountingHole_3.2mm_M3_Pad_Via 4 MountingHole_Pad
9 J1 TerminalBlock_MetzConnect_Type055_RT01504HDWU_1x04_P5.00mm_Horizontal 1 DNP
10 P1 33311-24AW-2 1 33311-24AW-2
11 R1, R13, R14, R2 R0603 4 4.7k C23162
12 R10, R3, R4, R5, R6, R7, R8, R9 R1206 8 4.7k C17936
13 R11, R12, R23, R24, R25, R26 R0603 6 DNP
14 R15, R16, R17, R18, R19, R20, R21, R22 R0603 8 10k C25804
15 U1, U2 MSOP-10_3x3mm_P0.5mm 2 MAX9924UAUB+ C143633
16 U3 SOT-363 1 74HC2G17GW C94189
17 U4 MSOP-8_3x3mm_P0.65mm 1 74LVC2G86 C130023

BIN
VR-Hall/production/gerber.zip Normal file
View File

Binary file not shown.

54
VR-Hall/production/positions.csv Normal file
View File

@ -0,0 +1,54 @@
Designator,Mid X,Mid Y,Rotation,Layer
C1,26.0,28.5,270.0,top
C10,46.0,10.5,270.0,top
C11,21.0,13.5,270.0,top
C12,39.0,3.525,90.0,top
C2,22.0,28.5,270.0,top
C3,41.0,20.5,0.0,top
C4,33.0,20.5,0.0,top
C5,36.0,10.5,270.0,top
C6,44.0,10.5,270.0,top
C7,26.0,16.5,0.0,top
C8,21.0,16.5,180.0,top
C9,38.0,10.5,270.0,top
D1,26.0,20.0,180.0,top
D2,21.0,20.0,0.0,top
D3,11.0,19.5,180.0,top
D4,11.0,17.5,180.0,top
D5,11.0,23.5,180.0,top
D6,11.0,21.5,180.0,top
D7,11.0,15.5,0.0,top
D8,11.0,13.5,0.0,top
G1,13.0,31.0,0.0,top
J1,26.0,5.5,180.0,top
P1,11.9675,37.484,0.0,top
R1,24.0,28.5,90.0,top
R10,29.0,24.5,90.0,top
R11,41.0,17.5,0.0,top
R12,33.0,17.5,0.0,top
R13,25.0,24.5,90.0,top
R14,22.0,24.5,90.0,top
R15,40.0,7.5,180.0,top
R16,32.0,7.5,180.0,top
R17,6.0,18.0,180.0,top
R18,6.0,16.0,180.0,top
R19,6.0,24.0,180.0,top
R2,20.0,28.5,90.0,top
R20,6.0,22.0,180.0,top
R21,6.0,14.0,180.0,top
R22,6.0,10.0,180.0,top
R23,6.0,8.0,180.0,top
R24,6.0,12.0,180.0,top
R25,6.0,20.0,180.0,top
R26,6.0,26.0,180.0,top
R3,39.5,29.5,90.0,top
R4,36.0,29.5,90.0,top
R5,32.5,29.5,90.0,top
R6,29.0,29.5,90.0,top
R7,39.5,24.5,90.0,top
R8,36.0,24.5,90.0,top
R9,32.5,24.5,90.0,top
U1,41.0,12.5,270.0,top
U2,33.0,12.5,270.0,top
U3,24.0,13.5,270.0,top
U4,34.0,3.525,0.0,top
1 Designator Mid X Mid Y Rotation Layer
2 C1 26.0 28.5 270.0 top
3 C10 46.0 10.5 270.0 top
4 C11 21.0 13.5 270.0 top
5 C12 39.0 3.525 90.0 top
6 C2 22.0 28.5 270.0 top
7 C3 41.0 20.5 0.0 top
8 C4 33.0 20.5 0.0 top
9 C5 36.0 10.5 270.0 top
10 C6 44.0 10.5 270.0 top
11 C7 26.0 16.5 0.0 top
12 C8 21.0 16.5 180.0 top
13 C9 38.0 10.5 270.0 top
14 D1 26.0 20.0 180.0 top
15 D2 21.0 20.0 0.0 top
16 D3 11.0 19.5 180.0 top
17 D4 11.0 17.5 180.0 top
18 D5 11.0 23.5 180.0 top
19 D6 11.0 21.5 180.0 top
20 D7 11.0 15.5 0.0 top
21 D8 11.0 13.5 0.0 top
22 G1 13.0 31.0 0.0 top
23 J1 26.0 5.5 180.0 top
24 P1 11.9675 37.484 0.0 top
25 R1 24.0 28.5 90.0 top
26 R10 29.0 24.5 90.0 top
27 R11 41.0 17.5 0.0 top
28 R12 33.0 17.5 0.0 top
29 R13 25.0 24.5 90.0 top
30 R14 22.0 24.5 90.0 top
31 R15 40.0 7.5 180.0 top
32 R16 32.0 7.5 180.0 top
33 R17 6.0 18.0 180.0 top
34 R18 6.0 16.0 180.0 top
35 R19 6.0 24.0 180.0 top
36 R2 20.0 28.5 90.0 top
37 R20 6.0 22.0 180.0 top
38 R21 6.0 14.0 180.0 top
39 R22 6.0 10.0 180.0 top
40 R23 6.0 8.0 180.0 top
41 R24 6.0 12.0 180.0 top
42 R25 6.0 20.0 180.0 top
43 R26 6.0 26.0 180.0 top
44 R3 39.5 29.5 90.0 top
45 R4 36.0 29.5 90.0 top
46 R5 32.5 29.5 90.0 top
47 R6 29.0 29.5 90.0 top
48 R7 39.5 24.5 90.0 top
49 R8 36.0 24.5 90.0 top
50 R9 32.5 24.5 90.0 top
51 U1 41.0 12.5 270.0 top
52 U2 33.0 12.5 270.0 top
53 U3 24.0 13.5 270.0 top
54 U4 34.0 3.525 0.0 top

6
VR-Hall/sym-lib-table Normal file
View File

@ -0,0 +1,6 @@
(sym_lib_table
(lib (name "33311-24AW-2")(type "KiCad")(uri "${KIPRJMOD}/../ext/kicad6-libraries/33311-24AW-2.kicad_sym")(options "")(descr ""))
(lib (name "chips")(type "KiCad")(uri "${KIPRJMOD}/../ext/kicad6-libraries/chips.kicad_sym")(options "")(descr ""))
(lib (name "semiconductors")(type "KiCad")(uri "${KIPRJMOD}/../ext/kicad6-libraries/semiconductors.kicad_sym")(options "")(descr ""))
(lib (name "hellen-one-common")(type "KiCad")(uri "${KIPRJMOD}/../ext/hellen-one/kicad/hellen-one-common.kicad_sym")(options "")(descr "Hellen-One common library"))
)

380
classic-designs/frankenso/frankenso.kicad_pro Normal file
View File

@ -0,0 +1,380 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.127,
"copper_line_width": 0.127,
"copper_text_italic": false,
"copper_text_size_h": 1.016,
"copper_text_size_v": 1.016,
"copper_text_thickness": 0.127,
"copper_text_upright": true,
"courtyard_line_width": 0.05,
"other_line_width": 0.254,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": true,
"silk_line_width": 0.254,
"silk_text_italic": false,
"silk_text_size_h": 0.508,
"silk_text_size_v": 0.508,
"silk_text_thickness": 0.127,
"silk_text_upright": true
},
"diff_pair_dimensions": [
{
"gap": 0.25,
"via_gap": 0.25,
"width": 0.2
}
],
"drc_exclusions": [],
"rule_severitieslegacy_courtyards_overlap": true,
"rule_severitieslegacy_no_courtyard_defined": false,
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.508,
"min_microvia_drill": 0.127,
"min_through_hole_diameter": 0.3302,
"min_track_width": 0.1524,
"min_via_diameter": 0.0,
"solder_mask_clearance": 0.07619999999999999,
"solder_mask_min_width": 0.0,
"solder_paste_clearance": 0.0,
"solder_paste_margin_ratio": -0.0
},
"track_widths": [
0.1524,
0.1524,
0.2159,
0.3048,
1.0668,
1.651,
1.6764,
2.7178
],
"via_dimensions": [
{
"diameter": 0.6858,
"drill": 0.3302
},
{
"diameter": 0.6858,
"drill": 0.3302
},
{
"diameter": 0.78994,
"drill": 0.43434
},
{
"diameter": 1.54178,
"drill": 1.18618
}
]
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "error",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "frankenso.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "frankenso.net",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": "../rusefi_lib/Border.kicad_wks"
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 60.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.25,
"pin_symbol_size": 0.0,
"text_offset_ratio": 0.08
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "Pcbnew",
"page_layout_descr_file": "../rusefi_lib/Border.kicad_wks",
"plot_directory": "",
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [],
"text_variables": {}
}

2
ext/hellen-one

@ -1 +1 @@
Subproject commit 4b77ad9d21666b3cd91e542e3dc999dc61a85707
Subproject commit a31162bae51eef4db6cbb0029feda82056933ad8

2
ext/kicad6-libraries

@ -1 +1 @@
Subproject commit 016efe4408c7ce38db367e211c012c8d69915ef9
Subproject commit db562ba9c1676e8cd117dd0bab22ead44a21c2a2

2
ext/libfirmware

@ -1 +1 @@
Subproject commit 3f6997c5e0bc00231d864b21e19afb9b65b17460
Subproject commit 1e60b23e8f740e8f16049f7b8052a6a3c750ce70

94
frequency-divider/frequency-divider.kicad_pro
View File

@ -1,5 +1,6 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
@ -63,19 +64,26 @@
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
@ -85,9 +93,15 @@
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "error",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
@ -95,7 +109,6 @@
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rule_severitieslegacy_courtyards_overlap": true,
@ -105,18 +118,63 @@
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.15,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.09999999999999999,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.299,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.2,
@ -138,7 +196,8 @@
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
@ -322,18 +381,23 @@
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "ignore",
"no_connect_connected": "warning",
@ -343,6 +407,7 @@
"pin_to_pin": "warning",
"power_pin_not_driven": "ignore",
"similar_labels": "warning",
"simulation_model_issue": "error",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
@ -354,13 +419,13 @@
"pinned_symbol_libs": []
},
"meta": {
"filename": "input-divider.kicad_pro",
"filename": "frequency-divider.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -374,10 +439,10 @@
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.8,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -386,19 +451,20 @@
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "HV",
"nets": [],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 1.0,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
"wire_width": 6
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
@ -414,6 +480,8 @@
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_bus_thickness": 12.0,
"default_junction_size": 40.0,
"default_line_thickness": 6.0,
@ -448,7 +516,11 @@
"page_layout_descr_file": "",
"plot_directory": "gerber/",
"spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},