mirror of https://github.com/rusefi/rusefi.git
simplify MCU selection (#2308)
* set mcu type in hw_ports * move f4 linker script * move f7 linker script * don't set default linker file in makefiles * extra line * prometheus actually didn't depend on anything special for f469 * dead line * h7 * dead
This commit is contained in:
Matthew Kennedy
GitHub
parent
6db8b612dd
commit
423acd384b
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@ -202,11 +202,6 @@ ifeq ($(USE_BOOTLOADER),yes)
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include $(PROJECT_DIR)/bootloader/bootloader.mk
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endif
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# Define linker script file here
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ifeq ($(LDSCRIPT),)
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LDSCRIPT= config/stm32f4ems/STM32F407xG.ld
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endif
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$(info PROJECT_BOARD: $(PROJECT_BOARD))
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$(info PROJECT_CPU: $(PROJECT_CPU))
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$(info CONFDIR: $(CONFDIR))
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@ -156,11 +156,6 @@ include $(PROJECT_DIR)/controllers/controllers.mk
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include $(PROJECT_DIR)/hw_layer/$(CPU_HWLAYER)/hw_ports.mk
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include $(PROJECT_DIR)/hw_layer/drivers/drivers.mk
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# Define linker script file here
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ifeq ($(LDSCRIPT),)
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LDSCRIPT= $(CONFIG)/stm32f4ems/STM32F407xG.ld
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endif
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# C sources that can be compiled in ARM or THUMB mode depending on the global
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# setting.
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CSRC = $(ALLCSRC) \
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@ -6,19 +6,15 @@ BOARDINC = $(BOARDS_DIR)/hellen/hellen72
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# Target processor details
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ifeq ($(PROJECT_CPU),ARCH_STM32F4)
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MCU_DEFS = -DSTM32F427xx
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BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
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BOARDINC += $(PROJECT_DIR)/config/stm32f4ems # For board.h
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BOARDINC += $(BOARDS_DIR)/st_stm32f4
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LDSCRIPT = $(BOARDS_DIR)/prometheus/STM32F405xG.ld
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else
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# todo: add support for STM32H7
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MCU_DEFS = -DSTM32H743xx
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BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H743ZI/board.c
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CONFDIR = config/stm32h7ems
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BOARDINC += $(PROJECT_DIR)/config/boards/nucleo_h743 # For board.h
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BOARDINC += $(PROJECT_DIR)/config/stm32h7ems # efifeatures/halconf/chconf.h
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LDSCRIPT = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld/STM32H743xI.ld
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endif
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# Set this if you want a default engine type other than normal Hellen72
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@ -35,7 +31,7 @@ ifeq ($(LED_COMMUNICATION_BRAIN_PIN),)
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endif
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# Add them all together
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DDEFS += $(MCU_DEFS) -DEFI_USE_OSC=TRUE -DFIRMWARE_ID=\"hellen72\" $(DEFAULT_ENGINE_TYPE) $(LED_CRITICAL_ERROR_BRAIN_PIN) $(LED_COMMUNICATION_BRAIN_PIN)
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DDEFS += -DEFI_USE_OSC=TRUE -DFIRMWARE_ID=\"hellen72\" $(DEFAULT_ENGINE_TYPE) $(LED_CRITICAL_ERROR_BRAIN_PIN) $(LED_COMMUNICATION_BRAIN_PIN)
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# -DEFI_SOFTWARE_KNOCK=TRUE -DSTM32_ADC_USE_ADC3=TRUE
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DDEFS += -DEFI_ICU_INPUTS=FALSE -DHAL_TRIGGER_USE_PAL=TRUE -DHAL_VSS_USE_PAL=TRUE
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# todo: is it broken?
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@ -5,10 +5,6 @@ BOARDCPPSRC = $(PROJECT_DIR)/config/boards/me7_pnp/board_configuration.cpp
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# Required include directories
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BOARDINC = $(PROJECT_DIR)/config/boards/NUCLEO_F767 $(PROJECT_DIR)/config/stm32f7ems
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LDSCRIPT= $(PROJECT_DIR)/config/boards/nucleo_f767/STM32F76xxI.ld
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# Override DEFAULT_ENGINE_TYPE
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DDEFS += -DDEFAULT_ENGINE_TYPE=VAG_18_TURBO -DSTM32F767xx
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@ -1,8 +1,6 @@
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cd ../../..
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set LDSCRIPT = config/boards/NUCLEO_F767/STM32F76xxI.ld
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set PROJECT_BOARD=microrusefi
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set PROJECT_CPU=ARCH_STM32F7
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@ -5,21 +5,17 @@ BOARDCPPSRC = $(BOARDS_DIR)/microrusefi/board_configuration.cpp
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# Target processor details
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ifeq ($(PROJECT_CPU),ARCH_STM32F4)
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MCU_DEFS = -DSTM32F407xx
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BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
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BOARDINC = $(BOARDS_DIR)/microrusefi
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BOARDINC += $(PROJECT_DIR)/config/stm32f4ems # For board.h
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BOARDINC += $(BOARDS_DIR)/st_stm32f4
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BOARDINC += $(BOARDS_DIR)/microrusefi # For knock_config.h
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LDSCRIPT = $(BOARDS_DIR)/prometheus/STM32F405xG.ld
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else
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MCU_DEFS = -DSTM32F767xx
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BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F767ZI/board.c
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CONFDIR = config/stm32f7ems
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BOARDINC = $(BOARDS_DIR)/nucleo_f767 # For board.h
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BOARDINC += $(PROJECT_DIR)/config/stm32f7ems # efifeatures/halconf/chconf.h
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BOARDINC += $(BOARDS_DIR)/microrusefi # For knock_config.h
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LDSCRIPT = $(BOARDS_DIR)/nucleo_f767/STM32F76xxI.ld
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endif
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# Set this if you want a default engine type other than normal MRE
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@ -38,7 +34,7 @@ EFI_CONSOLE_TTL_PINS = -DEFI_CONSOLE_TX_BRAIN_PIN=GPIOB_10 -DEFI_CONSOLE_RX_BRAI
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# Add them all together
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DDEFS += $(MCU_DEFS) -DEFI_USE_OSC=TRUE -DFIRMWARE_ID=\"microRusEFI\" $(DEFAULT_ENGINE_TYPE) $(LED_CRITICAL_ERROR_BRAIN_PIN) $(EFI_CONSOLE_TTL_PINS) -DEFI_SOFTWARE_KNOCK=TRUE -DSTM32_ADC_USE_ADC3=TRUE
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DDEFS += -DEFI_USE_OSC=TRUE -DFIRMWARE_ID=\"microRusEFI\" $(DEFAULT_ENGINE_TYPE) $(LED_CRITICAL_ERROR_BRAIN_PIN) $(EFI_CONSOLE_TTL_PINS) -DEFI_SOFTWARE_KNOCK=TRUE -DSTM32_ADC_USE_ADC3=TRUE
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# We are running on microRusEFI hardware!
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DDEFS += -DHW_MICRO_RUSEFI=1
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@ -4,6 +4,4 @@ export PROJECT_BOARD=microrusefi
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export PROJECT_CPU=ARCH_STM32F7
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export EXTRA_PARAMS="-DSHORT_BOARD_NAME=mre_f7"
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export LDSCRIPT="config/boards/NUCLEO_F767/STM32F76xxI.ld"
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bash ../common_make.sh
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@ -4,6 +4,5 @@ export PROJECT_BOARD=microrusefi
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export PROJECT_CPU=ARCH_STM32F7
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export EXTRA_PARAMS=-DSHORT_BOARD_NAME=mre_f7
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export DEFAULT_ENGINE_TYPE="-DDEFAULT_ENGINE_TYPE=MRE_BOARD_TEST"
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export LDSCRIPT="config/boards/NUCLEO_F767/STM32F76xxI.ld"
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bash ../common_make.sh
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@ -6,8 +6,6 @@ BOARDCPPSRC = $(PROJECT_DIR)/config/boards/nucleo_f767/board_configuration.cpp
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BOARDINC = $(PROJECT_DIR)/config/boards/nucleo_f767 $(PROJECT_DIR)/config/stm32f7ems
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CONFDIR = config/stm32f7ems
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LDSCRIPT = $(PROJECT_DIR)/config/boards/nucleo_f767/STM32F76xxI.ld
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# Override DEFAULT_ENGINE_TYPE
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DDEFS += -DDEFAULT_ENGINE_TYPE=MINIMAL_PINS -DSTM32F767xx
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@ -1,101 +0,0 @@
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* ST32F469xI memory setup.
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* Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0.
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* 'bl' is related to rusefi bootloader
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*/
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MEMORY
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{
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bl : org = 0x08000000, len = 16k /* bootloader section */
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flash : org = DEFINED(BOOTLOADER) ? 0x08008000 : 0x08000000, len = DEFINED(BOOTLOADER) ? 864k : 896k /* change address & length if bootloader */
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flash0 : org = DEFINED(BOOTLOADER) ? 0x08008000 : 0x08000000, len = DEFINED(BOOTLOADER) ? 864k : 896k /* change address & length if bootloader */
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flash1 : org = 0x00000000, len = 0
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flash2 : org = 0x00000000, len = 0
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flash3 : org = 0x00000000, len = 0
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flash4 : org = 0x00000000, len = 0
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flash5 : org = 0x00000000, len = 0
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flash6 : org = 0x00000000, len = 0
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flash7 : org = 0x00000000, len = 0
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ram0 : org = 0x20000000, len = 384k /* SRAM1 + SRAM2 + SRAM3 */
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ram1 : org = 0x20000000, len = 160k /* SRAM1 */
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ram2 : org = 0x20028000, len = 32k /* SRAM2 */
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ram3 : org = 0x20030000, len = 128k /* SRAM3 */
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ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
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ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
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ram6 : org = 0x00000000, len = 0
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ram7 : org = 0x00000000, len = 0
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}
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/* For each data/text section two region are defined, a virtual region
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and a load region (_LMA suffix).*/
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/* Flash region to be used for exception vectors.*/
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REGION_ALIAS("VECTORS_FLASH", flash0);
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REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
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/* Flash region to be used for constructors and destructors.*/
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REGION_ALIAS("XTORS_FLASH", flash0);
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REGION_ALIAS("XTORS_FLASH_LMA", flash0);
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/* Flash region to be used for code text.*/
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REGION_ALIAS("TEXT_FLASH", flash0);
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REGION_ALIAS("TEXT_FLASH_LMA", flash0);
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/* Flash region to be used for read only data.*/
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REGION_ALIAS("RODATA_FLASH", flash0);
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REGION_ALIAS("RODATA_FLASH_LMA", flash0);
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/* Flash region to be used for various.*/
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REGION_ALIAS("VARIOUS_FLASH", flash0);
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REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
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/* Flash region to be used for RAM(n) initialization data.*/
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REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
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/* RAM region to be used for Main stack. This stack accommodates the processing
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of all exceptions and interrupts.*/
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REGION_ALIAS("MAIN_STACK_RAM", ram0);
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/* RAM region to be used for the process stack. This is the stack used by
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the main() function.*/
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REGION_ALIAS("PROCESS_STACK_RAM", ram0);
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/* RAM region to be used for data segment.*/
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REGION_ALIAS("DATA_RAM", ram0);
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REGION_ALIAS("DATA_RAM_LMA", flash0);
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/* RAM region to be used for BSS segment.*/
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REGION_ALIAS("BSS_RAM", ram0);
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/* RAM region to be used for the default heap.*/
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REGION_ALIAS("HEAP_RAM", ram0);
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/* Bootloader section */
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SECTIONS
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{
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.bl : ALIGN(4)
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{
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. = ALIGN(4);
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*(.bl)
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*(.bl.*)
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. = ALIGN(4);
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} > bl AT > bl
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}
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/* Generic rules inclusion.*/
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INCLUDE rules.ld
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@ -51,21 +51,6 @@
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*/
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#define STM32_VDD 300U
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/*
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* MCU type as defined in the ST header.
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* this declaration would cause stm32_registry.h to define STM32F40_41xxx and STM32F4XX automatically
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*
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* See also STM32F4xx_MCUCONF is defined in mcuconf.h
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*/
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#if !defined(_FROM_ASM_)
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#if defined(STM32F469xx) && defined(STM32F405xx)
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#error "Both STM32F469xx and STM32F405xx cannot be defined"
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#endif
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#if !defined(STM32F405xx) && !defined(STM32F469xx)
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#error "You must define STM32F469xx or STM32F405xx for Prometheus board"
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#endif
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#endif /* _FROM_ASM_ */
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/*
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* IO pins assignments.
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*/
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@ -1,5 +1,5 @@
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# List of all the board related files.
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BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F469I_DISCOVERY/board.c \
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BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c \
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$(PROJECT_DIR)/config/boards/prometheus/board_extra.c
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BOARDCPPSRC = $(PROJECT_DIR)/config/boards/Prometheus/board_configuration.cpp
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@ -22,12 +22,10 @@ ifeq ($(DEBUG_LEVEL_OPT),)
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endif
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ifeq ($(PROMETHEUS_BOARD),405)
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LDSCRIPT = $(PROJECT_DIR)/config/boards/prometheus/STM32F405xG.ld
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DDEFS += -DDEFAULT_ENGINE_TYPE=PROMETHEUS_DEFAULTS -DSTM32F405xx -DFIRMWARE_ID=\"prometeus405\"
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DDEFS += -DDEFAULT_ENGINE_TYPE=PROMETHEUS_DEFAULTS -DFIRMWARE_ID=\"prometeus405\"
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else
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# Override DEFAULT_ENGINE_TYPE
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LDSCRIPT = $(PROJECT_DIR)/config/boards/prometheus/STM32F469xI.ld
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DDEFS += -DDEFAULT_ENGINE_TYPE=PROMETHEUS_DEFAULTS -DSTM32F469xx -DFIRMWARE_ID=\"prometeus469\"
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DDEFS += -DDEFAULT_ENGINE_TYPE=PROMETHEUS_DEFAULTS -DFIRMWARE_ID=\"prometeus469\"
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endif
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# Shared variables
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@ -1,28 +1,23 @@
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# List of all the board related files.
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BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F767ZI/board.c
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BOARDCPPSRC = $(PROJECT_DIR)/config/boards/proteus/board_configuration.cpp \
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$(PROJECT_DIR)/config/boards/proteus/adc_hack.cpp
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BOARDINC = $(PROJECT_DIR)/config/boards/proteus
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# Target processor details
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ifeq ($(PROJECT_CPU),ARCH_STM32F4)
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MCU_DEFS = -DSTM32F407xx
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BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
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BOARDINC += $(PROJECT_DIR)/config/stm32f4ems # For board.h
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BOARDINC += $(BOARDS_DIR)/st_stm32f4
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LDSCRIPT = $(BOARDS_DIR)/prometheus/STM32F405xG.ld
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else
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MCU_DEFS = -DSTM32F767xx
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BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F767ZI/board.c
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BOARDINC += $(BOARDS_DIR)/nucleo_f767 # For board.h
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BOARDINC += $(PROJECT_DIR)/config/stm32f7ems # efifeatures/halconf/chconf.h
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LDSCRIPT = $(BOARDS_DIR)/nucleo_f767/STM32F76xxI.ld
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CONFDIR = config/stm32f4ems
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PROTEUS_LEGACY = TRUE
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endif
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# Override DEFAULT_ENGINE_TYPE
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DDEFS += $(MCU_DEFS) -DEFI_USE_OSC=TRUE
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DDEFS += -DEFI_USE_OSC=TRUE
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DDEFS += -DLED_CRITICAL_ERROR_BRAIN_PIN=GPIOE_3
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DDEFS += -DFIRMWARE_ID=\"proteus\" -DDEFAULT_ENGINE_TYPE=PROTEUS_DEFAULTS
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DDEFS += -DEFI_ICU_INPUTS=FALSE -DHAL_TRIGGER_USE_PAL=TRUE
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@ -4,6 +4,4 @@ export PROJECT_BOARD=proteus
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export PROJECT_CPU=ARCH_STM32F7
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export EXTRA_PARAMS=-DSHORT_BOARD_NAME=proteus_f7
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export LDSCRIPT=config/boards/NUCLEO_F767/STM32F76xxI.ld
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bash ../common_make.sh
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@ -3,7 +3,6 @@
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export PROJECT_BOARD=proteus
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export PROJECT_CPU=ARCH_STM32F7
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export LDSCRIPT=config/boards/NUCLEO_F767/STM32F76xxI.ld
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export EXTRA_PARAMS="-DVR_HW_CHECK_MODE=TRUE -DHW_CHECK_ALWAYS_STIMULATE=TRUE -DHW_CHECK_SPARK_FSIO=TRUE -DSHORT_BOARD_NAME=proteus_f7"
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export DEFAULT_ENGINE_TYPE=-DDEFAULT_ENGINE_TYPE=PROTEUS_QC_TEST_BOARD
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@ -5,18 +5,14 @@ BOARDCPPSRC = $(BOARDS_DIR)/skeleton/board_configuration.cpp
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# Target processor details
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ifeq ($(PROJECT_CPU),ARCH_STM32F4)
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MCU_DEFS = -DSTM32F407xx
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BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
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BOARDINC = $(BOARDS_DIR)/skeleton
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BOARDINC += $(PROJECT_DIR)/config/stm32f4ems # For board.h
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BOARDINC += $(BOARDS_DIR)/st_stm32f4
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LDSCRIPT = $(BOARDS_DIR)/prometheus/STM32F405xG.ld
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else
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MCU_DEFS = -DSTM32F767xx
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BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F767ZI/board.c
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BOARDINC = $(BOARDS_DIR)/nucleo_f767 # For board.h
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BOARDINC += $(PROJECT_DIR)/config/stm32f7ems # efifeatures/halconf/chconf.h
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LDSCRIPT = $(BOARDS_DIR)/nucleo_f767/STM32F76xxI.ld
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endif
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# Set this if you want a default engine type
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|
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@ -25,7 +21,7 @@ ifeq ($(DEFAULT_ENGINE_TYPE),)
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endif
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|
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# Add them all together
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DDEFS += $(MCU_DEFS) -DEFI_USE_OSC=TRUE -DLED_CRITICAL_ERROR_BRAIN_PIN=GPIOE_3 -DFIRMWARE_ID=\"skeleton\" $(DEFAULT_ENGINE_TYPE)
|
||||
DDEFS += -DEFI_USE_OSC=TRUE -DLED_CRITICAL_ERROR_BRAIN_PIN=GPIOE_3 -DFIRMWARE_ID=\"skeleton\" $(DEFAULT_ENGINE_TYPE)
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(BOARDSRC)
|
||||
|
|
|
|||
|
|
@ -14,8 +14,6 @@ ifeq ($(USE_BOOTLOADER),yes)
|
|||
BOOTLOADERINC = $(PROJECT_DIR)/bootloader/subaru_eg33
|
||||
endif
|
||||
|
||||
LDSCRIPT = $(BOARD_DIR)/STM32F76xxI.ld
|
||||
|
||||
#FIX THIS
|
||||
CONFIGPATH = $(PROJECT_DIR)/config/stm32f7ems
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@ export DEFAULT_ENGINE_TYPE="-DDEFAULT_ENGINE_TYPE=SUBARUEG33_DEFAULTS"
|
|||
#export DEBUG_LEVEL_OPT="-O0"
|
||||
#export USE_BOOTLOADER=yes
|
||||
|
||||
#export LDSCRIPT="config/boards/NUCLEO_F767/STM32F76xxI.ld"
|
||||
#bash config/boards/common_make.sh
|
||||
|
||||
#CROSS_COMPILE=../../toolchain/gcc-arm-none-eabi-8-2018-q4-major/bin/arm-none-eabi- make $*
|
||||
|
|
|
|||
|
|
@ -4,3 +4,6 @@ HW_LAYER_EMS += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f4/stm32f4xx_hal_flash.
|
|||
$(PROJECT_DIR)/hw_layer/ports/stm32/stm32f4/stm32f4xx_hal_flash_ex.c \
|
||||
|
||||
HW_LAYER_EMS_CPP += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f4/mpu_util.cpp
|
||||
|
||||
DDEFS += -DSTM32F407xx
|
||||
LDSCRIPT = $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f4/STM32F405xG.ld
|
||||
|
|
|
|||
|
|
@ -4,3 +4,6 @@ HW_LAYER_EMS += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f7/stm32f7xx_hal_flash.
|
|||
$(PROJECT_DIR)/hw_layer/ports/stm32/stm32f7/stm32f7xx_hal_flash_ex.c
|
||||
|
||||
HW_LAYER_EMS_CPP += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f7/mpu_util.cpp
|
||||
|
||||
DDEFS += -DSTM32F767xx
|
||||
LDSCRIPT = $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f7/STM32F76xxI.ld
|
||||
|
|
|
|||
51
firmware/config/boards/subaru_eg33/STM32F76xxI.ld → firmware/hw_layer/ports/stm32/stm32h7/STM32H743xI.ld
Normal file → Executable file
51
firmware/config/boards/subaru_eg33/STM32F76xxI.ld → firmware/hw_layer/ports/stm32/stm32h7/STM32H743xI.ld
Normal file → Executable file
|
|
@ -15,47 +15,49 @@
|
|||
*/
|
||||
|
||||
/*
|
||||
* STM32F76xxI generic setup.
|
||||
* STM32H743xI generic setup.
|
||||
*
|
||||
* RAM0 - Data, Heap.
|
||||
* RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.
|
||||
*
|
||||
* Notes:
|
||||
* BSS is placed in DTCM RAM in order to simplify DMA buffers management.
|
||||
* AXI SRAM - BSS, Data, Heap.
|
||||
* SRAM1+SRAM2 - None.
|
||||
* SRAM3 - NOCACHE, ETH.
|
||||
* SRAM4 - None.
|
||||
* DTCM-RAM - Main Stack, Process Stack.
|
||||
* ITCM-RAM - None.
|
||||
* BCKP SRAM - None.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash0 (rx) : org = 0x08000000, len = 2M /* Flash as AXIM (writable) */
|
||||
flash1 (rx) : org = 0x00200000, len = 2M /* Flash as ITCM */
|
||||
flash2 (rx) : org = 0x00000000, len = 0
|
||||
flash0 (rx) : org = 0x08000000, len = 2M /* Flash bank1+bank2 */
|
||||
flash1 (rx) : org = 0x08000000, len = 1M /* Flash bank 1 */
|
||||
flash2 (rx) : org = 0x08100000, len = 1M /* Flash bank 2 */
|
||||
flash3 (rx) : org = 0x00000000, len = 0
|
||||
flash4 (rx) : org = 0x00000000, len = 0
|
||||
flash5 (rx) : org = 0x00000000, len = 0
|
||||
flash6 (rx) : org = 0x00000000, len = 0
|
||||
flash7 (rx) : org = 0x00000000, len = 0
|
||||
ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */
|
||||
ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */
|
||||
ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */
|
||||
ram3 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */
|
||||
ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
|
||||
ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
|
||||
ram6 (wx) : org = 0x00000000, len = 0
|
||||
ram7 (wx) : org = 0x00000000, len = 0
|
||||
ram0 (wx) : org = 0x24000000, len = 512k /* AXI SRAM */
|
||||
ram1 (wx) : org = 0x30000000, len = 256k /* AHB SRAM1+SRAM2 */
|
||||
ram2 (wx) : org = 0x30000000, len = 288k /* AHB SRAM1+SRAM2+SRAM3 */
|
||||
ram3 (wx) : org = 0x30040000, len = 32k /* AHB SRAM3 */
|
||||
ram4 (wx) : org = 0x38000000, len = 64k /* AHB SRAM4 */
|
||||
ram5 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */
|
||||
ram6 (wx) : org = 0x00000000, len = 64k /* ITCM-RAM */
|
||||
ram7 (wx) : org = 0x38800000, len = 4k /* BCKP SRAM */
|
||||
}
|
||||
|
||||
/* For each data/text section two region are defined, a virtual region
|
||||
and a load region (_LMA suffix).*/
|
||||
|
||||
/* Flash region to be used for exception vectors.*/
|
||||
REGION_ALIAS("VECTORS_FLASH", flash1);
|
||||
REGION_ALIAS("VECTORS_FLASH", flash0);
|
||||
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for constructors and destructors.*/
|
||||
REGION_ALIAS("XTORS_FLASH", flash1);
|
||||
REGION_ALIAS("XTORS_FLASH", flash0);
|
||||
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for code text.*/
|
||||
REGION_ALIAS("TEXT_FLASH", flash1);
|
||||
REGION_ALIAS("TEXT_FLASH", flash0);
|
||||
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for read only data.*/
|
||||
|
|
@ -63,7 +65,7 @@ REGION_ALIAS("RODATA_FLASH", flash0);
|
|||
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for various.*/
|
||||
REGION_ALIAS("VARIOUS_FLASH", flash1);
|
||||
REGION_ALIAS("VARIOUS_FLASH", flash0);
|
||||
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for RAM(n) initialization data.*/
|
||||
|
|
@ -71,11 +73,11 @@ REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
|
|||
|
||||
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||
of all exceptions and interrupts.*/
|
||||
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||
REGION_ALIAS("MAIN_STACK_RAM", ram5);
|
||||
|
||||
/* RAM region to be used for the process stack. This is the stack used by
|
||||
the main() function.*/
|
||||
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||
REGION_ALIAS("PROCESS_STACK_RAM", ram5);
|
||||
|
||||
/* RAM region to be used for data segment.*/
|
||||
REGION_ALIAS("DATA_RAM", ram0);
|
||||
|
|
@ -91,7 +93,8 @@ REGION_ALIAS("HEAP_RAM", ram0);
|
|||
INCLUDE rules_stacks.ld
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Custom sections for STM32F7xx. */
|
||||
/* Custom sections for STM32H7xx. */
|
||||
/* SRAM3 is assumed to be marked non-cacheable using MPU. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/* RAM region to be used for nocache segment.*/
|
||||
|
|
@ -4,3 +4,6 @@ HW_LAYER_EMS += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32h7/stm32h7xx_hal_flash.
|
|||
$(PROJECT_DIR)/hw_layer/ports/stm32/stm32h7/stm32h7xx_hal_flash_ex.c
|
||||
|
||||
HW_LAYER_EMS_CPP += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32h7/mpu_util.cpp
|
||||
|
||||
DDEFS += -DSTM32H743xx
|
||||
LDSCRIPT = $(PROJECT_DIR)/hw_layer/ports/stm32/stm32h7/STM32H743xI.ld
|
||||
|
|
|
|||
|
|
@ -111,10 +111,6 @@ include $(PROJECT_DIR)/init/init.mk
|
|||
include test.mk
|
||||
include tests/tests.mk
|
||||
|
||||
# Define linker script file here
|
||||
#LDSCRIPT= config/system/STM32F407xG.ld
|
||||
#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
|
||||
|
||||
# C sources that can be compiled in ARM or THUMB mode depending on the global
|
||||
# setting.
|
||||
CSRC = $(UTILSRC) \
|
||||
|
|
|
|||
Loading…
Reference in New Issue