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simplify MCU selection (#2308) 

* set mcu type in hw_ports

* move f4 linker script

* move f7 linker script

* don't set default linker file in makefiles

* extra line

* prometheus actually didn't depend on anything special for f469

* dead line

* h7

* dead
This commit is contained in:
Matthew Kennedy 2021-02-07 23:11:44 -08:00 committed by GitHub
parent 6db8b612dd
commit 423acd384b
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
25 changed files with 43 additions and 197 deletions
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5
firmware/Makefile
View File

@ -202,11 +202,6 @@ ifeq ($(USE_BOOTLOADER),yes)
include $(PROJECT_DIR)/bootloader/bootloader.mk include $(PROJECT_DIR)/bootloader/bootloader.mk
endif endif
# Define linker script file here
ifeq ($(LDSCRIPT),)
LDSCRIPT= config/stm32f4ems/STM32F407xG.ld
endif
$(info PROJECT_BOARD: $(PROJECT_BOARD)) $(info PROJECT_BOARD: $(PROJECT_BOARD))
$(info PROJECT_CPU: $(PROJECT_CPU)) $(info PROJECT_CPU: $(PROJECT_CPU))
$(info CONFDIR: $(CONFDIR)) $(info CONFDIR: $(CONFDIR))

5
firmware/bootloader/src/Makefile
View File

@ -156,11 +156,6 @@ include $(PROJECT_DIR)/controllers/controllers.mk
include $(PROJECT_DIR)/hw_layer/$(CPU_HWLAYER)/hw_ports.mk include $(PROJECT_DIR)/hw_layer/$(CPU_HWLAYER)/hw_ports.mk
include $(PROJECT_DIR)/hw_layer/drivers/drivers.mk include $(PROJECT_DIR)/hw_layer/drivers/drivers.mk
# Define linker script file here
ifeq ($(LDSCRIPT),)
LDSCRIPT= $(CONFIG)/stm32f4ems/STM32F407xG.ld
endif
# C sources that can be compiled in ARM or THUMB mode depending on the global # C sources that can be compiled in ARM or THUMB mode depending on the global
# setting. # setting.
CSRC = $(ALLCSRC) \ CSRC = $(ALLCSRC) \

6
firmware/config/boards/hellen/hellen72/board.mk
View File

@ -6,19 +6,15 @@ BOARDINC = $(BOARDS_DIR)/hellen/hellen72
# Target processor details # Target processor details
ifeq ($(PROJECT_CPU),ARCH_STM32F4) ifeq ($(PROJECT_CPU),ARCH_STM32F4)
MCU_DEFS = -DSTM32F427xx
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
BOARDINC += $(PROJECT_DIR)/config/stm32f4ems # For board.h BOARDINC += $(PROJECT_DIR)/config/stm32f4ems # For board.h
BOARDINC += $(BOARDS_DIR)/st_stm32f4 BOARDINC += $(BOARDS_DIR)/st_stm32f4
LDSCRIPT = $(BOARDS_DIR)/prometheus/STM32F405xG.ld
else else
# todo: add support for STM32H7 # todo: add support for STM32H7
MCU_DEFS = -DSTM32H743xx
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H743ZI/board.c BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H743ZI/board.c
CONFDIR = config/stm32h7ems CONFDIR = config/stm32h7ems
BOARDINC += $(PROJECT_DIR)/config/boards/nucleo_h743 # For board.h BOARDINC += $(PROJECT_DIR)/config/boards/nucleo_h743 # For board.h
BOARDINC += $(PROJECT_DIR)/config/stm32h7ems # efifeatures/halconf/chconf.h BOARDINC += $(PROJECT_DIR)/config/stm32h7ems # efifeatures/halconf/chconf.h
LDSCRIPT = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld/STM32H743xI.ld
endif endif
# Set this if you want a default engine type other than normal Hellen72 # Set this if you want a default engine type other than normal Hellen72
@ -35,7 +31,7 @@ ifeq ($(LED_COMMUNICATION_BRAIN_PIN),)
endif endif
# Add them all together # Add them all together
DDEFS += $(MCU_DEFS) -DEFI_USE_OSC=TRUE -DFIRMWARE_ID=\"hellen72\" $(DEFAULT_ENGINE_TYPE) $(LED_CRITICAL_ERROR_BRAIN_PIN) $(LED_COMMUNICATION_BRAIN_PIN) DDEFS += -DEFI_USE_OSC=TRUE -DFIRMWARE_ID=\"hellen72\" $(DEFAULT_ENGINE_TYPE) $(LED_CRITICAL_ERROR_BRAIN_PIN) $(LED_COMMUNICATION_BRAIN_PIN)
# -DEFI_SOFTWARE_KNOCK=TRUE -DSTM32_ADC_USE_ADC3=TRUE # -DEFI_SOFTWARE_KNOCK=TRUE -DSTM32_ADC_USE_ADC3=TRUE
DDEFS += -DEFI_ICU_INPUTS=FALSE -DHAL_TRIGGER_USE_PAL=TRUE -DHAL_VSS_USE_PAL=TRUE DDEFS += -DEFI_ICU_INPUTS=FALSE -DHAL_TRIGGER_USE_PAL=TRUE -DHAL_VSS_USE_PAL=TRUE
# todo: is it broken? # todo: is it broken?

4
firmware/config/boards/me7_pnp/board.mk
View File

@ -5,10 +5,6 @@ BOARDCPPSRC = $(PROJECT_DIR)/config/boards/me7_pnp/board_configuration.cpp
# Required include directories # Required include directories
BOARDINC = $(PROJECT_DIR)/config/boards/NUCLEO_F767 $(PROJECT_DIR)/config/stm32f7ems BOARDINC = $(PROJECT_DIR)/config/boards/NUCLEO_F767 $(PROJECT_DIR)/config/stm32f7ems
LDSCRIPT= $(PROJECT_DIR)/config/boards/nucleo_f767/STM32F76xxI.ld
# Override DEFAULT_ENGINE_TYPE # Override DEFAULT_ENGINE_TYPE
DDEFS += -DDEFAULT_ENGINE_TYPE=VAG_18_TURBO -DSTM32F767xx DDEFS += -DDEFAULT_ENGINE_TYPE=VAG_18_TURBO -DSTM32F767xx

2
firmware/config/boards/microrusefi/!compile-nucleo-Manhattan.bat
View File

@ -1,8 +1,6 @@
cd ../../.. cd ../../..
set LDSCRIPT = config/boards/NUCLEO_F767/STM32F76xxI.ld
set PROJECT_BOARD=microrusefi set PROJECT_BOARD=microrusefi
set PROJECT_CPU=ARCH_STM32F7 set PROJECT_CPU=ARCH_STM32F7

6
firmware/config/boards/microrusefi/board.mk
View File

@ -5,21 +5,17 @@ BOARDCPPSRC = $(BOARDS_DIR)/microrusefi/board_configuration.cpp
# Target processor details # Target processor details
ifeq ($(PROJECT_CPU),ARCH_STM32F4) ifeq ($(PROJECT_CPU),ARCH_STM32F4)
MCU_DEFS = -DSTM32F407xx
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
BOARDINC = $(BOARDS_DIR)/microrusefi BOARDINC = $(BOARDS_DIR)/microrusefi
BOARDINC += $(PROJECT_DIR)/config/stm32f4ems # For board.h BOARDINC += $(PROJECT_DIR)/config/stm32f4ems # For board.h
BOARDINC += $(BOARDS_DIR)/st_stm32f4 BOARDINC += $(BOARDS_DIR)/st_stm32f4
BOARDINC += $(BOARDS_DIR)/microrusefi # For knock_config.h BOARDINC += $(BOARDS_DIR)/microrusefi # For knock_config.h
LDSCRIPT = $(BOARDS_DIR)/prometheus/STM32F405xG.ld
else else
MCU_DEFS = -DSTM32F767xx
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F767ZI/board.c BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F767ZI/board.c
CONFDIR = config/stm32f7ems CONFDIR = config/stm32f7ems
BOARDINC = $(BOARDS_DIR)/nucleo_f767 # For board.h BOARDINC = $(BOARDS_DIR)/nucleo_f767 # For board.h
BOARDINC += $(PROJECT_DIR)/config/stm32f7ems # efifeatures/halconf/chconf.h BOARDINC += $(PROJECT_DIR)/config/stm32f7ems # efifeatures/halconf/chconf.h
BOARDINC += $(BOARDS_DIR)/microrusefi # For knock_config.h BOARDINC += $(BOARDS_DIR)/microrusefi # For knock_config.h
LDSCRIPT = $(BOARDS_DIR)/nucleo_f767/STM32F76xxI.ld
endif endif
# Set this if you want a default engine type other than normal MRE # Set this if you want a default engine type other than normal MRE
@ -38,7 +34,7 @@ EFI_CONSOLE_TTL_PINS = -DEFI_CONSOLE_TX_BRAIN_PIN=GPIOB_10 -DEFI_CONSOLE_RX_BRAI
# Add them all together # Add them all together
DDEFS += $(MCU_DEFS) -DEFI_USE_OSC=TRUE -DFIRMWARE_ID=\"microRusEFI\" $(DEFAULT_ENGINE_TYPE) $(LED_CRITICAL_ERROR_BRAIN_PIN) $(EFI_CONSOLE_TTL_PINS) -DEFI_SOFTWARE_KNOCK=TRUE -DSTM32_ADC_USE_ADC3=TRUE DDEFS += -DEFI_USE_OSC=TRUE -DFIRMWARE_ID=\"microRusEFI\" $(DEFAULT_ENGINE_TYPE) $(LED_CRITICAL_ERROR_BRAIN_PIN) $(EFI_CONSOLE_TTL_PINS) -DEFI_SOFTWARE_KNOCK=TRUE -DSTM32_ADC_USE_ADC3=TRUE
# We are running on microRusEFI hardware! # We are running on microRusEFI hardware!
DDEFS += -DHW_MICRO_RUSEFI=1 DDEFS += -DHW_MICRO_RUSEFI=1

2
firmware/config/boards/microrusefi/compile_mre_f7.sh
View File

@ -4,6 +4,4 @@ export PROJECT_BOARD=microrusefi
export PROJECT_CPU=ARCH_STM32F7 export PROJECT_CPU=ARCH_STM32F7
export EXTRA_PARAMS="-DSHORT_BOARD_NAME=mre_f7" export EXTRA_PARAMS="-DSHORT_BOARD_NAME=mre_f7"
export LDSCRIPT="config/boards/NUCLEO_F767/STM32F76xxI.ld"
bash ../common_make.sh bash ../common_make.sh

1
firmware/config/boards/microrusefi/compile_mre_f7_test.sh
View File

@ -4,6 +4,5 @@ export PROJECT_BOARD=microrusefi
export PROJECT_CPU=ARCH_STM32F7 export PROJECT_CPU=ARCH_STM32F7
export EXTRA_PARAMS=-DSHORT_BOARD_NAME=mre_f7 export EXTRA_PARAMS=-DSHORT_BOARD_NAME=mre_f7
export DEFAULT_ENGINE_TYPE="-DDEFAULT_ENGINE_TYPE=MRE_BOARD_TEST" export DEFAULT_ENGINE_TYPE="-DDEFAULT_ENGINE_TYPE=MRE_BOARD_TEST"
export LDSCRIPT="config/boards/NUCLEO_F767/STM32F76xxI.ld"
bash ../common_make.sh bash ../common_make.sh

2
firmware/config/boards/nucleo_f767/board.mk
View File

@ -6,8 +6,6 @@ BOARDCPPSRC = $(PROJECT_DIR)/config/boards/nucleo_f767/board_configuration.cpp
BOARDINC = $(PROJECT_DIR)/config/boards/nucleo_f767 $(PROJECT_DIR)/config/stm32f7ems BOARDINC = $(PROJECT_DIR)/config/boards/nucleo_f767 $(PROJECT_DIR)/config/stm32f7ems
CONFDIR = config/stm32f7ems CONFDIR = config/stm32f7ems
LDSCRIPT = $(PROJECT_DIR)/config/boards/nucleo_f767/STM32F76xxI.ld
# Override DEFAULT_ENGINE_TYPE # Override DEFAULT_ENGINE_TYPE
DDEFS += -DDEFAULT_ENGINE_TYPE=MINIMAL_PINS -DSTM32F767xx DDEFS += -DDEFAULT_ENGINE_TYPE=MINIMAL_PINS -DSTM32F767xx

101
firmware/config/boards/prometheus/STM32F469xI.ld
View File

@ -1,101 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* ST32F469xI memory setup.
* Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0.
* 'bl' is related to rusefi bootloader
*/
MEMORY
{
bl : org = 0x08000000, len = 16k /* bootloader section */
flash : org = DEFINED(BOOTLOADER) ? 0x08008000 : 0x08000000, len = DEFINED(BOOTLOADER) ? 864k : 896k /* change address & length if bootloader */
flash0 : org = DEFINED(BOOTLOADER) ? 0x08008000 : 0x08000000, len = DEFINED(BOOTLOADER) ? 864k : 896k /* change address & length if bootloader */
flash1 : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 384k /* SRAM1 + SRAM2 + SRAM3 */
ram1 : org = 0x20000000, len = 160k /* SRAM1 */
ram2 : org = 0x20028000, len = 32k /* SRAM2 */
ram3 : org = 0x20030000, len = 128k /* SRAM3 */
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Bootloader section */
SECTIONS
{
.bl : ALIGN(4)
{
. = ALIGN(4);
*(.bl)
*(.bl.*)
. = ALIGN(4);
} > bl AT > bl
}
/* Generic rules inclusion.*/
INCLUDE rules.ld

15
firmware/config/boards/prometheus/board.h
View File

@ -51,21 +51,6 @@
*/ */
#define STM32_VDD 300U #define STM32_VDD 300U
/*
* MCU type as defined in the ST header.
* this declaration would cause stm32_registry.h to define STM32F40_41xxx and STM32F4XX automatically
*
* See also STM32F4xx_MCUCONF is defined in mcuconf.h
*/
#if !defined(_FROM_ASM_)
#if defined(STM32F469xx) && defined(STM32F405xx)
#error "Both STM32F469xx and STM32F405xx cannot be defined"
#endif
#if !defined(STM32F405xx) && !defined(STM32F469xx)
#error "You must define STM32F469xx or STM32F405xx for Prometheus board"
#endif
#endif /* _FROM_ASM_ */
/* /*
* IO pins assignments. * IO pins assignments.
*/ */

8
firmware/config/boards/prometheus/prometheus-common.mk
View File

@ -1,5 +1,5 @@
# List of all the board related files. # List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F469I_DISCOVERY/board.c \ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c \
$(PROJECT_DIR)/config/boards/prometheus/board_extra.c $(PROJECT_DIR)/config/boards/prometheus/board_extra.c
BOARDCPPSRC = $(PROJECT_DIR)/config/boards/Prometheus/board_configuration.cpp BOARDCPPSRC = $(PROJECT_DIR)/config/boards/Prometheus/board_configuration.cpp
@ -22,12 +22,10 @@ ifeq ($(DEBUG_LEVEL_OPT),)
endif endif
ifeq ($(PROMETHEUS_BOARD),405) ifeq ($(PROMETHEUS_BOARD),405)
LDSCRIPT = $(PROJECT_DIR)/config/boards/prometheus/STM32F405xG.ld DDEFS += -DDEFAULT_ENGINE_TYPE=PROMETHEUS_DEFAULTS -DFIRMWARE_ID=\"prometeus405\"
DDEFS += -DDEFAULT_ENGINE_TYPE=PROMETHEUS_DEFAULTS -DSTM32F405xx -DFIRMWARE_ID=\"prometeus405\"
else else
# Override DEFAULT_ENGINE_TYPE # Override DEFAULT_ENGINE_TYPE
LDSCRIPT = $(PROJECT_DIR)/config/boards/prometheus/STM32F469xI.ld DDEFS += -DDEFAULT_ENGINE_TYPE=PROMETHEUS_DEFAULTS -DFIRMWARE_ID=\"prometeus469\"
DDEFS += -DDEFAULT_ENGINE_TYPE=PROMETHEUS_DEFAULTS -DSTM32F469xx -DFIRMWARE_ID=\"prometeus469\"
endif endif
# Shared variables # Shared variables

7
firmware/config/boards/proteus/board.mk
View File

@ -1,28 +1,23 @@
# List of all the board related files. # List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F767ZI/board.c
BOARDCPPSRC = $(PROJECT_DIR)/config/boards/proteus/board_configuration.cpp \ BOARDCPPSRC = $(PROJECT_DIR)/config/boards/proteus/board_configuration.cpp \
$(PROJECT_DIR)/config/boards/proteus/adc_hack.cpp $(PROJECT_DIR)/config/boards/proteus/adc_hack.cpp
BOARDINC = $(PROJECT_DIR)/config/boards/proteus BOARDINC = $(PROJECT_DIR)/config/boards/proteus
# Target processor details # Target processor details
ifeq ($(PROJECT_CPU),ARCH_STM32F4) ifeq ($(PROJECT_CPU),ARCH_STM32F4)
MCU_DEFS = -DSTM32F407xx
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
BOARDINC += $(PROJECT_DIR)/config/stm32f4ems # For board.h BOARDINC += $(PROJECT_DIR)/config/stm32f4ems # For board.h
BOARDINC += $(BOARDS_DIR)/st_stm32f4 BOARDINC += $(BOARDS_DIR)/st_stm32f4
LDSCRIPT = $(BOARDS_DIR)/prometheus/STM32F405xG.ld
else else
MCU_DEFS = -DSTM32F767xx
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F767ZI/board.c BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F767ZI/board.c
BOARDINC += $(BOARDS_DIR)/nucleo_f767 # For board.h BOARDINC += $(BOARDS_DIR)/nucleo_f767 # For board.h
BOARDINC += $(PROJECT_DIR)/config/stm32f7ems # efifeatures/halconf/chconf.h BOARDINC += $(PROJECT_DIR)/config/stm32f7ems # efifeatures/halconf/chconf.h
LDSCRIPT = $(BOARDS_DIR)/nucleo_f767/STM32F76xxI.ld
CONFDIR = config/stm32f4ems CONFDIR = config/stm32f4ems
PROTEUS_LEGACY = TRUE PROTEUS_LEGACY = TRUE
endif endif
# Override DEFAULT_ENGINE_TYPE # Override DEFAULT_ENGINE_TYPE
DDEFS += $(MCU_DEFS) -DEFI_USE_OSC=TRUE DDEFS += -DEFI_USE_OSC=TRUE
DDEFS += -DLED_CRITICAL_ERROR_BRAIN_PIN=GPIOE_3 DDEFS += -DLED_CRITICAL_ERROR_BRAIN_PIN=GPIOE_3
DDEFS += -DFIRMWARE_ID=\"proteus\" -DDEFAULT_ENGINE_TYPE=PROTEUS_DEFAULTS DDEFS += -DFIRMWARE_ID=\"proteus\" -DDEFAULT_ENGINE_TYPE=PROTEUS_DEFAULTS
DDEFS += -DEFI_ICU_INPUTS=FALSE -DHAL_TRIGGER_USE_PAL=TRUE DDEFS += -DEFI_ICU_INPUTS=FALSE -DHAL_TRIGGER_USE_PAL=TRUE

2
firmware/config/boards/proteus/compile_proteus_f7.sh
View File

@ -4,6 +4,4 @@ export PROJECT_BOARD=proteus
export PROJECT_CPU=ARCH_STM32F7 export PROJECT_CPU=ARCH_STM32F7
export EXTRA_PARAMS=-DSHORT_BOARD_NAME=proteus_f7 export EXTRA_PARAMS=-DSHORT_BOARD_NAME=proteus_f7
export LDSCRIPT=config/boards/NUCLEO_F767/STM32F76xxI.ld
bash ../common_make.sh bash ../common_make.sh

1
firmware/config/boards/proteus/compile_proteus_f7_hardware_QC_special_build.sh
View File

@ -3,7 +3,6 @@
export PROJECT_BOARD=proteus export PROJECT_BOARD=proteus
export PROJECT_CPU=ARCH_STM32F7 export PROJECT_CPU=ARCH_STM32F7
export LDSCRIPT=config/boards/NUCLEO_F767/STM32F76xxI.ld
export EXTRA_PARAMS="-DVR_HW_CHECK_MODE=TRUE -DHW_CHECK_ALWAYS_STIMULATE=TRUE -DHW_CHECK_SPARK_FSIO=TRUE -DSHORT_BOARD_NAME=proteus_f7" export EXTRA_PARAMS="-DVR_HW_CHECK_MODE=TRUE -DHW_CHECK_ALWAYS_STIMULATE=TRUE -DHW_CHECK_SPARK_FSIO=TRUE -DSHORT_BOARD_NAME=proteus_f7"
export DEFAULT_ENGINE_TYPE=-DDEFAULT_ENGINE_TYPE=PROTEUS_QC_TEST_BOARD export DEFAULT_ENGINE_TYPE=-DDEFAULT_ENGINE_TYPE=PROTEUS_QC_TEST_BOARD

6
firmware/config/boards/skeleton/board.mk
View File

@ -5,18 +5,14 @@ BOARDCPPSRC = $(BOARDS_DIR)/skeleton/board_configuration.cpp
# Target processor details # Target processor details
ifeq ($(PROJECT_CPU),ARCH_STM32F4) ifeq ($(PROJECT_CPU),ARCH_STM32F4)
MCU_DEFS = -DSTM32F407xx
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
BOARDINC = $(BOARDS_DIR)/skeleton BOARDINC = $(BOARDS_DIR)/skeleton
BOARDINC += $(PROJECT_DIR)/config/stm32f4ems # For board.h BOARDINC += $(PROJECT_DIR)/config/stm32f4ems # For board.h
BOARDINC += $(BOARDS_DIR)/st_stm32f4 BOARDINC += $(BOARDS_DIR)/st_stm32f4
LDSCRIPT = $(BOARDS_DIR)/prometheus/STM32F405xG.ld
else else
MCU_DEFS = -DSTM32F767xx
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F767ZI/board.c BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F767ZI/board.c
BOARDINC = $(BOARDS_DIR)/nucleo_f767 # For board.h BOARDINC = $(BOARDS_DIR)/nucleo_f767 # For board.h
BOARDINC += $(PROJECT_DIR)/config/stm32f7ems # efifeatures/halconf/chconf.h BOARDINC += $(PROJECT_DIR)/config/stm32f7ems # efifeatures/halconf/chconf.h
LDSCRIPT = $(BOARDS_DIR)/nucleo_f767/STM32F76xxI.ld
endif endif
# Set this if you want a default engine type # Set this if you want a default engine type
@ -25,7 +21,7 @@ ifeq ($(DEFAULT_ENGINE_TYPE),)
endif endif
# Add them all together # Add them all together
DDEFS += $(MCU_DEFS) -DEFI_USE_OSC=TRUE -DLED_CRITICAL_ERROR_BRAIN_PIN=GPIOE_3 -DFIRMWARE_ID=\"skeleton\" $(DEFAULT_ENGINE_TYPE) DDEFS += -DEFI_USE_OSC=TRUE -DLED_CRITICAL_ERROR_BRAIN_PIN=GPIOE_3 -DFIRMWARE_ID=\"skeleton\" $(DEFAULT_ENGINE_TYPE)
# Shared variables # Shared variables
ALLCSRC += $(BOARDSRC) ALLCSRC += $(BOARDSRC)

2
firmware/config/boards/subaru_eg33/board.mk
View File

@ -14,8 +14,6 @@ ifeq ($(USE_BOOTLOADER),yes)
BOOTLOADERINC = $(PROJECT_DIR)/bootloader/subaru_eg33 BOOTLOADERINC = $(PROJECT_DIR)/bootloader/subaru_eg33
endif endif
LDSCRIPT = $(BOARD_DIR)/STM32F76xxI.ld
#FIX THIS #FIX THIS
CONFIGPATH = $(PROJECT_DIR)/config/stm32f7ems CONFIGPATH = $(PROJECT_DIR)/config/stm32f7ems

1
firmware/config/boards/subaru_eg33/make.sh
View File

@ -8,7 +8,6 @@ export DEFAULT_ENGINE_TYPE="-DDEFAULT_ENGINE_TYPE=SUBARUEG33_DEFAULTS"
#export DEBUG_LEVEL_OPT="-O0" #export DEBUG_LEVEL_OPT="-O0"
#export USE_BOOTLOADER=yes #export USE_BOOTLOADER=yes
#export LDSCRIPT="config/boards/NUCLEO_F767/STM32F76xxI.ld"
#bash config/boards/common_make.sh #bash config/boards/common_make.sh
#CROSS_COMPILE=../../toolchain/gcc-arm-none-eabi-8-2018-q4-major/bin/arm-none-eabi- make $* #CROSS_COMPILE=../../toolchain/gcc-arm-none-eabi-8-2018-q4-major/bin/arm-none-eabi- make $*

0
firmware/config/boards/prometheus/STM32F405xG.ld → firmware/hw_layer/ports/stm32/stm32f4/STM32F405xG.ld
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3
firmware/hw_layer/ports/stm32/stm32f4/hw_ports.mk
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@ -4,3 +4,6 @@ HW_LAYER_EMS += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f4/stm32f4xx_hal_flash.
$(PROJECT_DIR)/hw_layer/ports/stm32/stm32f4/stm32f4xx_hal_flash_ex.c \ $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f4/stm32f4xx_hal_flash_ex.c \
HW_LAYER_EMS_CPP += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f4/mpu_util.cpp HW_LAYER_EMS_CPP += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f4/mpu_util.cpp
DDEFS += -DSTM32F407xx
LDSCRIPT = $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f4/STM32F405xG.ld

0
firmware/config/boards/nucleo_f767/STM32F76xxI.ld → firmware/hw_layer/ports/stm32/stm32f7/STM32F76xxI.ld
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3
firmware/hw_layer/ports/stm32/stm32f7/hw_ports.mk
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@ -4,3 +4,6 @@ HW_LAYER_EMS += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f7/stm32f7xx_hal_flash.
$(PROJECT_DIR)/hw_layer/ports/stm32/stm32f7/stm32f7xx_hal_flash_ex.c $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f7/stm32f7xx_hal_flash_ex.c
HW_LAYER_EMS_CPP += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f7/mpu_util.cpp HW_LAYER_EMS_CPP += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f7/mpu_util.cpp
DDEFS += -DSTM32F767xx
LDSCRIPT = $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f7/STM32F76xxI.ld

51
firmware/config/boards/subaru_eg33/STM32F76xxI.ld → firmware/hw_layer/ports/stm32/stm32h7/STM32H743xI.ld Normal file → Executable file
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@ -15,47 +15,49 @@
*/ */
/* /*
* STM32F76xxI generic setup. * STM32H743xI generic setup.
* *
* RAM0 - Data, Heap. * AXI SRAM - BSS, Data, Heap.
* RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. * SRAM1+SRAM2 - None.
* * SRAM3 - NOCACHE, ETH.
* Notes: * SRAM4 - None.
* BSS is placed in DTCM RAM in order to simplify DMA buffers management. * DTCM-RAM - Main Stack, Process Stack.
* ITCM-RAM - None.
* BCKP SRAM - None.
*/ */
MEMORY MEMORY
{ {
flash0 (rx) : org = 0x08000000, len = 2M /* Flash as AXIM (writable) */ flash0 (rx) : org = 0x08000000, len = 2M /* Flash bank1+bank2 */
flash1 (rx) : org = 0x00200000, len = 2M /* Flash as ITCM */ flash1 (rx) : org = 0x08000000, len = 1M /* Flash bank 1 */
flash2 (rx) : org = 0x00000000, len = 0 flash2 (rx) : org = 0x08100000, len = 1M /* Flash bank 2 */
flash3 (rx) : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x24000000, len = 512k /* AXI SRAM */
ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */ ram1 (wx) : org = 0x30000000, len = 256k /* AHB SRAM1+SRAM2 */
ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */ ram2 (wx) : org = 0x30000000, len = 288k /* AHB SRAM1+SRAM2+SRAM3 */
ram3 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */ ram3 (wx) : org = 0x30040000, len = 32k /* AHB SRAM3 */
ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */ ram4 (wx) : org = 0x38000000, len = 64k /* AHB SRAM4 */
ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ ram5 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */
ram6 (wx) : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 64k /* ITCM-RAM */
ram7 (wx) : org = 0x00000000, len = 0 ram7 (wx) : org = 0x38800000, len = 4k /* BCKP SRAM */
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/ and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/ /* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash1); REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0); REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/ /* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash1); REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0); REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/ /* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash1); REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0); REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/ /* Flash region to be used for read only data.*/
@ -63,7 +65,7 @@ REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0); REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/ /* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash1); REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/ /* Flash region to be used for RAM(n) initialization data.*/
@ -71,11 +73,11 @@ REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing /* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/ of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0); REGION_ALIAS("MAIN_STACK_RAM", ram5);
/* RAM region to be used for the process stack. This is the stack used by /* RAM region to be used for the process stack. This is the stack used by
the main() function.*/ the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0); REGION_ALIAS("PROCESS_STACK_RAM", ram5);
/* RAM region to be used for data segment.*/ /* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0); REGION_ALIAS("DATA_RAM", ram0);
@ -91,7 +93,8 @@ REGION_ALIAS("HEAP_RAM", ram0);
INCLUDE rules_stacks.ld INCLUDE rules_stacks.ld
/*===========================================================================*/ /*===========================================================================*/
/* Custom sections for STM32F7xx. */ /* Custom sections for STM32H7xx. */
/* SRAM3 is assumed to be marked non-cacheable using MPU. */
/*===========================================================================*/ /*===========================================================================*/
/* RAM region to be used for nocache segment.*/ /* RAM region to be used for nocache segment.*/

3
firmware/hw_layer/ports/stm32/stm32h7/hw_ports.mk
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@ -4,3 +4,6 @@ HW_LAYER_EMS += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32h7/stm32h7xx_hal_flash.
$(PROJECT_DIR)/hw_layer/ports/stm32/stm32h7/stm32h7xx_hal_flash_ex.c $(PROJECT_DIR)/hw_layer/ports/stm32/stm32h7/stm32h7xx_hal_flash_ex.c
HW_LAYER_EMS_CPP += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32h7/mpu_util.cpp HW_LAYER_EMS_CPP += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32h7/mpu_util.cpp
DDEFS += -DSTM32H743xx
LDSCRIPT = $(PROJECT_DIR)/hw_layer/ports/stm32/stm32h7/STM32H743xI.ld

4
unit_tests/Makefile
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@ -111,10 +111,6 @@ include $(PROJECT_DIR)/init/init.mk
include test.mk include test.mk
include tests/tests.mk include tests/tests.mk
# Define linker script file here
#LDSCRIPT= config/system/STM32F407xG.ld
#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global # C sources that can be compiled in ARM or THUMB mode depending on the global
# setting. # setting.
CSRC = $(UTILSRC) \ CSRC = $(UTILSRC) \