common rail

This commit is contained in:
rusefi 2018-02-05 04:41:12 +03:00
parent fca6007cf4
commit 4d1cbfd4dd
7 changed files with 54667 additions and 0 deletions

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update=2/4/2018 5:45:40 PM
version=1
last_client=kicad
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[general]
version=1
[pcbnew]
version=1
PageLayoutDescrFile=../rusefi_lib/Border.kicad_wks
LastNetListRead=frankenso.net
PadDrill=0
PadDrillOvalY=0
PadSizeH=0.70104
PadSizeV=1.6002
PcbTextSizeV=1.016
PcbTextSizeH=1.016
PcbTextThickness=0.127
ModuleTextSizeV=0.508
ModuleTextSizeH=0.508
ModuleTextSizeThickness=0.127
SolderMaskClearance=0.2
SolderMaskMinWidth=0
DrawSegmentWidth=0.127
BoardOutlineThickness=0.127
ModuleOutlineThickness=0.254
[eeschema]
version=1
LibDir=../rusefi_lib
[eeschema/libraries]
LibName1=Common_Rail_MC33816-rescue
LibName2=power
LibName3=device
LibName4=transistors
LibName5=conn
LibName6=linear
LibName7=regul
LibName8=74xx
LibName9=cmos4000
LibName10=adc-dac
LibName11=memory
LibName12=xilinx
LibName13=microcontrollers
LibName14=dsp
LibName15=microchip
LibName16=analog_switches
LibName17=motorola
LibName18=texas
LibName19=intel
LibName20=audio
LibName21=interface
LibName22=digital-audio
LibName23=philips
LibName24=display
LibName25=cypress
LibName26=siliconi
LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves
LibName31=mc33816
[schematic_editor]
version=1
PageLayoutDescrFile=../rusefi_lib/Border.kicad_wks
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=60

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1) TBD

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$Comp
L R R7
U 1 1 4C2F52C5
P 3600 8700
F 0 "blah" V 2480 1750 50 0000 C CNN
F 1 "DOUBLE_SCHOTTKY" H 6950 4125 60 0001 C CNN
F 2 "sot23" V 3805 3950 60 0001 C CNN
F 3 "" H 7325 3975 60 0001 C CNN
F 4 "st,BAS70-04FILM" V 3805 3950 60 0001 C CNN "MFG,MFG#"
F 5 "DIGI,497-2516-1-ND" V 3805 3950 60 0001 C CNN "VEND1,VEND1#"
F 6 "," H 7325 3975 60 0001 C CNN "VEND2,VEND2#"

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#!/usr/bin/python
# This script will update KICAD .sch files with component properties found in the property.sch file.
#It first creates a file list, then opens each .sch file renames the old file to .sch.old file, and
#then it recreates the orginal file.
import commands,sys,os
currentline = []
fileNames = os.listdir("../")#get file list
#fileNames = ["../digi_protect_I3.sch","../digi_protect_I4.sch","../freeEMS_lib.lib"]#limit how many fileNames we look at for debug purposes
#fileNames = ["digi_protect_I3.sch"]#limit how many fileNames we look at for debug purposes
mytemplatefile=open("property.sch","r")#Open template file and create a search variable, and a replacement text file
for i in range (1,6): #Read the first several lines effectively skipping these lines
mytemplatefile.readline()#Increment the readline pointer
searchvar = mytemplatefile.readline()#create the search variable
searchvar = searchvar[0:searchvar.find('" ')+2]#save the part we need to compare against
#mytemplatefile.readline()#toss one line of the template
templateText=mytemplatefile.read()#create the replacement text variable.
mytemplatefile.close()#not needed any more, so close it.
for fileName in fileNames:#rake through each file
if fileName.endswith (".sch"):#make sure it's a schematic
if not os.path.exists('..//'+fileName+'.old'):#check that this file hasn't been processed yet, debug code
print "Processing "+fileName#let us know you are working
os.rename('..//'+fileName, '..//'+fileName+'.old')#remane newfile, to .old file
inFile = open('..//'+fileName+'.old',"r")
outFile = open('..//'+fileName,'w')
line = inFile.readline()
while line!='':# Process input file one line at a time, and replace when required
if line.startswith(searchvar):#is a component to be replaced?
outFile.write(line)#copy identified line, such the component designator is the same as the orginal file
line = inFile.readline()#read one line from orginal file
#outFile.write(line)#copy one line after identified line, such the component designator is the same as the orginal file
outFile.write(templateText)#copy new data to the output file
while line != '' and not line.startswith(' '):#skip the old data from the orginal file.
line = inFile.readline()
outFile.write(line)#not a new replaced component, so just copy the string to the new file
else:
outFile.write(line)#not a new replaced component, so just copy the string to the new file
line=inFile.readline()#incriment the line
outFile.close()
inFile.close()
os.remove('..//'+fileName+'.old')#remove old file
else:#debug code
print "Already Processed "+fileName#debug code