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reducing GPIO code duplication

This commit is contained in:
rusefillc 2023-05-24 08:51:24 -04:00
parent 805d55a26f
commit cc4175f428
7 changed files with 24 additions and 50 deletions
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16
firmware/controllers/system/efi_gpio.cpp
View File

@ -713,3 +713,19 @@ void turnAllPinsOff(void) {
}
}
#endif /* EFI_GPIO_HARDWARE */
#if EFI_PROD_CODE
/**
* this method returns the numeric part of pin name. For instance, for PC13 this would return '13'
*/
ioportmask_t getHwPin(const char *msg, brain_pin_e brainPin) {
if (!isBrainPinValid(brainPin))
return EFI_ERROR_CODE;
if (brain_pin_is_onchip(brainPin))
return getBrainPinIndex(brainPin);
firmwareError(ObdCode::CUSTOM_ERR_INVALID_PIN, "%s: Invalid on-chip Gpio: %d", msg, brainPin);
return EFI_ERROR_CODE;
}
#endif // EFI_PROD_CODE

16
firmware/hw_layer/ports/cypress/cypress_pins.cpp
View File

@ -11,8 +11,6 @@
#if EFI_GPIO_HARDWARE
#define PORT_SIZE 16
static ioportid_t ports[] = {
GPIOA,
GPIOB,
@ -112,20 +110,6 @@ ioportid_t getHwPort(const char *msg, brain_pin_e brainPin) {
return ports[(brainPin - Gpio::A0) / PORT_SIZE];
}
/**
* this method returns the numeric part of pin name. For instance, for PC13 this would return '13'
*/
ioportmask_t getHwPin(const char *msg, brain_pin_e brainPin) {
if (!isBrainPinValid(brainPin))
return EFI_ERROR_CODE;
if (brain_pin_is_onchip(brainPin))
return getBrainPinIndex(brainPin);
firmwareError(ObdCode::CUSTOM_ERR_INVALID_PIN, "%s: Invalid on-chip brain_pin_e: %d", msg, brainPin);
return EFI_ERROR_CODE;
}
/**
* Parse string representation of physical pin into brain_pin_e ordinal.
*

2
firmware/hw_layer/ports/cypress/port_mpu_util.h
View File

@ -8,6 +8,8 @@
#pragma once
#define PORT_SIZE 16
// 168 ticks in microsecond in case of 168MHz 407
#define US_TO_NT_MULTIPLIER (CORE_CLOCK / 1000000)

17
firmware/hw_layer/ports/kinetis/kinetis_pins.cpp
View File

@ -11,9 +11,6 @@
#if EFI_GPIO_HARDWARE
// This is the radical departure from STM32
#define PORT_SIZE 18
static ioportid_t ports[] = {GPIOA,
GPIOB,
GPIOC,
@ -75,20 +72,6 @@ ioportid_t getHwPort(const char *msg, brain_pin_e brainPin) {
return ports[(brainPin - Gpio::A0) / PORT_SIZE];
}
/**
* this method returns the numeric part of pin name. For instance, for PC13 this would return '13'
*/
ioportmask_t getHwPin(const char *msg, brain_pin_e brainPin) {
if (!isBrainPinValid(brainPin))
return EFI_ERROR_CODE;
if (brain_pin_is_onchip(brainPin))
return getBrainPinIndex(brainPin);
firmwareError(ObdCode::CUSTOM_ERR_INVALID_PIN, "%s: Invalid on-chip Gpio: %d", msg, brainPin);
return EFI_ERROR_CODE;
}
/**
* Parse string representation of physical pin into Gpio ordinal.
*

3
firmware/hw_layer/ports/kinetis/port_mpu_util.h
View File

@ -8,6 +8,9 @@
#pragma once
// This is the radical departure from STM32
#define PORT_SIZE 18
// 168 ticks in microsecond in case of 168MHz 407
#define US_TO_NT_MULTIPLIER (CORE_CLOCK / 1000000)

4
firmware/hw_layer/ports/stm32/port_mpu_util.h
View File

@ -1,5 +1,5 @@
/**
* @file stm32_common_mpu_util.h
* @file port_mpu_util.h
* @brief Low level common STM32 header
*
* @date Aug 3, 2019
@ -10,6 +10,8 @@
#include "device_mpu_util.h"
#define PORT_SIZE 16
#define MCU_SERIAL_NUMBER_BYTES 12
// 4mhz was chosen because it's the GCD of (84, 108, 200), the three speeds of STM32 TIM5 clock currently supported

16
firmware/hw_layer/ports/stm32/stm32_pins.cpp
View File

@ -12,8 +12,6 @@
#if EFI_GPIO_HARDWARE
#define PORT_SIZE 16
static ioportid_t ports[] = {GPIOA,
GPIOB,
GPIOC,
@ -166,20 +164,6 @@ ioportid_t getHwPort(const char *msg, brain_pin_e brainPin) {
return ports[(brainPin - Gpio::A0) / PORT_SIZE];
}
/**
* this method returns the numeric part of pin name. For instance, for PC13 this would return '13'
*/
ioportmask_t getHwPin(const char *msg, brain_pin_e brainPin) {
if (!isBrainPinValid(brainPin))
return EFI_ERROR_CODE;
if (brain_pin_is_onchip(brainPin))
return getBrainPinIndex(brainPin);
firmwareError(ObdCode::CUSTOM_ERR_INVALID_PIN, "%s: Invalid on-chip Gpio: %d", msg, brainPin);
return EFI_ERROR_CODE;
}
/**
* Parse string representation of physical pin into Gpio ordinal.
*