mirror of https://github.com/rusefi/rusefi.git
146 lines
5.6 KiB
Diff
146 lines
5.6 KiB
Diff
diff --git a/os/hal/include/hal_uart.h b/os/hal/include/hal_uart.h
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index a07464993..3a6abb6b9 100644
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--- a/os/hal/include/hal_uart.h
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+++ b/os/hal/include/hal_uart.h
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@@ -298,6 +298,26 @@ typedef enum {
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_uart_wakeup_rx_complete_isr(uartp); \
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}
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+/**
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+ * @brief Common ISR code for RX half-transfer data.
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+ * @details This code handles the portable part of the ISR code:
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+ * - Callback invocation.
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+ * - Waiting thread wakeup, if any.
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+ * - Driver state transitions.
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+ * .
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+ * @note This macro is meant to be used in the low level drivers
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+ * implementation only.
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+ *
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+ * @param[in] uartp pointer to the @p UARTDriver object
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+ * @param[in] full flag set to 1 for the second half, and 0 for the first half
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+ *
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+ * @notapi
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+ */
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+#define _uart_rx_half_isr_code(uartp, full) { \
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+ if ((uartp)->config->rxhalf_cb != NULL) \
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+ (uartp)->config->rxhalf_cb(uartp, full); \
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+}
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+
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/**
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* @brief Common ISR code for RX error.
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* @details This code handles the portable part of the ISR code:
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diff --git a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c
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index f4370d28d..e2caea0e1 100644
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--- a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c
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+++ b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c
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@@ -236,6 +236,11 @@ static void usart_start(UARTDriver *uartp) {
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/* Mustn't ever set TCIE here - if done, it causes an immediate
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interrupt.*/
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cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE;
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+
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+ /* Add Idle interrupt if needed */
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+ if (uartp->config->timeout_cb != NULL)
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+ cr1 |= USART_CR1_IDLEIE;
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+
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u->CR1 = uartp->config->cr1 | cr1;
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/* Starting the receiver idle loop.*/
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@@ -264,6 +269,15 @@ static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) {
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received character and then the driver stays in the same state.*/
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_uart_rx_idle_code(uartp);
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}
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+ /* DMA half-transter interrupt handling - for the 1st/2nd half transfers. */
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+ else if (uartp->config->rxhalf_cb != NULL) {
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+ if ((flags & STM32_DMA_ISR_HTIF) != 0) {
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+ _uart_rx_half_isr_code(uartp, 0);
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+ }
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+ else if ((flags & STM32_DMA_ISR_TCIF) != 0) {
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+ _uart_rx_half_isr_code(uartp, 1);
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+ }
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+ }
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else {
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/* Receiver in active state, a callback is generated, if enabled, after
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a completed transfer.*/
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@@ -322,6 +336,11 @@ static void serve_usart_irq(UARTDriver *uartp) {
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/* End of transmission, a callback is generated.*/
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_uart_tx2_isr_code(uartp);
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}
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+
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+ /* Idle interrupt sources are only checked if enabled in CR1.*/
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+ if ((sr & USART_SR_IDLE) && (cr1 & USART_CR1_IDLEIE)) {
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+ _uart_timeout_isr_code(uartp);
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+ }
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}
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/*===========================================================================*/
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@@ -793,8 +812,14 @@ void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
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/* RX DMA channel preparation.*/
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dmaStreamSetMemory0(uartp->dmarx, rxbuf);
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dmaStreamSetTransactionSize(uartp->dmarx, n);
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- dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M |
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- STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
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+
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+ uint32_t mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
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+
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+ /* DMA half-transfer interrupt & circular mode, if needed */
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+ if (uartp->config->rxhalf_cb != NULL)
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+ mode |= STM32_DMA_CR_HTIE | STM32_DMA_CR_CIRC;
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+
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+ dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode);
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/* Starting transfer.*/
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dmaStreamEnable(uartp->dmarx);
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diff --git a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h
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index fcf73e7fb..a0b1c1a96 100644
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--- a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h
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+++ b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h
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@@ -462,6 +462,14 @@ typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c);
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*/
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typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e);
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+/**
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+ * @brief Receive Half-transfer UART notification callback type.
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+ *
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+ * @param[in] uartp pointer to the @p UARTDriver object
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+ * @param[in] full flag set to 1 for the second half, and 0 for the first half
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+ */
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+typedef void (*uarthcb_t)(UARTDriver *uartp, uartflags_t full);
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+
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/**
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* @brief Driver configuration structure.
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* @note It could be empty on some architectures.
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@@ -504,6 +512,16 @@ typedef struct {
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* @brief Initialization value for the CR3 register.
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*/
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uint16_t cr3;
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+ /* Additional (optional) handlers. Placed here for the struct compatibility.*/
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+ /**
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+ * @brief Receiver timeout (idle) callback.
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+ * @details Handles an idle interrupt for USARTv1.
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+ */
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+ uartcb_t timeout_cb;
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+ /**
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+ * @brief Half-transfer receive buffer callback.
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+ */
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+ uarthcb_t rxhalf_cb;
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} UARTConfig;
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/**
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diff --git a/os/rt/include/chdebug.h b/os/rt/include/chdebug.h
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index 43163bed1..f7f86e19c 100644
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--- a/os/rt/include/chdebug.h
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+++ b/os/rt/include/chdebug.h
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@@ -60,9 +60,10 @@
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/* Module macros. */
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/*===========================================================================*/
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+//rusEfi additional hooks
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#if CH_DBG_SYSTEM_STATE_CHECK == TRUE
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-#define _dbg_enter_lock() (ch.dbg.lock_cnt = (cnt_t)1)
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-#define _dbg_leave_lock() (ch.dbg.lock_cnt = (cnt_t)0)
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+#define _dbg_enter_lock() {(ch.dbg.lock_cnt = (cnt_t)1); ON_LOCK_HOOK;}
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+#define _dbg_leave_lock() {ON_UNLOCK_HOOK;(ch.dbg.lock_cnt = (cnt_t)0);}
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#endif
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/* When the state checker feature is disabled then the following functions
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