mirror of https://github.com/rusefi/rusefi.git
127 lines
4.9 KiB
C
127 lines
4.9 KiB
C
/**
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* @file main_hardfault.c
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*
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* This black magic improves hard fault debugging experience
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*
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* http://www.chibios.com/forum/viewtopic.php?t=2506
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*/
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#include "hal.h"
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#include <string.h>
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/**
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* Executes the BKPT instruction that causes the debugger to stop.
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* If no debugger is attached, this will be ignored
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*/
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#define bkpt() __asm volatile("BKPT #0\n")
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void NMI_Handler(void) {
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NVIC_SystemReset();
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}
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//See http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/BABBGBEC.html
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typedef enum {
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Reset = 1,
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NMI = 2,
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HardFault = 3,
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MemManage = 4,
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BusFault = 5,
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UsageFault = 6,
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} FaultType;
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void logHardFault(uint32_t type, uintptr_t faultAddress, struct port_extctx* ctx, uint32_t csfr);
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void HardFault_Handler_C(void* sp) {
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//Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info
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//Get thread context. Contains main registers including PC and LR
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struct port_extctx ctx;
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memcpy(&ctx, sp, sizeof(struct port_extctx));
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//Interrupt status register: Which interrupt have we encountered, e.g. HardFault?
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FaultType faultType = (FaultType)__get_IPSR();
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(void)faultType;
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//For HardFault/BusFault this is the address that was accessed causing the error
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uint32_t faultAddress = SCB->BFAR;
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//Flags about hardfault / busfault
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//See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference
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bool isFaultPrecise = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 1) ? true : false);
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bool isFaultImprecise = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 2) ? true : false);
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bool isFaultOnUnstacking = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 3) ? true : false);
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bool isFaultOnStacking = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 4) ? true : false);
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bool isFaultAddressValid = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 7) ? true : false);
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(void)isFaultPrecise;
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(void)isFaultImprecise;
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(void)isFaultOnUnstacking;
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(void)isFaultOnStacking;
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(void)isFaultAddressValid;
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logHardFault(faultType, faultAddress, &ctx, SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos);
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//Cause debugger to stop. Ignored if no debugger is attached
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bkpt();
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NVIC_SystemReset();
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}
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void UsageFault_Handler_C(void* sp) {
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//Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info
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//Get thread context. Contains main registers including PC and LR
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struct port_extctx ctx;
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memcpy(&ctx, sp, sizeof(struct port_extctx));
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//Interrupt status register: Which interrupt have we encountered, e.g. HardFault?
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FaultType faultType = (FaultType)__get_IPSR();
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(void)faultType;
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//Flags about hardfault / busfault
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//See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference
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bool isUndefinedInstructionFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 0) ? true : false);
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bool isEPSRUsageFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 1) ? true : false);
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bool isInvalidPCFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 2) ? true : false);
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bool isNoCoprocessorFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 3) ? true : false);
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bool isUnalignedAccessFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 8) ? true : false);
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bool isDivideByZeroFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 9) ? true : false);
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(void)isUndefinedInstructionFault;
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(void)isEPSRUsageFault;
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(void)isInvalidPCFault;
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(void)isNoCoprocessorFault;
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(void)isUnalignedAccessFault;
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(void)isDivideByZeroFault;
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logHardFault(faultType, 0, &ctx, SCB->CFSR);
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bkpt();
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NVIC_SystemReset();
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}
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void MemManage_Handler_C(void* sp) {
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//Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info
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//Get thread context. Contains main registers including PC and LR
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struct port_extctx ctx;
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memcpy(&ctx, sp, sizeof(struct port_extctx));
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//Interrupt status register: Which interrupt have we encountered, e.g. HardFault?
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FaultType faultType = (FaultType)__get_IPSR();
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(void)faultType;
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//For HardFault/BusFault this is the address that was accessed causing the error
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uint32_t faultAddress = SCB->MMFAR;
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//Flags about hardfault / busfault
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//See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference
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bool isInstructionAccessViolation = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 0) ? true : false);
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bool isDataAccessViolation = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 1) ? true : false);
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bool isExceptionUnstackingFault = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 3) ? true : false);
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bool isExceptionStackingFault = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 4) ? true : false);
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bool isFaultAddressValid = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 7) ? true : false);
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(void)isInstructionAccessViolation;
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(void)isDataAccessViolation;
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(void)isExceptionUnstackingFault;
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(void)isExceptionStackingFault;
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(void)isFaultAddressValid;
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logHardFault(faultType, faultAddress, &ctx, SCB->CFSR);
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bkpt();
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NVIC_SystemReset();
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}
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