mirror of https://github.com/rusefi/rusefi.git
345 lines
5.9 KiB
C
345 lines
5.9 KiB
C
/*
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* @file rusefi_hw_enums.h
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*
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* @date Jun 2, 2019
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* @author Andrey Belomutskiy, (c) 2012-2020
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*/
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#pragma once
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// todo: migrate/unify with pin_output_mode_e? rename? something is messy here
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// this enum is currently only used for SPI pins
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typedef enum __attribute__ ((__packed__)) {
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// todo: here we have a rare example of stm32-specific enum, todo: make this not stm32 specific?
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PO_DEFAULT = 0,
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PO_OPENDRAIN = 4, // PAL_STM32_OTYPE_OPENDRAIN
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PO_PULLUP = 32, // PAL_STM32_PUDR_PULLUP
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PO_PULLDOWN = 64 // PAL_STM32_PUPDR_PULLDOWN
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} pin_mode_e;
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/**
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* Hardware pin. This enum is platform-specific.
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*/
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enum class Gpio : uint16_t {
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Unassigned = 0,
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// only used as return value of 'parseBrainPin' function do we really this this logic special value at all?!
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Invalid = 1,
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A0 = 2,
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A1 = 3,
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A2 = 4,
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A3 = 5,
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A4 = 6,
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A5 = 7,
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A6 = 8,
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A7 = 9,
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A8 = 10,
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A9 = 11,
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A10 = 12,
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A11 = 13,
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A12 = 14,
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A13 = 15,
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A14 = 16,
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A15 = 17,
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B0 = 18,
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B1 = 19,
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B2 = 20,
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B3 = 21,
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B4 = 22,
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B5 = 23,
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B6 = 24,
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B7 = 25,
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B8 = 26,
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B9 = 27,
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B10 = 28,
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B11 = 29,
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B12 = 30,
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B13 = 31,
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B14 = 32,
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B15 = 33,
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C0 = 34,
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C1 = 35,
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C2 = 36,
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C3 = 37,
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C4 = 38,
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C5 = 39,
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C6 = 40,
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C7 = 41,
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C8 = 42,
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C9 = 43,
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C10 = 44,
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C11 = 45,
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C12 = 46,
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C13 = 47,
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C14 = 48,
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C15 = 49,
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D0 = 50,
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D1 = 51,
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D2 = 52,
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D3 = 53,
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D4 = 54,
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D5 = 55,
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D6 = 56,
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D7 = 57,
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D8 = 58,
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D9 = 59,
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D10 = 60,
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D11 = 61,
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D12 = 62,
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D13 = 63,
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D14 = 64,
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D15 = 65,
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E0 = 66,
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E1 = 67,
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E2 = 68,
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E3 = 69,
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E4 = 70,
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E5 = 71,
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E6 = 72,
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E7 = 73,
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E8 = 74,
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E9 = 75,
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E10 = 76,
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E11 = 77,
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E12 = 78,
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E13 = 79,
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E14 = 80,
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E15 = 81,
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F0 = 82,
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F1 = 83,
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F2 = 84,
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F3 = 85,
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F4 = 86,
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F5 = 87,
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F6 = 88,
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F7 = 89,
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F8 = 90,
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F9 = 91,
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F10 = 92,
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F11 = 93,
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F12 = 94,
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F13 = 95,
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F14 = 96,
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F15 = 97,
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G0 = 98,
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G1 = 99,
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G2 = 100,
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G3 = 101,
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G4 = 102,
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G5 = 103,
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G6 = 104,
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G7 = 105,
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G8 = 106,
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G9 = 107,
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G10 = 108,
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G11 = 109,
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G12 = 110,
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G13 = 111,
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G14 = 112,
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G15 = 113,
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H0 = 114,
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H1 = 115,
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H2 = 116,
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H3 = 117,
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H4 = 118,
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H5 = 119,
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H6 = 120,
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H7 = 121,
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H8 = 122,
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H9 = 123,
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H10 = 124,
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H11 = 125,
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H12 = 126,
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H13 = 127,
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H14 = 128,
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H15 = 129,
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/* Used by 176-pin STM32 MCUs */
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I0 = 130,
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I1 = 131,
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I2 = 132,
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I3 = 133,
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I4 = 134,
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I5 = 135,
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I6 = 136,
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I7 = 137,
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I8 = 138,
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I9 = 139,
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I10 = 140,
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I11 = 141,
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I12 = 142,
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I13 = 143,
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I14 = 144,
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I15 = 145,
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/* MC33972 pins go right after on_chip pins */
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MC33972_PIN_1 = 146,
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MC33972_PIN_21 = 166,
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MC33972_PIN_22 = 167,
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TLE8888_PIN_1 = 168,
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TLE8888_PIN_2 = 169,
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TLE8888_PIN_3 = 170,
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TLE8888_PIN_4 = 171,
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TLE8888_PIN_5 = 172,
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TLE8888_PIN_6 = 173,
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TLE8888_PIN_7 = 174,
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TLE8888_PIN_8 = 175,
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TLE8888_PIN_9 = 176,
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TLE8888_PIN_10 = 177,
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TLE8888_PIN_11 = 178,
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TLE8888_PIN_12 = 179,
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TLE8888_PIN_13 = 180,
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TLE8888_PIN_14 = 181,
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TLE8888_PIN_15 = 182,
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TLE8888_PIN_16 = 183,
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TLE8888_PIN_17 = 184,
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TLE8888_PIN_18 = 185,
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TLE8888_PIN_19 = 186,
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TLE8888_PIN_20 = 187,
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TLE8888_PIN_21 = 188,
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TLE8888_PIN_22 = 189,
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TLE8888_PIN_23 = 190,
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TLE8888_PIN_24 = 191,
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TLE8888_PIN_25 = 192,
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TLE8888_PIN_26 = 193,
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TLE8888_PIN_27 = 194,
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TLE8888_PIN_28 = 195,
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TLE8888_PIN_MR = 196,
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TLE8888_PIN_KEY = 197,
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TLE8888_PIN_WAKE = 198,
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/* TLE6240 pins */
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TLE6240_PIN_1 = 199,
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TLE6240_PIN_2 = 200,
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TLE6240_PIN_3 = 201,
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TLE6240_PIN_4 = 202,
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TLE6240_PIN_5 = 203,
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TLE6240_PIN_6 = 204,
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TLE6240_PIN_7 = 205,
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TLE6240_PIN_8 = 206,
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TLE6240_PIN_9 = 207,
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TLE6240_PIN_10 = 208,
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TLE6240_PIN_11 = 209,
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TLE6240_PIN_12 = 210,
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TLE6240_PIN_13 = 211,
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TLE6240_PIN_14 = 212,
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TLE6240_PIN_15 = 213,
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TLE6240_PIN_16 = 214,
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/* L9779 */
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L9779_IGN_1 = 215,
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L9779_IGN_2 = 216,
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L9779_IGN_3 = 217,
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L9779_IGN_4 = 218,
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L9779_OUT_1 = 219,
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L9779_OUT_2 = 220,
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L9779_OUT_3 = 221,
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L9779_OUT_4 = 222,
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L9779_OUT_5 = 223,
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L9779_OUT_6 = 224,
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L9779_OUT_7 = 225,
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L9779_OUT_8 = 226,
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L9779_OUT_9 = 227,
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L9779_OUT_10 = 228,
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L9779_OUT_11 = 229,
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L9779_OUT_12 = 230,
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L9779_OUT_13 = 231,
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L9779_OUT_14 = 232,
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L9779_OUT_15 = 233,
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L9779_OUT_16 = 234,
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L9779_OUT_17 = 235,
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L9779_OUT_18 = 236,
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L9779_OUT_19 = 237,
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L9779_OUT_20 = 238,
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L9779_OUT_A = 239,
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L9779_OUT_B = 240,
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L9779_OUT_C = 241,
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L9779_OUT_D = 242,
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L9779_OUT_25 = 243,
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L9779_OUT_26 = 244,
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L9779_OUT_27 = 245,
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L9779_OUT_28 = 246,
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L9779_OUT_MRD = 247,
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L9779_PIN_KEY = 248,
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CAN_PIN_0 = 249,
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CAN_PIN_1 = 250,
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CAN_PIN_2 = 251,
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CAN_PIN_3 = 252,
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CAN_PIN_4 = 253,
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CAN_PIN_5 = 254,
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CAN_PIN_6 = 255,
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CAN_PIN_7 = 256,
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PROTECTED_PIN_0 = 257,
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PROTECTED_PIN_1 = 258,
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PROTECTED_PIN_2 = 259,
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PROTECTED_PIN_3 = 260,
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PROTECTED_PIN_4 = 261,
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PROTECTED_PIN_5 = 262,
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PROTECTED_PIN_6 = 263,
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PROTECTED_PIN_7 = 264,
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PROTECTED_PIN_8 = 265,
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PROTECTED_PIN_9 = 266,
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PROTECTED_PIN_10 = 267,
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PROTECTED_PIN_11 = 268,
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PROTECTED_PIN_12 = 269,
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PROTECTED_PIN_13 = 270,
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PROTECTED_PIN_14 = 271,
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PROTECTED_PIN_15 = 272,
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};
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/* Please keep updating these defines */
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#define BRAIN_PIN_ONCHIP_LAST Gpio::I15
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#define BRAIN_PIN_ONCHIP_PINS (BRAIN_PIN_ONCHIP_LAST - Gpio::A0 + 1)
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#define BRAIN_PIN_LAST Gpio::PROTECTED_PIN_15
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#define BRAIN_PIN_TOTAL_PINS (BRAIN_PIN_LAST - Gpio::A0 + 1)
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/**
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* Frankenso analog #1 PC2 ADC12
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* Frankenso analog #2 PC1 ADC11
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* Frankenso analog #3 PA0 ADC0
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* Frankenso analog #4 PC3 ADC13
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* Frankenso analog #5 PA2 ADC2
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* Frankenso analog #6 PA1 ADC1
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* Frankenso analog #7 PA4 ADC4
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* Frankenso analog #8 PA3 ADC3
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* Frankenso analog #9 PA7 ADC7
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* Frankenso analog #10 PA6 ADC6
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* Frankenso analog #11 PC5 ADC15
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* Frankenso analog #12 PC4 ADC14
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*/
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typedef enum __attribute__ ((__packed__)) {
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EFI_ADC_NONE = 0,
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EFI_ADC_0 = 1, // PA0
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EFI_ADC_1 = 2, // PA1
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EFI_ADC_2 = 3, // PA2
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EFI_ADC_3 = 4, // PA3
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EFI_ADC_4 = 5, // PA4
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EFI_ADC_5 = 6, // PA5
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EFI_ADC_6 = 7, // PA6
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EFI_ADC_7 = 8, // PA7
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EFI_ADC_8 = 9, // PB0
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EFI_ADC_9 = 10, // PB1
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EFI_ADC_10 = 11, // PC0
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EFI_ADC_11 = 12, // PC1
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EFI_ADC_12 = 13, // PC2
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EFI_ADC_13 = 14, // PC3
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EFI_ADC_14 = 15, // PC4
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EFI_ADC_15 = 16, // PC5
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EFI_ADC_LAST_CHANNEL = 17, // Please keep this in sync with the last valid channel index!
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EFI_ADC_ERROR = 50,
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} adc_channel_e;
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