mirror of https://github.com/rusefi/rusefi.git
502 lines
13 KiB
C++
502 lines
13 KiB
C++
/*
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* tle6240.c
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*
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* TLE6240GP Smart 16-Channel Low-Side Switch
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*
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* All 16 channels can be controlled via the serial interface (SPI).
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* In addition to the serial control it is possible to control channel 1 to 4
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* and 9 to 12 direct in parallel with a separate input pin.
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*
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* Looks like 3.3v SI and SCLK are NOT possible (H above 0.7Vs required, that's 3.5v for 5.0Vs)
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* 5 MHz SPI
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* Update: looks like possible:
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* DS page 3: "Compatible with 3 V Microcontrollers"
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* DS page 12: "Input High Voltage 2.0 V min"
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*
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* @date Dec 29, 2018
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* @author Andrey Belomutskiy, (c) 2012-2020
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*
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* @date Mar 06, 2019
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* @author Andrey Gusakov, (c) 2019
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*/
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#include "pch.h"
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#include "gpio/gpio_ext.h"
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#include "gpio/tle6240.h"
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#if (BOARD_TLE6240_COUNT > 0)
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/*
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* TODO list:
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* - add irq support with fallback to polling mode (now polling mode only)
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* - handle low-active inputs (set with PRG pin). Now driver assume high-active
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* - add way to export native pin data of direct driven outputs. To avoid
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* call to tle6240_writePad that will finally call native gpio set/clear fn.
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* In this case direct drive gpios should not be occupied by markUsed in init?
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* - fill deinit function with some code?
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* - support emergency shutdown using reset pin
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* - convert diagnostic to some enum
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* - use DMA (currently there is issue (?) with SPI+DMA on STM32F7xx)
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*/
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/*==========================================================================*/
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/* Driver local definitions. */
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/*==========================================================================*/
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#define DRIVER_NAME "tle6240"
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static bool drv_task_ready = false;
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typedef enum {
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TLE6240_DISABLED = 0,
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TLE6240_WAIT_INIT,
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TLE6240_READY,
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TLE6240_FAILED
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} tle6240_drv_state;
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/* set 0000b for channes == 0..7 and 1111b for channels 8..15 */
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#define CMD_CHIP(ch) ((ch < 8) ? 0x00 : 0x0f)
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/* Full Diagnoscit, data byte ignored */
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#define CMD_FULL_DIAG(ch) (((0x00 | CMD_CHIP(ch)) << 8) | 0x00)
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/* Get state of 8 paralled inputs and 1-bit Diagnostic, data byte ignored */
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#define CMD_IO_SHORTDIAG(ch) (((0xc0 | CMD_CHIP(ch)) << 8) | 0x00)
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/* Echo function test of SPI, SI will be connected to SO on next access */
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#define CMD_ECHO(ch) (((0xA0 | CMD_CHIP(ch)) << 8) | 0x00)
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/* in data ORed, Full diagnostic output on next access */
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#define CMD_OR_DIAG(ch, data) (((0x30 | CMD_CHIP(ch)) << 8) | (data & 0xff))
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/* in data ANDed, Full diagnostic output on next access */
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#define CMD_AND_DIAG(ch, data) (((0xf0 | CMD_CHIP(ch)) << 8) | (data & 0xff))
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/*==========================================================================*/
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/* Driver exported variables. */
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/*==========================================================================*/
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/*==========================================================================*/
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/* Driver local variables and types. */
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/*==========================================================================*/
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/* OS */
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SEMAPHORE_DECL(tle6240_wake, 10 /* or BOARD_TLE6240_COUNT ? */);
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static THD_WORKING_AREA(tle6240_thread_1_wa, 256);
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/* Driver */
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struct Tle6240 : public GpioChip {
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int init() override;
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int writePad(size_t pin, int value) override;
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brain_pin_diag_e getDiag(size_t pin) override;
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// internal functions
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int spi_rw(uint16_t tx, uint16_t *rx);
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int update_output_and_diag();
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int chip_init();
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const tle6240_config *cfg;
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/* cached output state - state last send to chip */
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uint16_t o_state_cached;
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/* state to be sended to chip */
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uint16_t o_state;
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/* direct driven output mask */
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uint16_t o_direct_mask;
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/* full diagnostic status */
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uint16_t diag[2];
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/* diagnostic for ch 8..15 was requsted by last access
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* can skip one transaction next time */
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bool diag_8_reguested;
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tle6240_drv_state drv_state;
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};
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static Tle6240 chips[BOARD_TLE6240_COUNT];
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static const char* tle6240_pin_names[TLE6240_OUTPUTS] = {
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"tle6240.OUT1", "tle6240.OUT2", "tle6240.OUT3", "tle6240.OUT4",
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"tle6240.OUT5", "tle6240.OUT6", "tle6240.OUT7", "tle6240.OUT8",
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"tle6240.OUT9", "tle6240.OUT10", "tle6240.OUT11", "tle6240.OUT12",
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"tle6240.OUT13", "tle6240.OUT14", "tle6240.OUT15", "tle6240.OUT16",
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};
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/*==========================================================================*/
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/* Driver local functions. */
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/*==========================================================================*/
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/**
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* @brief TLE6240 send and receive routine.
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* @details Sends and receives 16 bits. CS asserted before and released
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* after transaction.
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*/
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int Tle6240::spi_rw(uint16_t tx, uint16_t *rx)
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{
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uint16_t rxb;
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SPIDriver *spi = cfg->spi_bus;
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/* Acquire ownership of the bus. */
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spiAcquireBus(spi);
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/* Setup transfer parameters. */
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spiStart(spi, &cfg->spi_config);
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/* Slave Select assertion. */
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spiSelect(spi);
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/* Atomic transfer operations. */
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rxb = spiPolledExchange(spi, tx);
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/* Slave Select de-assertion. */
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spiUnselect(spi);
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/* Ownership release. */
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spiReleaseBus(spi);
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if (rx)
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*rx = rxb;
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/* no errors for now */
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return 0;
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}
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/**
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* @brief TLE6240 send output registers data.
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* @details Sends ORed data to register, also receive 2-bit diagnostic.
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*/
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int Tle6240::update_output_and_diag()
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{
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int ret;
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uint16_t out_data;
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/* atomic */
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/* set value only for non-direct driven pins */
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out_data = o_state & (~o_direct_mask);
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if (diag_8_reguested) {
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/* diagnostic for OUT8..15 was requested on prev access */
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ret = spi_rw(CMD_OR_DIAG(0, (out_data >> 0) & 0xff), &diag[1]);
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ret |= spi_rw(CMD_OR_DIAG(8, (out_data >> 8) & 0xff), &diag[0]);
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} else {
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ret = spi_rw(CMD_OR_DIAG(0, (out_data >> 0) & 0xff), NULL);
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ret |= spi_rw(CMD_OR_DIAG(8, (out_data >> 8) & 0xff), &diag[0]);
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/* send same one more time to receive OUT8..15 diagnostic */
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ret |= spi_rw(CMD_OR_DIAG(8, (out_data >> 8) & 0xff), &diag[1]);
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}
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diag_8_reguested = false;
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if (ret == 0) {
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/* atomic */
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o_state_cached = out_data;
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diag_8_reguested = true;
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}
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return ret;
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}
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/**
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* @brief TLE6240 chip init.
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* @details Checks communication. Mark all used pins.
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* Checks direct io signals integrity using test cmd.
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* Reads initial diagnostic state.
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*/
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int Tle6240::chip_init()
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{
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int n;
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int ret;
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uint16_t rx;
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/* mark pins used */
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//ret = gpio_pin_markUsed(cfg->spi_config.ssport, cfg->spi_config.sspad, DRIVER_NAME " CS");
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ret = 0;
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if (cfg->reset.port != NULL)
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ret |= gpio_pin_markUsed(cfg->reset.port, cfg->reset.pad, DRIVER_NAME " RST");
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for (n = 0; n < TLE6240_DIRECT_OUTPUTS; n++)
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if (cfg->direct_io[n].port)
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ret |= gpio_pin_markUsed(cfg->direct_io[n].port, cfg->direct_io[n].pad, DRIVER_NAME " DIRECT IO");
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if (ret) {
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ret = -1;
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goto err_gpios;
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}
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/* release reset */
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if (cfg->reset.port) {
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palClearPort(cfg->reset.port,
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PAL_PORT_BIT(cfg->reset.pad));
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chThdSleepMilliseconds(1);
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palSetPort(cfg->reset.port,
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PAL_PORT_BIT(cfg->reset.pad));
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chThdSleepMilliseconds(10);
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}
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/* check SPI communication */
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/* 0. set echo mode, chip number - don't care */
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ret = spi_rw(CMD_ECHO(0), nullptr);
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/* 1. check loopback */
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ret |= spi_rw(0x5555, &rx);
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if (ret || (rx != 0x5555)) {
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//print(DRIVER_NAME " spi loopback test failed\n");
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ret = -2;
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goto err_gpios;
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}
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/* check direct io communication */
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/* 0. set all direct out to 0 */
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for (n = 0; n < TLE6240_DIRECT_OUTPUTS; n++) {
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int i = (n < 4) ? n : (n + 4);
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if (o_direct_mask & (1 << i)) {
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palClearPort(cfg->direct_io[n].port,
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PAL_PORT_BIT(cfg->direct_io[n].pad));
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}
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}
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/* 1. disable IN0..7 outputs first (ADNed with 0x00)
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* also will get full diag on next access */
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ret = spi_rw(CMD_AND_DIAG(0, 0x00), NULL);
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/* 2. get diag for OUT0..7 and send disable OUT8..15 */
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ret |= spi_rw(CMD_AND_DIAG(8, 0x00), &diag[0]);
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/* 3. get diag for OUT8..15 and readback input status */
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ret |= spi_rw(CMD_IO_SHORTDIAG(0), &diag[1]);
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/* 4. send dummy short diag command and get 8 bit of input data and
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* 8 bit of short diag */
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ret |= spi_rw(CMD_IO_SHORTDIAG(0), &rx);
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rx = ((rx >> 4) & 0x0f00) | ((rx >> 8) & 0x000f);
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if (ret || (rx & o_direct_mask)) {
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//print(DRIVER_NAME " direct io test #1 failed (invalid io mask %04x)\n", (rx & chip->o_direct_mask));
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ret = -3;
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goto err_gpios;
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}
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/* 5. set all direct io to 1 */
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for (n = 0; n < TLE6240_DIRECT_OUTPUTS; n++) {
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int i = (n < 4) ? n : (n + 4);
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if (o_direct_mask & (1 << i)) {
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palSetPort(cfg->direct_io[n].port,
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PAL_PORT_BIT(cfg->direct_io[n].pad));
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}
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}
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/* 6. read chort diagnostic again */
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ret |= spi_rw(CMD_IO_SHORTDIAG(0), &rx);
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rx = ((rx >> 4) & 0x0f00) | ((rx >> 8) & 0x000f);
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rx &= o_direct_mask;
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if (ret || (rx != o_direct_mask)) {
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//print(DRIVER_NAME " direct io test #2 failed (invalid io mask %04x)\n", (rx ^ (~chip->o_direct_mask)));
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ret = -4;
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goto err_gpios;
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}
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/* 7. set all all pins to OR mode, and upload pin states */
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ret = update_output_and_diag();
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if (ret) {
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//print(DRIVER_NAME " final setup error\n");
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ret = -5;
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goto err_gpios;
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}
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return 0;
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err_gpios:
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/* unmark pins */
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//gpio_pin_markUnused(cfg->spi_config.ssport, cfg->spi_config.sspad);
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if (cfg->reset.port != NULL)
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gpio_pin_markUnused(cfg->reset.port, cfg->reset.pad);
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for (n = 0; n < TLE6240_DIRECT_OUTPUTS; n++)
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if (cfg->direct_io[n].port)
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gpio_pin_markUnused(cfg->direct_io[n].port, cfg->direct_io[n].pad);
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return ret;
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}
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/**
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* @brief TLE6240 chip driver wakeup.
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* @details Wake up driver. Will cause output register and
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* diagnostic update.
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*/
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static int tle6240_wake_driver()
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{
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/* Entering a reentrant critical zone.*/
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chibios_rt::CriticalSectionLocker csl;
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chSemSignalI(&tle6240_wake);
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if (!port_is_isr_context()) {
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/**
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* chSemSignalI above requires rescheduling
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* interrupt handlers have implicit rescheduling
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*/
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chSchRescheduleS();
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}
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return 0;
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}
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/*==========================================================================*/
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/* Driver thread. */
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/*==========================================================================*/
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static THD_FUNCTION(tle6240_driver_thread, p)
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{
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int i;
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msg_t msg;
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(void)p;
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chRegSetThreadName(DRIVER_NAME);
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while(1) {
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msg = chSemWaitTimeout(&tle6240_wake, TIME_MS2I(TLE6240_POLL_INTERVAL_MS));
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/* should we care about msg == MSG_TIMEOUT? */
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(void)msg;
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for (i = 0; i < BOARD_TLE6240_COUNT; i++) {
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int ret;
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Tle6240& chip = chips[i];
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if (!chip.cfg ||
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(chip.drv_state == TLE6240_DISABLED) ||
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(chip.drv_state == TLE6240_FAILED))
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continue;
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ret = chip.update_output_and_diag();
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if (ret) {
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/* set state to TLE6240_FAILED? */
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}
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}
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}
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}
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/*==========================================================================*/
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/* Driver interrupt handlers. */
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/*==========================================================================*/
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/* TODO: add IRQ support */
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/*==========================================================================*/
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/* Driver exported functions. */
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/*==========================================================================*/
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int Tle6240::writePad(unsigned int pin, int value)
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{
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if (pin >= TLE6240_OUTPUTS)
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return -1;
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{
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chibios_rt::CriticalSectionLocker csl;
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if (value)
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o_state |= (1 << pin);
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else
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o_state &= ~(1 << pin);
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}
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/* direct driven? */
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if (o_direct_mask & (1 << pin)) {
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int n = (pin < 8) ? pin : (pin - 4);
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/* TODO: ensure that TLE6240 configured in active high mode */
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if (value)
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palSetPort(cfg->direct_io[n].port,
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PAL_PORT_BIT(cfg->direct_io[n].pad));
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else
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palClearPort(cfg->direct_io[n].port,
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PAL_PORT_BIT(cfg->direct_io[n].pad));
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} else {
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tle6240_wake_driver();
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}
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return 0;
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}
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brain_pin_diag_e Tle6240::getDiag(size_t pin)
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{
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int val;
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int diagVal;
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if (pin >= TLE6240_OUTPUTS)
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return PIN_UNKNOWN;
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val = (diag[(pin > 7) ? 1 : 0] >> ((pin % 8) * 2)) & 0x03;
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if (val == 0x3)
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diagVal = PIN_OK;
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else if (val == 0x2)
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/* Overload, shorted load or overtemperature */
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diagVal = PIN_OVERLOAD | PIN_DRIVER_OVERTEMP;
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else if (val == 0x1)
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diagVal = PIN_OPEN;
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else if (val == 0x0)
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diagVal = PIN_SHORT_TO_GND;
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return static_cast<brain_pin_diag_e>(diagVal);
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}
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int Tle6240::init()
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{
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int ret = chip_init();
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if (ret)
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return ret;
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drv_state = TLE6240_READY;
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if (!drv_task_ready) {
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chThdCreateStatic(tle6240_thread_1_wa, sizeof(tle6240_thread_1_wa),
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PRIO_GPIOCHIP, tle6240_driver_thread, nullptr);
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drv_task_ready = true;
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}
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return 0;
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}
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/**
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* @brief TLE6240 driver add.
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* @details Checks for valid config
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*/
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int tle6240_add(brain_pin_e base, unsigned int index, const tle6240_config *cfg)
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{
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int i;
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int ret;
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Tle6240 *chip;
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/* no config or no such chip */
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if ((!cfg) || (!cfg->spi_bus) || (index >= BOARD_TLE6240_COUNT))
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return -1;
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/* check for valid cs.
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* TODO: remove this check? CS can be driven by SPI */
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//if (cfg->spi_config.ssport == NULL)
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// return -1;
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chip = &chips[index];
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/* already initted? */
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if (chip->cfg != NULL)
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return -1;
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chip->cfg = cfg;
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chip->o_state = 0;
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chip->o_state_cached = 0;
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chip->o_direct_mask = 0;
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chip->drv_state = TLE6240_WAIT_INIT;
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for (i = 0; i < TLE6240_DIRECT_OUTPUTS; i++) {
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if (cfg->direct_io[i].port != 0)
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chip->o_direct_mask |= (1 << ((i < 4) ? i : (i + 4)));
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}
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/* register, return gpio chip base */
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ret = gpiochip_register(base, DRIVER_NAME, *chip, TLE6240_OUTPUTS);
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if (ret < 0)
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return ret;
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/* set default pin names, board init code can rewrite */
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gpiochips_setPinNames(base, tle6240_pin_names);
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return ret;
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}
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#else /* BOARD_TLE6240_COUNT > 0 */
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int tle6240_add(brain_pin_e base, unsigned int index, const tle6240_config *cfg)
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{
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(void)base; (void)index; (void)cfg;
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return -1;
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}
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#endif /* BOARD_TLE6240_COUNT */
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