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Add some ground work for Teensy inj and ign channels 5-8

This commit is contained in:
Josh Stewart 2017-02-20 21:34:28 +11:00
parent 4f5d1afdae
commit b7aacc6040
2 changed files with 64 additions and 8 deletions
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36
speeduino/scheduler.h
View File

@ -84,45 +84,73 @@ See page 136 of the processors datasheet: http://www.atmel.com/Images/doc2549.pd
#define FUEL2_COUNTER FTM0_CNT
#define FUEL3_COUNTER FTM0_CNT
#define FUEL4_COUNTER FTM0_CNT
#define FUEL5_COUNTER FTM3_CNT
#define FUEL6_COUNTER FTM3_CNT
#define FUEL7_COUNTER FTM3_CNT
#define FUEL8_COUNTER FTM3_CNT
#define IGN1_COUNTER FTM0_CNT
#define IGN2_COUNTER FTM0_CNT
#define IGN3_COUNTER FTM0_CNT
#define IGN4_COUNTER FTM0_CNT
#define IGN5_COUNTER FTM1_CNT
#define IGN5_COUNTER FTM3_CNT
#define IGN6_COUNTER FTM3_CNT
#define IGN7_COUNTER FTM3_CNT
#define IGN8_COUNTER FTM3_CNT
#define FUEL1_COMPARE FTM0_C0V
#define FUEL2_COMPARE FTM0_C1V
#define FUEL3_COMPARE FTM0_C2V
#define FUEL4_COMPARE FTM0_C3V
#define FUEL5_COMPARE FTM3_C0V
#define FUEL6_COMPARE FTM3_C1V
#define FUEL7_COMPARE FTM3_C2V
#define FUEL8_COMPARE FTM3_C3V
#define IGN1_COMPARE FTM0_C4V
#define IGN2_COMPARE FTM0_C5V
#define IGN3_COMPARE FTM0_C6V
#define IGN4_COMPARE FTM0_C7V
#define IGN5_COMPARE FTM1_C0V
#define IGN5_COMPARE FTM3_C4V
#define IGN6_COMPARE FTM3_C5V
#define IGN7_COMPARE FTM3_C6V
#define IGN8_COMPARE FTM3_C7V
#define FUEL1_TIMER_ENABLE() FTM0_C0SC |= FTM_CSC_CHIE //Write 1 to the CHIE (Channel Interrupt Enable) bit of channel 0 Status/Control
#define FUEL2_TIMER_ENABLE() FTM0_C1SC |= FTM_CSC_CHIE
#define FUEL3_TIMER_ENABLE() FTM0_C2SC |= FTM_CSC_CHIE
#define FUEL4_TIMER_ENABLE() FTM0_C3SC |= FTM_CSC_CHIE
#define FUEL5_TIMER_ENABLE() FTM3_C0SC |= FTM_CSC_CHIE
#define FUEL6_TIMER_ENABLE() FTM3_C1SC |= FTM_CSC_CHIE
#define FUEL7_TIMER_ENABLE() FTM3_C2SC |= FTM_CSC_CHIE
#define FUEL8_TIMER_ENABLE() FTM3_C3SC |= FTM_CSC_CHIE
#define FUEL1_TIMER_DISABLE() FTM0_C0SC &= ~FTM_CSC_CHIE //Write 0 to the CHIE (Channel Interrupt Enable) bit of channel 0 Status/Control
#define FUEL2_TIMER_DISABLE() FTM0_C1SC &= ~FTM_CSC_CHIE
#define FUEL3_TIMER_DISABLE() FTM0_C2SC &= ~FTM_CSC_CHIE
#define FUEL4_TIMER_DISABLE() FTM0_C3SC &= ~FTM_CSC_CHIE
#define FUEL5_TIMER_DISABLE() FTM3_C0SC &= ~FTM_CSC_CHIE //Write 0 to the CHIE (Channel Interrupt Enable) bit of channel 0 Status/Control
#define FUEL6_TIMER_DISABLE() FTM3_C1SC &= ~FTM_CSC_CHIE
#define FUEL7_TIMER_DISABLE() FTM3_C2SC &= ~FTM_CSC_CHIE
#define FUEL8_TIMER_DISABLE() FTM3_C3SC &= ~FTM_CSC_CHIE
#define IGN1_TIMER_ENABLE() FTM0_C4SC |= FTM_CSC_CHIE
#define IGN2_TIMER_ENABLE() FTM0_C5SC |= FTM_CSC_CHIE
#define IGN3_TIMER_ENABLE() FTM0_C6SC |= FTM_CSC_CHIE
#define IGN4_TIMER_ENABLE() FTM0_C7SC |= FTM_CSC_CHIE
#define IGN5_TIMER_ENABLE() FTM1_C0SC |= FTM_CSC_CHIE
#define IGN5_TIMER_ENABLE() FTM3_C4SC |= FTM_CSC_CHIE
#define IGN6_TIMER_ENABLE() FTM3_C5SC |= FTM_CSC_CHIE
#define IGN7_TIMER_ENABLE() FTM3_C6SC |= FTM_CSC_CHIE
#define IGN8_TIMER_ENABLE() FTM3_C7SC |= FTM_CSC_CHIE
#define IGN1_TIMER_DISABLE() FTM0_C4SC &= ~FTM_CSC_CHIE
#define IGN2_TIMER_DISABLE() FTM0_C5SC &= ~FTM_CSC_CHIE
#define IGN3_TIMER_DISABLE() FTM0_C6SC &= ~FTM_CSC_CHIE
#define IGN4_TIMER_DISABLE() FTM0_C7SC &= ~FTM_CSC_CHIE
#define IGN5_TIMER_DISABLE() FTM1_C0SC &= ~FTM_CSC_CHIE
#define IGN5_TIMER_DISABLE() FTM3_C4SC &= ~FTM_CSC_CHIE
#define IGN6_TIMER_DISABLE() FTM3_C5SC &= ~FTM_CSC_CHIE
#define IGN7_TIMER_DISABLE() FTM3_C6SC &= ~FTM_CSC_CHIE
#define IGN8_TIMER_DISABLE() FTM3_C7SC &= ~FTM_CSC_CHIE
#define MAX_TIMER_PERIOD 139808 // 2.13333333uS * 65535
#define uS_TO_TIMER_COMPARE(uS) ((uS * 15) >> 5) //Converts a given number of uS into the required number of timer ticks until that time has passed.

36
speeduino/scheduler.ino
View File

@ -122,10 +122,38 @@ void initialiseSchedulers()
FTM0_C7SC |= FTM_CSC_MSA; //Enable Compare mode
FTM0_C7SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
//Do the same, but on flex timer 1 (Used for channels 5+)
FTM1_C0SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
FTM1_C0SC |= FTM_CSC_MSA; //Enable Compare mode
FTM1_C0SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
//Do the same, but on flex timer 3 (Used for channels 5-8)
FTM3_C0SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
FTM3_C0SC |= FTM_CSC_MSA; //Enable Compare mode
FTM3_C0SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
FTM3_C1SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
FTM3_C1SC |= FTM_CSC_MSA; //Enable Compare mode
FTM3_C1SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
FTM3_C2SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
FTM3_C2SC |= FTM_CSC_MSA; //Enable Compare mode
FTM3_C2SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
FTM3_C3SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
FTM3_C3SC |= FTM_CSC_MSA; //Enable Compare mode
FTM3_C3SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
FTM3_C4SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
FTM3_C4SC |= FTM_CSC_MSA; //Enable Compare mode
FTM3_C4SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
FTM3_C5SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
FTM3_C5SC |= FTM_CSC_MSA; //Enable Compare mode
FTM3_C5SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
FTM3_C6SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
FTM3_C6SC |= FTM_CSC_MSA; //Enable Compare mode
FTM3_C6SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
FTM3_C7SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
FTM3_C7SC |= FTM_CSC_MSA; //Enable Compare mode
FTM3_C7SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
// enable IRQ Interrupt
NVIC_ENABLE_IRQ(IRQ_FTM0);