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Fix fault handlers for Cortex-M0 (#180)

This commit is contained in:
Andrey G 2023-01-16 14:49:00 +03:00 committed by GitHub
parent e5a7952db0
commit 2132e50c93
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1 changed files with 6 additions and 0 deletions
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6
firmware/main.cpp
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@ -100,6 +100,7 @@ extern "C" void HardFault_Handler_C(void* sp) {
//Interrupt status register: Which interrupt have we encountered, e.g. HardFault? //Interrupt status register: Which interrupt have we encountered, e.g. HardFault?
FaultType faultType = (FaultType)__get_IPSR(); FaultType faultType = (FaultType)__get_IPSR();
(void)faultType; (void)faultType;
#if (__CORTEX_M > 0)
//For HardFault/BusFault this is the address that was accessed causing the error //For HardFault/BusFault this is the address that was accessed causing the error
uint32_t faultAddress = SCB->BFAR; uint32_t faultAddress = SCB->BFAR;
@ -115,6 +116,7 @@ extern "C" void HardFault_Handler_C(void* sp) {
(void)isFaultOnUnstacking; (void)isFaultOnUnstacking;
(void)isFaultOnStacking; (void)isFaultOnStacking;
(void)isFaultAddressValid; (void)isFaultAddressValid;
#endif
//Cause debugger to stop. Ignored if no debugger is attached //Cause debugger to stop. Ignored if no debugger is attached
bkpt(); bkpt();
@ -130,6 +132,7 @@ extern "C" void UsageFault_Handler_C(void* sp) {
//Interrupt status register: Which interrupt have we encountered, e.g. HardFault? //Interrupt status register: Which interrupt have we encountered, e.g. HardFault?
FaultType faultType = (FaultType)__get_IPSR(); FaultType faultType = (FaultType)__get_IPSR();
(void)faultType; (void)faultType;
#if (__CORTEX_M > 0)
//Flags about hardfault / busfault //Flags about hardfault / busfault
//See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference //See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference
bool isUndefinedInstructionFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 0) ? true : false); bool isUndefinedInstructionFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 0) ? true : false);
@ -144,6 +147,7 @@ extern "C" void UsageFault_Handler_C(void* sp) {
(void)isNoCoprocessorFault; (void)isNoCoprocessorFault;
(void)isUnalignedAccessFault; (void)isUnalignedAccessFault;
(void)isDivideByZeroFault; (void)isDivideByZeroFault;
#endif
bkpt(); bkpt();
NVIC_SystemReset(); NVIC_SystemReset();
@ -158,6 +162,7 @@ extern "C" void MemManage_Handler_C(void* sp) {
//Interrupt status register: Which interrupt have we encountered, e.g. HardFault? //Interrupt status register: Which interrupt have we encountered, e.g. HardFault?
FaultType faultType = (FaultType)__get_IPSR(); FaultType faultType = (FaultType)__get_IPSR();
(void)faultType; (void)faultType;
#if (__CORTEX_M > 0)
//For HardFault/BusFault this is the address that was accessed causing the error //For HardFault/BusFault this is the address that was accessed causing the error
uint32_t faultAddress = SCB->MMFAR; uint32_t faultAddress = SCB->MMFAR;
@ -173,6 +178,7 @@ extern "C" void MemManage_Handler_C(void* sp) {
(void)isExceptionUnstackingFault; (void)isExceptionUnstackingFault;
(void)isExceptionStackingFault; (void)isExceptionStackingFault;
(void)isFaultAddressValid; (void)isFaultAddressValid;
#endif
bkpt(); bkpt();
NVIC_SystemReset(); NVIC_SystemReset();