From 25c5e249d92e08ed9a4dd82e9a58bd1d1cf0b059 Mon Sep 17 00:00:00 2001 From: rusefillc <48498823+rusefillc@users.noreply.github.com> Date: Thu, 27 Apr 2023 17:12:48 -0400 Subject: [PATCH] Dual 1 (#241) * f1_dual_rev1: add pinmux settings for port F and G To supress compiler warning. (cherry picked from commit 89876fe8eaad933308b63a4b0b1666deb75bfc84) * f1_dual_rev1: fix remaps -disable JTAG to free PA15, PB3, PB4 -use SPI3 for EGT chips without remaping (cherry picked from commit 598f1aa0779ba6e90ccf2eb74445d074f2bfbc75) * f1_dual_rev1: disable unused TIM1, TIM2 (cherry picked from commit 9e71c3813fd09c080c0eb2f1e63fe82b475efb4f) * f1_dual_rev1: run at 72MHz from HSE (cherry picked from commit eaa4577ef85bdfdba637c203646883202a1f8e02) * f1_dual_rev1: fix can timings (cherry picked from commit 6437b3d92047adefe6534efaa57062bdda449d37) * f1_dual_rev1: add CAN timings for 125L, 250K and 1Mbps (cherry picked from commit bc988d10dda43bfc8b4566de274e3b99bc6b8a5e) --------- Co-authored-by: Andrey Gusakov --- firmware/boards/f1_dual_rev1/board.c | 6 ++-- firmware/boards/f1_dual_rev1/board.h | 16 ++++++++++ firmware/boards/f1_dual_rev1/mcuconf.h | 23 +++++++------ firmware/boards/f1_dual_rev1/port_shared.cpp | 32 +++++++++++++++++-- .../f1_dual_rev1/wideband_board_config.h | 2 +- 5 files changed, 62 insertions(+), 17 deletions(-) diff --git a/firmware/boards/f1_dual_rev1/board.c b/firmware/boards/f1_dual_rev1/board.c index 8dd0f57..d5d4458 100644 --- a/firmware/boards/f1_dual_rev1/board.c +++ b/firmware/boards/f1_dual_rev1/board.c @@ -30,6 +30,8 @@ const PALConfig pal_default_config = {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, + {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH}, + {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH}, }; #endif @@ -46,6 +48,6 @@ void __early_init(void) { * Board-specific initialization code. */ void boardInit(void) { - AFIO->MAPR |= AFIO_MAPR_SPI1_REMAP | /* remap SPI1 to PB3, PB4, PB5 and PA15 */ - AFIO_MAPR_I2C1_REMAP; /* remap I2C1 to PB8, PB9 */ + AFIO->MAPR |= AFIO_MAPR_I2C1_REMAP | /* remap I2C1 to PB8, PB9 */ + AFIO_MAPR_SWJ_CFG_1; /* JTAG-DP disabled, SW-DP enabled, PA13, PA14 are only used */ } diff --git a/firmware/boards/f1_dual_rev1/board.h b/firmware/boards/f1_dual_rev1/board.h index 1b1615a..5c2530e 100644 --- a/firmware/boards/f1_dual_rev1/board.h +++ b/firmware/boards/f1_dual_rev1/board.h @@ -162,6 +162,22 @@ #define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */ #define VAL_GPIOEODR 0x0000FFFF +/* + * Port F setup. + * Everything input with pull-up except: + */ +#define VAL_GPIOFCRL 0x88888888 /* PF7...PF0 */ +#define VAL_GPIOFCRH 0x88888888 /* PF15...PF8 */ +#define VAL_GPIOFODR 0x0000FFFF + +/* + * Port G setup. + * Everything input with pull-up except: + */ +#define VAL_GPIOGCRL 0x88888888 /* PG7...PG0 */ +#define VAL_GPIOGCRH 0x88888888 /* PG15...PG8 */ +#define VAL_GPIOGODR 0x0000FFFF + /* * USB bus activation macro, required by the USB driver. */ diff --git a/firmware/boards/f1_dual_rev1/mcuconf.h b/firmware/boards/f1_dual_rev1/mcuconf.h index 5f217fa..b242b1e 100644 --- a/firmware/boards/f1_dual_rev1/mcuconf.h +++ b/firmware/boards/f1_dual_rev1/mcuconf.h @@ -35,26 +35,25 @@ /* * HAL driver system settings. - * TL,DR: we run at 48MHz. - * It's not possible to run at 72 on HSI because of the PLL's limited configuration options, so 48MHz right now. + * We run at 72MHz from HSE. */ #define STM32_NO_INIT FALSE #define STM32_HSI_ENABLED TRUE #define STM32_LSI_ENABLED FALSE -#define STM32_HSE_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE #define STM32_LSE_ENABLED FALSE #define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLSRC STM32_PLLSRC_HSE #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#define STM32_PLLMUL_VALUE 12 +#define STM32_PLLMUL_VALUE 9 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV2 -#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV2 #define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_USB_CLOCK_REQUIRED TRUE -#define STM32_USBPRE STM32_USBPRE_DIV1 +#define STM32_USBPRE STM32_USBPRE_DIV1P5 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 @@ -145,8 +144,8 @@ * PWM driver system settings. */ #define STM32_PWM_USE_ADVANCED TRUE -#define STM32_PWM_USE_TIM1 TRUE -#define STM32_PWM_USE_TIM2 TRUE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 TRUE #define STM32_PWM_USE_TIM5 FALSE @@ -180,9 +179,9 @@ /* * SPI driver system settings. */ -#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI1 FALSE #define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI3 TRUE #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 diff --git a/firmware/boards/f1_dual_rev1/port_shared.cpp b/firmware/boards/f1_dual_rev1/port_shared.cpp index 8647809..440755c 100644 --- a/firmware/boards/f1_dual_rev1/port_shared.cpp +++ b/firmware/boards/f1_dual_rev1/port_shared.cpp @@ -2,15 +2,43 @@ // board-specific stuff shared between bootloader and firmware +static const CANConfig canConfig125 = +{ + CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP, + /* + For 36MHz http://www.bittiming.can-wiki.info/ gives us Pre-scaler=18, Seq 1=13 and Seq 2=2. Subtract '1' for register values + */ + CAN_BTR_BRP(17) | CAN_BTR_TS1(12) | CAN_BTR_TS2(1) | CAN_BTR_SJW(0), +}; + +static const CANConfig canConfig250 = +{ + CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP, + /* + For 36MHz http://www.bittiming.can-wiki.info/ gives us Pre-scaler=9, Seq 1=13 and Seq 2=2. Subtract '1' for register values + */ + CAN_BTR_BRP(8) | CAN_BTR_TS1(12) | CAN_BTR_TS2(1) | CAN_BTR_SJW(0), +}; + static const CANConfig canConfig500 = { CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP, /* - For 24MHz http://www.bittiming.can-wiki.info/ gives us Pre-scaler=3, Seq 1=13 and Seq 2=2. Subtract '1' for register values + For 36MHz http://www.bittiming.can-wiki.info/ gives us Pre-scaler=4, Seq 1=15 and Seq 2=2. Subtract '1' for register values */ - CAN_BTR_SJW(0) | CAN_BTR_BRP(2) | CAN_BTR_TS1(12) | CAN_BTR_TS2(1), + CAN_BTR_BRP(3) | CAN_BTR_TS1(14) | CAN_BTR_TS2(1) | CAN_BTR_SJW(0), }; +static const CANConfig canConfig1000 = +{ + CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP, + /* + For 36MHz http://www.bittiming.can-wiki.info/ gives us Pre-scaler=2, Seq 1=15 and Seq 2=2. Subtract '1' for register values + */ + CAN_BTR_BRP(1) | CAN_BTR_TS1(14) | CAN_BTR_TS2(1) | CAN_BTR_SJW(0), +}; + + const CANConfig& GetCanConfig() { return canConfig500; } diff --git a/firmware/boards/f1_dual_rev1/wideband_board_config.h b/firmware/boards/f1_dual_rev1/wideband_board_config.h index 887d008..9bc190f 100644 --- a/firmware/boards/f1_dual_rev1/wideband_board_config.h +++ b/firmware/boards/f1_dual_rev1/wideband_board_config.h @@ -68,7 +68,7 @@ // ******************************* // MAX31855 spi port // ******************************* -#define EGT_SPI_DRIVER (&SPID1) +#define EGT_SPI_DRIVER (&SPID3) // Serial connection over BT module // enable BT module setup attempt