diff --git a/firmware/auxout.cpp b/firmware/auxout.cpp
index e5f4f51..dedcc26 100644
--- a/firmware/auxout.cpp
+++ b/firmware/auxout.cpp
@@ -16,8 +16,9 @@
 
 // Rev2 low pass filter cut frequency is about 21Hz (sic!)
 // 48Mhz / (2 ^ 12) ~= 12 KHz
+// 64mhz / (2 ^ 12) ~= 16 KHz
 static const PWMConfig auxPwmConfig = {
-    48'000'000,
+    STM32_SYSCLK,
     1 << 12,
     nullptr,
     {
diff --git a/firmware/boards/f1_dual/mcuconf.h b/firmware/boards/f1_dual/mcuconf.h
index 3c4fae8..db8539c 100644
--- a/firmware/boards/f1_dual/mcuconf.h
+++ b/firmware/boards/f1_dual/mcuconf.h
@@ -35,8 +35,7 @@
 
 /*
  * HAL driver system settings.
- * TL,DR: we run at 48MHz.
- * It's not possible to run at 72 on HSI because of the PLL's limited configuration options, so 48MHz right now.
+ * Main clock runs at 64MHz, impossible to run maximum rated 72 using HSI due to PLL limitations
  */
 #define STM32_NO_INIT                       FALSE
 #define STM32_HSI_ENABLED                   TRUE
@@ -46,11 +45,11 @@
 #define STM32_SW                            STM32_SW_PLL
 #define STM32_PLLSRC                        STM32_PLLSRC_HSI
 #define STM32_PLLXTPRE                      STM32_PLLXTPRE_DIV1
-#define STM32_PLLMUL_VALUE                  12
+#define STM32_PLLMUL_VALUE                  16
 #define STM32_HPRE                          STM32_HPRE_DIV1
 #define STM32_PPRE1                         STM32_PPRE1_DIV2
 #define STM32_PPRE2                         STM32_PPRE2_DIV1
-#define STM32_ADCPRE                        STM32_ADCPRE_DIV4
+#define STM32_ADCPRE                        STM32_ADCPRE_DIV6
 #define STM32_USB_CLOCK_REQUIRED            TRUE
 #define STM32_USBPRE                        STM32_USBPRE_DIV1
 #define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
diff --git a/firmware/boards/f1_rev3/mcuconf.h b/firmware/boards/f1_rev3/mcuconf.h
index 2e9ee68..c6c2541 100644
--- a/firmware/boards/f1_rev3/mcuconf.h
+++ b/firmware/boards/f1_rev3/mcuconf.h
@@ -35,8 +35,7 @@
 
 /*
  * HAL driver system settings.
- * TL,DR: we run at 48MHz.
- * It's not possible to run at 72 on HSI because of the PLL's limited configuration options, so 48MHz right now.
+ * Main clock runs at 64MHz, impossible to run maximum rated 72 using HSI due to PLL limitations
  */
 #define STM32_NO_INIT                       FALSE
 #define STM32_HSI_ENABLED                   TRUE
@@ -46,11 +45,11 @@
 #define STM32_SW                            STM32_SW_PLL
 #define STM32_PLLSRC                        STM32_PLLSRC_HSI
 #define STM32_PLLXTPRE                      STM32_PLLXTPRE_DIV1
-#define STM32_PLLMUL_VALUE                  12
+#define STM32_PLLMUL_VALUE                  16
 #define STM32_HPRE                          STM32_HPRE_DIV1
 #define STM32_PPRE1                         STM32_PPRE1_DIV2
 #define STM32_PPRE2                         STM32_PPRE2_DIV1
-#define STM32_ADCPRE                        STM32_ADCPRE_DIV4
+#define STM32_ADCPRE                        STM32_ADCPRE_DIV6
 #define STM32_USB_CLOCK_REQUIRED            TRUE
 #define STM32_USBPRE                        STM32_USBPRE_DIV1
 #define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
diff --git a/firmware/pump_dac.cpp b/firmware/pump_dac.cpp
index 5bc3827..10262c0 100644
--- a/firmware/pump_dac.cpp
+++ b/firmware/pump_dac.cpp
@@ -7,8 +7,9 @@
 #include "hal.h"
 
 // 48MHz / 1024 = 46.8khz PWM
+// 64MHz / 1024 = 62.5khz PWM
 static const PWMConfig pumpDacConfig = {
-    48'000'000,
+    STM32_SYSCLK,
     1024,
     nullptr,
     {