From a6052895e98b4733b17200fa09cebf4b9e6b049b Mon Sep 17 00:00:00 2001 From: Andrey G Date: Mon, 23 Jan 2023 22:23:14 +0300 Subject: [PATCH] f1_dual/rev3: Revert CPU clock back to 48 MHz due to ADC problems on GD32 (#181) --- firmware/boards/f1_dual/mcuconf.h | 7 ++++--- firmware/boards/f1_dual/port_shared.cpp | 4 ++-- firmware/boards/f1_rev3/mcuconf.h | 7 ++++--- firmware/boards/f1_rev3/port_shared.cpp | 4 ++-- 4 files changed, 12 insertions(+), 10 deletions(-) diff --git a/firmware/boards/f1_dual/mcuconf.h b/firmware/boards/f1_dual/mcuconf.h index db8539c..3c4fae8 100644 --- a/firmware/boards/f1_dual/mcuconf.h +++ b/firmware/boards/f1_dual/mcuconf.h @@ -35,7 +35,8 @@ /* * HAL driver system settings. - * Main clock runs at 64MHz, impossible to run maximum rated 72 using HSI due to PLL limitations + * TL,DR: we run at 48MHz. + * It's not possible to run at 72 on HSI because of the PLL's limited configuration options, so 48MHz right now. */ #define STM32_NO_INIT FALSE #define STM32_HSI_ENABLED TRUE @@ -45,11 +46,11 @@ #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSI #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#define STM32_PLLMUL_VALUE 16 +#define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV2 #define STM32_PPRE2 STM32_PPRE2_DIV1 -#define STM32_ADCPRE STM32_ADCPRE_DIV6 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_USB_CLOCK_REQUIRED TRUE #define STM32_USBPRE STM32_USBPRE_DIV1 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK diff --git a/firmware/boards/f1_dual/port_shared.cpp b/firmware/boards/f1_dual/port_shared.cpp index 3e2cbff..ad7927d 100644 --- a/firmware/boards/f1_dual/port_shared.cpp +++ b/firmware/boards/f1_dual/port_shared.cpp @@ -6,7 +6,7 @@ const CANConfig canConfig500 = { CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP, /* - For 32MHz http://www.bittiming.can-wiki.info/ gives us Pre-scaler=4, Seq 1=13 and Seq 2=2. Subtract '1' for register values + For 24MHz http://www.bittiming.can-wiki.info/ gives us Pre-scaler=3, Seq 1=13 and Seq 2=2. Subtract '1' for register values */ - CAN_BTR_SJW(0) | CAN_BTR_BRP(4 - 1) | CAN_BTR_TS1(13 - 1) | CAN_BTR_TS2(2 - 1), + CAN_BTR_SJW(0) | CAN_BTR_BRP(2) | CAN_BTR_TS1(12) | CAN_BTR_TS2(1), }; diff --git a/firmware/boards/f1_rev3/mcuconf.h b/firmware/boards/f1_rev3/mcuconf.h index c6c2541..2e9ee68 100644 --- a/firmware/boards/f1_rev3/mcuconf.h +++ b/firmware/boards/f1_rev3/mcuconf.h @@ -35,7 +35,8 @@ /* * HAL driver system settings. - * Main clock runs at 64MHz, impossible to run maximum rated 72 using HSI due to PLL limitations + * TL,DR: we run at 48MHz. + * It's not possible to run at 72 on HSI because of the PLL's limited configuration options, so 48MHz right now. */ #define STM32_NO_INIT FALSE #define STM32_HSI_ENABLED TRUE @@ -45,11 +46,11 @@ #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSI #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#define STM32_PLLMUL_VALUE 16 +#define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV2 #define STM32_PPRE2 STM32_PPRE2_DIV1 -#define STM32_ADCPRE STM32_ADCPRE_DIV6 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_USB_CLOCK_REQUIRED TRUE #define STM32_USBPRE STM32_USBPRE_DIV1 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK diff --git a/firmware/boards/f1_rev3/port_shared.cpp b/firmware/boards/f1_rev3/port_shared.cpp index 3e2cbff..ad7927d 100644 --- a/firmware/boards/f1_rev3/port_shared.cpp +++ b/firmware/boards/f1_rev3/port_shared.cpp @@ -6,7 +6,7 @@ const CANConfig canConfig500 = { CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP, /* - For 32MHz http://www.bittiming.can-wiki.info/ gives us Pre-scaler=4, Seq 1=13 and Seq 2=2. Subtract '1' for register values + For 24MHz http://www.bittiming.can-wiki.info/ gives us Pre-scaler=3, Seq 1=13 and Seq 2=2. Subtract '1' for register values */ - CAN_BTR_SJW(0) | CAN_BTR_BRP(4 - 1) | CAN_BTR_TS1(13 - 1) | CAN_BTR_TS2(2 - 1), + CAN_BTR_SJW(0) | CAN_BTR_BRP(2) | CAN_BTR_TS1(12) | CAN_BTR_TS2(1), };