mirror of https://github.com/rusefi/wideband.git
board
This commit is contained in:
parent
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commit
b3b7dc94ae
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|||
EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# Amplifier_Operational_MCP6004
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#
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DEF Amplifier_Operational_MCP6004 U 0 5 Y Y 5 L N
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F0 "U" 0 200 50 H V L CNN
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F1 "Amplifier_Operational_MCP6004" 0 -200 50 H V L CNN
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F2 "" -50 100 50 H I C CNN
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F3 "" 50 200 50 H I C CNN
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ALIAS LM324 TLC274 TLC279 TL074 LM324A MCP6004 TL084 TL064 LMV324 LMC6484 MCP604 MC33079 MC33174 MC33179 OPA1604 OPA1679 OPA4134 OPA4340UA OPA4376 MCP6L94 TSV914 ADA4807-4 TSV994
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$FPLIST
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SOIC*3.9x8.7mm*P1.27mm*
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DIP*W7.62mm*
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TSSOP*4.4x5mm*P0.65mm*
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SSOP*5.3x6.2mm*P0.65mm*
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MSOP*3x3mm*P0.5mm*
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$ENDFPLIST
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DRAW
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P 4 1 1 10 -200 200 200 0 -200 -200 -200 200 f
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P 4 2 1 10 -200 200 200 0 -200 -200 -200 200 f
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P 4 3 1 10 -200 200 200 0 -200 -200 -200 200 f
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P 4 4 1 10 -200 200 200 0 -200 -200 -200 200 f
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X ~ 1 300 0 100 L 50 50 1 1 O
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X - 2 -300 -100 100 R 50 50 1 1 I
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X + 3 -300 100 100 R 50 50 1 1 I
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X + 5 -300 100 100 R 50 50 2 1 I
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X - 6 -300 -100 100 R 50 50 2 1 I
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X ~ 7 300 0 100 L 50 50 2 1 O
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X + 10 -300 100 100 R 50 50 3 1 I
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X ~ 8 300 0 100 L 50 50 3 1 O
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X - 9 -300 -100 100 R 50 50 3 1 I
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||||
X + 12 -300 100 100 R 50 50 4 1 I
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X - 13 -300 -100 100 R 50 50 4 1 I
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X ~ 14 300 0 100 L 50 50 4 1 O
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X V- 11 -100 -300 150 U 50 50 5 1 W
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X V+ 4 -100 300 150 D 50 50 5 1 W
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ENDDRAW
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ENDDEF
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#
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# Connector_Generic_Conn_01x06
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#
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DEF Connector_Generic_Conn_01x06 J 0 40 Y N 1 F N
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F0 "J" 0 300 50 H V C CNN
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F1 "Connector_Generic_Conn_01x06" 0 -400 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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Connector*:*_1x??_*
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$ENDFPLIST
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DRAW
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S -50 -295 0 -305 1 1 6 N
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S -50 -195 0 -205 1 1 6 N
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S -50 -95 0 -105 1 1 6 N
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S -50 5 0 -5 1 1 6 N
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S -50 105 0 95 1 1 6 N
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S -50 205 0 195 1 1 6 N
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S -50 250 50 -350 1 1 10 f
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X Pin_1 1 -200 200 150 R 50 50 1 1 P
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X Pin_2 2 -200 100 150 R 50 50 1 1 P
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X Pin_3 3 -200 0 150 R 50 50 1 1 P
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X Pin_4 4 -200 -100 150 R 50 50 1 1 P
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X Pin_5 5 -200 -200 150 R 50 50 1 1 P
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X Pin_6 6 -200 -300 150 R 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Connector_Generic_Conn_01x08
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#
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DEF Connector_Generic_Conn_01x08 J 0 40 Y N 1 F N
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F0 "J" 0 400 50 H V C CNN
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F1 "Connector_Generic_Conn_01x08" 0 -500 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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Connector*:*_1x??_*
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$ENDFPLIST
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DRAW
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S -50 -395 0 -405 1 1 6 N
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S -50 -295 0 -305 1 1 6 N
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S -50 -195 0 -205 1 1 6 N
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S -50 -95 0 -105 1 1 6 N
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S -50 5 0 -5 1 1 6 N
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S -50 105 0 95 1 1 6 N
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S -50 205 0 195 1 1 6 N
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S -50 305 0 295 1 1 6 N
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S -50 350 50 -450 1 1 10 f
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X Pin_1 1 -200 300 150 R 50 50 1 1 P
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X Pin_2 2 -200 200 150 R 50 50 1 1 P
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X Pin_3 3 -200 100 150 R 50 50 1 1 P
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X Pin_4 4 -200 0 150 R 50 50 1 1 P
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X Pin_5 5 -200 -100 150 R 50 50 1 1 P
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X Pin_6 6 -200 -200 150 R 50 50 1 1 P
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X Pin_7 7 -200 -300 150 R 50 50 1 1 P
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X Pin_8 8 -200 -400 150 R 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Connector_Generic_Conn_02x05_Odd_Even
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#
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DEF Connector_Generic_Conn_02x05_Odd_Even J 0 40 Y N 1 F N
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F0 "J" 50 300 50 H V C CNN
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F1 "Connector_Generic_Conn_02x05_Odd_Even" 50 -300 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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Connector*:*_2x??_*
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$ENDFPLIST
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DRAW
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S -50 -195 0 -205 1 1 6 N
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S -50 -95 0 -105 1 1 6 N
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S -50 5 0 -5 1 1 6 N
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S -50 105 0 95 1 1 6 N
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S -50 205 0 195 1 1 6 N
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S -50 250 150 -250 1 1 10 f
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S 150 -195 100 -205 1 1 6 N
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S 150 -95 100 -105 1 1 6 N
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S 150 5 100 -5 1 1 6 N
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S 150 105 100 95 1 1 6 N
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S 150 205 100 195 1 1 6 N
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X Pin_1 1 -200 200 150 R 50 50 1 1 P
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X Pin_10 10 300 -200 150 L 50 50 1 1 P
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X Pin_2 2 300 200 150 L 50 50 1 1 P
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X Pin_3 3 -200 100 150 R 50 50 1 1 P
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X Pin_4 4 300 100 150 L 50 50 1 1 P
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X Pin_5 5 -200 0 150 R 50 50 1 1 P
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X Pin_6 6 300 0 150 L 50 50 1 1 P
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X Pin_7 7 -200 -100 150 R 50 50 1 1 P
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X Pin_8 8 300 -100 150 L 50 50 1 1 P
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X Pin_9 9 -200 -200 150 R 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_C
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#
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DEF Device_C C 0 10 N Y 1 F N
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F0 "C" 25 100 50 H V L CNN
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F1 "Device_C" 25 -100 50 H V L CNN
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F2 "" 38 -150 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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C_*
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$ENDFPLIST
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DRAW
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P 2 0 1 20 -80 -30 80 -30 N
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P 2 0 1 20 -80 30 80 30 N
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X ~ 1 0 150 110 D 50 50 1 1 P
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X ~ 2 0 -150 110 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_LED
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#
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DEF Device_LED D 0 40 N N 1 F N
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F0 "D" 0 100 50 H V C CNN
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F1 "Device_LED" 0 -100 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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LED*
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LED_SMD:*
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LED_THT:*
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$ENDFPLIST
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DRAW
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P 2 0 1 8 -50 -50 -50 50 N
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P 2 0 1 0 -50 0 50 0 N
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P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N
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P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
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P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
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X K 1 -150 0 100 R 50 50 1 1 P
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X A 2 150 0 100 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_Q_NMOS_GDS
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#
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DEF Device_Q_NMOS_GDS Q 0 0 Y N 1 F N
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F0 "Q" 200 50 50 H V L CNN
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F1 "Device_Q_NMOS_GDS" 200 -50 50 H V L CNN
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F2 "" 200 100 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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C 65 0 110 0 1 10 N
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C 100 -70 10 0 1 0 F
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C 100 70 10 0 1 0 F
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P 2 0 1 0 10 0 -100 0 N
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P 2 0 1 10 10 75 10 -75 N
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P 2 0 1 10 30 -50 30 -90 N
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P 2 0 1 10 30 20 30 -20 N
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P 2 0 1 10 30 90 30 50 N
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P 2 0 1 0 100 100 100 70 N
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P 3 0 1 0 100 -100 100 0 30 0 N
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P 4 0 1 0 30 -70 130 -70 130 70 30 70 N
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P 4 0 1 0 40 0 80 15 80 -15 40 0 F
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P 4 0 1 0 110 20 115 15 145 15 150 10 N
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P 4 0 1 0 130 15 115 -10 145 -10 130 15 N
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X G 1 -200 0 100 R 50 50 1 1 I
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X D 2 100 200 100 D 50 50 1 1 P
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X S 3 100 -200 100 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_R
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#
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DEF Device_R R 0 0 N Y 1 F N
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F0 "R" 80 0 50 V V C CNN
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F1 "Device_R" 0 0 50 V V C CNN
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F2 "" -70 0 50 V I C CNN
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||||
F3 "" 0 0 50 H I C CNN
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||||
$FPLIST
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R_*
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$ENDFPLIST
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||||
DRAW
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S -40 -100 40 100 0 1 10 N
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X ~ 1 0 150 50 D 50 50 1 1 P
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X ~ 2 0 -150 50 U 50 50 1 1 P
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||||
ENDDRAW
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ENDDEF
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||||
#
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||||
# MCU_ST_STM32F0_STM32F042K6Ux
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#
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DEF MCU_ST_STM32F0_STM32F042K6Ux U 0 20 Y Y 1 F N
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F0 "U" -400 850 50 H V L CNN
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F1 "MCU_ST_STM32F0_STM32F042K6Ux" 200 850 50 H V L CNN
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F2 "Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.45x3.45mm" -400 -900 50 H I R CNN
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||||
F3 "" 0 0 50 H I C CNN
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||||
ALIAS STM32F042K6Ux
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||||
$FPLIST
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||||
QFN*1EP*5x5mm*P0.5mm*
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||||
$ENDFPLIST
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||||
DRAW
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||||
S -400 -900 400 800 0 1 10 f
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||||
X VDD 1 -100 900 100 D 50 50 1 1 W
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||||
X PA4 10 500 300 100 L 50 50 1 1 B
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||||
X PA5 11 500 200 100 L 50 50 1 1 B
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||||
X PA6 12 500 100 100 L 50 50 1 1 B
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||||
X PA7 13 500 0 100 L 50 50 1 1 B
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||||
X PB0 14 -500 0 100 R 50 50 1 1 B
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||||
X PB1 15 -500 -100 100 R 50 50 1 1 B
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||||
X PB2 16 -500 -200 100 R 50 50 1 1 B
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||||
X VDDIO2 17 100 900 100 D 50 50 1 1 W
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||||
X PA8 18 500 -100 100 L 50 50 1 1 B
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X PA9 19 500 -200 100 L 50 50 1 1 B
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||||
X PF0 2 -500 400 100 R 50 50 1 1 I
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||||
X PA10 20 500 -300 100 L 50 50 1 1 B
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||||
X PA11 21 500 -400 100 L 50 50 1 1 B
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X PA12 22 500 -500 100 L 50 50 1 1 B
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X PA13 23 500 -600 100 L 50 50 1 1 B
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X PA14 24 500 -700 100 L 50 50 1 1 B
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X PA15 25 500 -800 100 L 50 50 1 1 B
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||||
X PB3 26 -500 -300 100 R 50 50 1 1 B
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||||
X PB4 27 -500 -400 100 R 50 50 1 1 B
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||||
X PB5 28 -500 -500 100 R 50 50 1 1 B
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||||
X PB6 29 -500 -600 100 R 50 50 1 1 B
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||||
X PF1 3 -500 300 100 R 50 50 1 1 I
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||||
X PB7 30 -500 -700 100 R 50 50 1 1 B
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||||
X PF11 31 -500 200 100 R 50 50 1 1 B
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||||
X PB8 32 -500 -800 100 R 50 50 1 1 B
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||||
X VSS 33 0 -1000 100 U 50 50 1 1 W
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||||
X NRST 4 -500 700 100 R 50 50 1 1 I
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||||
X VDDA 5 0 900 100 D 50 50 1 1 W
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X PA0 6 500 700 100 L 50 50 1 1 B
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X PA1 7 500 600 100 L 50 50 1 1 B
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X PA2 8 500 500 100 L 50 50 1 1 B
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X PA3 9 500 400 100 L 50 50 1 1 B
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ENDDRAW
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ENDDEF
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||||
#
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# Regulator_Linear_XC6206PxxxMR
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#
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DEF Regulator_Linear_XC6206PxxxMR U 0 10 Y Y 1 F N
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F0 "U" -150 125 50 H V C CNN
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F1 "Regulator_Linear_XC6206PxxxMR" 0 125 50 H V L CNN
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F2 "Package_TO_SOT_SMD:SOT-23" 0 225 50 H I C CIN
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F3 "" 0 0 50 H I C CNN
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ALIAS APE8865N-15-HF-3 APE8865N-16-HF-3 APE8865N-17-HF-3 APE8865N-18-HF-3 APE8865N-19-HF-3 APE8865N-20-HF-3 APE8865N-21-HF-3 APE8865N-22-HF-3 APE8865N-23-HF-3 APE8865N-24-HF-3 APE8865N-25-HF-3 APE8865N-26-HF-3 APE8865N-27-HF-3 APE8865N-28-HF-3 APE8865N-29-HF-3 APE8865N-30-HF-3 APE8865N-31-HF-3 APE8865N-32-HF-3 APE8865N-33-HF-3 AP2127N-1.0 AP2127N-1.2 AP2127N-1.5 AP2127N-1.8 AP2127N-2.5 AP2127N-2.8 AP2127N-3.0 AP2127N-3.3 XC6206PxxxMR
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$FPLIST
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SOT?23*
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$ENDFPLIST
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DRAW
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S -200 75 200 -200 0 1 10 f
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X GND 1 0 -300 100 U 50 50 1 1 W
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X VO 2 300 0 100 L 50 50 1 1 w
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X VI 3 -300 0 100 R 50 50 1 1 W
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ENDDRAW
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ENDDEF
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#
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# power_+3.3V
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#
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DEF power_+3.3V #PWR 0 0 Y Y 1 F P
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F0 "#PWR" 0 -150 50 H I C CNN
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F1 "power_+3.3V" 0 140 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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ALIAS +3.3V
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DRAW
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P 2 0 1 0 -30 50 0 100 N
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P 2 0 1 0 0 0 0 100 N
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P 2 0 1 0 0 100 30 50 N
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X +3V3 1 0 0 0 U 50 50 1 1 W N
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ENDDRAW
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||||
ENDDEF
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||||
#
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# power_+5V
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#
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DEF power_+5V #PWR 0 0 Y Y 1 F P
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F0 "#PWR" 0 -150 50 H I C CNN
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F1 "power_+5V" 0 140 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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P 2 0 1 0 -30 50 0 100 N
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P 2 0 1 0 0 0 0 100 N
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P 2 0 1 0 0 100 30 50 N
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X +5V 1 0 0 0 U 50 50 1 1 W N
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ENDDRAW
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||||
ENDDEF
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#
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# power_GND
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#
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DEF power_GND #PWR 0 0 Y Y 1 F P
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F0 "#PWR" 0 -250 50 H I C CNN
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||||
F1 "power_GND" 0 -150 50 H V C CNN
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||||
F2 "" 0 0 50 H I C CNN
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||||
F3 "" 0 0 50 H I C CNN
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||||
DRAW
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||||
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
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||||
X GND 1 0 0 0 D 50 50 1 1 W N
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||||
ENDDRAW
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||||
ENDDEF
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||||
#
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# power_PWR_FLAG
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#
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DEF power_PWR_FLAG #FLG 0 0 N N 1 F P
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||||
F0 "#FLG" 0 75 50 H I C CNN
|
||||
F1 "power_PWR_FLAG" 0 150 50 H V C CNN
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||||
F2 "" 0 0 50 H I C CNN
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||||
F3 "" 0 0 50 H I C CNN
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||||
DRAW
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||||
P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
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||||
X pwr 1 0 0 0 U 50 50 0 0 w
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||||
ENDDRAW
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||||
ENDDEF
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||||
#
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#End Library
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,243 @@
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update=Thursday, September 17, 2020 at 11:00:43 PM
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version=1
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last_client=kicad
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[general]
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||||
version=1
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||||
RootSch=
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||||
BoardNm=
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||||
[cvpcb]
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||||
version=1
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||||
NetIExt=net
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||||
[eeschema]
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||||
version=1
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||||
LibDir=
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||||
[eeschema/libraries]
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||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
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||||
LastNetListRead=
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||||
CopperLayerCount=2
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||||
BoardThickness=1.6
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||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.1651
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||||
MinViaDiameter=0.4
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||||
MinViaDrill=0.3
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||||
MinMicroViaDiameter=0.2
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||||
MinMicroViaDrill=0.09999999999999999
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||||
MinHoleToHole=0.25
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||||
TrackWidth1=0.25
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||||
TrackWidth2=0.25
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||||
TrackWidth3=0.5
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||||
TrackWidth4=3
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||||
ViaDiameter1=0.6
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||||
ViaDrill1=0.3
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||||
ViaDiameter2=0.6
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||||
ViaDrill2=0.3
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||||
dPairWidth1=0.2
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||||
dPairGap1=0.25
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||||
dPairViaGap1=0.25
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||||
SilkLineWidth=0.12
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||||
SilkTextSizeV=1
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||||
SilkTextSizeH=1
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||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.05
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0.051
|
||||
SolderMaskMinWidth=0.25
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.1651
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.6
|
||||
ViaDrill=0.3
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue